From 9f5b0b0b76ed471a6765867511457eb90df8b741 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Sep 2007 12:31:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/buzzer.c | 82 ++++++++++++++++ demos/LPC214x-GCC/buzzer.h | 28 ++++++ demos/LPC214x-GCC/ch.ld | 85 +++++++++++++++++ demos/LPC214x-GCC/chconf.h | 153 ++++++++++++++++++++++++++++++ demos/LPC214x-GCC/chcore.c | 225 ++++++++++++++++++++++++++++++++++++++++++++ demos/LPC214x-GCC/chcore.h | 98 +++++++++++++++++++ demos/LPC214x-GCC/chcore2.s | 168 +++++++++++++++++++++++++++++++++ demos/LPC214x-GCC/chtypes.h | 52 ++++++++++ demos/LPC214x-GCC/crt0.s | 146 ++++++++++++++++++++++++++++ demos/LPC214x-GCC/main.c | 79 ++++++++++++++++ demos/LPC214x-GCC/makefile | 156 ++++++++++++++++++++++++++++++ 11 files changed, 1272 insertions(+) create mode 100644 demos/LPC214x-GCC/buzzer.c create mode 100644 demos/LPC214x-GCC/buzzer.h create mode 100644 demos/LPC214x-GCC/ch.ld create mode 100644 demos/LPC214x-GCC/chconf.h create mode 100644 demos/LPC214x-GCC/chcore.c create mode 100644 demos/LPC214x-GCC/chcore.h create mode 100644 demos/LPC214x-GCC/chcore2.s create mode 100644 demos/LPC214x-GCC/chtypes.h create mode 100644 demos/LPC214x-GCC/crt0.s create mode 100644 demos/LPC214x-GCC/main.c create mode 100644 demos/LPC214x-GCC/makefile (limited to 'demos') diff --git a/demos/LPC214x-GCC/buzzer.c b/demos/LPC214x-GCC/buzzer.c new file mode 100644 index 000000000..4700bfb45 --- /dev/null +++ b/demos/LPC214x-GCC/buzzer.c @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Buzzer driver for Olimex LPC-P2148. + * Uses the timer 1 for wave generation and a Virtual Timer for the sound + * duration. + * The driver also generates an event when the sound is done and the buzzer + * goes silent. + */ +#include + +#include "lpc214x.h" +#include "buzzer.h" + +EventSource BuzzerSilentEventSource; + +#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1) +#define StopCounter(t) ((t)->TC_EMR = 0, (t)->TC_TCR = 2) + +void InitBuzzer(void) { + + chEvtInit(&BuzzerSilentEventSource); + + /* + * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions. + * Enables Timer1 clock. + */ + PINSEL0 &= 0xF0FFFFFF; + PINSEL0 |= 0x0A000000; + PCONP = (PCONP & PCALL) | PCTIM1; + + /* + * Timer setup. + */ + TC *tc = T1Base; + StopCounter(tc); + tc->TC_CTCR = 0; // Clock source is PCLK. + tc->TC_PR = 0; // Prescaler disabled. + tc->TC_MCR = 2; // Clear TC on match MR0. +} + +static void stop(void *p) { + TC *tc = T1Base; + + StopCounter(tc); + chEvtSendI(&BuzzerSilentEventSource); +} + +void PlaySound(int freq, t_time duration) { + static VirtualTimer bvt; + TC *tc = T1Base; + + chSysLock(); + + if (bvt.vt_func) { // If a sound is already being played + chVTResetI(&bvt); // then aborts it. + StopCounter(tc); + } + + tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); + StartCounter(tc); + chVTSetI(&bvt, duration, stop, NULL); + + chSysUnlock(); +} diff --git a/demos/LPC214x-GCC/buzzer.h b/demos/LPC214x-GCC/buzzer.h new file mode 100644 index 000000000..3334d8b5c --- /dev/null +++ b/demos/LPC214x-GCC/buzzer.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BUZZER_H_ +#define _BUZZER_H_ + +void InitBuzzer(void); +void PlaySound(int freq, t_time duration); + +extern EventSource BuzzerSilentEventSource; + +#endif /* _BUZZER_H_ */ diff --git a/demos/LPC214x-GCC/ch.ld b/demos/LPC214x-GCC/ch.ld new file mode 100644 index 000000000..6ce8a0b32 --- /dev/null +++ b/demos/LPC214x-GCC/ch.ld @@ -0,0 +1,85 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0080; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : + { + _text = .; + *(.text); + *(.rodata); + *(.rodata*); + *(.glue_7t); + *(.glue_7); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/LPC214x-GCC/chconf.h b/demos/LPC214x-GCC/chconf.h new file mode 100644 index 000000000..bb03058c8 --- /dev/null +++ b/demos/LPC214x-GCC/chconf.h @@ -0,0 +1,153 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Semaphores APIs with priority + * shift are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES.*/ +//#define CH_USE_RT_SEMAPHORES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +//#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +//#define CH_USE_MESSAGES_TIMEOUT + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +//#define CH_USE_MESSAGES_EVENT + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/LPC214x-GCC/chcore.c b/demos/LPC214x-GCC/chcore.c new file mode 100644 index 000000000..3d72c20db --- /dev/null +++ b/demos/LPC214x-GCC/chcore.c @@ -0,0 +1,225 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "lpc214x_serial.h" +#include "buzzer.h" + +extern void IrqHandler(void); +extern void T0IrqHandler(void); + +#define VAL_TC0_PRESCALER 0 + +/* + * Pins configuration for Olimex LPC-P2148. + * + * PINSEL0 + * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD + * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 + * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 + * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- + * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + * + * PINSEL1 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 SSE MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 L1 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 10 10 10 10 00 + * OUT -- OUT OUT -- -- -- -- -- OUT OUT -- -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 + * + * PINSEL2 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- + * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- + */ +#define VAL_PINSEL0 0x00055555 +#define VAL_PINSEL1 0x100842A8 +#define VAL_PINSEL2 0x00000004 +#define VAL_FIO0DIR 0xB0603C00 +#define VAL_FIO1DIR 0x00000000 + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { + int i; + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLLBase; + pll->PLL0_CFG = 0x23; /* P and M values. */ + pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + while (!(pll->PLL0_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL0_CON = 0x3; /* Connects the PLL. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; + + /* + * I/O pins configuration. + */ + PINSEL0 = VAL_PINSEL0; + PINSEL1 = VAL_PINSEL1; + PINSEL2 = VAL_PINSEL2; + IO0DIR = VAL_FIO0DIR; + IO0SET = 0xFFFFFFFF; + IO1DIR = VAL_FIO1DIR; + IO1SET = 0xFFFFFFFF; + + /* + * Interrupt vectors assignment. + * NOTE: Better reset everything in the VIC, it is a HUGE source of trouble. + */ + VIC *vic = VICBase; + vic->VIC_IntSelect = 0; + vic->VIC_IntEnable = 0; + vic->VIC_VectAddr = 0; + for (i = 0; i < 16; i++) { + vic->VIC_VectCntls[i] = 0; + vic->VIC_VectAddrs[i] = 0; + } + vic->VIC_DefVectAddr = (IOREG32)IrqHandler; + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); + SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); + SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); + + /* + * System Timer initialization, 1ms intervals. + */ + vic->VIC_IntEnable |= INTMASK(SOURCE_Timer0); + TC *timer = T0Base; + timer->TC_PR = VAL_TC0_PRESCALER; + timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); + timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ + timer->TC_TCR = 2; /* Reset counter and prescaler. */ + timer->TC_TCR = 1; /* Timer enabled. */ + + /* + * Other subsystems. + */ + InitSerial(); + InitBuzzer(); +} + +void chSysPause(void) { + + while (TRUE) { +// Note, it is disabled because it causes trouble with the JTAG probe. +// Enable it in the final code only. +// PCON = 1; /* Stops CPU clock until next interrupt. */ + } +} + +/* + * System halt. + * Yellow LED only. + */ +void chSysHalt(void) { + + chSysLock(); + IO0SET = 0x80000C00; + IO0CLR = 0x80000000; + while (TRUE) + ; +} + +/* + * Set a vector for an interrupt source, the vector is enabled too. + */ +void SetVICVector(void *handler, int vector, int source) { + + VIC *vicp = VICBase; + vicp->VIC_VectAddrs[vector] = (IOREG32)handler; + vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20); +} + +/* + * Undefined Instruction exception handler. + * Yellow LED + RED LED 2. + */ +void UndHandler(void) { + IO0SET = 0x80000C00; + IO0CLR = 0x80000800; + while(TRUE) + ; +} + +/* + * Prefetch exception handler. + * Yellow LED + RED LED 1. + */ +void PrefetchHandler(void) { + IO0SET = 0x80000C00; + IO0CLR = 0x80000400; + while(TRUE) + ; +} + +/* + * Abort exception handler. + * Yellow LED + both RED LEDs. + */ +void AbortHandler(void) { + IO0SET = 0x80000C00; + IO0CLR = 0x80000C00; + while(TRUE) + ; +} + +/* + * Non-vectored IRQs handling here. + */ +void NonVectoredIrq(void) { + VICVectAddr = 0; +} + +/* + * Timer 0 IRQ handling here. + */ +void Timer0Irq(void) { + chSchTimerHandlerI(); + T0IR = 1; /* Clear interrupt on match MR0. */ + VICVectAddr = 0; +} diff --git a/demos/LPC214x-GCC/chcore.h b/demos/LPC214x-GCC/chcore.h new file mode 100644 index 000000000..6dfdae6e9 --- /dev/null +++ b/demos/LPC214x-GCC/chcore.h @@ -0,0 +1,98 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +typedef void *regarm; + +/* + * Stack saved context. + */ +struct stackregs { + regarm r4; + regarm r5; + regarm r6; +#ifndef MK_CURRP_REGISTER_CACHE + regarm r7; +#endif + regarm r8; + regarm r9; + regarm r10; + regarm r11; + regarm lr; +}; + +typedef struct { + struct stackregs *r13; +} Context; + +#ifdef MK_CURRP_REGISTER_CACHE +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct stackregs)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->r6 = 0; \ + tp->p_ctx.r13->r8 = 0; \ + tp->p_ctx.r13->r9 = 0; \ + tp->p_ctx.r13->r10 = 0; \ + tp->p_ctx.r13->r11 = 0; \ + tp->p_ctx.r13->lr = threadstart; \ +} +#else +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct stackregs)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->r6 = 0; \ + tp->p_ctx.r13->r7 = 0; \ + tp->p_ctx.r13->r8 = 0; \ + tp->p_ctx.r13->r9 = 0; \ + tp->p_ctx.r13->r10 = 0; \ + tp->p_ctx.r13->r11 = 0; \ + tp->p_ctx.r13->lr = threadstart; \ +} +#endif + +#define chSysLock() asm("msr CPSR_c, #0x9F") + +#define chSysUnlock() asm("msr CPSR_c, #0x1F") + +#define INT_REQUIRED_STACK 0x40 // Must include registers and stack frames. + +#define UserStackSize(n) (sizeof(Thread) + \ + sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) + +void chSysHalt(void) __attribute__((noreturn)); +void chSysPause(void); +void chSysSwitchI(Context *oldp, Context *newp); +void threadstart(void); +void DefFiqHandler(void); +void DefIrqHandler(void); +void SpuriousHandler(void); + +void SetVICVector(void *handler, int vector, int source); + +#endif /* _CHCORE_H_ */ diff --git a/demos/LPC214x-GCC/chcore2.s b/demos/LPC214x-GCC/chcore2.s new file mode 100644 index 000000000..eec962655 --- /dev/null +++ b/demos/LPC214x-GCC/chcore2.s @@ -0,0 +1,168 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "chconf.h" + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text +.code 32 +.balign 4 + +.globl threadstart +threadstart: + msr CPSR_c, #MODE_SYS + mov r0, r5 +/* blx r4*/ + mov lr, pc + bx r4 + bl chThdExit + +.globl SwiHandler +SwiHandler: + b SwiHandler + +.globl DefIrqHandler +DefIrqHandler: + b DefIrqHandler + +.globl FiqHandler +FiqHandler: + b FiqHandler + +.globl chSysSwitchI +chSysSwitchI: +#ifdef MK_CURRP_REGISTER_CACHE + stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + bx lr +#else + stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + bx lr +#endif + +/* + * System stack frame structure after a context switch in the + * interrupt handler: + * + * High +------------+ + * | R12 | -+ + * | R3 | | + * | R2 | | + * | R1 | | External context: IRQ handler frame + * | R0 | | + * | LR_IRQ | | (user code return address) + * | SPSR | -+ (user code status) + * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space + * | LR | -+ (system code return address) + * | R11 | | + * | R10 | | + * | R9 | | + * | R8 | | Internal context: mk_SwitchI() frame + * | (R7) | | (optional, see MK_CURRP_REGISTER_CACHE) + * | R6 | | + * | R5 | | + * SP-> | R4 | -+ + * Low +------------+ + */ +.globl IrqHandler +IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc} + bl NonVectoredIrq + b IrqCommon + +.globl T0IrqHandler +T0IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc}^ + bl Timer0Irq + b IrqCommon + +.globl UART0IrqHandler +UART0IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc}^ + bl UART0Irq + b IrqCommon + +.globl UART1IrqHandler +UART1IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc}^ + bl UART1Irq + b IrqCommon + +/* + * Common exit point for all IRQ routines, it performs the rescheduling if + * required. + */ +IrqCommon: + bl chSchRescRequiredI + cmp r0, #0 // Simply returns if a + ldmeqfd sp!, {r0-r3, r12, pc}^ // reschedule is not required. + + // Saves the IRQ mode registers in the system stack. + ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0-r3, r12} // Registers on System Stack. + msr CPSR_c, #MODE_IRQ | I_BIT + mrs r0, SPSR + mov r1, lr + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. + + // Context switch. + bl chSchDoRescheduleI + + // Re-establish the IRQ conditions again. + ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. + msr CPSR_c, #MODE_IRQ | I_BIT + msr SPSR_fsxc, r0 + mov lr, r1 + msr CPSR_c, #MODE_SYS | I_BIT + ldmfd sp!, {r0-r3, r12} + msr CPSR_c, #MODE_IRQ | I_BIT + subs pc, lr, #0 diff --git a/demos/LPC214x-GCC/chtypes.h b/demos/LPC214x-GCC/chtypes.h new file mode 100644 index 000000000..48bf7a7d9 --- /dev/null +++ b/demos/LPC214x-GCC/chtypes.h @@ -0,0 +1,52 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +/* + * Generic types often dependant on the compiler. + */ +#define BOOL char +#define BYTE8 unsigned char +#define WORD16 short +#define UWORD16 unsigned short +#define LONG32 int +#define ULONG32 unsigned int +#define PTR_EQ int + +typedef BYTE8 t_tmode; +typedef BYTE8 t_tstate; +typedef WORD16 t_prio; +typedef PTR_EQ t_msg; +typedef LONG32 t_eventid; +typedef ULONG32 t_eventmask; +typedef ULONG32 t_time; +typedef LONG32 t_semcnt; +typedef ULONG32 t_size; + +#define MINPRIO 0x8000 +#define MAXPRIO 0x7fff + +#define MINDELTA 0 +#define MAXDELTA 0xffff + +#define INLINE inline + +#endif /* _CHTYPES_H_ */ diff --git a/demos/LPC214x-GCC/crt0.s b/demos/LPC214x-GCC/crt0.s new file mode 100644 index 000000000..9b413191b --- /dev/null +++ b/demos/LPC214x-GCC/crt0.s @@ -0,0 +1,146 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Generic ARM startup file for ChibiOS/RT. + */ + +.extern _main + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text +.code 32 +.balign 4 +/* + * System entry points. + */ +_start: + b ResetHandler + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ + ldr pc, _fiq + +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler +_fiq: + .word FiqHandler + .word 0 + .word 0 + +/* + * Reset handler. + */ +ResetHandler: + /* + * Stack pointers initialization. + */ + ldr r0, =__ram_end__ + /* Undefined */ + msr CPSR_c, #MODE_UND | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__und_stack_size__ + sub r0, r0, r1 + /* Abort */ + msr CPSR_c, #MODE_ABT | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__abt_stack_size__ + sub r0, r0, r1 + /* FIQ */ + msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__fiq_stack_size__ + sub r0, r0, r1 + /* IRQ */ + msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__irq_stack_size__ + sub r0, r0, r1 + /* Supervisor */ + msr CPSR_c, #MODE_SVC | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__svc_stack_size__ + sub r0, r0, r1 + /* System */ + msr CPSR_c, #MODE_SYS | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__sys_stack_size__ + sub r0, r0, r1 + /* + * Check on allocated stacks size. This should never happen unless you + * don't care to verify the map file after compiling your application. + */ + ldr r1, =_bss_end + cmp r0, r1 + bge ramsizeok + bl chSysHalt +ramsizeok: + /* + * Data initialization. + * NOTE: It assumes that the DATA size is a multiple of 4. + */ + ldr r1, =_textdata + ldr r2, =_data + ldr r3, =_edata +dataloop: + cmp r2, r3 + ldrlo r0, [r1], #4 + strlo r0, [r2], #4 + blo dataloop + /* + * BSS initialization. + * NOTE: It assumes that the BSS size is a multiple of 4. + */ + mov r0, #0 + ldr r1, =_bss_start + ldr r2, =_bss_end +bssloop: + cmp r1, r2 + strlo r0, [r1], #4 + blo bssloop + /* + * Application-provided HW initialization routine. + */ + bl hwinit + /* + * main(0, NULL). + */ + mov r0, #0 + mov r1, #0 + bl main + bl chSysHalt diff --git a/demos/LPC214x-GCC/main.c b/demos/LPC214x-GCC/main.c new file mode 100644 index 000000000..94c68ed48 --- /dev/null +++ b/demos/LPC214x-GCC/main.c @@ -0,0 +1,79 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "lpc214x_serial.h" +#include "buzzer.h" + +static BYTE8 waThread1[UserStackSize(16)]; + +static t_msg Thread1(void *arg) { + + while (TRUE) { + IO0CLR = 0x00000800; + chThdSleep(200); + IO0SET = 0x00000C00; + chThdSleep(800); + IO0CLR = 0x00000400; + chThdSleep(200); + IO0SET = 0x00000C00; + chThdSleep(800); + } + return 0; +} + +static BYTE8 waThread2[UserStackSize(16)]; + +static t_msg Thread2(void *arg) { + + while (TRUE) { + IO0CLR = 0x80000000; + chThdSleep(200); + IO0SET = 0x80000000; + chThdSleep(300); + } + return 0; +} + +static BYTE8 waThread3[UserStackSize(16)]; + +static t_msg Thread3(void *arg) { + + while (TRUE) { + if (!(IO0PIN & 0x00008000)) // Button 1 + PlaySound(1000, 100); + if (!(IO0PIN & 0x00010000)) // Button 2 + chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + chThdSleep(500); + + } + return 0; +} + +int main(int argc, char **argv) { + + chSysInit(); + chThdCreate(NORMALPRIO + 1, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreate(NORMALPRIO + 1, 0, waThread2, sizeof(waThread2), Thread2, NULL); + chThdCreate(NORMALPRIO + 1, 0, waThread3, sizeof(waThread3), Thread3, NULL); + chSysPause(); + return 0; +} diff --git a/demos/LPC214x-GCC/makefile b/demos/LPC214x-GCC/makefile new file mode 100644 index 000000000..b07f8360f --- /dev/null +++ b/demos/LPC214x-GCC/makefile @@ -0,0 +1,156 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = chcore.c buzzer.c main.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ + ../../src/chqueues.c ../../src/chserial.c + +# List ASM source files here +ASRC = crt0.s chcore2.s + +# List all user directories here +UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +# NOTE: -mthumb-interwork increases the code size, remove it if you don't really need it. +# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. +#OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT = -O0 -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +#ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** -- cgit v1.2.3 From 549f84d1206d14b5778cf5a723ee6b0942132158 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Sep 2007 12:36:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MSVS/ch.sln | 21 +++ demos/Win32-MSVS/ch.vcproj | 246 +++++++++++++++++++++++++++++++++++ demos/Win32-MSVS/chconf.h | 158 +++++++++++++++++++++++ demos/Win32-MSVS/chcore.c | 112 ++++++++++++++++ demos/Win32-MSVS/chcore.h | 74 +++++++++++ demos/Win32-MSVS/chtypes.h | 52 ++++++++ demos/Win32-MSVS/demo.c | 305 ++++++++++++++++++++++++++++++++++++++++++++ demos/Win32-MinGW/chconf.h | 158 +++++++++++++++++++++++ demos/Win32-MinGW/chcore.c | 105 +++++++++++++++ demos/Win32-MinGW/chcore.h | 74 +++++++++++ demos/Win32-MinGW/chcore2.s | 43 +++++++ demos/Win32-MinGW/chtypes.h | 52 ++++++++ demos/Win32-MinGW/demo.c | 305 ++++++++++++++++++++++++++++++++++++++++++++ demos/Win32-MinGW/makefile | 129 +++++++++++++++++++ 14 files changed, 1834 insertions(+) create mode 100644 demos/Win32-MSVS/ch.sln create mode 100644 demos/Win32-MSVS/ch.vcproj create mode 100644 demos/Win32-MSVS/chconf.h create mode 100644 demos/Win32-MSVS/chcore.c create mode 100644 demos/Win32-MSVS/chcore.h create mode 100644 demos/Win32-MSVS/chtypes.h create mode 100644 demos/Win32-MSVS/demo.c create mode 100644 demos/Win32-MinGW/chconf.h create mode 100644 demos/Win32-MinGW/chcore.c create mode 100644 demos/Win32-MinGW/chcore.h create mode 100644 demos/Win32-MinGW/chcore2.s create mode 100644 demos/Win32-MinGW/chtypes.h create mode 100644 demos/Win32-MinGW/demo.c create mode 100644 demos/Win32-MinGW/makefile (limited to 'demos') diff --git a/demos/Win32-MSVS/ch.sln b/demos/Win32-MSVS/ch.sln new file mode 100644 index 000000000..cb9406206 --- /dev/null +++ b/demos/Win32-MSVS/ch.sln @@ -0,0 +1,21 @@ +Microsoft Visual Studio Solution File, Format Version 8.00 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ch", "ch.vcproj", "{0A528619-7F3F-4459-AAC5-DE8BA570D51D}" + ProjectSection(ProjectDependencies) = postProject + EndProjectSection +EndProject +Global + GlobalSection(SolutionConfiguration) = preSolution + Debug = Debug + Release = Release + EndGlobalSection + GlobalSection(ProjectConfiguration) = postSolution + {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Debug.ActiveCfg = Debug|Win32 + {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Debug.Build.0 = Debug|Win32 + {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Release.ActiveCfg = Release|Win32 + {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Release.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + EndGlobalSection + GlobalSection(ExtensibilityAddIns) = postSolution + EndGlobalSection +EndGlobal diff --git a/demos/Win32-MSVS/ch.vcproj b/demos/Win32-MSVS/ch.vcproj new file mode 100644 index 000000000..b1619033c --- /dev/null +++ b/demos/Win32-MSVS/ch.vcproj @@ -0,0 +1,246 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h new file mode 100644 index 000000000..59a13d224 --- /dev/null +++ b/demos/Win32-MSVS/chconf.h @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for Visual Studio 7 demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/* + * NOTE: this is just documentation for doxigen, the real configuration file + * is the one into the project directories. + */ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Semaphores APIs with priority + * shift are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES.*/ +#define CH_USE_RT_SEMAPHORES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_TIMEOUT + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 100 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 10 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-\. + */ +//#define CH_CURRP_REGISTER_CACHE "reg" + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c new file mode 100644 index 000000000..bb038a4d6 --- /dev/null +++ b/demos/Win32-MSVS/chcore.c @@ -0,0 +1,112 @@ +#include +#include + +#undef CDECL + +#include + +static LARGE_INTEGER nextcnt; +static LARGE_INTEGER slice; + +void InitSimCom1(void); +void InitSimCom2(void); +BOOL Com1ConnInterruptSimCom(void); +BOOL Com2ConnInterruptSimCom(void); +BOOL Com1InInterruptSimCom(void); +BOOL Com2InInterruptSimCom(void); +BOOL Com1OutInterruptSimCom(void); +BOOL Com2OutInterruptSimCom(void); + +/* + * Simulated HW initialization. + */ +void InitCore(void) { + WSADATA wsaData; + + // Initialization. + if (WSAStartup(2, &wsaData) != 0) { + printf("Unable to locate a winsock DLL\n"); + exit(1); + } + + printf("Win32 ChibiOS/RT simulator\n\n"); + printf("Thread structure %d bytes\n", sizeof(Thread)); + if (!QueryPerformanceFrequency(&slice)) { + printf("QueryPerformanceFrequency() error"); + exit(1); + } + printf("Core Frequency %d Hz\n", slice.LowPart); + slice.QuadPart /= CH_FREQUENCY; + QueryPerformanceCounter(&nextcnt); + nextcnt.QuadPart += slice.QuadPart; + + InitSimCom1(); + InitSimCom2(); +} + +/* + * Interrupt simulation. + */ +static void ChkIntSources(void) { + LARGE_INTEGER n; + + if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || + Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || + Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { + chSchRescheduleI(); + return; + } + + // Interrupt Timer simulation (10ms interval). + QueryPerformanceCounter(&n); + if (n.QuadPart > nextcnt.QuadPart) { + nextcnt.QuadPart += slice.QuadPart; + chSchTimerHandlerI(); + if (chSchRescRequiredI()) + chSchDoRescheduleI(); + } +} + +void __fastcall chSysPause(void) { + + while (TRUE) { + + ChkIntSources(); + Sleep(0); + } +} + +__declspec(naked) void __fastcall chSysHalt(void) { + + exit(2); +} + +__declspec(naked) void __fastcall chSysSwitchI(Context *oldp, Context *newp) { + + __asm { + // Switch out code + push ebp + push esi + push edi + push ebx + mov dword ptr [ecx],esp + // Switch in code + mov esp,[edx] + pop ebx + pop edi + pop esi + pop ebp + ret + } +} + +__declspec(naked) void __fastcall threadexit(void) { + + __asm { +// add esp,4 ; The thread parameter + push eax ; The exit code returned by the thread + call chThdExit + add esp,4 + call chSysHalt ; Should *never* happen + } +} diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h new file mode 100644 index 000000000..487dd175a --- /dev/null +++ b/demos/Win32-MSVS/chcore.h @@ -0,0 +1,74 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Core file for Visual Studio 7 demo project. + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +typedef void *regx86; + +/* + * Stack saved context. + */ +struct stackregs { + regx86 ebx; + regx86 edi; + regx86 esi; + regx86 ebp; + regx86 eip; +}; + +typedef struct { + struct stackregs *esp; +} Context; + +#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) + +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + BYTE8 *esp = (BYTE8 *)workspace + wsize; \ + APUSH(esp, arg); \ + APUSH(esp, threadexit); \ + esp -= sizeof(struct stackregs); \ + ((struct stackregs *)esp)->eip = pf; \ + ((struct stackregs *)esp)->ebx = 0; \ + ((struct stackregs *)esp)->edi = 0; \ + ((struct stackregs *)esp)->esi = 0; \ + ((struct stackregs *)esp)->ebp = 0; \ + tp->p_ctx.esp = (struct stackregs *)esp; \ +} + +#define chSysLock() + +#define chSysUnlock() + +#define INT_REQUIRED_STACK 0x0 + +#define UserStackSize(n) (sizeof(Thread) + sizeof(PTR_EQ) + sizeof(PTR_EQ) + \ + sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) + +void __fastcall chSysHalt(void); +void __fastcall chSysPause(void); +void __fastcall chSysSwitchI(Context *oldp, Context *newp); +void __fastcall threadexit(void); + +#endif /* _CHCORE_H_ */ diff --git a/demos/Win32-MSVS/chtypes.h b/demos/Win32-MSVS/chtypes.h new file mode 100644 index 000000000..33eb4b963 --- /dev/null +++ b/demos/Win32-MSVS/chtypes.h @@ -0,0 +1,52 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +/* + * Generic types often dependant on the compiler. + */ +#define BOOL char +#define BYTE8 unsigned char +#define WORD16 short +#define UWORD16 unsigned short +#define LONG32 int +#define ULONG32 unsigned int +#define PTR_EQ int + +typedef BYTE8 t_tmode; +typedef BYTE8 t_tstate; +typedef WORD16 t_prio; +typedef PTR_EQ t_msg; +typedef LONG32 t_eventid; +typedef ULONG32 t_eventmask; +typedef ULONG32 t_time; +typedef LONG32 t_semcnt; +typedef ULONG32 t_size; + +#define MINPRIO 0x8000 +#define MAXPRIO 0x7fff + +#define MINDELTA 0 +#define MAXDELTA 0xffff + +#define INLINE __inline + +#endif /* _CHTYPES_H_ */ diff --git a/demos/Win32-MSVS/demo.c b/demos/Win32-MSVS/demo.c new file mode 100644 index 000000000..d068ca730 --- /dev/null +++ b/demos/Win32-MSVS/demo.c @@ -0,0 +1,305 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include + +static ULONG32 wdguard; +static BYTE8 wdarea[UserStackSize(2048)]; + +static ULONG32 iguard; +static BYTE8 iarea[UserStackSize(2048)]; + +static ULONG32 cdguard; +static BYTE8 cdarea[UserStackSize(2048)]; +static Thread *cdtp; + +static t_msg WatchdogThread(void *arg); +static t_msg ConsoleThread(void *arg); +static t_msg InitThread(void *arg); + +void InitCore(void); +extern FullDuplexDriver COM1, COM2; + +#define cprint(msg) chMsgSend(cdtp, (t_msg)msg) + +/*------------------------------------------------------------------------* + * Simulator main, start here your threads, examples inside. * + *------------------------------------------------------------------------*/ +int main(void) { + + InitCore(); + + // Startup ChibiOS/RT. + chSysInit(); + chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); + cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); + chThdCreate(NORMALPRIO, 0, iarea, sizeof(iarea), InitThread, NULL); + chSysPause(); + return 0; +} + +/* + * Watchdog thread, it checks magic values located under the various stack + * areas. The system is halted if something is wrong. + */ +static t_msg WatchdogThread(void *arg) { + wdguard = 0xA51F2E3D; + iguard = 0xA51F2E3D; + cdguard = 0xA51F2E3D; + while (TRUE) { + + if ((wdguard != 0xA51F2E3D) || + (iguard != 0xA51F2E3D) || + (cdguard != 0xA51F2E3D)) { + printf("Halted by watchdog"); + chSysHalt(); + } + chThdSleep(5); + } + return 0; +} + +/* + * Console print server done using synchronous messages. This makes the access + * to the C printf() thread safe and the print operation atomic among threads. + * In this example the message is the zero termitated string itself. + */ +static t_msg ConsoleThread(void *arg) { + + while (!chThdShouldTerminate()) { + printf((char *)chMsgWait()); + chMsgRelease(RDY_OK); + } + return 0; +} + +static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { + + while (*msg) + chFDDPut(sd, *msg++); +} + +static BOOL GetLineFDD(FullDuplexDriver *sd, char *line, int size) { + char *p = line; + + while (TRUE) { + short c = chIQGet(&sd->sd_iqueue); + if (c < 0) + return TRUE; + if (c == 4) { + PrintLineFDD(sd, "^D\r\n"); + return TRUE; + } + if (c == 8) { + if (p != line) { + chFDDPut(sd, (BYTE8)c); + chFDDPut(sd, 0x20); + chFDDPut(sd, (BYTE8)c); + p--; + } + continue; + } + if (c == '\r') { + PrintLineFDD(sd, "\r\n"); + *p = 0; + return FALSE; + } + if (c < 0x20) + continue; + if (p < line + size - 1) { + chFDDPut(sd, (BYTE8)c); + *p++ = (BYTE8)c; + } + } +} + +/* + * Example thread, not much to see here. It simulates the CTRL-C but there + * are no real signals involved. + */ +static t_msg HelloWorldThread(void *arg) { + int i; + short c; + FullDuplexDriver *sd = (FullDuplexDriver *)arg; + + for (i = 0; i < 100; i++) { + + PrintLineFDD(sd, "Hello World\r\n"); + c = chFDDGetTimeout(sd, 33); + switch (c) { + case -1: + continue; + case -2: + return 1; + case 3: + PrintLineFDD(sd, "^C\r\n"); + return 0; + default: + chThdSleep(33); + } + } + return 0; +} + +static BOOL checkend(FullDuplexDriver *sd) { + + char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ + if (lp) { + PrintLineFDD(sd, lp); + PrintLineFDD(sd, " ?\r\n"); + return TRUE; + } + return FALSE; +} + +/* + * Simple command shell thread, the argument is the serial line for the + * standard input and output. It recognizes few simple commands. + */ +static t_msg ShellThread(void *arg) { + FullDuplexDriver *sd = (FullDuplexDriver *)arg; + char *lp, line[64]; + Thread *tp; + BYTE8 tarea[UserStackSize(1024)]; + + chIQReset(&sd->sd_iqueue); + chOQReset(&sd->sd_oqueue); + PrintLineFDD(sd, "ChibiOS/RT Command Shell\r\n\n"); + while (TRUE) { + PrintLineFDD(sd, "ch> "); + if (GetLineFDD(sd, line, sizeof(line))) { + PrintLineFDD(sd, "\nlogout"); + break; + } + lp = strtok(line, " \009"); // Note: not thread safe but it is just a demo. + if (lp) { + if ((stricmp(lp, "help") == 0) || + (stricmp(lp, "h") == 0) || + (stricmp(lp, "?") == 0)) { + if (checkend(sd)) + continue; + PrintLineFDD(sd, "Commands:\r\n"); + PrintLineFDD(sd, " help,h,? - This help\r\n"); + PrintLineFDD(sd, " exit - Logout from ChibiOS/RT\r\n"); + PrintLineFDD(sd, " time - Prints the system timer value\r\n"); + PrintLineFDD(sd, " hello - Runs the Hello World demo thread\r\n"); + } + else if (stricmp(lp, "exit") == 0) { + if (checkend(sd)) + continue; + PrintLineFDD(sd, "\nlogout"); + break; + } + else if (stricmp(lp, "time") == 0) { + if (checkend(sd)) + continue; + sprintf(line, "Time: %d\r\n", chSysGetTime()); + PrintLineFDD(sd, line); + } + else if (stricmp(lp, "hello") == 0) { + if (checkend(sd)) + continue; + tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), + HelloWorldThread, sd); + if (chThdWait(tp)) + break; // Lost connection while executing the hello thread. + } + else { + PrintLineFDD(sd, lp); + PrintLineFDD(sd, " ?\r\n"); + } + } + } + return 0; +} + +static BYTE8 s1area[UserStackSize(4096)]; +static Thread *s1; +EventListener s1tel; + +static void COM1Handler(t_eventid id) { + t_dflags flags; + + if (s1 && chThdTerminated(s1)) { + s1 = NULL; + cprint("Init: disconnection on COM1\n"); + } + flags = chFDDGetAndClearFlags(&COM1); + if ((flags & SD_CONNECTED) && (s1 == NULL)) { + cprint("Init: connection on COM1\n"); + s1 = chThdCreate(NORMALPRIO, P_SUSPENDED, s1area, sizeof(s1area), + ShellThread, &COM1); + chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); + chThdResume(s1); + } + if ((flags & SD_DISCONNECTED) && (s1 != NULL)) + chIQReset(&COM1.sd_iqueue); +} + +static BYTE8 s2area[UserStackSize(4096)]; +static Thread *s2; +EventListener s2tel; + +static void COM2Handler(t_eventid id) { + t_dflags flags; + + if (s2 && chThdTerminated(s2)) { + s2 = NULL; + cprint("Init: disconnection on COM2\n"); + } + flags = chFDDGetAndClearFlags(&COM2); + if ((flags & SD_CONNECTED) && (s2 == NULL)) { + cprint("Init: connection on COM2\n"); + s2 = chThdCreate(NORMALPRIO, P_SUSPENDED, s2area, sizeof(s1area), + ShellThread, &COM2); + chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); + chThdResume(s2); + } + if ((flags & SD_DISCONNECTED) && (s2 != NULL)) + chIQReset(&COM2.sd_iqueue); +} + +static t_evhandler fhandlers[2] = { + COM1Handler, + COM2Handler +}; + +/* + * Init-like thread, it starts the shells and handles their termination. + * It is a good example of events usage. + */ +static t_msg InitThread(void *arg) { + EventListener c1fel, c2fel; + + cprint("Console service started on COM1, COM2\n"); + cprint(" - Listening for connections on COM1\n"); + chFDDGetAndClearFlags(&COM1); + chEvtRegister(&COM1.sd_sevent, &c1fel, 0); + cprint(" - Listening for connections on COM2\n"); + chFDDGetAndClearFlags(&COM2); + chEvtRegister(&COM2.sd_sevent, &c2fel, 1); + while (!chThdShouldTerminate()) + chEvtWait(ALL_EVENTS, fhandlers); + chEvtUnregister(&COM2.sd_sevent, &c2fel); // Never invoked but this is an example... + chEvtUnregister(&COM1.sd_sevent, &c1fel); // Never invoked but this is an example... + return 0; +} diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h new file mode 100644 index 000000000..13de9f457 --- /dev/null +++ b/demos/Win32-MinGW/chconf.h @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for MingGW32 demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/* + * NOTE: this is just documentation for doxigen, the real configuration file + * is the one into the project directories. + */ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Semaphores APIs with priority + * shift are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES.*/ +#define CH_USE_RT_SEMAPHORES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_TIMEOUT + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 100 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 10 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-\. + */ +//#define CH_CURRP_REGISTER_CACHE "reg" + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c new file mode 100644 index 000000000..d48188b49 --- /dev/null +++ b/demos/Win32-MinGW/chcore.c @@ -0,0 +1,105 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Core file for MingGW32 demo project. + */ + +#include +#include + +#undef CDECL + +#include + +static LARGE_INTEGER nextcnt; +static LARGE_INTEGER slice; + +void InitSimCom1(void); +void InitSimCom2(void); +BOOL Com1ConnInterruptSimCom(void); +BOOL Com2ConnInterruptSimCom(void); +BOOL Com1InInterruptSimCom(void); +BOOL Com2InInterruptSimCom(void); +BOOL Com1OutInterruptSimCom(void); +BOOL Com2OutInterruptSimCom(void); + +/* + * Simulated HW initialization. + */ +void InitCore(void) { + WSADATA wsaData; + + // Initialization. + if (WSAStartup(2, &wsaData) != 0) { + printf("Unable to locate a winsock DLL\n"); + exit(1); + } + + printf("Win32 ChobiOS/RT simulator\n\n"); + printf("Thread structure %d bytes\n", sizeof(Thread)); + if (!QueryPerformanceFrequency(&slice)) { + printf("QueryPerformanceFrequency() error"); + exit(1); + } + printf("Core Frequency %d Hz\n", (int)slice.LowPart); + slice.QuadPart /= CH_FREQUENCY; + QueryPerformanceCounter(&nextcnt); + nextcnt.QuadPart += slice.QuadPart; + + InitSimCom1(); + InitSimCom2(); +} + +/* + * Interrupt simulation. + */ +static void ChkIntSources(void) { + LARGE_INTEGER n; + + if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || + Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || + Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { + chSchRescheduleI(); + return; + } + + // Interrupt Timer simulation (10ms interval). + QueryPerformanceCounter(&n); + if (n.QuadPart > nextcnt.QuadPart) { + nextcnt.QuadPart += slice.QuadPart; + chSchTimerHandlerI(); + if (chSchRescRequiredI()) + chSchDoRescheduleI(); + } +} + +__attribute__((fastcall)) void chSysPause(void) { + + while (TRUE) { + + ChkIntSources(); + Sleep(0); + } +} + +__attribute__((fastcall)) void chSysHalt(void) { + + exit(2); +} diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h new file mode 100644 index 000000000..b8872c819 --- /dev/null +++ b/demos/Win32-MinGW/chcore.h @@ -0,0 +1,74 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Core file for MingGW32 demo project. + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +typedef void *regx86; + +/* + * Stack saved context. + */ +struct stackregs { + regx86 ebx; + regx86 edi; + regx86 esi; + regx86 ebp; + regx86 eip; +}; + +typedef struct { + struct stackregs *esp; +} Context; + +#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) + +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + BYTE8 *esp = (BYTE8 *)workspace + wsize; \ + APUSH(esp, arg); \ + APUSH(esp, threadstart); \ + esp -= sizeof(struct stackregs); \ + ((struct stackregs *)esp)->eip = pf; \ + ((struct stackregs *)esp)->ebx = 0; \ + ((struct stackregs *)esp)->edi = 0; \ + ((struct stackregs *)esp)->esi = 0; \ + ((struct stackregs *)esp)->ebp = 0; \ + tp->p_ctx.esp = (struct stackregs *)esp; \ +} + +#define chSysLock() + +#define chSysUnlock() + +#define INT_REQUIRED_STACK 0x0 + +#define UserStackSize(n) (sizeof(Thread) + sizeof(PTR_EQ) + sizeof(PTR_EQ) + \ + sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) + +__attribute__((fastcall)) void chSysHalt(void); +__attribute__((fastcall)) void chSysPause(void); +__attribute__((fastcall)) void chSysSwitchI(Context *oldp, Context *newp); +__attribute__((fastcall)) void threadstart(void); + +#endif /* _CHCORE_H_ */ diff --git a/demos/Win32-MinGW/chcore2.s b/demos/Win32-MinGW/chcore2.s new file mode 100644 index 000000000..80985e3f7 --- /dev/null +++ b/demos/Win32-MinGW/chcore2.s @@ -0,0 +1,43 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +.text + +.p2align 4,,15 +.globl @chSysSwitchI@8 +@chSysSwitchI@8: + # Switch out + push %ebp + push %esi + push %edi + push %ebx + movl %esp,(%ecx) + # Switch in + movl (%edx),%esp + pop %ebx + pop %edi + pop %esi + pop %ebp + ret + +.p2align 4,,15 +.globl @threadstart@0 +@threadstart@0: + push %ecx + call _chThdExit diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h new file mode 100644 index 000000000..48bf7a7d9 --- /dev/null +++ b/demos/Win32-MinGW/chtypes.h @@ -0,0 +1,52 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +/* + * Generic types often dependant on the compiler. + */ +#define BOOL char +#define BYTE8 unsigned char +#define WORD16 short +#define UWORD16 unsigned short +#define LONG32 int +#define ULONG32 unsigned int +#define PTR_EQ int + +typedef BYTE8 t_tmode; +typedef BYTE8 t_tstate; +typedef WORD16 t_prio; +typedef PTR_EQ t_msg; +typedef LONG32 t_eventid; +typedef ULONG32 t_eventmask; +typedef ULONG32 t_time; +typedef LONG32 t_semcnt; +typedef ULONG32 t_size; + +#define MINPRIO 0x8000 +#define MAXPRIO 0x7fff + +#define MINDELTA 0 +#define MAXDELTA 0xffff + +#define INLINE inline + +#endif /* _CHTYPES_H_ */ diff --git a/demos/Win32-MinGW/demo.c b/demos/Win32-MinGW/demo.c new file mode 100644 index 000000000..166923d2c --- /dev/null +++ b/demos/Win32-MinGW/demo.c @@ -0,0 +1,305 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include + +static ULONG32 wdguard; +static BYTE8 wdarea[UserStackSize(2048)]; + +static ULONG32 iguard; +static BYTE8 iarea[UserStackSize(2048)]; + +static ULONG32 cdguard; +static BYTE8 cdarea[UserStackSize(2048)]; +static Thread *cdtp; + +static t_msg WatchdogThread(void *arg); +static t_msg ConsoleThread(void *arg); +static t_msg InitThread(void *arg); + +void InitCore(void); +extern FullDuplexDriver COM1, COM2; + +#define cprint(msg) chMsgSend(cdtp, (t_msg)msg) + +/*------------------------------------------------------------------------* + * Simulator main, start here your threads, examples inside. * + *------------------------------------------------------------------------*/ +int main(void) { + + InitCore(); + + // Startup ChibiOS/RT. + chSysInit(); + chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); + cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); + chThdCreate(NORMALPRIO, 0, iarea, sizeof(iarea), InitThread, NULL); + chSysPause(); + return 0; +} + +/* + * Watchdog thread, it checks magic values located under the various stack + * areas. The system is halted if something is wrong. + */ +static t_msg WatchdogThread(void *arg) { + wdguard = 0xA51F2E3D; + iguard = 0xA51F2E3D; + cdguard = 0xA51F2E3D; + while (TRUE) { + + if ((wdguard != 0xA51F2E3D) || + (iguard != 0xA51F2E3D) || + (cdguard != 0xA51F2E3D)) { + printf("Halted by watchdog"); + chSysHalt(); + } + chThdSleep(5); + } + return 0; +} + +/* + * Console print server done using synchronous messages. This makes the access + * to the C printf() thread safe and the print operation atomic among threads. + * In this example the message is the zero termitated string itself. + */ +static t_msg ConsoleThread(void *arg) { + + while (!chThdShouldTerminate()) { + printf((char *)chMsgWait()); + chMsgRelease(RDY_OK); + } + return 0; +} + +static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { + + while (*msg) + chFDDPut(sd, *msg++); +} + +static BOOL GetLineFDD(FullDuplexDriver *sd, char *line, int size) { + char *p = line; + + while (TRUE) { + short c = chIQGet(&sd->sd_iqueue); + if (c < 0) + return TRUE; + if (c == 4) { + PrintLineFDD(sd, "^D\r\n"); + return TRUE; + } + if (c == 8) { + if (p != line) { + chFDDPut(sd, (BYTE8)c); + chFDDPut(sd, 0x20); + chFDDPut(sd, (BYTE8)c); + p--; + } + continue; + } + if (c == '\r') { + PrintLineFDD(sd, "\r\n"); + *p = 0; + return FALSE; + } + if (c < 0x20) + continue; + if (p < line + size - 1) { + chFDDPut(sd, (BYTE8)c); + *p++ = (BYTE8)c; + } + } +} + +/* + * Example thread, not much to see here. It simulates the CTRL-C but there + * are no real signals involved. + */ +static t_msg HelloWorldThread(void *arg) { + int i; + short c; + FullDuplexDriver *sd = (FullDuplexDriver *)arg; + + for (i = 0; i < 100; i++) { + + PrintLineFDD(sd, "Hello World\r\n"); + c = chFDDGetTimeout(sd, 33); + switch (c) { + case -1: + continue; + case -2: + return 1; + case 3: + PrintLineFDD(sd, "^C\r\n"); + return 0; + default: + chThdSleep(33); + } + } + return 0; +} + +static BOOL checkend(FullDuplexDriver *sd) { + + char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ + if (lp) { + PrintLineFDD(sd, lp); + PrintLineFDD(sd, " ?\r\n"); + return TRUE; + } + return FALSE; +} + +/* + * Simple command shell thread, the argument is the serial line for the + * standard input and output. It recognizes few simple commands. + */ +static t_msg ShellThread(void *arg) { + FullDuplexDriver *sd = (FullDuplexDriver *)arg; + char *lp, line[64]; + Thread *tp; + BYTE8 tarea[UserStackSize(1024)]; + + chIQReset(&sd->sd_iqueue); + chOQReset(&sd->sd_oqueue); + PrintLineFDD(sd, "ChibiOS/RT Command Shell\r\n\n"); + while (TRUE) { + PrintLineFDD(sd, "ch> "); + if (GetLineFDD(sd, line, sizeof(line))) { + PrintLineFDD(sd, "\nlogout"); + break; + } + lp = strtok(line, " \009"); // Note: not thread safe but it is just a demo. + if (lp) { + if ((stricmp(lp, "help") == 0) || + (stricmp(lp, "h") == 0) || + (stricmp(lp, "?") == 0)) { + if (checkend(sd)) + continue; + PrintLineFDD(sd, "Commands:\r\n"); + PrintLineFDD(sd, " help,h,? - This help\r\n"); + PrintLineFDD(sd, " exit - Logout from ChibiOS/RT\r\n"); + PrintLineFDD(sd, " time - Prints the system timer value\r\n"); + PrintLineFDD(sd, " hello - Runs the Hello World demo thread\r\n"); + } + else if (stricmp(lp, "exit") == 0) { + if (checkend(sd)) + continue; + PrintLineFDD(sd, "\nlogout"); + break; + } + else if (stricmp(lp, "time") == 0) { + if (checkend(sd)) + continue; + sprintf(line, "Time: %d\r\n", chSysGetTime()); + PrintLineFDD(sd, line); + } + else if (stricmp(lp, "hello") == 0) { + if (checkend(sd)) + continue; + tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), + HelloWorldThread, sd); + if (chThdWait(tp)) + break; // Lost connection while executing the hello thread. + } + else { + PrintLineFDD(sd, lp); + PrintLineFDD(sd, " ?\r\n"); + } + } + } + return 0; +} + +static BYTE8 s1area[UserStackSize(4096)]; +static Thread *s1; +EventListener s1tel; + +static void COM1Handler(t_eventid id) { + t_dflags flags; + + if (s1 && chThdTerminated(s1)) { + s1 = NULL; + cprint("Init: disconnection on COM1\n"); + } + flags = chFDDGetAndClearFlags(&COM1); + if ((flags & SD_CONNECTED) && (s1 == NULL)) { + cprint("Init: connection on COM1\n"); + s1 = chThdCreate(NORMALPRIO, P_SUSPENDED, s1area, sizeof(s1area), + ShellThread, &COM1); + chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); + chThdResume(s1); + } + if ((flags & SD_DISCONNECTED) && (s1 != NULL)) + chIQReset(&COM1.sd_iqueue); +} + +static BYTE8 s2area[UserStackSize(4096)]; +static Thread *s2; +EventListener s2tel; + +static void COM2Handler(t_eventid id) { + t_dflags flags; + + if (s2 && chThdTerminated(s2)) { + s2 = NULL; + cprint("Init: disconnection on COM2\n"); + } + flags = chFDDGetAndClearFlags(&COM2); + if ((flags & SD_CONNECTED) && (s2 == NULL)) { + cprint("Init: connection on COM2\n"); + s2 = chThdCreate(NORMALPRIO, P_SUSPENDED, s2area, sizeof(s1area), + ShellThread, &COM2); + chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); + chThdResume(s2); + } + if ((flags & SD_DISCONNECTED) && (s2 != NULL)) + chIQReset(&COM2.sd_iqueue); +} + +static t_evhandler fhandlers[2] = { + COM1Handler, + COM2Handler +}; + +/* + * Init-like thread, it starts the shells and handles their termination. + * It is a good example of events usage. + */ +static t_msg InitThread(void *arg) { + EventListener c1fel, c2fel; + + cprint("Console service started on COM1, COM2\n"); + cprint(" - Listening for connections on COM1\n"); + chFDDGetAndClearFlags(&COM1); + chEvtRegister(&COM1.sd_sevent, &c1fel, 0); + cprint(" - Listening for connections on COM2\n"); + chFDDGetAndClearFlags(&COM2); + chEvtRegister(&COM2.sd_sevent, &c2fel, 1); + while (!chThdShouldTerminate()) + chEvtWait(ALL_EVENTS, fhandlers); + chEvtUnregister(&COM2.sd_sevent, &c2fel); // Never invoked but this is an example... + chEvtUnregister(&COM1.sd_sevent, &c1fel); // Never invoked but this is an example... + return 0; +} diff --git a/demos/Win32-MinGW/makefile b/demos/Win32-MinGW/makefile new file mode 100644 index 000000000..b7dc8b024 --- /dev/null +++ b/demos/Win32-MinGW/makefile @@ -0,0 +1,129 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = mingw32- +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = -lws2_32 + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = chcore.c demo.c \ + ../../ports/win32/simcom.c \ + ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ + ../../src/chqueues.c ../../src/chserial.c + +# List ASM source files here +ASRC = chcore2.s + +# List all user directories here +UINCDIR = ../../src/include + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -Os -fomit-frame-pointer -fno-strict-aliasing + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).exe + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%exe: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).exe + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** -- cgit v1.2.3 From bd7b535e0633cf44ac25db3e9347b89e485545a8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 19 Sep 2007 17:03:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/readme.txt | 22 ++++++++++++++++++++++ demos/Win32-MSVS/readme.txt | 22 ++++++++++++++++++++++ demos/Win32-MinGW/readme.txt | 22 ++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 demos/LPC214x-GCC/readme.txt create mode 100644 demos/Win32-MSVS/readme.txt create mode 100644 demos/Win32-MinGW/readme.txt (limited to 'demos') diff --git a/demos/LPC214x-GCC/readme.txt b/demos/LPC214x-GCC/readme.txt new file mode 100644 index 000000000..c39f179d2 --- /dev/null +++ b/demos/LPC214x-GCC/readme.txt @@ -0,0 +1,22 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI LPC214X. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads. By pressing +the buttons on the board it is possible to activate the buzzer and send a +message over the serial ports. +See main.c for details. Buzzer.c contains an interesting device driver +example that uses a physical timer for the waveform generation and a virtual +timer for the sound duration. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/Win32-MSVS/readme.txt b/demos/Win32-MSVS/readme.txt new file mode 100644 index 000000000..6025e4879 --- /dev/null +++ b/demos/Win32-MSVS/readme.txt @@ -0,0 +1,22 @@ +***************************************************************************** +** ChibiOS/RT port for x86 into a Win32 process ** +***************************************************************************** + +** TARGET ** + +The demo runs under any Windows version as an application program. The serial +I/O is simulated over TCP/IP sockets. + +** The Demo ** + +The demo listens on the two serial ports, when a connection is detected a +thread is started that serves a small command shell. +The demo shows how create/terminate threads at runtime, how listen to events, +how ho work with serial ports, how use the messages. +You can develop your ChibiOS/RT application using this demo as a simulator +then you can recompile it for a different architecture. +See demo.c for details. + +** Build Procedure ** + +The demo was built using the Visual Studio 7, any later version should work. diff --git a/demos/Win32-MinGW/readme.txt b/demos/Win32-MinGW/readme.txt new file mode 100644 index 000000000..283ee42b2 --- /dev/null +++ b/demos/Win32-MinGW/readme.txt @@ -0,0 +1,22 @@ +***************************************************************************** +** ChibiOS/RT port for x86 into a Win32 process ** +***************************************************************************** + +** TARGET ** + +The demo runs under any Windows version as an application program. The serial +I/O is simulated over TCP/IP sockets. + +** The Demo ** + +The demo listens on the two serial ports, when a connection is detected a +thread is started that serves a small command shell. +The demo shows how create/terminate threads at runtime, how listen to events, +how ho work with serial ports, how use the messages. +You can develop your ChibiOS/RT application using this demo as a simulator +then you can recompile it for a different architecture. +See demo.c for details. + +** Build Procedure ** + +The demo was built using the MinGW toolchain. -- cgit v1.2.3 From f322242e43515d688fcb025eb8575f7b04558f45 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 21 Sep 2007 16:33:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/makefile | 156 -------------------------------------------- demos/LPC214x-GCC/makefile_ | 156 ++++++++++++++++++++++++++++++++++++++++++++ demos/Win32-MinGW/makefile | 129 ------------------------------------ demos/Win32-MinGW/makefile_ | 129 ++++++++++++++++++++++++++++++++++++ 4 files changed, 285 insertions(+), 285 deletions(-) delete mode 100644 demos/LPC214x-GCC/makefile create mode 100644 demos/LPC214x-GCC/makefile_ delete mode 100644 demos/Win32-MinGW/makefile create mode 100644 demos/Win32-MinGW/makefile_ (limited to 'demos') diff --git a/demos/LPC214x-GCC/makefile b/demos/LPC214x-GCC/makefile deleted file mode 100644 index b07f8360f..000000000 --- a/demos/LPC214x-GCC/makefile +++ /dev/null @@ -1,156 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List C source files here -SRC = chcore.c buzzer.c main.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ - ../../src/chqueues.c ../../src/chserial.c - -# List ASM source files here -ASRC = crt0.s chcore2.s - -# List all user directories here -UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -# NOTE: -mthumb-interwork increases the code size, remove it if you don't really need it. -# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. -#OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing -#OPT = -O0 -ggdb -fomit-frame-pointer -fno-strict-aliasing -OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - -# -# End of user defines -############################################################################################## - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -#ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -%elf: $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/LPC214x-GCC/makefile_ b/demos/LPC214x-GCC/makefile_ new file mode 100644 index 000000000..b07f8360f --- /dev/null +++ b/demos/LPC214x-GCC/makefile_ @@ -0,0 +1,156 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = chcore.c buzzer.c main.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ + ../../src/chqueues.c ../../src/chserial.c + +# List ASM source files here +ASRC = crt0.s chcore2.s + +# List all user directories here +UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +# NOTE: -mthumb-interwork increases the code size, remove it if you don't really need it. +# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. +#OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT = -O0 -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +#ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/Win32-MinGW/makefile b/demos/Win32-MinGW/makefile deleted file mode 100644 index b7dc8b024..000000000 --- a/demos/Win32-MinGW/makefile +++ /dev/null @@ -1,129 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = mingw32- -CC = $(TRGT)gcc -AS = $(TRGT)gcc -x assembler-with-cpp - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = -lws2_32 - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List C source files here -SRC = chcore.c demo.c \ - ../../ports/win32/simcom.c \ - ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ - ../../src/chqueues.c ../../src/chserial.c - -# List ASM source files here -ASRC = chcore2.s - -# List all user directories here -UINCDIR = ../../src/include - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -OPT = -Os -fomit-frame-pointer -fno-strict-aliasing - -# -# End of user defines -############################################################################################## - - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) - -LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT).exe - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -%exe: $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).exe - -rm -f $(PROJECT).map - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/Win32-MinGW/makefile_ b/demos/Win32-MinGW/makefile_ new file mode 100644 index 000000000..b7dc8b024 --- /dev/null +++ b/demos/Win32-MinGW/makefile_ @@ -0,0 +1,129 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = mingw32- +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = -lws2_32 + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = chcore.c demo.c \ + ../../ports/win32/simcom.c \ + ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ + ../../src/chqueues.c ../../src/chserial.c + +# List ASM source files here +ASRC = chcore2.s + +# List all user directories here +UINCDIR = ../../src/include + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -Os -fomit-frame-pointer -fno-strict-aliasing + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).exe + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%exe: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).exe + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** -- cgit v1.2.3 From 81c833b2db713bf998b4f60d480e41f19a3a486c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 21 Sep 2007 16:34:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/Makefile | 156 ++++++++++++++++++++++++++++++++++++++++++++ demos/LPC214x-GCC/makefile_ | 156 -------------------------------------------- demos/Win32-MinGW/Makefile | 129 ++++++++++++++++++++++++++++++++++++ demos/Win32-MinGW/makefile_ | 129 ------------------------------------ 4 files changed, 285 insertions(+), 285 deletions(-) create mode 100644 demos/LPC214x-GCC/Makefile delete mode 100644 demos/LPC214x-GCC/makefile_ create mode 100644 demos/Win32-MinGW/Makefile delete mode 100644 demos/Win32-MinGW/makefile_ (limited to 'demos') diff --git a/demos/LPC214x-GCC/Makefile b/demos/LPC214x-GCC/Makefile new file mode 100644 index 000000000..b07f8360f --- /dev/null +++ b/demos/LPC214x-GCC/Makefile @@ -0,0 +1,156 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = chcore.c buzzer.c main.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ + ../../src/chqueues.c ../../src/chserial.c + +# List ASM source files here +ASRC = crt0.s chcore2.s + +# List all user directories here +UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +# NOTE: -mthumb-interwork increases the code size, remove it if you don't really need it. +# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. +#OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT = -O0 -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +#ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/LPC214x-GCC/makefile_ b/demos/LPC214x-GCC/makefile_ deleted file mode 100644 index b07f8360f..000000000 --- a/demos/LPC214x-GCC/makefile_ +++ /dev/null @@ -1,156 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List C source files here -SRC = chcore.c buzzer.c main.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ - ../../src/chqueues.c ../../src/chserial.c - -# List ASM source files here -ASRC = crt0.s chcore2.s - -# List all user directories here -UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -# NOTE: -mthumb-interwork increases the code size, remove it if you don't really need it. -# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. -#OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing -#OPT = -O0 -ggdb -fomit-frame-pointer -fno-strict-aliasing -OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - -# -# End of user defines -############################################################################################## - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -#ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -%elf: $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile new file mode 100644 index 000000000..b7dc8b024 --- /dev/null +++ b/demos/Win32-MinGW/Makefile @@ -0,0 +1,129 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = mingw32- +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = -lws2_32 + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List C source files here +SRC = chcore.c demo.c \ + ../../ports/win32/simcom.c \ + ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ + ../../src/chqueues.c ../../src/chserial.c + +# List ASM source files here +ASRC = chcore2.s + +# List all user directories here +UINCDIR = ../../src/include + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -Os -fomit-frame-pointer -fno-strict-aliasing + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).exe + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%exe: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).exe + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/Win32-MinGW/makefile_ b/demos/Win32-MinGW/makefile_ deleted file mode 100644 index b7dc8b024..000000000 --- a/demos/Win32-MinGW/makefile_ +++ /dev/null @@ -1,129 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = mingw32- -CC = $(TRGT)gcc -AS = $(TRGT)gcc -x assembler-with-cpp - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = -lws2_32 - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List C source files here -SRC = chcore.c demo.c \ - ../../ports/win32/simcom.c \ - ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ - ../../src/chqueues.c ../../src/chserial.c - -# List ASM source files here -ASRC = chcore2.s - -# List all user directories here -UINCDIR = ../../src/include - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -OPT = -Os -fomit-frame-pointer -fno-strict-aliasing - -# -# End of user defines -############################################################################################## - - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) - -LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT).exe - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -%exe: $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).exe - -rm -f $(PROJECT).map - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** -- cgit v1.2.3 From cfdef89c7180aa2846afb0a96371dba87ee6714c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 22 Sep 2007 14:10:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@18 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/Makefile | 60 +++++++++++++++++++++++++++++++-------------- demos/LPC214x-GCC/chcore.h | 6 ++++- demos/LPC214x-GCC/chcore2.s | 26 +++++++++++++++++--- demos/LPC214x-GCC/main.c | 7 +++--- 4 files changed, 73 insertions(+), 26 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/Makefile b/demos/LPC214x-GCC/Makefile index b07f8360f..e96550727 100644 --- a/demos/LPC214x-GCC/Makefile +++ b/demos/LPC214x-GCC/Makefile @@ -61,15 +61,20 @@ UDEFS = # Define ASM defines here UADEFS = -# List C source files here -SRC = chcore.c buzzer.c main.c \ +# List ARM-mode C source files here +ASRC = chcore.c main.c buzzer.c \ ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ ../../src/chqueues.c ../../src/chserial.c +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = + # List ASM source files here -ASRC = crt0.s chcore2.s +ASMSRC = crt0.s chcore2.s # List all user directories here UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC @@ -80,12 +85,18 @@ ULIBDIR = # List all user libraries here ULIBS = -# Define optimisation level here -# NOTE: -mthumb-interwork increases the code size, remove it if you don't really need it. +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -mthumb-interwork increases the code size, remove it if you dont have +# Thumb code anywhere in the project. # NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. -#OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing -#OPT = -O0 -ggdb -fomit-frame-pointer -fno-strict-aliasing OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT += -ffixed-f7 # Define warning options here WARN = -Wall -Wstrict-prototypes @@ -98,33 +109,44 @@ INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) -#ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms +ifneq ($(TSRC),) + ASFLAGS += -mthumb-interwork -D THUMB_INTERWORK + CPFLAGS += -mthumb-interwork -D THUMB_INTERWORK + LDFLAGS += -mthumb-interwork +endif + # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d # -# makefile rules +# Makefile rules # all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ +$(AOBJS) : %.o : %.c + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ -%o : %s +$(ASMOBJS) : %.o : %.s $(AS) -c $(ASFLAGS) $< -o $@ %elf: $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ %hex: %elf $(HEX) $< $@ @@ -142,10 +164,12 @@ clean: -rm -f $(PROJECT).map -rm -f $(PROJECT).hex -rm -f $(PROJECT).bin - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) -rm -fR .dep # diff --git a/demos/LPC214x-GCC/chcore.h b/demos/LPC214x-GCC/chcore.h index 6dfdae6e9..bc49994ce 100644 --- a/demos/LPC214x-GCC/chcore.h +++ b/demos/LPC214x-GCC/chcore.h @@ -76,9 +76,13 @@ typedef struct { } #endif +#ifdef THUMB +extern void chSysLock(void); +extern void chSysUnlock(void); +#else /* !THUMB */ #define chSysLock() asm("msr CPSR_c, #0x9F") - #define chSysUnlock() asm("msr CPSR_c, #0x1F") +#endif /* THUMB */ #define INT_REQUIRED_STACK 0x40 // Must include registers and stack frames. diff --git a/demos/LPC214x-GCC/chcore2.s b/demos/LPC214x-GCC/chcore2.s index eec962655..f734eebba 100644 --- a/demos/LPC214x-GCC/chcore2.s +++ b/demos/LPC214x-GCC/chcore2.s @@ -55,21 +55,41 @@ DefIrqHandler: FiqHandler: b FiqHandler +#ifdef THUMB_INTERWORK +.globl chSysLock +chSysLock: + msr CPSR_c, #0x9F + bx lr + +.globl chSysUnlock +chSysUnlock: + msr CPSR_c, #0x1F + bx lr +#endif + .globl chSysSwitchI chSysSwitchI: -#ifdef MK_CURRP_REGISTER_CACHE +#ifdef CH_CURRP_REGISTER_CACHE stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} str sp, [r0, #0] ldr sp, [r1, #0] +#ifdef THUMB_INTERWORK ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - bx lr + bx lr +#else + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} +#endif #else stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} str sp, [r0, #0] ldr sp, [r1, #0] +#ifdef THUMB_INTERWORK ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - bx lr + bx lr +#else + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} #endif +#endif /* CH_CURRP_REGISTER_CACHE */ /* * System stack frame structure after a context switch in the diff --git a/demos/LPC214x-GCC/main.c b/demos/LPC214x-GCC/main.c index 94c68ed48..a696b223f 100644 --- a/demos/LPC214x-GCC/main.c +++ b/demos/LPC214x-GCC/main.c @@ -63,7 +63,6 @@ static t_msg Thread3(void *arg) { if (!(IO0PIN & 0x00010000)) // Button 2 chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); chThdSleep(500); - } return 0; } @@ -71,9 +70,9 @@ static t_msg Thread3(void *arg) { int main(int argc, char **argv) { chSysInit(); - chThdCreate(NORMALPRIO + 1, 0, waThread1, sizeof(waThread1), Thread1, NULL); - chThdCreate(NORMALPRIO + 1, 0, waThread2, sizeof(waThread2), Thread2, NULL); - chThdCreate(NORMALPRIO + 1, 0, waThread3, sizeof(waThread3), Thread3, NULL); + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); + chThdCreate(NORMALPRIO, 0, waThread3, sizeof(waThread3), Thread3, NULL); chSysPause(); return 0; } -- cgit v1.2.3 From f6c9ebb65b9a1239638125b7c1f910f12c722b79 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 25 Sep 2007 17:39:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@20 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/chconf.h | 8 ++++---- demos/LPC214x-GCC/chtypes.h | 2 +- demos/Win32-MSVS/chtypes.h | 2 +- demos/Win32-MinGW/chtypes.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/chconf.h b/demos/LPC214x-GCC/chconf.h index bb03058c8..30670c8fd 100644 --- a/demos/LPC214x-GCC/chconf.h +++ b/demos/LPC214x-GCC/chconf.h @@ -72,7 +72,7 @@ /** Configuration option: if specified then the Semaphores APIs with priority * shift are included in the kernel. * @note requires \p CH_USE_SEMAPHORES.*/ -//#define CH_USE_RT_SEMAPHORES +#define CH_USE_RT_SEMAPHORES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ @@ -82,7 +82,7 @@ * function is included in the kernel. * @note requires \p CH_USE_EVENTS. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -//#define CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ @@ -92,13 +92,13 @@ * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -//#define CH_USE_MESSAGES_TIMEOUT +#define CH_USE_MESSAGES_TIMEOUT /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -//#define CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. diff --git a/demos/LPC214x-GCC/chtypes.h b/demos/LPC214x-GCC/chtypes.h index 48bf7a7d9..49c7c6c38 100644 --- a/demos/LPC214x-GCC/chtypes.h +++ b/demos/LPC214x-GCC/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef WORD16 t_prio; +typedef LONG32 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; diff --git a/demos/Win32-MSVS/chtypes.h b/demos/Win32-MSVS/chtypes.h index 33eb4b963..f7d05b855 100644 --- a/demos/Win32-MSVS/chtypes.h +++ b/demos/Win32-MSVS/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef WORD16 t_prio; +typedef LONG32 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 48bf7a7d9..49c7c6c38 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef WORD16 t_prio; +typedef LONG32 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; -- cgit v1.2.3 From 619b739d93252f4fc78a98e1bd1c36e9edbbca28 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 25 Sep 2007 18:38:01 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@21 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/chconf.h | 8 ++++---- demos/LPC214x-GCC/chtypes.h | 2 +- demos/Win32-MSVS/chtypes.h | 2 +- demos/Win32-MinGW/chtypes.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/chconf.h b/demos/LPC214x-GCC/chconf.h index 30670c8fd..bb03058c8 100644 --- a/demos/LPC214x-GCC/chconf.h +++ b/demos/LPC214x-GCC/chconf.h @@ -72,7 +72,7 @@ /** Configuration option: if specified then the Semaphores APIs with priority * shift are included in the kernel. * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_RT_SEMAPHORES +//#define CH_USE_RT_SEMAPHORES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ @@ -82,7 +82,7 @@ * function is included in the kernel. * @note requires \p CH_USE_EVENTS. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_EVENTS_TIMEOUT +//#define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ @@ -92,13 +92,13 @@ * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_TIMEOUT +//#define CH_USE_MESSAGES_TIMEOUT /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_EVENT +//#define CH_USE_MESSAGES_EVENT /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. diff --git a/demos/LPC214x-GCC/chtypes.h b/demos/LPC214x-GCC/chtypes.h index 49c7c6c38..48bf7a7d9 100644 --- a/demos/LPC214x-GCC/chtypes.h +++ b/demos/LPC214x-GCC/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef LONG32 t_prio; +typedef WORD16 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; diff --git a/demos/Win32-MSVS/chtypes.h b/demos/Win32-MSVS/chtypes.h index f7d05b855..33eb4b963 100644 --- a/demos/Win32-MSVS/chtypes.h +++ b/demos/Win32-MSVS/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef LONG32 t_prio; +typedef WORD16 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 49c7c6c38..48bf7a7d9 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef LONG32 t_prio; +typedef WORD16 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; -- cgit v1.2.3 From 95b238fc867da32f28c74b98b793fbd40345b595 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 25 Sep 2007 18:41:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@23 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/chconf.h | 8 ++++---- demos/LPC214x-GCC/chtypes.h | 2 +- demos/Win32-MSVS/chtypes.h | 2 +- demos/Win32-MinGW/chtypes.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/chconf.h b/demos/LPC214x-GCC/chconf.h index bb03058c8..30670c8fd 100644 --- a/demos/LPC214x-GCC/chconf.h +++ b/demos/LPC214x-GCC/chconf.h @@ -72,7 +72,7 @@ /** Configuration option: if specified then the Semaphores APIs with priority * shift are included in the kernel. * @note requires \p CH_USE_SEMAPHORES.*/ -//#define CH_USE_RT_SEMAPHORES +#define CH_USE_RT_SEMAPHORES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ @@ -82,7 +82,7 @@ * function is included in the kernel. * @note requires \p CH_USE_EVENTS. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -//#define CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ @@ -92,13 +92,13 @@ * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -//#define CH_USE_MESSAGES_TIMEOUT +#define CH_USE_MESSAGES_TIMEOUT /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -//#define CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. diff --git a/demos/LPC214x-GCC/chtypes.h b/demos/LPC214x-GCC/chtypes.h index 48bf7a7d9..49c7c6c38 100644 --- a/demos/LPC214x-GCC/chtypes.h +++ b/demos/LPC214x-GCC/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef WORD16 t_prio; +typedef LONG32 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; diff --git a/demos/Win32-MSVS/chtypes.h b/demos/Win32-MSVS/chtypes.h index 33eb4b963..f7d05b855 100644 --- a/demos/Win32-MSVS/chtypes.h +++ b/demos/Win32-MSVS/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef WORD16 t_prio; +typedef LONG32 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 48bf7a7d9..49c7c6c38 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -33,7 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef WORD16 t_prio; +typedef LONG32 t_prio; typedef PTR_EQ t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; -- cgit v1.2.3 From 9a0ef300bce50901d5de3d6d722e29b79a2f9a36 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 28 Sep 2007 18:42:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@25 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/main.c b/demos/LPC214x-GCC/main.c index a696b223f..c925671e9 100644 --- a/demos/LPC214x-GCC/main.c +++ b/demos/LPC214x-GCC/main.c @@ -23,7 +23,7 @@ #include "lpc214x_serial.h" #include "buzzer.h" -static BYTE8 waThread1[UserStackSize(16)]; +static BYTE8 waThread1[UserStackSize(32)]; static t_msg Thread1(void *arg) { @@ -40,7 +40,7 @@ static t_msg Thread1(void *arg) { return 0; } -static BYTE8 waThread2[UserStackSize(16)]; +static BYTE8 waThread2[UserStackSize(32)]; static t_msg Thread2(void *arg) { @@ -53,7 +53,7 @@ static t_msg Thread2(void *arg) { return 0; } -static BYTE8 waThread3[UserStackSize(16)]; +static BYTE8 waThread3[UserStackSize(32)]; static t_msg Thread3(void *arg) { -- cgit v1.2.3 From 3a90ab685aaae59f242ae31260e67e9125ae78cd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Oct 2007 17:42:47 +0000 Subject: Preparation for AVR core support. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@27 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/Makefile | 8 ++++---- demos/LPC214x-GCC/chtypes.h | 14 ++++---------- demos/Win32-MSVS/chtypes.h | 14 ++++---------- demos/Win32-MinGW/Makefile | 6 +++--- demos/Win32-MinGW/chcore.h | 2 +- demos/Win32-MinGW/chtypes.h | 14 ++++---------- 6 files changed, 20 insertions(+), 38 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/Makefile b/demos/LPC214x-GCC/Makefile index e96550727..7f75b31b2 100644 --- a/demos/LPC214x-GCC/Makefile +++ b/demos/LPC214x-GCC/Makefile @@ -64,9 +64,9 @@ UADEFS = # List ARM-mode C source files here ASRC = chcore.c main.c buzzer.c \ ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ - ../../src/chqueues.c ../../src/chserial.c + ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ + ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ + ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is @@ -112,7 +112,7 @@ ADEFS = $(DADEFS) $(UADEFS) AOBJS = $(ASRC:.c=.o) TOBJS = $(TSRC:.c=.o) OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) +ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) diff --git a/demos/LPC214x-GCC/chtypes.h b/demos/LPC214x-GCC/chtypes.h index 49c7c6c38..803b5ead4 100644 --- a/demos/LPC214x-GCC/chtypes.h +++ b/demos/LPC214x-GCC/chtypes.h @@ -25,28 +25,22 @@ */ #define BOOL char #define BYTE8 unsigned char +#define SBYTE8 char #define WORD16 short #define UWORD16 unsigned short #define LONG32 int #define ULONG32 unsigned int -#define PTR_EQ int typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef LONG32 t_prio; -typedef PTR_EQ t_msg; +typedef ULONG32 t_prio; +typedef LONG32 t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; typedef ULONG32 t_time; -typedef LONG32 t_semcnt; +typedef LONG32 t_cnt; typedef ULONG32 t_size; -#define MINPRIO 0x8000 -#define MAXPRIO 0x7fff - -#define MINDELTA 0 -#define MAXDELTA 0xffff - #define INLINE inline #endif /* _CHTYPES_H_ */ diff --git a/demos/Win32-MSVS/chtypes.h b/demos/Win32-MSVS/chtypes.h index f7d05b855..6481c22a8 100644 --- a/demos/Win32-MSVS/chtypes.h +++ b/demos/Win32-MSVS/chtypes.h @@ -25,28 +25,22 @@ */ #define BOOL char #define BYTE8 unsigned char +#define SBYTE8 char #define WORD16 short #define UWORD16 unsigned short #define LONG32 int #define ULONG32 unsigned int -#define PTR_EQ int typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef LONG32 t_prio; -typedef PTR_EQ t_msg; +typedef ULONG32 t_prio; +typedef LONG32 t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; typedef ULONG32 t_time; -typedef LONG32 t_semcnt; +typedef LONG32 t_cnt; typedef ULONG32 t_size; -#define MINPRIO 0x8000 -#define MAXPRIO 0x7fff - -#define MINDELTA 0 -#define MAXDELTA 0xffff - #define INLINE __inline #endif /* _CHTYPES_H_ */ diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index b7dc8b024..4ab603d8e 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -58,9 +58,9 @@ UADEFS = # List C source files here SRC = chcore.c demo.c \ ../../ports/win32/simcom.c \ - ../../src/chinit.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c \ - ../../src/chqueues.c ../../src/chserial.c + ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ + ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ + ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c # List ASM source files here ASRC = chcore2.s diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index b8872c819..7f0021854 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -63,7 +63,7 @@ typedef struct { #define INT_REQUIRED_STACK 0x0 -#define UserStackSize(n) (sizeof(Thread) + sizeof(PTR_EQ) + sizeof(PTR_EQ) + \ +#define UserStackSize(n) (sizeof(Thread) + sizeof(void *) * 2 + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) __attribute__((fastcall)) void chSysHalt(void); diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 49c7c6c38..803b5ead4 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -25,28 +25,22 @@ */ #define BOOL char #define BYTE8 unsigned char +#define SBYTE8 char #define WORD16 short #define UWORD16 unsigned short #define LONG32 int #define ULONG32 unsigned int -#define PTR_EQ int typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; -typedef LONG32 t_prio; -typedef PTR_EQ t_msg; +typedef ULONG32 t_prio; +typedef LONG32 t_msg; typedef LONG32 t_eventid; typedef ULONG32 t_eventmask; typedef ULONG32 t_time; -typedef LONG32 t_semcnt; +typedef LONG32 t_cnt; typedef ULONG32 t_size; -#define MINPRIO 0x8000 -#define MAXPRIO 0x7fff - -#define MINDELTA 0 -#define MAXDELTA 0xffff - #define INLINE inline #endif /* _CHTYPES_H_ */ -- cgit v1.2.3 From 1b269aa139ba66288cc2c3f1b463c73821343262 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Oct 2007 16:52:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@29 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/chcore.h | 8 ++++++++ demos/Win32-MSVS/ch.vcproj | 6 ++++++ demos/Win32-MSVS/chcore.h | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/chcore.h b/demos/LPC214x-GCC/chcore.h index bc49994ce..b2091b686 100644 --- a/demos/LPC214x-GCC/chcore.h +++ b/demos/LPC214x-GCC/chcore.h @@ -20,6 +20,14 @@ #ifndef _CHCORE_H_ #define _CHCORE_H_ +/* + * The following values are implementation dependent. You may change them in + * order to match your HW. + */ +#define FOSC 12000000 +#define CCLK 48000000 +#define PCLK 12000000 + typedef void *regarm; /* diff --git a/demos/Win32-MSVS/ch.vcproj b/demos/Win32-MSVS/ch.vcproj index b1619033c..185e65dc1 100644 --- a/demos/Win32-MSVS/ch.vcproj +++ b/demos/Win32-MSVS/ch.vcproj @@ -150,6 +150,9 @@ + + @@ -205,6 +208,9 @@ + + diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h index 487dd175a..26e0b66bf 100644 --- a/demos/Win32-MSVS/chcore.h +++ b/demos/Win32-MSVS/chcore.h @@ -63,7 +63,7 @@ typedef struct { #define INT_REQUIRED_STACK 0x0 -#define UserStackSize(n) (sizeof(Thread) + sizeof(PTR_EQ) + sizeof(PTR_EQ) + \ +#define UserStackSize(n) (sizeof(Thread) + sizeof(void *)*2 + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) void __fastcall chSysHalt(void); -- cgit v1.2.3 From 2310f80695b4051cb63ca14878dfc5e76acb94e6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 3 Oct 2007 17:14:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@30 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/chconf.h | 4 ++++ demos/Win32-MSVS/ch.vcproj | 7 +++++++ demos/Win32-MSVS/chconf.h | 8 ++++++-- demos/Win32-MSVS/demo.c | 21 ++++++++++++++++----- demos/Win32-MinGW/Makefile | 2 +- demos/Win32-MinGW/chconf.h | 8 ++++++-- demos/Win32-MinGW/chcore.c | 2 +- demos/Win32-MinGW/chcore2.s | 2 +- demos/Win32-MinGW/demo.c | 17 ++++++++++++++--- 9 files changed, 56 insertions(+), 15 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/chconf.h b/demos/LPC214x-GCC/chconf.h index 30670c8fd..da8553399 100644 --- a/demos/LPC214x-GCC/chconf.h +++ b/demos/LPC214x-GCC/chconf.h @@ -63,6 +63,10 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/Win32-MSVS/ch.vcproj b/demos/Win32-MSVS/ch.vcproj index 185e65dc1..8764f059d 100644 --- a/demos/Win32-MSVS/ch.vcproj +++ b/demos/Win32-MSVS/ch.vcproj @@ -182,6 +182,13 @@ RelativePath="..\..\ports\Win32\simcom.c"> + + + + Date: Wed, 3 Oct 2007 18:18:58 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@31 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/Makefile | 2 +- demos/LPC214x-GCC/main.c | 19 +++++++++++++------ demos/LPC214x-GCC/readme.txt | 3 ++- 3 files changed, 16 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/LPC214x-GCC/Makefile b/demos/LPC214x-GCC/Makefile index 7f75b31b2..8400d8f82 100644 --- a/demos/LPC214x-GCC/Makefile +++ b/demos/LPC214x-GCC/Makefile @@ -63,7 +63,7 @@ UADEFS = # List ARM-mode C source files here ASRC = chcore.c main.c buzzer.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../test/test.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c diff --git a/demos/LPC214x-GCC/main.c b/demos/LPC214x-GCC/main.c index c925671e9..0183b276b 100644 --- a/demos/LPC214x-GCC/main.c +++ b/demos/LPC214x-GCC/main.c @@ -53,15 +53,22 @@ static t_msg Thread2(void *arg) { return 0; } -static BYTE8 waThread3[UserStackSize(32)]; +static BYTE8 waThread3[UserStackSize(64)]; static t_msg Thread3(void *arg) { - + t_msg TestThread(void *p); + while (TRUE) { - if (!(IO0PIN & 0x00008000)) // Button 1 - PlaySound(1000, 100); - if (!(IO0PIN & 0x00010000)) // Button 2 - chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + if (!(IO0PIN & 0x00018000)) { + TestThread(&COM1); + PlaySound(500, 100); + } + else { + if (!(IO0PIN & 0x00008000)) // Button 1 + PlaySound(1000, 100); + if (!(IO0PIN & 0x00010000)) // Button 2 + chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + } chThdSleep(500); } return 0; diff --git a/demos/LPC214x-GCC/readme.txt b/demos/LPC214x-GCC/readme.txt index c39f179d2..f55f5b4c6 100644 --- a/demos/LPC214x-GCC/readme.txt +++ b/demos/LPC214x-GCC/readme.txt @@ -11,7 +11,8 @@ members of the LPC2000 family should be an easy task. The demo blinks the leds on the board by using multiple threads. By pressing the buttons on the board it is possible to activate the buzzer and send a -message over the serial ports. +message over the serial ports. Pressing both buttons activates the test +procedure on the serial port 1. See main.c for details. Buzzer.c contains an interesting device driver example that uses a physical timer for the waveform generation and a virtual timer for the sound duration. -- cgit v1.2.3 From f44731e0c0a0e36d676b061f52ff9a2c54030393 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 4 Oct 2007 17:39:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@35 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 180 ++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/buzzer.c | 82 ++++++++++++++ demos/ARM7-LPC214x-GCC/buzzer.h | 28 +++++ demos/ARM7-LPC214x-GCC/ch.ld | 85 ++++++++++++++ demos/ARM7-LPC214x-GCC/chconf.h | 157 ++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/chcore.c | 225 ++++++++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/chcore.h | 110 +++++++++++++++++++ demos/ARM7-LPC214x-GCC/chcore2.s | 188 +++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/chtypes.h | 46 ++++++++ demos/ARM7-LPC214x-GCC/crt0.s | 146 +++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/main.c | 85 ++++++++++++++ demos/ARM7-LPC214x-GCC/readme.txt | 23 ++++ 12 files changed, 1355 insertions(+) create mode 100644 demos/ARM7-LPC214x-GCC/Makefile create mode 100644 demos/ARM7-LPC214x-GCC/buzzer.c create mode 100644 demos/ARM7-LPC214x-GCC/buzzer.h create mode 100644 demos/ARM7-LPC214x-GCC/ch.ld create mode 100644 demos/ARM7-LPC214x-GCC/chconf.h create mode 100644 demos/ARM7-LPC214x-GCC/chcore.c create mode 100644 demos/ARM7-LPC214x-GCC/chcore.h create mode 100644 demos/ARM7-LPC214x-GCC/chcore2.s create mode 100644 demos/ARM7-LPC214x-GCC/chtypes.h create mode 100644 demos/ARM7-LPC214x-GCC/crt0.s create mode 100644 demos/ARM7-LPC214x-GCC/main.c create mode 100644 demos/ARM7-LPC214x-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile new file mode 100644 index 000000000..8400d8f82 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -0,0 +1,180 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +ASRC = chcore.c main.c buzzer.c \ + ../../test/test.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ + ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ + ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = + +# List ASM source files here +ASMSRC = crt0.s chcore2.s + +# List all user directories here +UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -mthumb-interwork increases the code size, remove it if you dont have +# Thumb code anywhere in the project. +# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. +OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT += -ffixed-f7 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +ifneq ($(TSRC),) + ASFLAGS += -mthumb-interwork -D THUMB_INTERWORK + CPFLAGS += -mthumb-interwork -D THUMB_INTERWORK + LDFLAGS += -mthumb-interwork +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c new file mode 100644 index 000000000..4700bfb45 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Buzzer driver for Olimex LPC-P2148. + * Uses the timer 1 for wave generation and a Virtual Timer for the sound + * duration. + * The driver also generates an event when the sound is done and the buzzer + * goes silent. + */ +#include + +#include "lpc214x.h" +#include "buzzer.h" + +EventSource BuzzerSilentEventSource; + +#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1) +#define StopCounter(t) ((t)->TC_EMR = 0, (t)->TC_TCR = 2) + +void InitBuzzer(void) { + + chEvtInit(&BuzzerSilentEventSource); + + /* + * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions. + * Enables Timer1 clock. + */ + PINSEL0 &= 0xF0FFFFFF; + PINSEL0 |= 0x0A000000; + PCONP = (PCONP & PCALL) | PCTIM1; + + /* + * Timer setup. + */ + TC *tc = T1Base; + StopCounter(tc); + tc->TC_CTCR = 0; // Clock source is PCLK. + tc->TC_PR = 0; // Prescaler disabled. + tc->TC_MCR = 2; // Clear TC on match MR0. +} + +static void stop(void *p) { + TC *tc = T1Base; + + StopCounter(tc); + chEvtSendI(&BuzzerSilentEventSource); +} + +void PlaySound(int freq, t_time duration) { + static VirtualTimer bvt; + TC *tc = T1Base; + + chSysLock(); + + if (bvt.vt_func) { // If a sound is already being played + chVTResetI(&bvt); // then aborts it. + StopCounter(tc); + } + + tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); + StartCounter(tc); + chVTSetI(&bvt, duration, stop, NULL); + + chSysUnlock(); +} diff --git a/demos/ARM7-LPC214x-GCC/buzzer.h b/demos/ARM7-LPC214x-GCC/buzzer.h new file mode 100644 index 000000000..3334d8b5c --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/buzzer.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BUZZER_H_ +#define _BUZZER_H_ + +void InitBuzzer(void); +void PlaySound(int freq, t_time duration); + +extern EventSource BuzzerSilentEventSource; + +#endif /* _BUZZER_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld new file mode 100644 index 000000000..6ce8a0b32 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -0,0 +1,85 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0080; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : + { + _text = .; + *(.text); + *(.rodata); + *(.rodata*); + *(.glue_7t); + *(.glue_7); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h new file mode 100644 index 000000000..da8553399 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Semaphores APIs with priority + * shift are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES.*/ +#define CH_USE_RT_SEMAPHORES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_TIMEOUT + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c new file mode 100644 index 000000000..3d72c20db --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -0,0 +1,225 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "lpc214x_serial.h" +#include "buzzer.h" + +extern void IrqHandler(void); +extern void T0IrqHandler(void); + +#define VAL_TC0_PRESCALER 0 + +/* + * Pins configuration for Olimex LPC-P2148. + * + * PINSEL0 + * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD + * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 + * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 + * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- + * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + * + * PINSEL1 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 SSE MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 L1 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 10 10 10 10 00 + * OUT -- OUT OUT -- -- -- -- -- OUT OUT -- -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 + * + * PINSEL2 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- + * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- + */ +#define VAL_PINSEL0 0x00055555 +#define VAL_PINSEL1 0x100842A8 +#define VAL_PINSEL2 0x00000004 +#define VAL_FIO0DIR 0xB0603C00 +#define VAL_FIO1DIR 0x00000000 + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { + int i; + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLLBase; + pll->PLL0_CFG = 0x23; /* P and M values. */ + pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + while (!(pll->PLL0_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL0_CON = 0x3; /* Connects the PLL. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; + + /* + * I/O pins configuration. + */ + PINSEL0 = VAL_PINSEL0; + PINSEL1 = VAL_PINSEL1; + PINSEL2 = VAL_PINSEL2; + IO0DIR = VAL_FIO0DIR; + IO0SET = 0xFFFFFFFF; + IO1DIR = VAL_FIO1DIR; + IO1SET = 0xFFFFFFFF; + + /* + * Interrupt vectors assignment. + * NOTE: Better reset everything in the VIC, it is a HUGE source of trouble. + */ + VIC *vic = VICBase; + vic->VIC_IntSelect = 0; + vic->VIC_IntEnable = 0; + vic->VIC_VectAddr = 0; + for (i = 0; i < 16; i++) { + vic->VIC_VectCntls[i] = 0; + vic->VIC_VectAddrs[i] = 0; + } + vic->VIC_DefVectAddr = (IOREG32)IrqHandler; + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); + SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); + SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); + + /* + * System Timer initialization, 1ms intervals. + */ + vic->VIC_IntEnable |= INTMASK(SOURCE_Timer0); + TC *timer = T0Base; + timer->TC_PR = VAL_TC0_PRESCALER; + timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); + timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ + timer->TC_TCR = 2; /* Reset counter and prescaler. */ + timer->TC_TCR = 1; /* Timer enabled. */ + + /* + * Other subsystems. + */ + InitSerial(); + InitBuzzer(); +} + +void chSysPause(void) { + + while (TRUE) { +// Note, it is disabled because it causes trouble with the JTAG probe. +// Enable it in the final code only. +// PCON = 1; /* Stops CPU clock until next interrupt. */ + } +} + +/* + * System halt. + * Yellow LED only. + */ +void chSysHalt(void) { + + chSysLock(); + IO0SET = 0x80000C00; + IO0CLR = 0x80000000; + while (TRUE) + ; +} + +/* + * Set a vector for an interrupt source, the vector is enabled too. + */ +void SetVICVector(void *handler, int vector, int source) { + + VIC *vicp = VICBase; + vicp->VIC_VectAddrs[vector] = (IOREG32)handler; + vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20); +} + +/* + * Undefined Instruction exception handler. + * Yellow LED + RED LED 2. + */ +void UndHandler(void) { + IO0SET = 0x80000C00; + IO0CLR = 0x80000800; + while(TRUE) + ; +} + +/* + * Prefetch exception handler. + * Yellow LED + RED LED 1. + */ +void PrefetchHandler(void) { + IO0SET = 0x80000C00; + IO0CLR = 0x80000400; + while(TRUE) + ; +} + +/* + * Abort exception handler. + * Yellow LED + both RED LEDs. + */ +void AbortHandler(void) { + IO0SET = 0x80000C00; + IO0CLR = 0x80000C00; + while(TRUE) + ; +} + +/* + * Non-vectored IRQs handling here. + */ +void NonVectoredIrq(void) { + VICVectAddr = 0; +} + +/* + * Timer 0 IRQ handling here. + */ +void Timer0Irq(void) { + chSchTimerHandlerI(); + T0IR = 1; /* Clear interrupt on match MR0. */ + VICVectAddr = 0; +} diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h new file mode 100644 index 000000000..b2091b686 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/* + * The following values are implementation dependent. You may change them in + * order to match your HW. + */ +#define FOSC 12000000 +#define CCLK 48000000 +#define PCLK 12000000 + +typedef void *regarm; + +/* + * Stack saved context. + */ +struct stackregs { + regarm r4; + regarm r5; + regarm r6; +#ifndef MK_CURRP_REGISTER_CACHE + regarm r7; +#endif + regarm r8; + regarm r9; + regarm r10; + regarm r11; + regarm lr; +}; + +typedef struct { + struct stackregs *r13; +} Context; + +#ifdef MK_CURRP_REGISTER_CACHE +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct stackregs)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->r6 = 0; \ + tp->p_ctx.r13->r8 = 0; \ + tp->p_ctx.r13->r9 = 0; \ + tp->p_ctx.r13->r10 = 0; \ + tp->p_ctx.r13->r11 = 0; \ + tp->p_ctx.r13->lr = threadstart; \ +} +#else +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct stackregs)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->r6 = 0; \ + tp->p_ctx.r13->r7 = 0; \ + tp->p_ctx.r13->r8 = 0; \ + tp->p_ctx.r13->r9 = 0; \ + tp->p_ctx.r13->r10 = 0; \ + tp->p_ctx.r13->r11 = 0; \ + tp->p_ctx.r13->lr = threadstart; \ +} +#endif + +#ifdef THUMB +extern void chSysLock(void); +extern void chSysUnlock(void); +#else /* !THUMB */ +#define chSysLock() asm("msr CPSR_c, #0x9F") +#define chSysUnlock() asm("msr CPSR_c, #0x1F") +#endif /* THUMB */ + +#define INT_REQUIRED_STACK 0x40 // Must include registers and stack frames. + +#define UserStackSize(n) (sizeof(Thread) + \ + sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) + +void chSysHalt(void) __attribute__((noreturn)); +void chSysPause(void); +void chSysSwitchI(Context *oldp, Context *newp); +void threadstart(void); +void DefFiqHandler(void); +void DefIrqHandler(void); +void SpuriousHandler(void); + +void SetVICVector(void *handler, int vector, int source); + +#endif /* _CHCORE_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s new file mode 100644 index 000000000..f734eebba --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -0,0 +1,188 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "chconf.h" + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text +.code 32 +.balign 4 + +.globl threadstart +threadstart: + msr CPSR_c, #MODE_SYS + mov r0, r5 +/* blx r4*/ + mov lr, pc + bx r4 + bl chThdExit + +.globl SwiHandler +SwiHandler: + b SwiHandler + +.globl DefIrqHandler +DefIrqHandler: + b DefIrqHandler + +.globl FiqHandler +FiqHandler: + b FiqHandler + +#ifdef THUMB_INTERWORK +.globl chSysLock +chSysLock: + msr CPSR_c, #0x9F + bx lr + +.globl chSysUnlock +chSysUnlock: + msr CPSR_c, #0x1F + bx lr +#endif + +.globl chSysSwitchI +chSysSwitchI: +#ifdef CH_CURRP_REGISTER_CACHE + stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] +#ifdef THUMB_INTERWORK + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + bx lr +#else + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} +#endif +#else + stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] +#ifdef THUMB_INTERWORK + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + bx lr +#else + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} +#endif +#endif /* CH_CURRP_REGISTER_CACHE */ + +/* + * System stack frame structure after a context switch in the + * interrupt handler: + * + * High +------------+ + * | R12 | -+ + * | R3 | | + * | R2 | | + * | R1 | | External context: IRQ handler frame + * | R0 | | + * | LR_IRQ | | (user code return address) + * | SPSR | -+ (user code status) + * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space + * | LR | -+ (system code return address) + * | R11 | | + * | R10 | | + * | R9 | | + * | R8 | | Internal context: mk_SwitchI() frame + * | (R7) | | (optional, see MK_CURRP_REGISTER_CACHE) + * | R6 | | + * | R5 | | + * SP-> | R4 | -+ + * Low +------------+ + */ +.globl IrqHandler +IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc} + bl NonVectoredIrq + b IrqCommon + +.globl T0IrqHandler +T0IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc}^ + bl Timer0Irq + b IrqCommon + +.globl UART0IrqHandler +UART0IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc}^ + bl UART0Irq + b IrqCommon + +.globl UART1IrqHandler +UART1IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc}^ + bl UART1Irq + b IrqCommon + +/* + * Common exit point for all IRQ routines, it performs the rescheduling if + * required. + */ +IrqCommon: + bl chSchRescRequiredI + cmp r0, #0 // Simply returns if a + ldmeqfd sp!, {r0-r3, r12, pc}^ // reschedule is not required. + + // Saves the IRQ mode registers in the system stack. + ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0-r3, r12} // Registers on System Stack. + msr CPSR_c, #MODE_IRQ | I_BIT + mrs r0, SPSR + mov r1, lr + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. + + // Context switch. + bl chSchDoRescheduleI + + // Re-establish the IRQ conditions again. + ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. + msr CPSR_c, #MODE_IRQ | I_BIT + msr SPSR_fsxc, r0 + mov lr, r1 + msr CPSR_c, #MODE_SYS | I_BIT + ldmfd sp!, {r0-r3, r12} + msr CPSR_c, #MODE_IRQ | I_BIT + subs pc, lr, #0 diff --git a/demos/ARM7-LPC214x-GCC/chtypes.h b/demos/ARM7-LPC214x-GCC/chtypes.h new file mode 100644 index 000000000..803b5ead4 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/chtypes.h @@ -0,0 +1,46 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +/* + * Generic types often dependant on the compiler. + */ +#define BOOL char +#define BYTE8 unsigned char +#define SBYTE8 char +#define WORD16 short +#define UWORD16 unsigned short +#define LONG32 int +#define ULONG32 unsigned int + +typedef BYTE8 t_tmode; +typedef BYTE8 t_tstate; +typedef ULONG32 t_prio; +typedef LONG32 t_msg; +typedef LONG32 t_eventid; +typedef ULONG32 t_eventmask; +typedef ULONG32 t_time; +typedef LONG32 t_cnt; +typedef ULONG32 t_size; + +#define INLINE inline + +#endif /* _CHTYPES_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/crt0.s b/demos/ARM7-LPC214x-GCC/crt0.s new file mode 100644 index 000000000..9b413191b --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/crt0.s @@ -0,0 +1,146 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Generic ARM startup file for ChibiOS/RT. + */ + +.extern _main + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text +.code 32 +.balign 4 +/* + * System entry points. + */ +_start: + b ResetHandler + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ + ldr pc, _fiq + +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler +_fiq: + .word FiqHandler + .word 0 + .word 0 + +/* + * Reset handler. + */ +ResetHandler: + /* + * Stack pointers initialization. + */ + ldr r0, =__ram_end__ + /* Undefined */ + msr CPSR_c, #MODE_UND | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__und_stack_size__ + sub r0, r0, r1 + /* Abort */ + msr CPSR_c, #MODE_ABT | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__abt_stack_size__ + sub r0, r0, r1 + /* FIQ */ + msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__fiq_stack_size__ + sub r0, r0, r1 + /* IRQ */ + msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__irq_stack_size__ + sub r0, r0, r1 + /* Supervisor */ + msr CPSR_c, #MODE_SVC | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__svc_stack_size__ + sub r0, r0, r1 + /* System */ + msr CPSR_c, #MODE_SYS | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__sys_stack_size__ + sub r0, r0, r1 + /* + * Check on allocated stacks size. This should never happen unless you + * don't care to verify the map file after compiling your application. + */ + ldr r1, =_bss_end + cmp r0, r1 + bge ramsizeok + bl chSysHalt +ramsizeok: + /* + * Data initialization. + * NOTE: It assumes that the DATA size is a multiple of 4. + */ + ldr r1, =_textdata + ldr r2, =_data + ldr r3, =_edata +dataloop: + cmp r2, r3 + ldrlo r0, [r1], #4 + strlo r0, [r2], #4 + blo dataloop + /* + * BSS initialization. + * NOTE: It assumes that the BSS size is a multiple of 4. + */ + mov r0, #0 + ldr r1, =_bss_start + ldr r2, =_bss_end +bssloop: + cmp r1, r2 + strlo r0, [r1], #4 + blo bssloop + /* + * Application-provided HW initialization routine. + */ + bl hwinit + /* + * main(0, NULL). + */ + mov r0, #0 + mov r1, #0 + bl main + bl chSysHalt diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c new file mode 100644 index 000000000..0183b276b --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -0,0 +1,85 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "lpc214x_serial.h" +#include "buzzer.h" + +static BYTE8 waThread1[UserStackSize(32)]; + +static t_msg Thread1(void *arg) { + + while (TRUE) { + IO0CLR = 0x00000800; + chThdSleep(200); + IO0SET = 0x00000C00; + chThdSleep(800); + IO0CLR = 0x00000400; + chThdSleep(200); + IO0SET = 0x00000C00; + chThdSleep(800); + } + return 0; +} + +static BYTE8 waThread2[UserStackSize(32)]; + +static t_msg Thread2(void *arg) { + + while (TRUE) { + IO0CLR = 0x80000000; + chThdSleep(200); + IO0SET = 0x80000000; + chThdSleep(300); + } + return 0; +} + +static BYTE8 waThread3[UserStackSize(64)]; + +static t_msg Thread3(void *arg) { + t_msg TestThread(void *p); + + while (TRUE) { + if (!(IO0PIN & 0x00018000)) { + TestThread(&COM1); + PlaySound(500, 100); + } + else { + if (!(IO0PIN & 0x00008000)) // Button 1 + PlaySound(1000, 100); + if (!(IO0PIN & 0x00010000)) // Button 2 + chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + } + chThdSleep(500); + } + return 0; +} + +int main(int argc, char **argv) { + + chSysInit(); + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); + chThdCreate(NORMALPRIO, 0, waThread3, sizeof(waThread3), Thread3, NULL); + chSysPause(); + return 0; +} diff --git a/demos/ARM7-LPC214x-GCC/readme.txt b/demos/ARM7-LPC214x-GCC/readme.txt new file mode 100644 index 000000000..f55f5b4c6 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/readme.txt @@ -0,0 +1,23 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI LPC214X. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads. By pressing +the buttons on the board it is possible to activate the buzzer and send a +message over the serial ports. Pressing both buttons activates the test +procedure on the serial port 1. +See main.c for details. Buzzer.c contains an interesting device driver +example that uses a physical timer for the waveform generation and a virtual +timer for the sound duration. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. -- cgit v1.2.3 From f1df31b81779b51f63ab50c855b6a655289bd732 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 4 Oct 2007 17:39:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@36 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/Makefile | 627 +++++++++++++++++++++++++++++++++++++++ demos/AVR-AT90CANx-GCC/chconf.h | 158 ++++++++++ demos/AVR-AT90CANx-GCC/chcore.c | 26 ++ demos/AVR-AT90CANx-GCC/chcore.h | 106 +++++++ demos/AVR-AT90CANx-GCC/chcore2.S | 124 ++++++++ demos/AVR-AT90CANx-GCC/chtypes.h | 47 +++ demos/AVR-AT90CANx-GCC/main.c | 38 +++ 7 files changed, 1126 insertions(+) create mode 100644 demos/AVR-AT90CANx-GCC/Makefile create mode 100644 demos/AVR-AT90CANx-GCC/chconf.h create mode 100644 demos/AVR-AT90CANx-GCC/chcore.c create mode 100644 demos/AVR-AT90CANx-GCC/chcore.h create mode 100644 demos/AVR-AT90CANx-GCC/chcore2.S create mode 100644 demos/AVR-AT90CANx-GCC/chtypes.h create mode 100644 demos/AVR-AT90CANx-GCC/main.c (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile new file mode 100644 index 000000000..b65fb4a74 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -0,0 +1,627 @@ +# Hey Emacs, this is a -*- makefile -*- +#---------------------------------------------------------------------------- +# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al. +# +# Released to the Public Domain +# +# Additional material for this makefile was written by: +# Peter Fleury +# Tim Henigan +# Colin O'Flynn +# Reiner Patommel +# Markus Pfaff +# Sander Pool +# Frederik Rouleau +# Carlos Lamas +# +#---------------------------------------------------------------------------- +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make coff = Convert ELF to AVR COFF. +# +# make extcoff = Convert ELF to AVR Extended COFF. +# +# make program = Download the hex file to the device, using avrdude. +# Please customize the avrdude settings below first! +# +# make debug = Start either simulavr or avarice as specified for debugging, +# with avr-gdb or avr-insight as the front end for debugging. +# +# make filename.s = Just compile filename.c into the assembler code only. +# +# make filename.i = Create a preprocessed source file for use in submitting +# bug reports to the GCC project. +# +# To rebuild project do "make clean" then "make all". +#---------------------------------------------------------------------------- + + +# MCU name +MCU = at90can128 + + +# Processor frequency. +# This will define a symbol, F_CPU, in all source code files equal to the +# processor frequency. You can then use this symbol in your source code to +# calculate timings. Do NOT tack on a 'UL' at the end, this will be done +# automatically to create a 32-bit value in your source code. +# Typical values are: +# F_CPU = 1000000 +# F_CPU = 1843200 +# F_CPU = 2000000 +# F_CPU = 3686400 +# F_CPU = 4000000 +# F_CPU = 7372800 +# F_CPU = 8000000 +# F_CPU = 11059200 +# F_CPU = 14745600 +# F_CPU = 16000000 +# F_CPU = 18432000 +# F_CPU = 20000000 +F_CPU = 16000000 + + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + + +# Target file name (without extension). +TARGET = ch + + +# Object files directory +# To put object files in current directory, use a dot (.), do NOT make +# this an empty or blank macro! +OBJDIR = . + + +# List C source files here. (C dependencies are automatically generated.) +SRC = ./main.c ./chcore.c ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c + + + +# List C++ source files here. (C dependencies are automatically generated.) +CPPSRC = + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = ./chcore2.S + + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = s + + +# Debugging format. +# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. +# AVR Studio 4.10 requires dwarf-2. +# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run. +DEBUG = dwarf-2 + + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRAINCDIRS = ../../src/include + + +# Compiler flag to set the C Standard level. +# c89 = "ANSI" C +# gnu89 = c89 plus GCC extensions +# c99 = ISO C99 standard (not yet fully implemented) +# gnu99 = c99 plus GCC extensions +CSTANDARD = -std=gnu99 + + +# Place -D or -U options here for C sources +CDEFS = -DF_CPU=$(F_CPU)UL + + +# Place -D or -U options here for ASM sources +ADEFS = -DF_CPU=$(F_CPU) + + +# Place -D or -U options here for C++ sources +CPPDEFS = -DF_CPU=$(F_CPU)UL +#CPPDEFS += -D__STDC_LIMIT_MACROS +#CPPDEFS += -D__STDC_CONSTANT_MACROS + + + +#---------------- Compiler Options C ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) +CFLAGS += -O$(OPT) +CFLAGS += -funsigned-char +CFLAGS += -funsigned-bitfields +CFLAGS += -fpack-struct +CFLAGS += -fshort-enums +CFLAGS += -fno-strict-aliasing +CFLAGS += -Wall +CFLAGS += -Wstrict-prototypes +#CFLAGS += -mshort-calls +#CFLAGS += -fno-unit-at-a-time +#CFLAGS += -Wundef +#CFLAGS += -Wunreachable-code +#CFLAGS += -Wsign-compare +CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +CFLAGS += $(CSTANDARD) + + +#---------------- Compiler Options C++ ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CPPFLAGS = -g$(DEBUG) +CPPFLAGS += $(CPPDEFS) +CPPFLAGS += -O$(OPT) +CPPFLAGS += -funsigned-char +CPPFLAGS += -funsigned-bitfields +CPPFLAGS += -fpack-struct +CPPFLAGS += -fshort-enums +CPPFLAGS += -fno-exceptions +CPPFLAGS += -Wall +CFLAGS += -Wundef +#CPPFLAGS += -mshort-calls +#CPPFLAGS += -fno-unit-at-a-time +#CPPFLAGS += -Wstrict-prototypes +#CPPFLAGS += -Wunreachable-code +#CPPFLAGS += -Wsign-compare +CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst) +CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +#CPPFLAGS += $(CSTANDARD) + + +#---------------- Assembler Options ---------------- +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +# -listing-cont-lines: Sets the maximum number of continuation lines of hex +# dump that will be displayed for a given single line of source input. +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100 + + +#---------------- Library Options ---------------- +# Minimalistic printf version +PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min + +# Floating point printf version (requires MATH_LIB = -lm below) +PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt + +# If this is left blank, then it will use the Standard printf version. +PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_FLOAT) + + +# Minimalistic scanf version +SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min + +# Floating point + %[ scanf version (requires MATH_LIB = -lm below) +SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt + +# If this is left blank, then it will use the Standard scanf version. +SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_FLOAT) + + +MATH_LIB = -lm + + +# List any extra directories to look for libraries here. +# Each directory must be seperated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRALIBDIRS = + + + +#---------------- External Memory Options ---------------- + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# used for variables (.data/.bss) and heap (malloc()). +#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# only used for heap (malloc()). +#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff + +EXTMEMOPTS = + + + +#---------------- Linker Options ---------------- +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += $(EXTMEMOPTS) +LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS)) +LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) +#LDFLAGS += -T linker_script.x + + + +#---------------- Programming Options (avrdude) ---------------- + +# Programming hardware: alf avr910 avrisp bascom bsd +# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 +# +# Type: avrdude -c ? +# to get a full listing. +# +AVRDUDE_PROGRAMMER = stk500 + +# com1 = serial port. Use lpt1 to connect to parallel port. +AVRDUDE_PORT = com1 # programmer connected to serial device + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE_COUNTER = -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_NO_VERIFY = -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_VERBOSE = -v -v + +AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) +AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY) +AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE) +AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER) + + + +#---------------- Debugging Options ---------------- + +# For simulavr only - target MCU frequency. +DEBUG_MFREQ = $(F_CPU) + +# Set the DEBUG_UI to either gdb or insight. +# DEBUG_UI = gdb +DEBUG_UI = insight + +# Set the debugging back-end to either avarice, simulavr. +DEBUG_BACKEND = avarice +#DEBUG_BACKEND = simulavr + +# GDB Init Filename. +GDBINIT_FILE = __avr_gdbinit + +# When using avarice settings for the JTAG +JTAG_DEV = /dev/com1 + +# Debugging port used to communicate between GDB / avarice / simulavr. +DEBUG_PORT = 4242 + +# Debugging host used to communicate between GDB / avarice / simulavr, normally +# just set to localhost unless doing some sort of crazy debugging when +# avarice is running on a different computer. +DEBUG_HOST = localhost + + + +#============================================================================ + + +# Define programs and commands. +SHELL = sh +CC = avr-gcc +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size +AR = avr-ar rcs +NM = avr-nm +AVRDUDE = avrdude +REMOVE = rm -f +REMOVEDIR = rm -rf +COPY = cp +WINSHELL = cmd + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_COFF = Converting to AVR COFF: +MSG_EXTENDED_COFF = Converting to AVR Extended COFF: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_CPP = Compiling C++: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: +MSG_CREATING_LIBRARY = Creating library: + + + + +# Define all object files. +OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o) + +# Define all listing files. +LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst) + + +# Compiler flags to generate dependency files. +GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d + + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) + + + + + +# Default target. +all: begin gccversion sizebefore build sizeafter end + +# Change the build target to build a HEX file or a library. +build: elf hex eep lss sym +#build: lib + + +elf: $(TARGET).elf +hex: $(TARGET).hex +eep: $(TARGET).eep +lss: $(TARGET).lss +sym: $(TARGET).sym +LIBNAME=lib$(TARGET).a +lib: $(LIBNAME) + + + +# Eye candy. +# AVR Studio 3.x does not check make's exit code but relies on +# the following magic strings to be generated by the compile job. +begin: + @echo + @echo $(MSG_BEGIN) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf + +sizebefore: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \ + 2>/dev/null; echo; fi + +sizeafter: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \ + 2>/dev/null; echo; fi + + + +# Display compiler version information. +gccversion : + @$(CC) --version + + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + + +# Generate avr-gdb config/init file which does the following: +# define the reset signal, load the target file, connect to target, and set +# a breakpoint at main(). +gdb-config: + @$(REMOVE) $(GDBINIT_FILE) + @echo define reset >> $(GDBINIT_FILE) + @echo SIGNAL SIGHUP >> $(GDBINIT_FILE) + @echo end >> $(GDBINIT_FILE) + @echo file $(TARGET).elf >> $(GDBINIT_FILE) + @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE) +ifeq ($(DEBUG_BACKEND),simulavr) + @echo load >> $(GDBINIT_FILE) +endif + @echo break main >> $(GDBINIT_FILE) + +debug: gdb-config $(TARGET).elf +ifeq ($(DEBUG_BACKEND), avarice) + @echo Starting AVaRICE - Press enter when "waiting to connect" message displays. + @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \ + $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT) + @$(WINSHELL) /c pause + +else + @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \ + $(DEBUG_MFREQ) --port $(DEBUG_PORT) +endif + @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE) + + + + +# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. +COFFCONVERT = $(OBJCOPY) --debugging +COFFCONVERT += --change-section-address .data-0x800000 +COFFCONVERT += --change-section-address .bss-0x800000 +COFFCONVERT += --change-section-address .noinit-0x800000 +COFFCONVERT += --change-section-address .eeprom-0x810000 + + + +coff: $(TARGET).elf + @echo + @echo $(MSG_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-avr $< $(TARGET).cof + + +extcoff: $(TARGET).elf + @echo + @echo $(MSG_EXTENDED_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof + + + +# Create final output files (.hex, .eep) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0 + +# Create extended listing file from ELF output file. +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + + +# Create library from object files. +.SECONDARY : $(TARGET).a +.PRECIOUS : $(OBJ) +%.a: $(OBJ) + @echo + @echo $(MSG_CREATING_LIBRARY) $@ + $(AR) $@ $(OBJ) + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +%.elf: $(OBJ) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +$(OBJDIR)/%.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create object files from C++ source files. +$(OBJDIR)/%.o : %.cpp + @echo + @echo $(MSG_COMPILING_CPP) $< + $(CC) -c $(ALL_CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +%.s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C++ source files. +%.s : %.cpp + $(CC) -S $(ALL_CPPFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +$(OBJDIR)/%.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Create preprocessed source for use in sending a bug report. +%.i : %.c + $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list end + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).eep + $(REMOVE) $(TARGET).cof + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lss + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRC:.c=.i) + $(REMOVEDIR) .dep + + +# Create object files directory +$(shell mkdir $(OBJDIR) 2>/dev/null) + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex eep lss sym coff extcoff \ +clean clean_list program debug gdb-config + + + + + + diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h new file mode 100644 index 000000000..0857a1fbd --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -0,0 +1,158 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/* + * NOTE: this is just documentation for doxigen, the real configuration file + * is the one into the project directories. + */ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +//#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Semaphores APIs with priority + * shift are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES.*/ +#define CH_USE_RT_SEMAPHORES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_TIMEOUT + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 100 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 10 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-\. + */ +//#define CH_CURRP_REGISTER_CACHE "reg" + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c new file mode 100644 index 000000000..2d0a2c0df --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/chcore.c @@ -0,0 +1,26 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +void chSysHalt(void) { + + while (TRUE) + ; +} diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h new file mode 100644 index 000000000..d263202d8 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/chcore.h @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup Core + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/* + * Interrupt saved context. + */ +struct extctx { + BYTE8 sr; + BYTE8 r31; + BYTE8 r30; + BYTE8 r27; + BYTE8 r26; + BYTE8 r25; + BYTE8 r24; + BYTE8 r23; + BYTE8 r22; + BYTE8 r21; + BYTE8 r20; + BYTE8 r19; + BYTE8 r18; + BYTE8 r1; + BYTE8 r0; + UWORD16 pc; +}; + +/* + * Stack saved context. + */ +struct intctx { + BYTE8 r29; + BYTE8 r28; + BYTE8 r17; + BYTE8 r16; + BYTE8 r15; + BYTE8 r14; + BYTE8 r13; + BYTE8 r12; + BYTE8 r11; + BYTE8 r10; + BYTE8 r9; + BYTE8 r8; + BYTE8 r7; + BYTE8 r6; + BYTE8 r5; + BYTE8 r4; + BYTE8 r3; + BYTE8 r2; + UWORD16 pc; +}; + +typedef struct { + struct intctx *sp; +} Context; + +/** + * Platform dependent part of the \p chThdCreate() API. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ +} + +/* + * Interrupt stack usage except for saved registers. + */ +#define EXTRA_INT_STACK 0x10 + +#define UserStackSize(n) (sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + EXTRA_INT_STACK + \ + (n)) + +#define chSysLock() asm("cli") +#define chSysUnlock() asm("sei") + +void chSysHalt(void); +void chSysPause(void); +void chSysSwitchI(Context *oldp, Context *newp); + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/demos/AVR-AT90CANx-GCC/chcore2.S b/demos/AVR-AT90CANx-GCC/chcore2.S new file mode 100644 index 000000000..a9d39690a --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/chcore2.S @@ -0,0 +1,124 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +.global chSysPause +chSysPause: + ldi r18, (1 << SE) + out _SFR_IO_ADDR(SMCR), r18 +stay: + sleep + rjmp stay + +.global chSysSwitchI +chSysSwitchI: + push r2 + push r3 + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + push r16 + push r17 + push r28 + push r29 + movw r30, r24 // Z <- oldp + in r0, _SFR_IO_ADDR(SPL) + st Z, r0 + in r0, _SFR_IO_ADDR(SPH) + std Z+1, r0 + + movw r30, r22 // Z <- newp + ld r0, Z + out _SFR_IO_ADDR(SPL), r0 + ldd r0, Z+1 + out _SFR_IO_ADDR(SPH), r0 + pop r29 + pop r28 + pop r17 + pop r16 + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + pop r3 + pop r2 + ret + +.global __vector_17 +__vector_17: + push r0 + push r1 + push r18 + push r19 + push r20 + push r21 + push r22 + push r23 + push r24 + push r25 + push r26 + push r27 + push r30 + push r31 + in r0, _SFR_IO_ADDR(SREG) + push r0 + clr r1 + call chSchTimerHandlerI +intcommon: + call chSchRescRequiredI + tst r24 + breq noschd + call chSchDoRescheduleI +noschd: + pop r0 + out _SFR_IO_ADDR(SREG), r0 + pop r31 + pop r30 + pop r27 + pop r26 + pop r25 + pop r24 + pop r23 + pop r22 + pop r21 + pop r20 + pop r19 + pop r18 + pop r1 + pop r0 + reti + diff --git a/demos/AVR-AT90CANx-GCC/chtypes.h b/demos/AVR-AT90CANx-GCC/chtypes.h new file mode 100644 index 000000000..d3c26caaf --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/chtypes.h @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +/* + * Generic types often dependant on the compiler. + */ +#define BOOL char +#define BYTE8 unsigned char +#define SBYTE8 signed char +#define WORD16 int +#define UWORD16 unsigned int +#define LONG32 long +#define ULONG32 unsigned long +#define PTR_EQ int + +typedef BYTE8 t_tmode; +typedef BYTE8 t_tstate; +typedef BYTE8 t_prio; +typedef WORD16 t_msg; +typedef BYTE8 t_eventid; +typedef BYTE8 t_eventmask; +typedef UWORD16 t_time; +typedef SBYTE8 t_cnt; +typedef UWORD16 t_size; + +#define INLINE inline + +#endif /* _CHTYPES_H_ */ diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c new file mode 100644 index 000000000..2c04d82dc --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -0,0 +1,38 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +static BYTE8 waThread1[UserStackSize(32)]; + +static t_msg Thread1(void *arg) { + + while (TRUE) { + chThdSleep(800); + } + return 0; +} + +int main(int argc, char **argv) { + + chSysInit(); + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chSysPause(); + return 0; +} -- cgit v1.2.3 From 286ae3e6fb6036dec366e5c977d68546007a78e5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 4 Oct 2007 17:40:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@37 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/LPC214x-GCC/Makefile | 180 ---------------------------------- demos/LPC214x-GCC/buzzer.c | 82 ---------------- demos/LPC214x-GCC/buzzer.h | 28 ------ demos/LPC214x-GCC/ch.ld | 85 ---------------- demos/LPC214x-GCC/chconf.h | 157 ------------------------------ demos/LPC214x-GCC/chcore.c | 225 ------------------------------------------- demos/LPC214x-GCC/chcore.h | 110 --------------------- demos/LPC214x-GCC/chcore2.s | 188 ------------------------------------ demos/LPC214x-GCC/chtypes.h | 46 --------- demos/LPC214x-GCC/crt0.s | 146 ---------------------------- demos/LPC214x-GCC/main.c | 85 ---------------- demos/LPC214x-GCC/readme.txt | 23 ----- 12 files changed, 1355 deletions(-) delete mode 100644 demos/LPC214x-GCC/Makefile delete mode 100644 demos/LPC214x-GCC/buzzer.c delete mode 100644 demos/LPC214x-GCC/buzzer.h delete mode 100644 demos/LPC214x-GCC/ch.ld delete mode 100644 demos/LPC214x-GCC/chconf.h delete mode 100644 demos/LPC214x-GCC/chcore.c delete mode 100644 demos/LPC214x-GCC/chcore.h delete mode 100644 demos/LPC214x-GCC/chcore2.s delete mode 100644 demos/LPC214x-GCC/chtypes.h delete mode 100644 demos/LPC214x-GCC/crt0.s delete mode 100644 demos/LPC214x-GCC/main.c delete mode 100644 demos/LPC214x-GCC/readme.txt (limited to 'demos') diff --git a/demos/LPC214x-GCC/Makefile b/demos/LPC214x-GCC/Makefile deleted file mode 100644 index 8400d8f82..000000000 --- a/demos/LPC214x-GCC/Makefile +++ /dev/null @@ -1,180 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List ARM-mode C source files here -ASRC = chcore.c main.c buzzer.c \ - ../../test/test.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ - ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ - ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = - -# List ASM source files here -ASMSRC = crt0.s chcore2.s - -# List all user directories here -UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -mthumb-interwork increases the code size, remove it if you dont have -# Thumb code anywhere in the project. -# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. -OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing -#OPT += -ffixed-f7 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - -# -# End of user defines -############################################################################################## - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms - -ifneq ($(TSRC),) - ASFLAGS += -mthumb-interwork -D THUMB_INTERWORK - CPFLAGS += -mthumb-interwork -D THUMB_INTERWORK - LDFLAGS += -mthumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - $(AS) -c $(ASFLAGS) $< -o $@ - -%elf: $(OBJS) - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/LPC214x-GCC/buzzer.c b/demos/LPC214x-GCC/buzzer.c deleted file mode 100644 index 4700bfb45..000000000 --- a/demos/LPC214x-GCC/buzzer.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Buzzer driver for Olimex LPC-P2148. - * Uses the timer 1 for wave generation and a Virtual Timer for the sound - * duration. - * The driver also generates an event when the sound is done and the buzzer - * goes silent. - */ -#include - -#include "lpc214x.h" -#include "buzzer.h" - -EventSource BuzzerSilentEventSource; - -#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1) -#define StopCounter(t) ((t)->TC_EMR = 0, (t)->TC_TCR = 2) - -void InitBuzzer(void) { - - chEvtInit(&BuzzerSilentEventSource); - - /* - * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions. - * Enables Timer1 clock. - */ - PINSEL0 &= 0xF0FFFFFF; - PINSEL0 |= 0x0A000000; - PCONP = (PCONP & PCALL) | PCTIM1; - - /* - * Timer setup. - */ - TC *tc = T1Base; - StopCounter(tc); - tc->TC_CTCR = 0; // Clock source is PCLK. - tc->TC_PR = 0; // Prescaler disabled. - tc->TC_MCR = 2; // Clear TC on match MR0. -} - -static void stop(void *p) { - TC *tc = T1Base; - - StopCounter(tc); - chEvtSendI(&BuzzerSilentEventSource); -} - -void PlaySound(int freq, t_time duration) { - static VirtualTimer bvt; - TC *tc = T1Base; - - chSysLock(); - - if (bvt.vt_func) { // If a sound is already being played - chVTResetI(&bvt); // then aborts it. - StopCounter(tc); - } - - tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); - StartCounter(tc); - chVTSetI(&bvt, duration, stop, NULL); - - chSysUnlock(); -} diff --git a/demos/LPC214x-GCC/buzzer.h b/demos/LPC214x-GCC/buzzer.h deleted file mode 100644 index 3334d8b5c..000000000 --- a/demos/LPC214x-GCC/buzzer.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BUZZER_H_ -#define _BUZZER_H_ - -void InitBuzzer(void); -void PlaySound(int freq, t_time duration); - -extern EventSource BuzzerSilentEventSource; - -#endif /* _BUZZER_H_ */ diff --git a/demos/LPC214x-GCC/ch.ld b/demos/LPC214x-GCC/ch.ld deleted file mode 100644 index 6ce8a0b32..000000000 --- a/demos/LPC214x-GCC/ch.ld +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * LPC2148 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0080; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; - -SECTIONS -{ - . = 0; - - .text : - { - _text = .; - *(.text); - *(.rodata); - *(.rodata*); - *(.glue_7t); - *(.glue_7); - . = ALIGN(4); - _etext = .; - } > flash - - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/LPC214x-GCC/chconf.h b/demos/LPC214x-GCC/chconf.h deleted file mode 100644 index da8553399..000000000 --- a/demos/LPC214x-GCC/chconf.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Configuration file for LPC214x-GCC demo project. - */ - -/** - * @addtogroup Config - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Semaphores APIs with priority - * shift are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_RT_SEMAPHORES - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_TIMEOUT - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 - -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ -#define CH_TIME_QUANTUM 20 - -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. - */ -//#define CH_CURRP_REGISTER_CACHE "r7" - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/LPC214x-GCC/chcore.c b/demos/LPC214x-GCC/chcore.c deleted file mode 100644 index 3d72c20db..000000000 --- a/demos/LPC214x-GCC/chcore.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include "lpc214x.h" -#include "lpc214x_serial.h" -#include "buzzer.h" - -extern void IrqHandler(void); -extern void T0IrqHandler(void); - -#define VAL_TC0_PRESCALER 0 - -/* - * Pins configuration for Olimex LPC-P2148. - * - * PINSEL0 - * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD - * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 - * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 - * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- - * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - * - * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 SSE MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 L1 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 10 10 10 10 00 - * OUT -- OUT OUT -- -- -- -- -- OUT OUT -- -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 - * - * PINSEL2 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- - * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- - */ -#define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100842A8 -#define VAL_PINSEL2 0x00000004 -#define VAL_FIO0DIR 0xB0603C00 -#define VAL_FIO1DIR 0x00000000 - -/* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. - */ -void hwinit(void) { - int i; - - /* - * All peripherals clock disabled by default in order to save power. - */ - PCONP = PCRTC | PCTIM0; - - /* - * MAM setup. - */ - MAMTIM = 0x3; /* 3 cycles for flash accesses. */ - MAMCR = 0x2; /* MAM fully enabled. */ - - /* - * PLL setup for Fosc=12MHz and CCLK=48MHz. - * P=2 M=3. - */ - PLL *pll = PLLBase; - pll->PLL0_CFG = 0x23; /* P and M values. */ - pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - while (!(pll->PLL0_STAT & 0x400)) - ; /* Wait for PLL lock. */ - - pll->PLL0_CON = 0x3; /* Connects the PLL. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - - /* - * VPB setup. - * PCLK = CCLK / 4. - */ - VPBDIV = VPD_D4; - - /* - * I/O pins configuration. - */ - PINSEL0 = VAL_PINSEL0; - PINSEL1 = VAL_PINSEL1; - PINSEL2 = VAL_PINSEL2; - IO0DIR = VAL_FIO0DIR; - IO0SET = 0xFFFFFFFF; - IO1DIR = VAL_FIO1DIR; - IO1SET = 0xFFFFFFFF; - - /* - * Interrupt vectors assignment. - * NOTE: Better reset everything in the VIC, it is a HUGE source of trouble. - */ - VIC *vic = VICBase; - vic->VIC_IntSelect = 0; - vic->VIC_IntEnable = 0; - vic->VIC_VectAddr = 0; - for (i = 0; i < 16; i++) { - vic->VIC_VectCntls[i] = 0; - vic->VIC_VectAddrs[i] = 0; - } - vic->VIC_DefVectAddr = (IOREG32)IrqHandler; - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); - SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); - - /* - * System Timer initialization, 1ms intervals. - */ - vic->VIC_IntEnable |= INTMASK(SOURCE_Timer0); - TC *timer = T0Base; - timer->TC_PR = VAL_TC0_PRESCALER; - timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); - timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ - timer->TC_TCR = 2; /* Reset counter and prescaler. */ - timer->TC_TCR = 1; /* Timer enabled. */ - - /* - * Other subsystems. - */ - InitSerial(); - InitBuzzer(); -} - -void chSysPause(void) { - - while (TRUE) { -// Note, it is disabled because it causes trouble with the JTAG probe. -// Enable it in the final code only. -// PCON = 1; /* Stops CPU clock until next interrupt. */ - } -} - -/* - * System halt. - * Yellow LED only. - */ -void chSysHalt(void) { - - chSysLock(); - IO0SET = 0x80000C00; - IO0CLR = 0x80000000; - while (TRUE) - ; -} - -/* - * Set a vector for an interrupt source, the vector is enabled too. - */ -void SetVICVector(void *handler, int vector, int source) { - - VIC *vicp = VICBase; - vicp->VIC_VectAddrs[vector] = (IOREG32)handler; - vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20); -} - -/* - * Undefined Instruction exception handler. - * Yellow LED + RED LED 2. - */ -void UndHandler(void) { - IO0SET = 0x80000C00; - IO0CLR = 0x80000800; - while(TRUE) - ; -} - -/* - * Prefetch exception handler. - * Yellow LED + RED LED 1. - */ -void PrefetchHandler(void) { - IO0SET = 0x80000C00; - IO0CLR = 0x80000400; - while(TRUE) - ; -} - -/* - * Abort exception handler. - * Yellow LED + both RED LEDs. - */ -void AbortHandler(void) { - IO0SET = 0x80000C00; - IO0CLR = 0x80000C00; - while(TRUE) - ; -} - -/* - * Non-vectored IRQs handling here. - */ -void NonVectoredIrq(void) { - VICVectAddr = 0; -} - -/* - * Timer 0 IRQ handling here. - */ -void Timer0Irq(void) { - chSchTimerHandlerI(); - T0IR = 1; /* Clear interrupt on match MR0. */ - VICVectAddr = 0; -} diff --git a/demos/LPC214x-GCC/chcore.h b/demos/LPC214x-GCC/chcore.h deleted file mode 100644 index b2091b686..000000000 --- a/demos/LPC214x-GCC/chcore.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/* - * The following values are implementation dependent. You may change them in - * order to match your HW. - */ -#define FOSC 12000000 -#define CCLK 48000000 -#define PCLK 12000000 - -typedef void *regarm; - -/* - * Stack saved context. - */ -struct stackregs { - regarm r4; - regarm r5; - regarm r6; -#ifndef MK_CURRP_REGISTER_CACHE - regarm r7; -#endif - regarm r8; - regarm r9; - regarm r10; - regarm r11; - regarm lr; -}; - -typedef struct { - struct stackregs *r13; -} Context; - -#ifdef MK_CURRP_REGISTER_CACHE -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ - tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct stackregs)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->r6 = 0; \ - tp->p_ctx.r13->r8 = 0; \ - tp->p_ctx.r13->r9 = 0; \ - tp->p_ctx.r13->r10 = 0; \ - tp->p_ctx.r13->r11 = 0; \ - tp->p_ctx.r13->lr = threadstart; \ -} -#else -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ - tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct stackregs)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->r6 = 0; \ - tp->p_ctx.r13->r7 = 0; \ - tp->p_ctx.r13->r8 = 0; \ - tp->p_ctx.r13->r9 = 0; \ - tp->p_ctx.r13->r10 = 0; \ - tp->p_ctx.r13->r11 = 0; \ - tp->p_ctx.r13->lr = threadstart; \ -} -#endif - -#ifdef THUMB -extern void chSysLock(void); -extern void chSysUnlock(void); -#else /* !THUMB */ -#define chSysLock() asm("msr CPSR_c, #0x9F") -#define chSysUnlock() asm("msr CPSR_c, #0x1F") -#endif /* THUMB */ - -#define INT_REQUIRED_STACK 0x40 // Must include registers and stack frames. - -#define UserStackSize(n) (sizeof(Thread) + \ - sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) - -void chSysHalt(void) __attribute__((noreturn)); -void chSysPause(void); -void chSysSwitchI(Context *oldp, Context *newp); -void threadstart(void); -void DefFiqHandler(void); -void DefIrqHandler(void); -void SpuriousHandler(void); - -void SetVICVector(void *handler, int vector, int source); - -#endif /* _CHCORE_H_ */ diff --git a/demos/LPC214x-GCC/chcore2.s b/demos/LPC214x-GCC/chcore2.s deleted file mode 100644 index f734eebba..000000000 --- a/demos/LPC214x-GCC/chcore2.s +++ /dev/null @@ -1,188 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "chconf.h" - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text -.code 32 -.balign 4 - -.globl threadstart -threadstart: - msr CPSR_c, #MODE_SYS - mov r0, r5 -/* blx r4*/ - mov lr, pc - bx r4 - bl chThdExit - -.globl SwiHandler -SwiHandler: - b SwiHandler - -.globl DefIrqHandler -DefIrqHandler: - b DefIrqHandler - -.globl FiqHandler -FiqHandler: - b FiqHandler - -#ifdef THUMB_INTERWORK -.globl chSysLock -chSysLock: - msr CPSR_c, #0x9F - bx lr - -.globl chSysUnlock -chSysUnlock: - msr CPSR_c, #0x1F - bx lr -#endif - -.globl chSysSwitchI -chSysSwitchI: -#ifdef CH_CURRP_REGISTER_CACHE - stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB_INTERWORK - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - bx lr -#else - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} -#endif -#else - stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB_INTERWORK - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - bx lr -#else - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} -#endif -#endif /* CH_CURRP_REGISTER_CACHE */ - -/* - * System stack frame structure after a context switch in the - * interrupt handler: - * - * High +------------+ - * | R12 | -+ - * | R3 | | - * | R2 | | - * | R1 | | External context: IRQ handler frame - * | R0 | | - * | LR_IRQ | | (user code return address) - * | SPSR | -+ (user code status) - * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space - * | LR | -+ (system code return address) - * | R11 | | - * | R10 | | - * | R9 | | - * | R8 | | Internal context: mk_SwitchI() frame - * | (R7) | | (optional, see MK_CURRP_REGISTER_CACHE) - * | R6 | | - * | R5 | | - * SP-> | R4 | -+ - * Low +------------+ - */ -.globl IrqHandler -IrqHandler: - sub lr, lr, #4 - stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc} - bl NonVectoredIrq - b IrqCommon - -.globl T0IrqHandler -T0IrqHandler: - sub lr, lr, #4 - stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc}^ - bl Timer0Irq - b IrqCommon - -.globl UART0IrqHandler -UART0IrqHandler: - sub lr, lr, #4 - stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc}^ - bl UART0Irq - b IrqCommon - -.globl UART1IrqHandler -UART1IrqHandler: - sub lr, lr, #4 - stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc}^ - bl UART1Irq - b IrqCommon - -/* - * Common exit point for all IRQ routines, it performs the rescheduling if - * required. - */ -IrqCommon: - bl chSchRescRequiredI - cmp r0, #0 // Simply returns if a - ldmeqfd sp!, {r0-r3, r12, pc}^ // reschedule is not required. - - // Saves the IRQ mode registers in the system stack. - ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0-r3, r12} // Registers on System Stack. - msr CPSR_c, #MODE_IRQ | I_BIT - mrs r0, SPSR - mov r1, lr - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. - - // Context switch. - bl chSchDoRescheduleI - - // Re-establish the IRQ conditions again. - ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. - msr CPSR_c, #MODE_IRQ | I_BIT - msr SPSR_fsxc, r0 - mov lr, r1 - msr CPSR_c, #MODE_SYS | I_BIT - ldmfd sp!, {r0-r3, r12} - msr CPSR_c, #MODE_IRQ | I_BIT - subs pc, lr, #0 diff --git a/demos/LPC214x-GCC/chtypes.h b/demos/LPC214x-GCC/chtypes.h deleted file mode 100644 index 803b5ead4..000000000 --- a/demos/LPC214x-GCC/chtypes.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -/* - * Generic types often dependant on the compiler. - */ -#define BOOL char -#define BYTE8 unsigned char -#define SBYTE8 char -#define WORD16 short -#define UWORD16 unsigned short -#define LONG32 int -#define ULONG32 unsigned int - -typedef BYTE8 t_tmode; -typedef BYTE8 t_tstate; -typedef ULONG32 t_prio; -typedef LONG32 t_msg; -typedef LONG32 t_eventid; -typedef ULONG32 t_eventmask; -typedef ULONG32 t_time; -typedef LONG32 t_cnt; -typedef ULONG32 t_size; - -#define INLINE inline - -#endif /* _CHTYPES_H_ */ diff --git a/demos/LPC214x-GCC/crt0.s b/demos/LPC214x-GCC/crt0.s deleted file mode 100644 index 9b413191b..000000000 --- a/demos/LPC214x-GCC/crt0.s +++ /dev/null @@ -1,146 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Generic ARM startup file for ChibiOS/RT. - */ - -.extern _main - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text -.code 32 -.balign 4 -/* - * System entry points. - */ -_start: - b ResetHandler - ldr pc, _undefined - ldr pc, _swi - ldr pc, _prefetch - ldr pc, _abort - nop - ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ - ldr pc, _fiq - -_undefined: - .word UndHandler -_swi: - .word SwiHandler -_prefetch: - .word PrefetchHandler -_abort: - .word AbortHandler -_fiq: - .word FiqHandler - .word 0 - .word 0 - -/* - * Reset handler. - */ -ResetHandler: - /* - * Stack pointers initialization. - */ - ldr r0, =__ram_end__ - /* Undefined */ - msr CPSR_c, #MODE_UND | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__und_stack_size__ - sub r0, r0, r1 - /* Abort */ - msr CPSR_c, #MODE_ABT | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__abt_stack_size__ - sub r0, r0, r1 - /* FIQ */ - msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__fiq_stack_size__ - sub r0, r0, r1 - /* IRQ */ - msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__irq_stack_size__ - sub r0, r0, r1 - /* Supervisor */ - msr CPSR_c, #MODE_SVC | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__svc_stack_size__ - sub r0, r0, r1 - /* System */ - msr CPSR_c, #MODE_SYS | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__sys_stack_size__ - sub r0, r0, r1 - /* - * Check on allocated stacks size. This should never happen unless you - * don't care to verify the map file after compiling your application. - */ - ldr r1, =_bss_end - cmp r0, r1 - bge ramsizeok - bl chSysHalt -ramsizeok: - /* - * Data initialization. - * NOTE: It assumes that the DATA size is a multiple of 4. - */ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata -dataloop: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dataloop - /* - * BSS initialization. - * NOTE: It assumes that the BSS size is a multiple of 4. - */ - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bssloop: - cmp r1, r2 - strlo r0, [r1], #4 - blo bssloop - /* - * Application-provided HW initialization routine. - */ - bl hwinit - /* - * main(0, NULL). - */ - mov r0, #0 - mov r1, #0 - bl main - bl chSysHalt diff --git a/demos/LPC214x-GCC/main.c b/demos/LPC214x-GCC/main.c deleted file mode 100644 index 0183b276b..000000000 --- a/demos/LPC214x-GCC/main.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include "lpc214x.h" -#include "lpc214x_serial.h" -#include "buzzer.h" - -static BYTE8 waThread1[UserStackSize(32)]; - -static t_msg Thread1(void *arg) { - - while (TRUE) { - IO0CLR = 0x00000800; - chThdSleep(200); - IO0SET = 0x00000C00; - chThdSleep(800); - IO0CLR = 0x00000400; - chThdSleep(200); - IO0SET = 0x00000C00; - chThdSleep(800); - } - return 0; -} - -static BYTE8 waThread2[UserStackSize(32)]; - -static t_msg Thread2(void *arg) { - - while (TRUE) { - IO0CLR = 0x80000000; - chThdSleep(200); - IO0SET = 0x80000000; - chThdSleep(300); - } - return 0; -} - -static BYTE8 waThread3[UserStackSize(64)]; - -static t_msg Thread3(void *arg) { - t_msg TestThread(void *p); - - while (TRUE) { - if (!(IO0PIN & 0x00018000)) { - TestThread(&COM1); - PlaySound(500, 100); - } - else { - if (!(IO0PIN & 0x00008000)) // Button 1 - PlaySound(1000, 100); - if (!(IO0PIN & 0x00010000)) // Button 2 - chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); - } - chThdSleep(500); - } - return 0; -} - -int main(int argc, char **argv) { - - chSysInit(); - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); - chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); - chThdCreate(NORMALPRIO, 0, waThread3, sizeof(waThread3), Thread3, NULL); - chSysPause(); - return 0; -} diff --git a/demos/LPC214x-GCC/readme.txt b/demos/LPC214x-GCC/readme.txt deleted file mode 100644 index f55f5b4c6..000000000 --- a/demos/LPC214x-GCC/readme.txt +++ /dev/null @@ -1,23 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI LPC214X. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex LPC-P2148 board. The port on other boards or other -members of the LPC2000 family should be an easy task. - -** The Demo ** - -The demo blinks the leds on the board by using multiple threads. By pressing -the buttons on the board it is possible to activate the buzzer and send a -message over the serial ports. Pressing both buttons activates the test -procedure on the serial port 1. -See main.c for details. Buzzer.c contains an interesting device driver -example that uses a physical timer for the waveform generation and a virtual -timer for the sound duration. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. -- cgit v1.2.3 From d6d799ed48f8193bee286187132221f831726a07 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Oct 2007 08:58:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@39 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 10 ++++++---- demos/ARM7-LPC214x-GCC/chcore.h | 2 +- demos/ARM7-LPC214x-GCC/main.c | 10 +++++----- demos/AVR-AT90CANx-GCC/chcore.h | 4 ++-- 4 files changed, 14 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 8400d8f82..b69ae8780 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -62,7 +62,7 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = chcore.c main.c buzzer.c \ +ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c \ ../../test/test.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ @@ -92,8 +92,6 @@ AOPT = TOPT = -mthumb -D THUMB # Common options here -# NOTE: -mthumb-interwork increases the code size, remove it if you dont have -# Thumb code anywhere in the project. # NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing #OPT += -ffixed-f7 @@ -117,7 +115,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms @@ -137,15 +135,19 @@ CPFLAGS += -MD -MP -MF .dep/$(@F).d all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp $(AOBJS) : %.o : %.c + @echo $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ $(TOBJS) : %.o : %.c + @echo $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ $(ASMOBJS) : %.o : %.s + @echo $(AS) -c $(ASFLAGS) $< -o $@ %elf: $(OBJS) + @echo $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ %hex: %elf diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index b2091b686..9c583c2ac 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -98,7 +98,7 @@ extern void chSysUnlock(void); sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) void chSysHalt(void) __attribute__((noreturn)); -void chSysPause(void); +void chSysPause(void) __attribute__((noreturn)); void chSysSwitchI(Context *oldp, Context *newp); void threadstart(void); void DefFiqHandler(void); diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 0183b276b..5db6815fb 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -57,18 +57,18 @@ static BYTE8 waThread3[UserStackSize(64)]; static t_msg Thread3(void *arg) { t_msg TestThread(void *p); - + while (TRUE) { - if (!(IO0PIN & 0x00018000)) { + if (!(IO0PIN & 0x00018000)) { TestThread(&COM1); PlaySound(500, 100); - } - else { + } + else { if (!(IO0PIN & 0x00008000)) // Button 1 PlaySound(1000, 100); if (!(IO0PIN & 0x00010000)) // Button 2 chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); - } + } chThdSleep(500); } return 0; diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h index d263202d8..799742f47 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.h +++ b/demos/AVR-AT90CANx-GCC/chcore.h @@ -97,8 +97,8 @@ typedef struct { #define chSysLock() asm("cli") #define chSysUnlock() asm("sei") -void chSysHalt(void); -void chSysPause(void); +void chSysHalt(void) __attribute__((noreturn)) ; +void chSysPause(void) __attribute__((noreturn)) ; void chSysSwitchI(Context *oldp, Context *newp); #endif /* _CHCORE_H_ */ -- cgit v1.2.3 From 00c6f5ea40f97385dce7ab7b9d20bc0cb909ad23 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Oct 2007 09:53:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@40 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.c | 2 ++ demos/Win32-MSVS/chcore.c | 4 +++- demos/Win32-MinGW/chcore.c | 4 +++- 3 files changed, 8 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 3d72c20db..d06e57657 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -145,6 +145,8 @@ void hwinit(void) { void chSysPause(void) { + chThdSetPriority(IDLEPRIO); + while (TRUE) { // Note, it is disabled because it causes trouble with the JTAG probe. // Enable it in the final code only. diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c index bb038a4d6..80fd11424 100644 --- a/demos/Win32-MSVS/chcore.c +++ b/demos/Win32-MSVS/chcore.c @@ -35,7 +35,7 @@ void InitCore(void) { printf("QueryPerformanceFrequency() error"); exit(1); } - printf("Core Frequency %d Hz\n", slice.LowPart); + printf("Core Frequency %u Hz\n", slice.LowPart); slice.QuadPart /= CH_FREQUENCY; QueryPerformanceCounter(&nextcnt); nextcnt.QuadPart += slice.QuadPart; @@ -69,6 +69,8 @@ static void ChkIntSources(void) { void __fastcall chSysPause(void) { + chThdSetPriority(IDLEPRIO); + while (TRUE) { ChkIntSources(); diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 77195c44c..4f677b929 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -58,7 +58,7 @@ void InitCore(void) { printf("QueryPerformanceFrequency() error"); exit(1); } - printf("Core Frequency %d Hz\n", (int)slice.LowPart); + printf("Core Frequency %u Hz\n", (int)slice.LowPart); slice.QuadPart /= CH_FREQUENCY; QueryPerformanceCounter(&nextcnt); nextcnt.QuadPart += slice.QuadPart; @@ -92,6 +92,8 @@ static void ChkIntSources(void) { __attribute__((fastcall)) void chSysPause(void) { + chThdSetPriority(IDLEPRIO); + while (TRUE) { ChkIntSources(); -- cgit v1.2.3 From cb5757e03204c11f425c20bb6766242618eb2b28 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Oct 2007 10:22:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@41 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chcore.c | 15 +++++++++++++++ demos/AVR-AT90CANx-GCC/chcore2.S | 8 -------- 2 files changed, 15 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c index 2d0a2c0df..53fe296ac 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.c +++ b/demos/AVR-AT90CANx-GCC/chcore.c @@ -19,8 +19,23 @@ #include +void chSysPause(void) { + + chThdSetPriority(IDLEPRIO); + + asm volatile ( + "ldi r18, 1 \n\t" // SE bit + "out 0x33, r18 \n" // SMCR + ); + while (TRUE) { + asm volatile ("sleep\n\t"); + } +} + void chSysHalt(void) { + chSysLock(); + while (TRUE) ; } diff --git a/demos/AVR-AT90CANx-GCC/chcore2.S b/demos/AVR-AT90CANx-GCC/chcore2.S index a9d39690a..d438ffb4f 100644 --- a/demos/AVR-AT90CANx-GCC/chcore2.S +++ b/demos/AVR-AT90CANx-GCC/chcore2.S @@ -19,14 +19,6 @@ #include -.global chSysPause -chSysPause: - ldi r18, (1 << SE) - out _SFR_IO_ADDR(SMCR), r18 -stay: - sleep - rjmp stay - .global chSysSwitchI chSysSwitchI: push r2 -- cgit v1.2.3 From e313c04627e8d7e16e0da58e4def155fbfb0c591 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Oct 2007 10:29:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@42 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chcore.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c index 53fe296ac..85dff271f 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.c +++ b/demos/AVR-AT90CANx-GCC/chcore.c @@ -24,11 +24,11 @@ void chSysPause(void) { chThdSetPriority(IDLEPRIO); asm volatile ( - "ldi r18, 1 \n\t" // SE bit - "out 0x33, r18 \n" // SMCR + "ldi r18, 1 \n\t" // SE bit + "out 0x33, r18" // SMCR ); while (TRUE) { - asm volatile ("sleep\n\t"); + asm volatile ("sleep"); } } -- cgit v1.2.3 From 62645922467a2c748bf081b7eefb6ad775675418 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Oct 2007 17:01:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@46 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/main.c | 41 +++++++++++++++++++++++++++-------------- 2 files changed, 28 insertions(+), 15 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index b69ae8780..2c8616b80 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -77,7 +77,7 @@ TSRC = ASMSRC = crt0.s chcore2.s # List all user directories here -UINCDIR = ../../src/include ../../ports/ARM7-LPC214x/GCC +UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 5db6815fb..564c03bfc 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -22,6 +22,7 @@ #include "lpc214x.h" #include "lpc214x_serial.h" #include "buzzer.h" +#include "evtimer.h" static BYTE8 waThread1[UserStackSize(32)]; @@ -53,24 +54,36 @@ static t_msg Thread2(void *arg) { return 0; } +static void TimerHandler(t_eventid id) { + + t_msg TestThread(void *p); + + if (!(IO0PIN & 0x00018000)) { // Both buttons + TestThread(&COM1); + PlaySound(500, 100); + } + else { + if (!(IO0PIN & 0x00008000)) // Button 1 + PlaySound(1000, 100); + if (!(IO0PIN & 0x00010000)) // Button 2 + chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + } +} + static BYTE8 waThread3[UserStackSize(64)]; +static EvTimer evt; +static t_evhandler evhndl[1] = { + TimerHandler +}; static t_msg Thread3(void *arg) { - t_msg TestThread(void *p); + struct EventListener el; - while (TRUE) { - if (!(IO0PIN & 0x00018000)) { - TestThread(&COM1); - PlaySound(500, 100); - } - else { - if (!(IO0PIN & 0x00008000)) // Button 1 - PlaySound(1000, 100); - if (!(IO0PIN & 0x00010000)) // Button 2 - chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); - } - chThdSleep(500); - } + evtInit(&evt, 500); + evtRegister(&evt, &el, 0); + evtStart(&evt); + while (TRUE) + chEvtWait(ALL_EVENTS, evhndl); return 0; } -- cgit v1.2.3 From 73642ca0cce31ed6982813a90b89e4de05da76cb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Oct 2007 06:59:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@48 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MSVS/chcore.c | 3 ++- demos/Win32-MinGW/chcore.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c index 80fd11424..01619f9cd 100644 --- a/demos/Win32-MSVS/chcore.c +++ b/demos/Win32-MSVS/chcore.c @@ -53,7 +53,8 @@ static void ChkIntSources(void) { if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { - chSchRescheduleI(); + if (chSchRescRequiredI()) + chSchDoRescheduleI(); return; } diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 4f677b929..ee04147e9 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -76,7 +76,8 @@ static void ChkIntSources(void) { if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { - chSchRescheduleI(); + if (chSchRescRequiredI()) + chSchDoRescheduleI(); return; } -- cgit v1.2.3 From 70c86d43ec79032c7172507fc12bf7d78d44a3de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 15 Oct 2007 14:52:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@53 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/buzzer.c | 2 +- demos/ARM7-LPC214x-GCC/chconf.h | 4 ++++ demos/AVR-AT90CANx-GCC/chconf.h | 4 ++++ demos/Win32-MSVS/chconf.h | 4 ++++ demos/Win32-MinGW/chconf.h | 4 ++++ 5 files changed, 17 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index 4700bfb45..b0abf9657 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -69,7 +69,7 @@ void PlaySound(int freq, t_time duration) { chSysLock(); - if (bvt.vt_func) { // If a sound is already being played + if (chVTIsArmedI(&bvt)) { // If a sound is already being played chVTResetI(&bvt); // then aborts it. StopCounter(tc); } diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index da8553399..f4d902a9a 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -51,6 +51,10 @@ * function is included in the kernel.*/ #define CH_USE_RESUME +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + /** Configuration option: if specified then the \p chThdTerminate() * and \p chThdShouldTerminate() functions are included in the kernel.*/ #define CH_USE_TERMINATE diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 0857a1fbd..2c849b3c6 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -52,6 +52,10 @@ * function is included in the kernel.*/ #define CH_USE_RESUME +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + /** Configuration option: if specified then the \p chThdTerminate() * and \p chThdShouldTerminate() functions are included in the kernel.*/ #define CH_USE_TERMINATE diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h index da7fcd266..1aa089575 100644 --- a/demos/Win32-MSVS/chconf.h +++ b/demos/Win32-MSVS/chconf.h @@ -56,6 +56,10 @@ * function is included in the kernel.*/ #define CH_USE_RESUME +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + /** Configuration option: if specified then the \p chThdTerminate() * and \p chThdShouldTerminate() functions are included in the kernel.*/ #define CH_USE_TERMINATE diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 5582ae80a..b7a8acedd 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -56,6 +56,10 @@ * function is included in the kernel.*/ #define CH_USE_RESUME +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + /** Configuration option: if specified then the \p chThdTerminate() * and \p chThdShouldTerminate() functions are included in the kernel.*/ #define CH_USE_TERMINATE -- cgit v1.2.3 From bca8923f622aa26a55b9b9ae834b1094487498c4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 19 Oct 2007 13:00:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@58 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MSVS/ch.vcproj | 3 +++ 1 file changed, 3 insertions(+) (limited to 'demos') diff --git a/demos/Win32-MSVS/ch.vcproj b/demos/Win32-MSVS/ch.vcproj index 8764f059d..26dd9557e 100644 --- a/demos/Win32-MSVS/ch.vcproj +++ b/demos/Win32-MSVS/ch.vcproj @@ -215,6 +215,9 @@ + + -- cgit v1.2.3 From 4674513d38a8872a95a895de05ed6a750c842591 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 23 Oct 2007 18:43:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@59 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 4 ++-- demos/ARM7-LPC214x-GCC/chcore.c | 34 +++++++++++----------------------- demos/AVR-AT90CANx-GCC/chcore.c | 35 ++++++++++++++++++++++++++++++----- demos/AVR-AT90CANx-GCC/main.c | 6 ++++++ 4 files changed, 49 insertions(+), 30 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 2c8616b80..fb9dba78b 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -62,8 +62,8 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c \ - ../../test/test.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ +ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c ../../test/test.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index d06e57657..e0de6fc02 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -20,7 +20,9 @@ #include #include "lpc214x.h" +#include "vic.h" #include "lpc214x_serial.h" + #include "buzzer.h" extern void IrqHandler(void); @@ -62,7 +64,6 @@ extern void T0IrqHandler(void); * NOTE: Interrupts are still disabled. */ void hwinit(void) { - int i; /* * All peripherals clock disabled by default in order to save power. @@ -110,17 +111,9 @@ void hwinit(void) { /* * Interrupt vectors assignment. - * NOTE: Better reset everything in the VIC, it is a HUGE source of trouble. */ - VIC *vic = VICBase; - vic->VIC_IntSelect = 0; - vic->VIC_IntEnable = 0; - vic->VIC_VectAddr = 0; - for (i = 0; i < 16; i++) { - vic->VIC_VectCntls[i] = 0; - vic->VIC_VectAddrs[i] = 0; - } - vic->VIC_DefVectAddr = (IOREG32)IrqHandler; + InitVIC(); + VICDefVectAddr = (IOREG32)IrqHandler; SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); @@ -128,7 +121,7 @@ void hwinit(void) { /* * System Timer initialization, 1ms intervals. */ - vic->VIC_IntEnable |= INTMASK(SOURCE_Timer0); + VICIntEnable = INTMASK(SOURCE_Timer0); TC *timer = T0Base; timer->TC_PR = VAL_TC0_PRESCALER; timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); @@ -167,21 +160,12 @@ void chSysHalt(void) { ; } -/* - * Set a vector for an interrupt source, the vector is enabled too. - */ -void SetVICVector(void *handler, int vector, int source) { - - VIC *vicp = VICBase; - vicp->VIC_VectAddrs[vector] = (IOREG32)handler; - vicp->VIC_VectCntls[vector] = (IOREG32)(source | 0x20); -} - /* * Undefined Instruction exception handler. * Yellow LED + RED LED 2. */ void UndHandler(void) { + IO0SET = 0x80000C00; IO0CLR = 0x80000800; while(TRUE) @@ -193,6 +177,7 @@ void UndHandler(void) { * Yellow LED + RED LED 1. */ void PrefetchHandler(void) { + IO0SET = 0x80000C00; IO0CLR = 0x80000400; while(TRUE) @@ -204,6 +189,7 @@ void PrefetchHandler(void) { * Yellow LED + both RED LEDs. */ void AbortHandler(void) { + IO0SET = 0x80000C00; IO0CLR = 0x80000C00; while(TRUE) @@ -214,6 +200,7 @@ void AbortHandler(void) { * Non-vectored IRQs handling here. */ void NonVectoredIrq(void) { + VICVectAddr = 0; } @@ -221,7 +208,8 @@ void NonVectoredIrq(void) { * Timer 0 IRQ handling here. */ void Timer0Irq(void) { - chSchTimerHandlerI(); + T0IR = 1; /* Clear interrupt on match MR0. */ VICVectAddr = 0; + chSchTimerHandlerI(); } diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c index 85dff271f..9d2e0e1b2 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.c +++ b/demos/AVR-AT90CANx-GCC/chcore.c @@ -19,16 +19,41 @@ #include +#include + +void hwinit(void) { + + /* + * I/O ports setup. + * Everything configured as input with pull-up initially. + */ + DDRA = 0; + PORTA = 0xFF; + DDRB = 0; + PORTB = 0xFF; + DDRC = 0; + PORTC = 0xFF; + DDRD = 0; + PORTD = 0xFF; + DDRE = 0; + PORTE = 0xFF; + DDRF = 0; + PORTF = 0xFF; + DDRG = 0; + PORTG = 0xFF; + + /* + * Enables Idle mode for SLEEP instruction. + */ + SMCR = 1; +} + void chSysPause(void) { chThdSetPriority(IDLEPRIO); - asm volatile ( - "ldi r18, 1 \n\t" // SE bit - "out 0x33, r18" // SMCR - ); while (TRUE) { - asm volatile ("sleep"); +// asm volatile ("sleep"); } } diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 2c04d82dc..48f58d080 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -19,6 +19,10 @@ #include +#include + +void hwinit(void); + static BYTE8 waThread1[UserStackSize(32)]; static t_msg Thread1(void *arg) { @@ -31,6 +35,8 @@ static t_msg Thread1(void *arg) { int main(int argc, char **argv) { + hwinit(); + chSysInit(); chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); chSysPause(); -- cgit v1.2.3 From f021c6fe95603891a9da63b04791e2e934555ec7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 25 Oct 2007 15:36:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@65 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chcore.c | 92 ++++++++++++++++++++++++++++++++++------- 1 file changed, 77 insertions(+), 15 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c index 9d2e0e1b2..ed9d90d01 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.c +++ b/demos/AVR-AT90CANx-GCC/chcore.c @@ -21,26 +21,88 @@ #include +/* + * All inputs with pullups. + */ +#define VAL_DDRA 0x00 +#define VAL_PORTA 0xFF + +/* + * All inputs with pullups. + */ +#define VAL_DDRB 0x00 +#define VAL_PORTB 0xFF + +/* + * All inputs with pullups. + */ +#define VAL_DDRC 0x00 +#define VAL_PORTC 0xFF + +/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 + * IN IN OUT IN OUT IN IN IN + * DDRD 0 0 1 0 1 0 0 0 + * PU HiZ VAL PU VAL HiZ HiZ HiZ + * PORTD 1 0 ?1 1 1 0 0 0 + */ +#define VAL_DDRD 0x28 +#define VAL_PORTD 0xB8 + +/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0 + * IN IN IN OUT IN IN OUT IN + * DDRE 0 0 0 1 0 0 1 0 + * PU PU HiZ VAL PU PU VAL HiZ + * PORTE 1 1 0 1 1 1 1 0 + */ +#define VAL_DDRE 0x12 +#define VAL_PORTE 0xDE + +/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 + * x x x x IN IN IN IN + * DDRF 0 0 0 0 0 0 0 0 + * x x x x PU PU PU PU + * PORTF 0 0 0 0 1 1 1 1 + * + */ +#define VAL_DDRF 0x00 +#define VAL_PORTF 0x0F + +/* x x x x x PG2 PG1 PG0 + * x x x x x IN IN IN + * DDRG 0 0 0 0 0 0 0 0 + * x x x x x PU PU PU + * PORTG 0 0 0 0 0 1 1 1 + * + */ +#define VAL_DDRG 0x00 +#define VAL_PORTG 0x07 + void hwinit(void) { /* * I/O ports setup. - * Everything configured as input with pull-up initially. */ - DDRA = 0; - PORTA = 0xFF; - DDRB = 0; - PORTB = 0xFF; - DDRC = 0; - PORTC = 0xFF; - DDRD = 0; - PORTD = 0xFF; - DDRE = 0; - PORTE = 0xFF; - DDRF = 0; - PORTF = 0xFF; - DDRG = 0; - PORTG = 0xFF; + DDRA = VAL_DDRA; + PORTA = VAL_PORTA; + DDRB = VAL_DDRB; + PORTB = VAL_PORTB; + DDRC = VAL_DDRC; + PORTC = VAL_PORTC; + DDRD = VAL_DDRD; + PORTD = VAL_PORTD; + DDRE = VAL_DDRE; + PORTE = VAL_PORTE; + DDRF = VAL_DDRF; + PORTF = VAL_PORTF; + DDRG = VAL_DDRG; + PORTG = VAL_PORTG; + + /* + * External interrupts setup, all disabled initially. + */ + EICRA = 0x00; + EICRB = 0x00; + EIMSK = 0x00; /* * Enables Idle mode for SLEEP instruction. -- cgit v1.2.3 From fb49ce4f3aae2a481be29d030b26a1485d6227de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Oct 2007 15:08:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@66 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chconf.h | 4 ++-- demos/AVR-AT90CANx-GCC/chcore.c | 47 +++++++++++++++++++++++++--------------- demos/AVR-AT90CANx-GCC/chcore.h | 10 +++++++-- demos/AVR-AT90CANx-GCC/chcore2.S | 9 +++++++- 4 files changed, 47 insertions(+), 23 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 2c849b3c6..63a391e08 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -138,11 +138,11 @@ /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 100 +#define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the * threads before preemption occurs.*/ -#define CH_TIME_QUANTUM 10 +#define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the * global \p currp variable. Caching this variable in a register can greatly diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c index ed9d90d01..262732676 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.c +++ b/demos/AVR-AT90CANx-GCC/chcore.c @@ -82,32 +82,43 @@ void hwinit(void) { /* * I/O ports setup. */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; + DDRA = VAL_DDRA; + PORTA = VAL_PORTA; + DDRB = VAL_DDRB; + PORTB = VAL_PORTB; + DDRC = VAL_DDRC; + PORTC = VAL_PORTC; + DDRD = VAL_DDRD; + PORTD = VAL_PORTD; + DDRE = VAL_DDRE; + PORTE = VAL_PORTE; + DDRF = VAL_DDRF; + PORTF = VAL_PORTF; + DDRG = VAL_DDRG; + PORTG = VAL_PORTG; /* * External interrupts setup, all disabled initially. */ - EICRA = 0x00; - EICRB = 0x00; - EIMSK = 0x00; + EICRA = 0x00; + EICRB = 0x00; + EIMSK = 0x00; /* * Enables Idle mode for SLEEP instruction. */ - SMCR = 1; + SMCR = 1; + + /* + * Timer 0 setup. + */ + TCCR0A = (1 << WGM01) | (0 << WGM00) | // CTC mode. + (0 << COM0A1) | (0 << COM0A0) | // OC0A disabled (normal I/O). + (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. + OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; + TCNT0 = 0; // Reset counter. + TIFR0 = (1 << OCF0A); // Reset pending (if any). + TIMSK0 = (1 << OCIE0A); // Interrupt on compare. } void chSysPause(void) { diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h index 799742f47..c3e0cfa34 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.h +++ b/demos/AVR-AT90CANx-GCC/chcore.h @@ -79,8 +79,13 @@ typedef struct { /** * Platform dependent part of the \p chThdCreate() API. */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.sp--; \ + tp->p_ctx.sp->r2 = (int)pf; \ + tp->p_ctx.sp->r3 = (int)pf >> 8; \ + tp->p_ctx.sp->r4 = (int)arg; \ + tp->p_ctx.sp->r5 = (int)arg >> 8; \ + tp->p_ctx.sp->pc = (UWORD16)threadstart; \ } /* @@ -100,6 +105,7 @@ typedef struct { void chSysHalt(void) __attribute__((noreturn)) ; void chSysPause(void) __attribute__((noreturn)) ; void chSysSwitchI(Context *oldp, Context *newp); +void threadstart(void); #endif /* _CHCORE_H_ */ diff --git a/demos/AVR-AT90CANx-GCC/chcore2.S b/demos/AVR-AT90CANx-GCC/chcore2.S index d438ffb4f..3564de521 100644 --- a/demos/AVR-AT90CANx-GCC/chcore2.S +++ b/demos/AVR-AT90CANx-GCC/chcore2.S @@ -19,6 +19,14 @@ #include +.global threadstart +threadstart: + sei + movw r24, r4 // argument + movw r30, r2 // thread function + icall + call chThdExit + .global chSysSwitchI chSysSwitchI: push r2 @@ -113,4 +121,3 @@ noschd: pop r1 pop r0 reti - -- cgit v1.2.3 From 35dea10cc76722976bfbf368dd50f7617ca86a45 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 30 Oct 2007 10:46:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@69 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 1 + demos/ARM7-LPC214x-GCC/chcore.c | 3 +++ demos/ARM7-LPC214x-GCC/chcore2.s | 10 ++++++++++ 3 files changed, 14 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index fb9dba78b..310124c2a 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -64,6 +64,7 @@ UADEFS = # List ARM-mode C source files here ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c ../../test/test.c \ ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index e0de6fc02..beee2a7ae 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -22,6 +22,7 @@ #include "lpc214x.h" #include "vic.h" #include "lpc214x_serial.h" +#include "lpc214x_ssp.h" #include "buzzer.h" @@ -117,6 +118,7 @@ void hwinit(void) { SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); + SetVICVector(SSPIrqHandler, 3, SOURCE_SPI1); /* * System Timer initialization, 1ms intervals. @@ -133,6 +135,7 @@ void hwinit(void) { * Other subsystems. */ InitSerial(); + InitSSP(); InitBuzzer(); } diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index f734eebba..97a38fdfe 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -155,6 +155,16 @@ UART1IrqHandler: bl UART1Irq b IrqCommon +.globl SSPIrqHandler +SSPIrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} + mrs r0, SPSR // Workaround for ARM7TDMI+VIC + tst r0, #I_BIT // spurious interrupts. + ldmnefd sp!, {r0-r3, r12, pc}^ + bl SSPIrq + b IrqCommon + /* * Common exit point for all IRQ routines, it performs the rescheduling if * required. -- cgit v1.2.3 From 2bca32f80b989a211fb39b7e04ef5834f79fea4a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 31 Oct 2007 15:52:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@71 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.c | 1 - demos/ARM7-LPC214x-GCC/chcore2.s | 10 ---------- demos/ARM7-LPC214x-GCC/main.c | 11 +++++++---- 3 files changed, 7 insertions(+), 15 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index beee2a7ae..9624c5b42 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -118,7 +118,6 @@ void hwinit(void) { SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); - SetVICVector(SSPIrqHandler, 3, SOURCE_SPI1); /* * System Timer initialization, 1ms intervals. diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index 97a38fdfe..f734eebba 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -155,16 +155,6 @@ UART1IrqHandler: bl UART1Irq b IrqCommon -.globl SSPIrqHandler -SSPIrqHandler: - sub lr, lr, #4 - stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc}^ - bl SSPIrq - b IrqCommon - /* * Common exit point for all IRQ routines, it performs the rescheduling if * required. diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 564c03bfc..702a25d98 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -21,6 +21,7 @@ #include "lpc214x.h" #include "lpc214x_serial.h" +#include "lpc214x_ssp.h" #include "buzzer.h" #include "evtimer.h" @@ -55,9 +56,9 @@ static t_msg Thread2(void *arg) { } static void TimerHandler(t_eventid id) { - + static BYTE8 sspbuf[16]; t_msg TestThread(void *p); - + if (!(IO0PIN & 0x00018000)) { // Both buttons TestThread(&COM1); PlaySound(500, 100); @@ -65,8 +66,10 @@ static void TimerHandler(t_eventid id) { else { if (!(IO0PIN & 0x00008000)) // Button 1 PlaySound(1000, 100); - if (!(IO0PIN & 0x00010000)) // Button 2 - chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + if (!(IO0PIN & 0x00010000)) { // Button 2 + sspRW(sspbuf, (BYTE8 *)"Hello World!\r\n", 14); + chFDDWrite(&COM1, sspbuf, 14); + } } } -- cgit v1.2.3 From 72103d892d8c90b54e0c4b863786db4340efd5e1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 1 Nov 2007 09:03:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@72 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 9624c5b42..5ee155eaa 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -42,11 +42,11 @@ extern void T0IrqHandler(void); * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 * * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 SSE MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 L1 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 10 10 10 10 00 - * OUT -- OUT OUT -- -- -- -- -- OUT OUT -- -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 + * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 * * PINSEL2 * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- @@ -55,9 +55,9 @@ extern void T0IrqHandler(void); * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- */ #define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100842A8 +#define VAL_PINSEL1 0x100840A8 #define VAL_PINSEL2 0x00000004 -#define VAL_FIO0DIR 0xB0603C00 +#define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 /* -- cgit v1.2.3 From 097718386bfff7950d358df1caaf26a4468532a1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 1 Nov 2007 11:41:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@74 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 310124c2a..0ee445783 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -62,7 +62,7 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = chcore.c main.c buzzer.c ../../src/lib/evtimer.c ../../test/test.c \ +ASRC = chcore.c main.c buzzer.c mmcsd.c ../../src/lib/evtimer.c ../../test/test.c \ ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ -- cgit v1.2.3 From 5630056259db2dd0c3f0c05072dd1e2d96cd772c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 1 Nov 2007 11:53:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@79 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/mmcsd.c | 97 ++++++++++++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/mmcsd.h | 31 ++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 demos/ARM7-LPC214x-GCC/mmcsd.c create mode 100644 demos/ARM7-LPC214x-GCC/mmcsd.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c new file mode 100644 index 000000000..ee4c2a93f --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -0,0 +1,97 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "lpc214x_ssp.h" + +#include "mmcsd.h" + +static EventSource MMCInsertEventSource; + +void MMCInit(void) { + + chEvtInit(&MMCInsertEventSource); +} + +/* + * Initializes a card after the power up by selecting the SPI mode. + */ +BOOL mmcInit(void) { + + /* + * Starting initialization with slow clock mode. + */ + SetSSP(254, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); + + /* + * SPI mode selection. + */ + sspRW(NULL, NULL, 16); /* 128 clock pulses without ~CS asserted. */ + int i = 0; + while (TRUE) { + chThdSleep(10); + if (mmcSendCommand(0, 0) == 0x01) + break; + if (++i >= CMD0_RETRY) + return TRUE; + } + + /* + * Initialization. + */ + i = 0; + while (TRUE) { + BYTE8 b; + chThdSleep(10); + b = mmcSendCommand(0, 0); + if (b == 0x00) + break; + if (b != 0x01) + return TRUE; + if (++i >= CMD1_RETRY) + return TRUE; + } + + /* + * Full speed. + */ + SetSSP(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); + return FALSE; +} + +/* + * Sends a simple command and returns a R1-type response. + */ +BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg) { + BYTE8 buf[6]; + + buf[0] = 0x40 | cmd; + buf[1] = arg >> 24; + buf[2] = arg >> 16; + buf[3] = arg >> 8; + buf[4] = arg; + buf[5] = 0x95; /* Valid for CMD0 ingnored by other commands. */ + sspAcquireBus(); + sspRW(NULL, buf, 6); + sspRW(buf, NULL, 1); + sspReleaseBus(); + return buf[0]; +} diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h new file mode 100644 index 000000000..40a559955 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _MMCSD_H_ +#define _MMCSD_H_ + +#define CMD0_RETRY 10 +#define CMD1_RETRY 100 + +void MMCInit(void); + +BOOL mmcInit(void); +BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); + +#endif /* _MMCSD_H_*/ -- cgit v1.2.3 From d0cc4f2406f3932312de7908afeb33daf0acc720 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 1 Nov 2007 16:03:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@81 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.c | 2 ++ demos/ARM7-LPC214x-GCC/main.c | 12 ++++++---- demos/ARM7-LPC214x-GCC/mmcsd.c | 51 ++++++++++++++++++++++++++++------------- demos/ARM7-LPC214x-GCC/mmcsd.h | 2 +- 4 files changed, 46 insertions(+), 21 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 5ee155eaa..128fb97aa 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -23,6 +23,7 @@ #include "vic.h" #include "lpc214x_serial.h" #include "lpc214x_ssp.h" +#include "mmcsd.h" #include "buzzer.h" @@ -135,6 +136,7 @@ void hwinit(void) { */ InitSerial(); InitSSP(); + InitMMC(); InitBuzzer(); } diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 702a25d98..9e0a4222c 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -21,7 +21,8 @@ #include "lpc214x.h" #include "lpc214x_serial.h" -#include "lpc214x_ssp.h" +//#include "lpc214x_ssp.h" +#include "mmcsd.h" #include "buzzer.h" #include "evtimer.h" @@ -56,7 +57,7 @@ static t_msg Thread2(void *arg) { } static void TimerHandler(t_eventid id) { - static BYTE8 sspbuf[16]; +// static BYTE8 sspbuf[16]; t_msg TestThread(void *p); if (!(IO0PIN & 0x00018000)) { // Both buttons @@ -67,8 +68,11 @@ static void TimerHandler(t_eventid id) { if (!(IO0PIN & 0x00008000)) // Button 1 PlaySound(1000, 100); if (!(IO0PIN & 0x00010000)) { // Button 2 - sspRW(sspbuf, (BYTE8 *)"Hello World!\r\n", 14); - chFDDWrite(&COM1, sspbuf, 14); +// sspRW(sspbuf, (BYTE8 *)"Hello World!\r\n", 14); +// chFDDWrite(&COM1, sspbuf, 14); + chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + if (!mmcInit()) + PlaySound(2000, 500); } } } diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index ee4c2a93f..1c0d5c7d8 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -26,7 +26,7 @@ static EventSource MMCInsertEventSource; -void MMCInit(void) { +void InitMMC(void) { chEvtInit(&MMCInsertEventSource); } @@ -47,11 +47,11 @@ BOOL mmcInit(void) { sspRW(NULL, NULL, 16); /* 128 clock pulses without ~CS asserted. */ int i = 0; while (TRUE) { - chThdSleep(10); if (mmcSendCommand(0, 0) == 0x01) break; if (++i >= CMD0_RETRY) return TRUE; + chThdSleep(10); } /* @@ -59,15 +59,14 @@ BOOL mmcInit(void) { */ i = 0; while (TRUE) { - BYTE8 b; - chThdSleep(10); - b = mmcSendCommand(0, 0); + BYTE8 b = mmcSendCommand(1, 0); if (b == 0x00) break; if (b != 0x01) return TRUE; if (++i >= CMD1_RETRY) return TRUE; + chThdSleep(10); } /* @@ -77,21 +76,41 @@ BOOL mmcInit(void) { return FALSE; } +static void sendhdr(BYTE8 cmd, ULONG32 arg) { + BYTE8 buf[8]; + + buf[0] = 0xFF; + buf[1] = 0x40 | cmd; + buf[2] = arg >> 24; + buf[3] = arg >> 16; + buf[4] = arg >> 8; + buf[5] = arg; + buf[6] = 0x95; /* Valid for CMD0 ingnored by other commands. */ + buf[7] = 0xFF; + sspRW(NULL, buf, 8); +} + +static BYTE8 recvr1(void) { + int i; + BYTE8 r1[1]; + + for (i = 0; i < 8; i++) { + sspRW(r1, NULL, 1); + if (r1[0] != 0xFF) + return r1[0]; + } + return 0xFF; +} + /* * Sends a simple command and returns a R1-type response. */ BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg) { - BYTE8 buf[6]; - - buf[0] = 0x40 | cmd; - buf[1] = arg >> 24; - buf[2] = arg >> 16; - buf[3] = arg >> 8; - buf[4] = arg; - buf[5] = 0x95; /* Valid for CMD0 ingnored by other commands. */ + BYTE8 r1; + sspAcquireBus(); - sspRW(NULL, buf, 6); - sspRW(buf, NULL, 1); + sendhdr(cmd, arg); + r1 = recvr1(); sspReleaseBus(); - return buf[0]; + return r1; } diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index 40a559955..4c9f1d643 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -23,7 +23,7 @@ #define CMD0_RETRY 10 #define CMD1_RETRY 100 -void MMCInit(void); +void InitMMC(void); BOOL mmcInit(void); BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); -- cgit v1.2.3 From 50cd4e00ef4614552dba01b865688c66629e1958 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 2 Nov 2007 15:34:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@82 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/main.c | 19 +++-- demos/ARM7-LPC214x-GCC/mmcsd.c | 180 ++++++++++++++++++++++++++++++++++------- demos/ARM7-LPC214x-GCC/mmcsd.h | 21 +++++ 3 files changed, 185 insertions(+), 35 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 9e0a4222c..614020271 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -21,7 +21,6 @@ #include "lpc214x.h" #include "lpc214x_serial.h" -//#include "lpc214x_ssp.h" #include "mmcsd.h" #include "buzzer.h" #include "evtimer.h" @@ -56,8 +55,9 @@ static t_msg Thread2(void *arg) { return 0; } +static BYTE8 rwbuf[512]; + static void TimerHandler(t_eventid id) { -// static BYTE8 sspbuf[16]; t_msg TestThread(void *p); if (!(IO0PIN & 0x00018000)) { // Both buttons @@ -68,16 +68,21 @@ static void TimerHandler(t_eventid id) { if (!(IO0PIN & 0x00008000)) // Button 1 PlaySound(1000, 100); if (!(IO0PIN & 0x00010000)) { // Button 2 -// sspRW(sspbuf, (BYTE8 *)"Hello World!\r\n", 14); -// chFDDWrite(&COM1, sspbuf, 14); + MMCCSD data; + chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); - if (!mmcInit()) - PlaySound(2000, 500); + if (mmcInit()) + return; + if (mmcGetSize(&data)) + return; + if (mmcBlockRead(0x200000, rwbuf)) + return; + PlaySound(2000, 100); } } } -static BYTE8 waThread3[UserStackSize(64)]; +static BYTE8 waThread3[UserStackSize(128)]; static EvTimer evt; static t_evhandler evhndl[1] = { TimerHandler diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 1c0d5c7d8..7867782c9 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -26,11 +26,64 @@ static EventSource MMCInsertEventSource; +/* + * Subsystem initialization. + */ void InitMMC(void) { chEvtInit(&MMCInsertEventSource); } +static void sendhdr(BYTE8 cmd, ULONG32 arg) { + BYTE8 buf[6]; + + /* + * Wait for the bus to become idle if a write operation was in progress. + */ + while (TRUE) { + sspRW(buf, NULL, 1); + if (buf[0] == 0xFF) + break; +#ifdef NICE_WAITING + chThdSleep(1); /* Trying to be nice with the other threads.*/ +#endif + } + + buf[0] = 0x40 | cmd; + buf[1] = arg >> 24; + buf[2] = arg >> 16; + buf[3] = arg >> 8; + buf[4] = arg; + buf[5] = 0x95; /* Valid for CMD0 ingnored by other commands. */ + sspRW(NULL, buf, 6); +} + +static BYTE8 recvr1(void) { + int i; + BYTE8 r1[1]; + + for (i = 0; i < 9; i++) { + sspRW(r1, NULL, 1); + if (r1[0] != 0xFF) + return r1[0]; + } + return 0xFF; /* Timeout.*/ +} + +static BOOL getdata(BYTE8 *buf, ULONG32 n) { + int i; + + for (i = 0; i < MMC_WAIT_DATA; i++) { + sspRW(buf, NULL, 1); + if (buf[0] == 0xFE) { + sspRW(buf, NULL, n); + sspRW(NULL, NULL, 2); /* CRC ignored.*/ + return FALSE; + } + } + return TRUE; /* Timeout.*/ +} + /* * Initializes a card after the power up by selecting the SPI mode. */ @@ -47,7 +100,7 @@ BOOL mmcInit(void) { sspRW(NULL, NULL, 16); /* 128 clock pulses without ~CS asserted. */ int i = 0; while (TRUE) { - if (mmcSendCommand(0, 0) == 0x01) + if (mmcSendCommand(CMDGOIDLE, 0) == 0x01) break; if (++i >= CMD0_RETRY) return TRUE; @@ -59,7 +112,7 @@ BOOL mmcInit(void) { */ i = 0; while (TRUE) { - BYTE8 b = mmcSendCommand(1, 0); + BYTE8 b = mmcSendCommand(CMDINIT, 0); if (b == 0x00) break; if (b != 0x01) @@ -76,32 +129,6 @@ BOOL mmcInit(void) { return FALSE; } -static void sendhdr(BYTE8 cmd, ULONG32 arg) { - BYTE8 buf[8]; - - buf[0] = 0xFF; - buf[1] = 0x40 | cmd; - buf[2] = arg >> 24; - buf[3] = arg >> 16; - buf[4] = arg >> 8; - buf[5] = arg; - buf[6] = 0x95; /* Valid for CMD0 ingnored by other commands. */ - buf[7] = 0xFF; - sspRW(NULL, buf, 8); -} - -static BYTE8 recvr1(void) { - int i; - BYTE8 r1[1]; - - for (i = 0; i < 8; i++) { - sspRW(r1, NULL, 1); - if (r1[0] != 0xFF) - return r1[0]; - } - return 0xFF; -} - /* * Sends a simple command and returns a R1-type response. */ @@ -114,3 +141,100 @@ BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg) { sspReleaseBus(); return r1; } + +/* + * Reads the card info record. + * @param data the pointer to a \p MMCCSD structure + * @return \p TRUE if an error happened + */ +BOOL mmcGetSize(MMCCSD *data) { + BYTE8 buf[16]; + + sspAcquireBus(); + sendhdr(CMDREADCSD, 0); + if (recvr1() != 0x00) { + sspReleaseBus(); + return TRUE; + } + if (getdata(buf, 16)) { + sspReleaseBus(); + return TRUE; + } + sspReleaseBus(); + + /* csize * multiplier */ + data->csize = (((buf[6] & 3) << 10) | (buf[7] << 2) | (buf[8] >> 6)) * + (1 << (2 + (((buf[9] & 3) << 1) | (buf[10] >> 7)))); + data->rdblklen = 1 << (buf[5] & 15); + return FALSE; +} + +/* + * Reads a block. + * @param blknum the block number + * @param buf the pointer to the read buffer + * @return \p TRUE if an error happened + */ +BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf) { + + sspAcquireBus(); + sendhdr(CMDREAD, blknum << 8); + if (recvr1() != 0x00) { + sspReleaseBus(); + return TRUE; + } + if (getdata(buf, 512)) { + sspReleaseBus(); + return TRUE; + } + sspReleaseBus(); + return FALSE; +} + +/* + * Writes a block. + * @param blknum the block number + * @param buf the pointer to the write buffer + * @return \p TRUE if an error happened + * @note The function DOES NOT wait for the SPI bus to become free after + * sending the data, the bus check is done before sending commands to + * the card, this allows to not make useless busy waiting. The invoking + * thread can do other things while the data is being written. + */ +BOOL mmcBlockWrite(ULONG32 blknum, BYTE8 *buf) { + static BYTE8 start[] = {0xFF, 0xFE}; + BYTE8 b[4]; + + sspAcquireBus(); + sendhdr(CMDWRITE, blknum << 8); + if (recvr1() != 0x00) { + sspReleaseBus(); + return TRUE; + } + sspRW(NULL, start, 2); /* Data prologue.*/ + sspRW(NULL, buf, 512); /* Data.*/ + sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ + sspRW(b, NULL, 1); + sspReleaseBus(); + if ((b[0] & 0x1E) != 0x05) + return TRUE; + return FALSE; +} + +/* + * Makes sure that pending operations are completed before returning. + */ +void mmcSynch(void) { + BYTE8 buf[4]; + + sspAcquireBus(); + while (TRUE) { + sspRW(buf, NULL, 1); + if (buf[0] == 0xFF) + break; +#ifdef NICE_WAITING + chThdSleep(1); /* Trying to be nice with the other threads.*/ +#endif + } + sspReleaseBus(); +} diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index 4c9f1d643..047fd0fb2 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -20,12 +20,33 @@ #ifndef _MMCSD_H_ #define _MMCSD_H_ +#define NICE_WAITING + +/* Following times are 10mS units.*/ #define CMD0_RETRY 10 #define CMD1_RETRY 100 +/* Byte transfer time units.*/ +#define MMC_WAIT_DATA 10000 + +#define CMDGOIDLE 0 +#define CMDINIT 1 +#define CMDREADCSD 9 +#define CMDREAD 17 +#define CMDWRITE 24 + +typedef struct { + ULONG32 csize; + ULONG32 rdblklen; +} MMCCSD; + void InitMMC(void); BOOL mmcInit(void); BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); +BOOL mmcGetSize(MMCCSD *data); +BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf); +BOOL mmcBlockWrite(ULONG32 blknum, BYTE8 *buf); +void mmcSynch(void); #endif /* _MMCSD_H_*/ -- cgit v1.2.3 From aece9ea5fcc12bc2ac7178bb231c9b7084518ff3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Nov 2007 16:25:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@83 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/buzzer.c | 10 ++++++++ demos/ARM7-LPC214x-GCC/buzzer.h | 1 + demos/ARM7-LPC214x-GCC/main.c | 44 ++++++++++++++++++++++----------- demos/ARM7-LPC214x-GCC/mmcsd.c | 55 ++++++++++++++++++++++++++++++++++++++++- demos/ARM7-LPC214x-GCC/mmcsd.h | 21 ++++++++++------ 5 files changed, 108 insertions(+), 23 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index b0abf9657..a93bafa98 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -80,3 +80,13 @@ void PlaySound(int freq, t_time duration) { chSysUnlock(); } + +void PlaySoundWait(int freq, t_time duration) { + TC *tc = T1Base; + + StopCounter(tc); + tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); + StartCounter(tc); + chThdSleep(duration); + StopCounter(tc); +} \ No newline at end of file diff --git a/demos/ARM7-LPC214x-GCC/buzzer.h b/demos/ARM7-LPC214x-GCC/buzzer.h index 3334d8b5c..f5f9e82ac 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.h +++ b/demos/ARM7-LPC214x-GCC/buzzer.h @@ -22,6 +22,7 @@ void InitBuzzer(void); void PlaySound(int freq, t_time duration); +void PlaySoundWait(int freq, t_time duration); extern EventSource BuzzerSilentEventSource; diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 614020271..9677918fd 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -55,8 +55,6 @@ static t_msg Thread2(void *arg) { return 0; } -static BYTE8 rwbuf[512]; - static void TimerHandler(t_eventid id) { t_msg TestThread(void *p); @@ -68,32 +66,50 @@ static void TimerHandler(t_eventid id) { if (!(IO0PIN & 0x00008000)) // Button 1 PlaySound(1000, 100); if (!(IO0PIN & 0x00010000)) { // Button 2 - MMCCSD data; - chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); - if (mmcInit()) - return; - if (mmcGetSize(&data)) - return; - if (mmcBlockRead(0x200000, rwbuf)) - return; PlaySound(2000, 100); } } } +static void InsertHandler(t_eventid id) { + static BYTE8 rwbuf[512]; + MMCCSD data; + + PlaySoundWait(1000, 100); + PlaySoundWait(2000, 100); + if (mmcInit()) + return; + /* Card ready, do stuff.*/ + if (mmcGetSize(&data)) + return; + if (mmcBlockRead(0x200000, rwbuf)) + return; +} + +static void RemoveHandler(t_eventid id) { + + PlaySoundWait(2000, 100); + PlaySoundWait(1000, 100); +} + static BYTE8 waThread3[UserStackSize(128)]; static EvTimer evt; -static t_evhandler evhndl[1] = { - TimerHandler +static t_evhandler evhndl[] = { + TimerHandler, + InsertHandler, + RemoveHandler }; static t_msg Thread3(void *arg) { - struct EventListener el; + struct EventListener el0, el1, el2; evtInit(&evt, 500); - evtRegister(&evt, &el, 0); evtStart(&evt); + mmcStartPolling(); + evtRegister(&evt, &el0, 0); + chEvtRegister(&MMCInsertEventSource, &el1, 1); + chEvtRegister(&MMCRemoveEventSource, &el2, 2); while (TRUE) chEvtWait(ALL_EVENTS, evhndl); return 0; diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 7867782c9..fb1c5c650 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -24,7 +24,10 @@ #include "mmcsd.h" -static EventSource MMCInsertEventSource; +EventSource MMCInsertEventSource, MMCRemoveEventSource; + +static VirtualTimer vt; +static int cnt; /* * Subsystem initialization. @@ -32,6 +35,56 @@ static EventSource MMCInsertEventSource; void InitMMC(void) { chEvtInit(&MMCInsertEventSource); + chEvtInit(&MMCRemoveEventSource); + cnt = POLLING_INTERVAL; +} + +void tmrfunc(void *par) { + + if (cnt) { + if (!(IO1PIN & (1 << 25))) { + if (!--cnt) + chEvtSendI(&MMCInsertEventSource); + } + else + cnt = POLLING_INTERVAL; + } + else { + if (IO1PIN & (1 << 25)) { + cnt = POLLING_INTERVAL; + chEvtSendI(&MMCRemoveEventSource); + } + } + chVTSetI(&vt, 10, tmrfunc, NULL); +} + +void mmcStartPolling(void) { + + chSysLock(); + + if (!chVTIsArmedI(&vt)) { + chVTSetI(&vt, 10, tmrfunc, NULL); + cnt = POLLING_INTERVAL; + } + + chSysUnlock(); +} + +void mmcStopPolling(void) { + + chSysLock(); + + if (chVTIsArmedI(&vt)) { + chVTResetI(&vt); + cnt = POLLING_INTERVAL; + } + + chSysUnlock(); +} + +BOOL mmcCardInserted (void) { + + return cnt == 0; } static void sendhdr(BYTE8 cmd, ULONG32 arg) { diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index 047fd0fb2..142d5f1a6 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -23,26 +23,31 @@ #define NICE_WAITING /* Following times are 10mS units.*/ -#define CMD0_RETRY 10 -#define CMD1_RETRY 100 +#define CMD0_RETRY 10 +#define CMD1_RETRY 100 +#define POLLING_INTERVAL 10 /* Byte transfer time units.*/ -#define MMC_WAIT_DATA 10000 +#define MMC_WAIT_DATA 10000 -#define CMDGOIDLE 0 -#define CMDINIT 1 -#define CMDREADCSD 9 -#define CMDREAD 17 -#define CMDWRITE 24 +#define CMDGOIDLE 0 +#define CMDINIT 1 +#define CMDREADCSD 9 +#define CMDREAD 17 +#define CMDWRITE 24 typedef struct { ULONG32 csize; ULONG32 rdblklen; } MMCCSD; +extern EventSource MMCInsertEventSource, MMCRemoveEventSource; + void InitMMC(void); BOOL mmcInit(void); +void mmcStartPolling(void); +void mmcStopPolling(void); BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); BOOL mmcGetSize(MMCCSD *data); BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf); -- cgit v1.2.3 From 8b1e399085a166ba91f012d5b057ee4cd1f8bfc0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Nov 2007 17:01:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@84 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/mmcsd.h | 1 + 1 file changed, 1 insertion(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index 142d5f1a6..a071075bb 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -48,6 +48,7 @@ void InitMMC(void); BOOL mmcInit(void); void mmcStartPolling(void); void mmcStopPolling(void); +BOOL mmcCardInserted (void); BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); BOOL mmcGetSize(MMCCSD *data); BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf); -- cgit v1.2.3 From 48cdf91217fd6460628315a63ccc9e87de21c193 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 4 Nov 2007 12:43:01 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@85 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/main.c | 3 +- demos/ARM7-LPC214x-GCC/mmcsd.c | 119 ++++++++++++++++++++++++++++++++++++----- demos/ARM7-LPC214x-GCC/mmcsd.h | 12 +++-- 3 files changed, 116 insertions(+), 18 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 9677918fd..fbd4f2726 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -83,8 +83,9 @@ static void InsertHandler(t_eventid id) { /* Card ready, do stuff.*/ if (mmcGetSize(&data)) return; - if (mmcBlockRead(0x200000, rwbuf)) + if (mmcRead(rwbuf, 0)) return; + PlaySound(440, 200); } static void RemoveHandler(t_eventid id) { diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index fb1c5c650..8723d8d96 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -58,6 +58,9 @@ void tmrfunc(void *par) { chVTSetI(&vt, 10, tmrfunc, NULL); } +/* + * Starts the card polling service. + */ void mmcStartPolling(void) { chSysLock(); @@ -70,6 +73,9 @@ void mmcStartPolling(void) { chSysUnlock(); } +/* + * Stops the card polling service. + */ void mmcStopPolling(void) { chSysLock(); @@ -82,17 +88,24 @@ void mmcStopPolling(void) { chSysUnlock(); } +/* + * Returns TRUE if the card is safely inserted in the reader. + */ BOOL mmcCardInserted (void) { return cnt == 0; } -static void sendhdr(BYTE8 cmd, ULONG32 arg) { - BYTE8 buf[6]; +static void wait(void) { + int i; + BYTE8 buf[4]; - /* - * Wait for the bus to become idle if a write operation was in progress. - */ + for (i = 0; i < 16; i++) { + sspRW(buf, NULL, 1); + if (buf[0] == 0xFF) + break; + } + /* Looks like it is a loooong wait.*/ while (TRUE) { sspRW(buf, NULL, 1); if (buf[0] == 0xFF) @@ -101,6 +114,15 @@ static void sendhdr(BYTE8 cmd, ULONG32 arg) { chThdSleep(1); /* Trying to be nice with the other threads.*/ #endif } +} + +static void sendhdr(BYTE8 cmd, ULONG32 arg) { + BYTE8 buf[6]; + + /* + * Wait for the bus to become idle if a write operation was in progress. + */ + wait(); buf[0] = 0x40 | cmd; buf[1] = arg >> 24; @@ -228,7 +250,7 @@ BOOL mmcGetSize(MMCCSD *data) { * @param buf the pointer to the read buffer * @return \p TRUE if an error happened */ -BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf) { +BOOL mmcRead(BYTE8 *buf, ULONG32 blknum) { sspAcquireBus(); sendhdr(CMDREAD, blknum << 8); @@ -244,6 +266,39 @@ BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf) { return FALSE; } +/* + * Reads multiple blocks. + * @param blknum the initial block + * @param n the number of blocks + * @param buf the pointer to the read buffer + * @return \p TRUE if an error happened + */ +BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { + static const BYTE8 stopcmd[] = {0x40 | CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; + + sspAcquireBus(); + sendhdr(CMDREADMULTIPLE, blknum << 8); + if (recvr1() != 0x00) { + sspReleaseBus(); + return TRUE; + } + while (n) { + if (getdata(buf, 512)) { + sspReleaseBus(); + return TRUE; + } + buf += 512; + n--; + } + sspRW(NULL, (BYTE8 *)stopcmd, sizeof(stopcmd)); + if (recvr1() != 0x00) { + sspReleaseBus(); + return TRUE; + } + sspReleaseBus(); + return FALSE; +} + /* * Writes a block. * @param blknum the block number @@ -254,8 +309,8 @@ BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf) { * the card, this allows to not make useless busy waiting. The invoking * thread can do other things while the data is being written. */ -BOOL mmcBlockWrite(ULONG32 blknum, BYTE8 *buf) { - static BYTE8 start[] = {0xFF, 0xFE}; +BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum) { + static const BYTE8 start[] = {0xFF, 0xFE}; BYTE8 b[4]; sspAcquireBus(); @@ -264,13 +319,53 @@ BOOL mmcBlockWrite(ULONG32 blknum, BYTE8 *buf) { sspReleaseBus(); return TRUE; } - sspRW(NULL, start, 2); /* Data prologue.*/ - sspRW(NULL, buf, 512); /* Data.*/ - sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ + sspRW(NULL, (BYTE8 *)start, 2); /* Data prologue.*/ + sspRW(NULL, buf, 512); /* Data.*/ + sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ sspRW(b, NULL, 1); sspReleaseBus(); - if ((b[0] & 0x1E) != 0x05) + if ((b[0] & 0x1F) != 0x05) + return TRUE; + return FALSE; +} + +/* + * Writes multiple blocks. + * @param blknum the initial block + * @param n the number of blocks + * @param buf the pointer to the write buffer + * @return \p TRUE if an error happened + * @note The function DOES NOT wait for the SPI bus to become free after + * sending the data, the bus check is done before sending commands to + * the card, this allows to not make useless busy waiting. The invoking + * thread can do other things while the data is being written. + */ +BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { + static const BYTE8 start[] = {0xFF, 0xFC}, + stop[] = {0xFD, 0xFF}; + BYTE8 b[4]; + + sspAcquireBus(); + sendhdr(CMDWRITEMULTIPLE, blknum << 8); + if (recvr1() != 0x00) { + sspReleaseBus(); return TRUE; + } + while (n) { + sspRW(NULL, (BYTE8 *)start, sizeof(start)); /* Data prologue.*/ + sspRW(NULL, buf, 512); /* Data.*/ + sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ + sspRW(b, NULL, 1); + if ((b[0] & 0x1F) != 0x05) { + sspReleaseBus(); + return TRUE; + } + wait(); + buf += 512; + n--; + } + sspRW(NULL, (BYTE8 *)stop, sizeof(stop)); /* Stops the transfer.*/ + sspReleaseBus(); return FALSE; } diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index a071075bb..823a76a3d 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -22,19 +22,19 @@ #define NICE_WAITING -/* Following times are 10mS units.*/ #define CMD0_RETRY 10 #define CMD1_RETRY 100 #define POLLING_INTERVAL 10 - -/* Byte transfer time units.*/ #define MMC_WAIT_DATA 10000 #define CMDGOIDLE 0 #define CMDINIT 1 #define CMDREADCSD 9 +#define CMDSTOP 12 #define CMDREAD 17 +#define CMDREADMULTIPLE 18 #define CMDWRITE 24 +#define CMDWRITEMULTIPLE 25 typedef struct { ULONG32 csize; @@ -51,8 +51,10 @@ void mmcStopPolling(void); BOOL mmcCardInserted (void); BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); BOOL mmcGetSize(MMCCSD *data); -BOOL mmcBlockRead(ULONG32 blknum, BYTE8 *buf); -BOOL mmcBlockWrite(ULONG32 blknum, BYTE8 *buf); +BOOL mmcRead(BYTE8 *buf, ULONG32 blknum); +BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); +BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum); +BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); void mmcSynch(void); #endif /* _MMCSD_H_*/ -- cgit v1.2.3 From a7ad3ace523d19be103e03f6244e0e797354fe0f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 12 Nov 2007 15:02:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@87 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 6 +++--- demos/ARM7-LPC214x-GCC/buzzer.c | 2 +- demos/ARM7-LPC214x-GCC/buzzer.h | 12 +++++++++--- demos/ARM7-LPC214x-GCC/chconf.h | 6 ++++++ demos/ARM7-LPC214x-GCC/chcore.h | 5 ++--- demos/ARM7-LPC214x-GCC/chtypes.h | 1 + demos/ARM7-LPC214x-GCC/mmcsd.h | 32 +++++++++++++++++++------------- 7 files changed, 41 insertions(+), 23 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 0ee445783..755c134e5 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -65,9 +65,9 @@ UADEFS = ASRC = chcore.c main.c buzzer.c mmcsd.c ../../src/lib/evtimer.c ../../test/test.c \ ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ - ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ - ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ - ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ + ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index a93bafa98..218d920d0 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -89,4 +89,4 @@ void PlaySoundWait(int freq, t_time duration) { StartCounter(tc); chThdSleep(duration); StopCounter(tc); -} \ No newline at end of file +} diff --git a/demos/ARM7-LPC214x-GCC/buzzer.h b/demos/ARM7-LPC214x-GCC/buzzer.h index f5f9e82ac..464e081d8 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.h +++ b/demos/ARM7-LPC214x-GCC/buzzer.h @@ -20,9 +20,15 @@ #ifndef _BUZZER_H_ #define _BUZZER_H_ -void InitBuzzer(void); -void PlaySound(int freq, t_time duration); -void PlaySoundWait(int freq, t_time duration); +#ifdef __cplusplus +extern "C" { +#endif + void InitBuzzer(void); + void PlaySound(int freq, t_time duration); + void PlaySoundWait(int freq, t_time duration); +#ifdef __cplusplus +} +#endif extern EventSource BuzzerSilentEventSource; diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index f4d902a9a..ba9957e49 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -156,6 +156,12 @@ */ //#define CH_CURRP_REGISTER_CACHE "r7" +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +#define CH_USE_DEBUG + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 9c583c2ac..5a42cdf89 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -92,8 +92,9 @@ extern void chSysUnlock(void); #define chSysUnlock() asm("msr CPSR_c, #0x1F") #endif /* THUMB */ -#define INT_REQUIRED_STACK 0x40 // Must include registers and stack frames. +#define chSysPuts(msg) {} +#define INT_REQUIRED_STACK 0x40 // Must include registers and stack frames. #define UserStackSize(n) (sizeof(Thread) + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) @@ -105,6 +106,4 @@ void DefFiqHandler(void); void DefIrqHandler(void); void SpuriousHandler(void); -void SetVICVector(void *handler, int vector, int source); - #endif /* _CHCORE_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chtypes.h b/demos/ARM7-LPC214x-GCC/chtypes.h index 803b5ead4..2ac219148 100644 --- a/demos/ARM7-LPC214x-GCC/chtypes.h +++ b/demos/ARM7-LPC214x-GCC/chtypes.h @@ -33,6 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; +typedef UWORD16 t_tid; typedef ULONG32 t_prio; typedef LONG32 t_msg; typedef LONG32 t_eventid; diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index 823a76a3d..b5f0ea57c 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -43,18 +43,24 @@ typedef struct { extern EventSource MMCInsertEventSource, MMCRemoveEventSource; -void InitMMC(void); - -BOOL mmcInit(void); -void mmcStartPolling(void); -void mmcStopPolling(void); -BOOL mmcCardInserted (void); -BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); -BOOL mmcGetSize(MMCCSD *data); -BOOL mmcRead(BYTE8 *buf, ULONG32 blknum); -BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); -BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum); -BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); -void mmcSynch(void); +#ifdef __cplusplus +} +#endif + void InitMMC(void); + + BOOL mmcInit(void); + void mmcStartPolling(void); + void mmcStopPolling(void); + BOOL mmcCardInserted (void); + BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); + BOOL mmcGetSize(MMCCSD *data); + BOOL mmcRead(BYTE8 *buf, ULONG32 blknum); + BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); + BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum); + BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); + void mmcSynch(void); +#ifdef __cplusplus +} +#endif #endif /* _MMCSD_H_*/ -- cgit v1.2.3 From e776216d02920673266e31d553078f4edec4a264 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 13 Nov 2007 16:38:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@89 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 4 ++-- demos/ARM7-LPC214x-GCC/chconf.h | 2 +- demos/ARM7-LPC214x-GCC/chcore.c | 2 +- demos/ARM7-LPC214x-GCC/chcore.h | 4 ++-- demos/ARM7-LPC214x-GCC/chcore2.s | 30 +++++++++++++----------------- 5 files changed, 19 insertions(+), 23 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 755c134e5..0c0ad93e9 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -93,9 +93,9 @@ AOPT = TOPT = -mthumb -D THUMB # Common options here -# NOTE: -ffixed-f7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing -#OPT += -ffixed-f7 +#OPT += -ffixed-r7 # Define warning options here WARN = -Wall -Wstrict-prototypes diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index ba9957e49..51aac3a64 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -160,7 +160,7 @@ * @note the debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. */ -#define CH_USE_DEBUG +//#define CH_USE_DEBUG #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 128fb97aa..2f60c9d53 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -214,6 +214,6 @@ void NonVectoredIrq(void) { void Timer0Irq(void) { T0IR = 1; /* Clear interrupt on match MR0. */ - VICVectAddr = 0; chSchTimerHandlerI(); + VICVectAddr = 0; } diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 5a42cdf89..9a1401f1c 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -37,7 +37,7 @@ struct stackregs { regarm r4; regarm r5; regarm r6; -#ifndef MK_CURRP_REGISTER_CACHE +#ifndef CH_CURRP_REGISTER_CACHE regarm r7; #endif regarm r8; @@ -51,7 +51,7 @@ typedef struct { struct stackregs *r13; } Context; -#ifdef MK_CURRP_REGISTER_CACHE +#ifdef CH_CURRP_REGISTER_CACHE #define SETUP_CONTEXT(workspace, wsize, pf, arg) \ { \ tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index f734eebba..1eb301fbe 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -47,10 +47,6 @@ threadstart: SwiHandler: b SwiHandler -.globl DefIrqHandler -DefIrqHandler: - b DefIrqHandler - .globl FiqHandler FiqHandler: b FiqHandler @@ -109,7 +105,7 @@ chSysSwitchI: * | R10 | | * | R9 | | * | R8 | | Internal context: mk_SwitchI() frame - * | (R7) | | (optional, see MK_CURRP_REGISTER_CACHE) + * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) * | R6 | | * | R5 | | * SP-> | R4 | -+ @@ -119,9 +115,9 @@ chSysSwitchI: IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc} +// mrs r0, SPSR // Workaround for ARM7TDMI+VIC +// tst r0, #I_BIT // spurious interrupts. +// ldmnefd sp!, {r0-r3, r12, pc} bl NonVectoredIrq b IrqCommon @@ -129,9 +125,9 @@ IrqHandler: T0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc}^ +// mrs r0, SPSR // Workaround for ARM7TDMI+VIC +// tst r0, #I_BIT // spurious interrupts. +// ldmnefd sp!, {r0-r3, r12, pc}^ bl Timer0Irq b IrqCommon @@ -139,9 +135,9 @@ T0IrqHandler: UART0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc}^ +// mrs r0, SPSR // Workaround for ARM7TDMI+VIC +// tst r0, #I_BIT // spurious interrupts. +// ldmnefd sp!, {r0-r3, r12, pc}^ bl UART0Irq b IrqCommon @@ -149,9 +145,9 @@ UART0IrqHandler: UART1IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} - mrs r0, SPSR // Workaround for ARM7TDMI+VIC - tst r0, #I_BIT // spurious interrupts. - ldmnefd sp!, {r0-r3, r12, pc}^ +// mrs r0, SPSR // Workaround for ARM7TDMI+VIC +// tst r0, #I_BIT // spurious interrupts. +// ldmnefd sp!, {r0-r3, r12, pc}^ bl UART1Irq b IrqCommon -- cgit v1.2.3 From 890c5532da783e8d58cfbf28822bcedaa8a0c61d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 14 Nov 2007 16:32:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@90 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 6 +++++- demos/ARM7-LPC214x-GCC/main.c | 10 ++++++++-- demos/AVR-AT90CANx-GCC/chconf.h | 6 ++++++ demos/AVR-AT90CANx-GCC/chcore.h | 1 + demos/AVR-AT90CANx-GCC/chtypes.h | 1 + demos/Win32-MSVS/ch.vcproj | 6 ++++++ demos/Win32-MSVS/chconf.h | 6 ++++++ demos/Win32-MSVS/chcore.c | 2 +- demos/Win32-MSVS/chcore.h | 2 +- demos/Win32-MSVS/chtypes.h | 1 + demos/Win32-MinGW/chconf.h | 6 ++++++ demos/Win32-MinGW/chcore.c | 2 +- demos/Win32-MinGW/chcore.h | 2 +- demos/Win32-MinGW/chtypes.h | 1 + 14 files changed, 45 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 0c0ad93e9..eb9cf9bc7 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -93,9 +93,13 @@ AOPT = TOPT = -mthumb -D THUMB # Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in chconf.h. +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing #OPT += -ffixed-r7 +#OPT += -falign-functions=16 # Define warning options here WARN = -Wall -Wstrict-prototypes diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index fbd4f2726..e10063bcb 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -119,8 +119,14 @@ static t_msg Thread3(void *arg) { int main(int argc, char **argv) { chSysInit(); - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); - chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); + /* + * If a button is pressed during the reset then the blinking leds are not + * started in order to make accurate benchmarks. + */ + if ((IO0PIN & 0x00018000) == 0x00018000) { + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); + } chThdCreate(NORMALPRIO, 0, waThread3, sizeof(waThread3), Thread3, NULL); chSysPause(); return 0; diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 63a391e08..c6146f5e7 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -157,6 +157,12 @@ */ //#define CH_CURRP_REGISTER_CACHE "reg" +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h index c3e0cfa34..935c37488 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.h +++ b/demos/AVR-AT90CANx-GCC/chcore.h @@ -101,6 +101,7 @@ typedef struct { #define chSysLock() asm("cli") #define chSysUnlock() asm("sei") +#define chSysPuts(msg) {} void chSysHalt(void) __attribute__((noreturn)) ; void chSysPause(void) __attribute__((noreturn)) ; diff --git a/demos/AVR-AT90CANx-GCC/chtypes.h b/demos/AVR-AT90CANx-GCC/chtypes.h index d3c26caaf..60e16aaf4 100644 --- a/demos/AVR-AT90CANx-GCC/chtypes.h +++ b/demos/AVR-AT90CANx-GCC/chtypes.h @@ -34,6 +34,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; +typedef BYTE8 t_tid; typedef BYTE8 t_prio; typedef WORD16 t_msg; typedef BYTE8 t_eventid; diff --git a/demos/Win32-MSVS/ch.vcproj b/demos/Win32-MSVS/ch.vcproj index 26dd9557e..3490c810b 100644 --- a/demos/Win32-MSVS/ch.vcproj +++ b/demos/Win32-MSVS/ch.vcproj @@ -141,6 +141,9 @@ + + @@ -209,6 +212,9 @@ + + diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h index 1aa089575..be1896046 100644 --- a/demos/Win32-MSVS/chconf.h +++ b/demos/Win32-MSVS/chconf.h @@ -161,6 +161,12 @@ */ //#define CH_CURRP_REGISTER_CACHE "reg" +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c index 01619f9cd..8aedbb465 100644 --- a/demos/Win32-MSVS/chcore.c +++ b/demos/Win32-MSVS/chcore.c @@ -47,7 +47,7 @@ void InitCore(void) { /* * Interrupt simulation. */ -static void ChkIntSources(void) { +void ChkIntSources(void) { LARGE_INTEGER n; if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h index 26e0b66bf..58e278fe4 100644 --- a/demos/Win32-MSVS/chcore.h +++ b/demos/Win32-MSVS/chcore.h @@ -58,8 +58,8 @@ typedef struct { } #define chSysLock() - #define chSysUnlock() +#define chSysPuts(msg) {} #define INT_REQUIRED_STACK 0x0 diff --git a/demos/Win32-MSVS/chtypes.h b/demos/Win32-MSVS/chtypes.h index 6481c22a8..5ab9a06e1 100644 --- a/demos/Win32-MSVS/chtypes.h +++ b/demos/Win32-MSVS/chtypes.h @@ -33,6 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; +typedef UWORD16 t_tid; typedef ULONG32 t_prio; typedef LONG32 t_msg; typedef LONG32 t_eventid; diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index b7a8acedd..8ce32defa 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -161,6 +161,12 @@ */ //#define CH_CURRP_REGISTER_CACHE "reg" +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index ee04147e9..c96611f8b 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -70,7 +70,7 @@ void InitCore(void) { /* * Interrupt simulation. */ -static void ChkIntSources(void) { +void ChkIntSources(void) { LARGE_INTEGER n; if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 7f0021854..6d3055081 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -58,8 +58,8 @@ typedef struct { } #define chSysLock() - #define chSysUnlock() +#define chSysPuts(msg) {} #define INT_REQUIRED_STACK 0x0 diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 803b5ead4..2ac219148 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -33,6 +33,7 @@ typedef BYTE8 t_tmode; typedef BYTE8 t_tstate; +typedef UWORD16 t_tid; typedef ULONG32 t_prio; typedef LONG32 t_msg; typedef LONG32 t_eventid; -- cgit v1.2.3 From 3fe3d0d6a9ba5b11ebd30f30d5dfcb600cea9e50 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 15 Nov 2007 15:35:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@91 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile.thumb | 187 ++++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/main.c | 2 +- 2 files changed, 188 insertions(+), 1 deletion(-) create mode 100644 demos/ARM7-LPC214x-GCC/Makefile.thumb (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb new file mode 100644 index 000000000..3840c1738 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -0,0 +1,187 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +ASRC = chcore.c + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = main.c buzzer.c mmcsd.c ../../src/lib/evtimer.c ../../test/test.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ + ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c + +# List ASM source files here +ASMSRC = crt0.s chcore2.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT += -ffixed-r7 +#OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +ifneq ($(TSRC),) + ASFLAGS += -mthumb-interwork -D THUMB_INTERWORK + CPFLAGS += -mthumb-interwork -D THUMB_INTERWORK + LDFLAGS += -mthumb-interwork +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index e10063bcb..c9afab898 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -94,7 +94,7 @@ static void RemoveHandler(t_eventid id) { PlaySoundWait(1000, 100); } -static BYTE8 waThread3[UserStackSize(128)]; +static BYTE8 waThread3[UserStackSize(256)]; static EvTimer evt; static t_evhandler evhndl[] = { TimerHandler, -- cgit v1.2.3 From da365c95e4460bda1f5b49a2e55ae144da1faf3f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Nov 2007 13:14:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@93 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 13 +++++---- demos/ARM7-LPC214x-GCC/Makefile.thumb | 11 ++++---- demos/ARM7-LPC214x-GCC/main.c | 53 +++++++++++++++++++++++++++++------ 3 files changed, 58 insertions(+), 19 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index eb9cf9bc7..b078b8f88 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -62,12 +62,15 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = chcore.c main.c buzzer.c mmcsd.c ../../src/lib/evtimer.c ../../test/test.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ +ASRC = chcore.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ - ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c + ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + buzzer.c mmcsd.c main.c + # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is @@ -99,7 +102,7 @@ TOPT = -mthumb -D THUMB # increases the code size. OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing #OPT += -ffixed-r7 -#OPT += -falign-functions=16 +OPT += -falign-functions=16 # Define warning options here WARN = -Wall -Wstrict-prototypes diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 3840c1738..8c6147f15 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -67,12 +67,13 @@ ASRC = chcore.c # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = main.c buzzer.c mmcsd.c ../../src/lib/evtimer.c ../../test/test.c \ +TSRC = ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ + ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ - ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c + ../../src/lib/evtimer.c ../../test/test.c \ + buzzer.c mmcsd.c main.c # List ASM source files here ASMSRC = crt0.s chcore2.s @@ -99,7 +100,7 @@ TOPT = -mthumb -D THUMB # increases the code size. OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing #OPT += -ffixed-r7 -#OPT += -falign-functions=16 +OPT += -falign-functions=16 # Define warning options here WARN = -Wall -Wstrict-prototypes diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index c9afab898..a889706e6 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -25,8 +25,13 @@ #include "buzzer.h" #include "evtimer.h" -static BYTE8 waThread1[UserStackSize(32)]; +static BYTE8 waIdleThread[UserStackSize(16)]; +static t_msg IdleThread(void *arg) { + + chSysPause(); +} +static BYTE8 waThread1[UserStackSize(32)]; static t_msg Thread1(void *arg) { while (TRUE) { @@ -43,7 +48,6 @@ static t_msg Thread1(void *arg) { } static BYTE8 waThread2[UserStackSize(32)]; - static t_msg Thread2(void *arg) { while (TRUE) { @@ -94,7 +98,7 @@ static void RemoveHandler(t_eventid id) { PlaySoundWait(1000, 100); } -static BYTE8 waThread3[UserStackSize(256)]; +/*static BYTE8 waThread3[UserStackSize(256)];*/ static EvTimer evt; static t_evhandler evhndl[] = { TimerHandler, @@ -102,7 +106,7 @@ static t_evhandler evhndl[] = { RemoveHandler }; -static t_msg Thread3(void *arg) { +/*static t_msg Thread3(void *arg) { struct EventListener el0, el1, el2; evtInit(&evt, 500); @@ -114,20 +118,51 @@ static t_msg Thread3(void *arg) { while (TRUE) chEvtWait(ALL_EVENTS, evhndl); return 0; -} +}*/ int main(int argc, char **argv) { + struct EventListener el0, el1, el2; + /* + * The main() function becomes a thread here, ChibiOS/RT goes live. + */ chSysInit(); + + /* + * This thread has the lowest priority in the system, its role is just to + * execute the chSysPause() and serve interrupts in its context. + * In ChibiOS/RT at least one thread in the system *must* execute + * chThdPause(), it can be done in a dedicated thread or in the main() + * function (that would never exit the call). + */ + chThdCreate(IDLEPRIO, 0, waIdleThread, sizeof(waIdleThread), IdleThread, NULL); + /* - * If a button is pressed during the reset then the blinking leds are not - * started in order to make accurate benchmarks. + * If a button is pressed during the reset then the blinking leds threads + * are not started in order to make accurate benchmarks. */ if ((IO0PIN & 0x00018000) == 0x00018000) { chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); } - chThdCreate(NORMALPRIO, 0, waThread3, sizeof(waThread3), Thread3, NULL); - chSysPause(); + + /* + * Allows the other threads to run by lowering the priority, remember, + * the priority is set to the maximum in the \p chSysInit(). + */ + chThdSetPriority(NORMALPRIO); + + /* + * Normal main() activity, in this demo it server events incoming from + * various sources. + */ + evtInit(&evt, 500); /* Initializes an event timer object. */ + evtRegister(&evt, &el0, 0); /* Registers on the timer event source. */ + evtStart(&evt); /* Starts the event timer. */ + mmcStartPolling(); /* Starts the MMC connector polling. */ + chEvtRegister(&MMCInsertEventSource, &el1, 1); + chEvtRegister(&MMCRemoveEventSource, &el2, 2); + while (TRUE) /* Just serve events. */ + chEvtWait(ALL_EVENTS, evhndl); return 0; } -- cgit v1.2.3 From 195a9c7951c29828d7eddefcd77d7a98d18f75f3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Nov 2007 16:15:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@94 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/ch.ld | 2 +- demos/ARM7-LPC214x-GCC/main.c | 56 +++++++++++++++++++++++++------------------ 2 files changed, 34 insertions(+), 24 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index 6ce8a0b32..ace1c3b53 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0080; +__sys_stack_size__ = 0x0100; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index a889706e6..14e03170d 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -25,12 +25,21 @@ #include "buzzer.h" #include "evtimer.h" +/* + * System Idle Thread, this thread only runs when on other threads in the + * system require the CPU. + * The role of this thread is to minimize the power consumption when idling + * and serve the interrupts. + */ static BYTE8 waIdleThread[UserStackSize(16)]; static t_msg IdleThread(void *arg) { chSysPause(); } +/* + * Red LEDs blinker thread, times are in milliseconds. + */ static BYTE8 waThread1[UserStackSize(32)]; static t_msg Thread1(void *arg) { @@ -47,6 +56,9 @@ static t_msg Thread1(void *arg) { return 0; } +/* + * Yellow LED blinker thread, times are in milliseconds. + */ static BYTE8 waThread2[UserStackSize(32)]; static t_msg Thread2(void *arg) { @@ -59,6 +71,9 @@ static t_msg Thread2(void *arg) { return 0; } +/* + * Executed as event handler at 500mS intervals. + */ static void TimerHandler(t_eventid id) { t_msg TestThread(void *p); @@ -76,6 +91,10 @@ static void TimerHandler(t_eventid id) { } } +/* + * Plays sounds when a MMC/SD card is inserted, then initializes the MMC + * driver and reads a sector. + */ static void InsertHandler(t_eventid id) { static BYTE8 rwbuf[512]; MMCCSD data; @@ -92,39 +111,30 @@ static void InsertHandler(t_eventid id) { PlaySound(440, 200); } +/* + * Plays sounds when a MMC/SD card is removed. + */ static void RemoveHandler(t_eventid id) { PlaySoundWait(2000, 100); PlaySoundWait(1000, 100); } -/*static BYTE8 waThread3[UserStackSize(256)];*/ -static EvTimer evt; -static t_evhandler evhndl[] = { - TimerHandler, - InsertHandler, - RemoveHandler -}; - -/*static t_msg Thread3(void *arg) { - struct EventListener el0, el1, el2; - - evtInit(&evt, 500); - evtStart(&evt); - mmcStartPolling(); - evtRegister(&evt, &el0, 0); - chEvtRegister(&MMCInsertEventSource, &el1, 1); - chEvtRegister(&MMCRemoveEventSource, &el2, 2); - while (TRUE) - chEvtWait(ALL_EVENTS, evhndl); - return 0; -}*/ - +/* + * Entry point, the interrupts are disabled on entry. + */ int main(int argc, char **argv) { + static const t_evhandler evhndl[] = { + TimerHandler, + InsertHandler, + RemoveHandler + }; + static EvTimer evt; struct EventListener el0, el1, el2; /* - * The main() function becomes a thread here, ChibiOS/RT goes live. + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. */ chSysInit(); -- cgit v1.2.3 From 4fc627f08b942df8312ad02f24a361b18c4b790b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Nov 2007 09:45:45 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@95 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/buzzer.c | 4 ++-- demos/ARM7-LPC214x-GCC/chcore.c | 9 +++++---- demos/ARM7-LPC214x-GCC/chcore.h | 4 ++++ demos/ARM7-LPC214x-GCC/main.c | 23 +---------------------- 4 files changed, 12 insertions(+), 28 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index 218d920d0..7d80d8881 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -52,8 +52,8 @@ void InitBuzzer(void) { TC *tc = T1Base; StopCounter(tc); tc->TC_CTCR = 0; // Clock source is PCLK. - tc->TC_PR = 0; // Prescaler disabled. - tc->TC_MCR = 2; // Clear TC on match MR0. + tc->TC_PR = 0; // Prescaler disabled. + tc->TC_MCR = 2; // Clear TC on match MR0. } static void stop(void *p) { diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 2f60c9d53..bf157cf43 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -140,14 +140,15 @@ void hwinit(void) { InitBuzzer(); } -void chSysPause(void) { - - chThdSetPriority(IDLEPRIO); +/* + * System idle thread loop. + */ +void _IdleThread(void *p) { while (TRUE) { // Note, it is disabled because it causes trouble with the JTAG probe. // Enable it in the final code only. -// PCON = 1; /* Stops CPU clock until next interrupt. */ +// PCON = 1; } } diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 9a1401f1c..7aef95d12 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -98,6 +98,10 @@ extern void chSysUnlock(void); #define UserStackSize(n) (sizeof(Thread) + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) + +#define IDLE_THREAD_STACK_SIZE 8 +void _IdleThread(void *p) __attribute__((noreturn)); + void chSysHalt(void) __attribute__((noreturn)); void chSysPause(void) __attribute__((noreturn)); void chSysSwitchI(Context *oldp, Context *newp); diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 14e03170d..1829e6eb6 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -25,18 +25,6 @@ #include "buzzer.h" #include "evtimer.h" -/* - * System Idle Thread, this thread only runs when on other threads in the - * system require the CPU. - * The role of this thread is to minimize the power consumption when idling - * and serve the interrupts. - */ -static BYTE8 waIdleThread[UserStackSize(16)]; -static t_msg IdleThread(void *arg) { - - chSysPause(); -} - /* * Red LEDs blinker thread, times are in milliseconds. */ @@ -138,15 +126,6 @@ int main(int argc, char **argv) { */ chSysInit(); - /* - * This thread has the lowest priority in the system, its role is just to - * execute the chSysPause() and serve interrupts in its context. - * In ChibiOS/RT at least one thread in the system *must* execute - * chThdPause(), it can be done in a dedicated thread or in the main() - * function (that would never exit the call). - */ - chThdCreate(IDLEPRIO, 0, waIdleThread, sizeof(waIdleThread), IdleThread, NULL); - /* * If a button is pressed during the reset then the blinking leds threads * are not started in order to make accurate benchmarks. @@ -163,7 +142,7 @@ int main(int argc, char **argv) { chThdSetPriority(NORMALPRIO); /* - * Normal main() activity, in this demo it server events incoming from + * Normal main() activity, in this demo it serves events generated by * various sources. */ evtInit(&evt, 500); /* Initializes an event timer object. */ -- cgit v1.2.3 From b3361bd0e8ca074dbf7f312a87bbcdbf0019ebc7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Nov 2007 11:09:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@97 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.h | 73 ++++++++++++++++++++-------------------- demos/ARM7-LPC214x-GCC/chcore2.s | 12 ------- demos/AVR-AT90CANx-GCC/chcore.c | 4 +-- demos/AVR-AT90CANx-GCC/chcore.h | 18 ++++++---- demos/AVR-AT90CANx-GCC/main.c | 14 ++++++-- demos/Win32-MSVS/chcore.c | 2 +- demos/Win32-MSVS/chcore.h | 5 +-- demos/Win32-MSVS/demo.c | 39 +++++++-------------- demos/Win32-MinGW/chcore.c | 4 +-- demos/Win32-MinGW/chcore.h | 5 +-- demos/Win32-MinGW/demo.c | 39 +++++++-------------- 11 files changed, 94 insertions(+), 121 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 7aef95d12..268cae39b 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -31,9 +31,22 @@ typedef void *regarm; /* - * Stack saved context. + * Interrupt saved context. */ -struct stackregs { +struct extctx { + regarm spsr_irq; + regarm lr_irq; + regarm r0; + regarm r1; + regarm r2; + regarm r3; + regarm r12; +}; + +/* + * System saved context. + */ +struct intctx { regarm r4; regarm r5; regarm r6; @@ -47,42 +60,25 @@ struct stackregs { regarm lr; }; +/* + * Port dependent part of the Thread structure, you may add fields in + * this structure. + */ typedef struct { - struct stackregs *r13; + struct intctx *r13; } Context; -#ifdef CH_CURRP_REGISTER_CACHE -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ - tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct stackregs)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->r6 = 0; \ - tp->p_ctx.r13->r8 = 0; \ - tp->p_ctx.r13->r9 = 0; \ - tp->p_ctx.r13->r10 = 0; \ - tp->p_ctx.r13->r11 = 0; \ - tp->p_ctx.r13->lr = threadstart; \ -} -#else -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ - tp->p_ctx.r13 = (struct stackregs *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct stackregs)); \ +/* + * Platform dependent part of the \p chThdCreate() API. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ tp->p_ctx.r13->r4 = pf; \ tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->r6 = 0; \ - tp->p_ctx.r13->r7 = 0; \ - tp->p_ctx.r13->r8 = 0; \ - tp->p_ctx.r13->r9 = 0; \ - tp->p_ctx.r13->r10 = 0; \ - tp->p_ctx.r13->r11 = 0; \ tp->p_ctx.r13->lr = threadstart; \ } -#endif #ifdef THUMB extern void chSysLock(void); @@ -94,16 +90,21 @@ extern void chSysUnlock(void); #define chSysPuts(msg) {} -#define INT_REQUIRED_STACK 0x40 // Must include registers and stack frames. -#define UserStackSize(n) (sizeof(Thread) + \ - sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) - +#ifdef THUMB +#define INT_REQUIRED_STACK 0x10 +#else /* !THUMB */ +#define INT_REQUIRED_STACK 0 +#endif /* THUMB */ +#define UserStackSize(n) (sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (INT_REQUIRED_STACK) + \ + (n)) #define IDLE_THREAD_STACK_SIZE 8 void _IdleThread(void *p) __attribute__((noreturn)); void chSysHalt(void) __attribute__((noreturn)); -void chSysPause(void) __attribute__((noreturn)); void chSysSwitchI(Context *oldp, Context *newp); void threadstart(void); void DefFiqHandler(void); diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index 1eb301fbe..e29c92f5e 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -115,9 +115,6 @@ chSysSwitchI: IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -// mrs r0, SPSR // Workaround for ARM7TDMI+VIC -// tst r0, #I_BIT // spurious interrupts. -// ldmnefd sp!, {r0-r3, r12, pc} bl NonVectoredIrq b IrqCommon @@ -125,9 +122,6 @@ IrqHandler: T0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -// mrs r0, SPSR // Workaround for ARM7TDMI+VIC -// tst r0, #I_BIT // spurious interrupts. -// ldmnefd sp!, {r0-r3, r12, pc}^ bl Timer0Irq b IrqCommon @@ -135,9 +129,6 @@ T0IrqHandler: UART0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -// mrs r0, SPSR // Workaround for ARM7TDMI+VIC -// tst r0, #I_BIT // spurious interrupts. -// ldmnefd sp!, {r0-r3, r12, pc}^ bl UART0Irq b IrqCommon @@ -145,9 +136,6 @@ UART0IrqHandler: UART1IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -// mrs r0, SPSR // Workaround for ARM7TDMI+VIC -// tst r0, #I_BIT // spurious interrupts. -// ldmnefd sp!, {r0-r3, r12, pc}^ bl UART1Irq b IrqCommon diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c index 262732676..3bc5b027e 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.c +++ b/demos/AVR-AT90CANx-GCC/chcore.c @@ -121,9 +121,7 @@ void hwinit(void) { TIMSK0 = (1 << OCIE0A); // Interrupt on compare. } -void chSysPause(void) { - - chThdSetPriority(IDLEPRIO); +void _IdleThread(void *p) { while (TRUE) { // asm volatile ("sleep"); diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h index 935c37488..32c939d32 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.h +++ b/demos/AVR-AT90CANx-GCC/chcore.h @@ -48,7 +48,7 @@ struct extctx { }; /* - * Stack saved context. + * System saved context. */ struct intctx { BYTE8 r29; @@ -72,6 +72,10 @@ struct intctx { UWORD16 pc; }; +/* + * Port dependent part of the Thread structure, you may add fields in + * this structure. + */ typedef struct { struct intctx *sp; } Context; @@ -93,18 +97,20 @@ typedef struct { */ #define EXTRA_INT_STACK 0x10 -#define UserStackSize(n) (sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - EXTRA_INT_STACK + \ +#define UserStackSize(n) (sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + EXTRA_INT_STACK + \ (n)) #define chSysLock() asm("cli") #define chSysUnlock() asm("sei") #define chSysPuts(msg) {} +#define IDLE_THREAD_STACK_SIZE 8 +void _IdleThread(void *p) __attribute__((noreturn)); + void chSysHalt(void) __attribute__((noreturn)) ; -void chSysPause(void) __attribute__((noreturn)) ; void chSysSwitchI(Context *oldp, Context *newp); void threadstart(void); diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 48f58d080..61156b040 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -24,7 +24,6 @@ void hwinit(void); static BYTE8 waThread1[UserStackSize(32)]; - static t_msg Thread1(void *arg) { while (TRUE) { @@ -37,8 +36,19 @@ int main(int argc, char **argv) { hwinit(); + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ chSysInit(); + + /* + * Starts the LED blinker thread. + */ chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); - chSysPause(); + + while(TRUE) + /* Do stuff*/ ; + return 0; } diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c index 8aedbb465..0df82eec6 100644 --- a/demos/Win32-MSVS/chcore.c +++ b/demos/Win32-MSVS/chcore.c @@ -68,7 +68,7 @@ void ChkIntSources(void) { } } -void __fastcall chSysPause(void) { +t_msg _IdleThread(void) { chThdSetPriority(IDLEPRIO); diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h index 58e278fe4..6d11921cf 100644 --- a/demos/Win32-MSVS/chcore.h +++ b/demos/Win32-MSVS/chcore.h @@ -62,12 +62,13 @@ typedef struct { #define chSysPuts(msg) {} #define INT_REQUIRED_STACK 0x0 - #define UserStackSize(n) (sizeof(Thread) + sizeof(void *)*2 + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) +#define IDLE_THREAD_STACK_SIZE 16384 +t_msg _IdleThread(void *p); + void __fastcall chSysHalt(void); -void __fastcall chSysPause(void); void __fastcall chSysSwitchI(Context *oldp, Context *newp); void __fastcall threadexit(void); diff --git a/demos/Win32-MSVS/demo.c b/demos/Win32-MSVS/demo.c index 077877f8e..1d4f4aa16 100644 --- a/demos/Win32-MSVS/demo.c +++ b/demos/Win32-MSVS/demo.c @@ -25,16 +25,12 @@ static ULONG32 wdguard; static BYTE8 wdarea[UserStackSize(2048)]; -static ULONG32 iguard; -static BYTE8 iarea[UserStackSize(2048)]; - static ULONG32 cdguard; static BYTE8 cdarea[UserStackSize(2048)]; static Thread *cdtp; static t_msg WatchdogThread(void *arg); static t_msg ConsoleThread(void *arg); -static t_msg InitThread(void *arg); t_msg TestThread(void *p); @@ -43,34 +39,16 @@ extern FullDuplexDriver COM1, COM2; #define cprint(msg) chMsgSend(cdtp, (t_msg)msg) -/*------------------------------------------------------------------------* - * Simulator main, start here your threads, examples inside. * - *------------------------------------------------------------------------*/ -int main(void) { - - InitCore(); - - // Startup ChibiOS/RT. - chSysInit(); - chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); - cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); - chThdCreate(NORMALPRIO, 0, iarea, sizeof(iarea), InitThread, NULL); - chSysPause(); - return 0; -} - /* * Watchdog thread, it checks magic values located under the various stack * areas. The system is halted if something is wrong. */ static t_msg WatchdogThread(void *arg) { wdguard = 0xA51F2E3D; - iguard = 0xA51F2E3D; cdguard = 0xA51F2E3D; while (TRUE) { if ((wdguard != 0xA51F2E3D) || - (iguard != 0xA51F2E3D) || (cdguard != 0xA51F2E3D)) { printf("Halted by watchdog"); chSysHalt(); @@ -294,13 +272,20 @@ static t_evhandler fhandlers[2] = { COM2Handler }; -/* - * Init-like thread, it starts the shells and handles their termination. - * It is a good example of events usage. - */ -static t_msg InitThread(void *arg) { +/*------------------------------------------------------------------------* + * Simulator main, start here your threads, examples inside. * + *------------------------------------------------------------------------*/ +int main(void) { EventListener c1fel, c2fel; + InitCore(); + + // Startup ChibiOS/RT. + chSysInit(); + + chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); + cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); + cprint("Console service started on COM1, COM2\n"); cprint(" - Listening for connections on COM1\n"); chFDDGetAndClearFlags(&COM1); diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index c96611f8b..eab41ab27 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -91,9 +91,7 @@ void ChkIntSources(void) { } } -__attribute__((fastcall)) void chSysPause(void) { - - chThdSetPriority(IDLEPRIO); +t_msg _IdleThread(void *p) { while (TRUE) { diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 6d3055081..a28aa2833 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -62,12 +62,13 @@ typedef struct { #define chSysPuts(msg) {} #define INT_REQUIRED_STACK 0x0 - #define UserStackSize(n) (sizeof(Thread) + sizeof(void *) * 2 + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) +#define IDLE_THREAD_STACK_SIZE 16384 +t_msg _IdleThread(void *p); + __attribute__((fastcall)) void chSysHalt(void); -__attribute__((fastcall)) void chSysPause(void); __attribute__((fastcall)) void chSysSwitchI(Context *oldp, Context *newp); __attribute__((fastcall)) void threadstart(void); diff --git a/demos/Win32-MinGW/demo.c b/demos/Win32-MinGW/demo.c index 077877f8e..1d4f4aa16 100644 --- a/demos/Win32-MinGW/demo.c +++ b/demos/Win32-MinGW/demo.c @@ -25,16 +25,12 @@ static ULONG32 wdguard; static BYTE8 wdarea[UserStackSize(2048)]; -static ULONG32 iguard; -static BYTE8 iarea[UserStackSize(2048)]; - static ULONG32 cdguard; static BYTE8 cdarea[UserStackSize(2048)]; static Thread *cdtp; static t_msg WatchdogThread(void *arg); static t_msg ConsoleThread(void *arg); -static t_msg InitThread(void *arg); t_msg TestThread(void *p); @@ -43,34 +39,16 @@ extern FullDuplexDriver COM1, COM2; #define cprint(msg) chMsgSend(cdtp, (t_msg)msg) -/*------------------------------------------------------------------------* - * Simulator main, start here your threads, examples inside. * - *------------------------------------------------------------------------*/ -int main(void) { - - InitCore(); - - // Startup ChibiOS/RT. - chSysInit(); - chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); - cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); - chThdCreate(NORMALPRIO, 0, iarea, sizeof(iarea), InitThread, NULL); - chSysPause(); - return 0; -} - /* * Watchdog thread, it checks magic values located under the various stack * areas. The system is halted if something is wrong. */ static t_msg WatchdogThread(void *arg) { wdguard = 0xA51F2E3D; - iguard = 0xA51F2E3D; cdguard = 0xA51F2E3D; while (TRUE) { if ((wdguard != 0xA51F2E3D) || - (iguard != 0xA51F2E3D) || (cdguard != 0xA51F2E3D)) { printf("Halted by watchdog"); chSysHalt(); @@ -294,13 +272,20 @@ static t_evhandler fhandlers[2] = { COM2Handler }; -/* - * Init-like thread, it starts the shells and handles their termination. - * It is a good example of events usage. - */ -static t_msg InitThread(void *arg) { +/*------------------------------------------------------------------------* + * Simulator main, start here your threads, examples inside. * + *------------------------------------------------------------------------*/ +int main(void) { EventListener c1fel, c2fel; + InitCore(); + + // Startup ChibiOS/RT. + chSysInit(); + + chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); + cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); + cprint("Console service started on COM1, COM2\n"); cprint(" - Listening for connections on COM1\n"); chFDDGetAndClearFlags(&COM1); -- cgit v1.2.3 From ba20b5cd23ae74c1f4f925b7b8d3a84dbd42fd9e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Nov 2007 13:44:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@98 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.h | 1 + 1 file changed, 1 insertion(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 268cae39b..5217e30f6 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -101,6 +101,7 @@ extern void chSysUnlock(void); (INT_REQUIRED_STACK) + \ (n)) +/* It requires zero bytes, but better be safe.*/ #define IDLE_THREAD_STACK_SIZE 8 void _IdleThread(void *p) __attribute__((noreturn)); -- cgit v1.2.3 From d1733a8bd3635776fe3c762891ede4abf77e2b24 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 Nov 2007 16:42:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@102 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 17 +++-- demos/ARM7-LPC214x-GCC/Makefile.thumb | 24 +++++-- demos/ARM7-LPC214x-GCC/chcore.c | 38 +---------- demos/ARM7-LPC214x-GCC/chcore2.s | 124 ++++++++++++++++++++++++++++------ demos/ARM7-LPC214x-GCC/crt0.s | 35 +++++++--- 5 files changed, 157 insertions(+), 81 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index b078b8f88..6c0750add 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -127,10 +127,19 @@ CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms +# Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) - ASFLAGS += -mthumb-interwork -D THUMB_INTERWORK - CPFLAGS += -mthumb-interwork -D THUMB_INTERWORK - LDFLAGS += -mthumb-interwork + ifneq ($(ASRC),) + # Both ARM and THUMB case + CPFLAGS += -mthumb-interwork -D THUMB + LDFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork -D THUMB + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly + CPFLAGS += -D THUMB + LDFLAGS += -mthumb + ASFLAGS += -mthumb-interwork -D THUMB -D PURE_THUMB + endif endif # Generate dependency information @@ -148,7 +157,7 @@ $(AOBJS) : %.o : %.c $(TOBJS) : %.o : %.c @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + $(CC) -c $(CPFLAGS) $(TOPT) -mthumb -I . $(INCDIR) $< -o $@ $(ASMOBJS) : %.o : %.s @echo diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 8c6147f15..05a63460d 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -62,12 +62,13 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = chcore.c +ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ +TSRC = chcore.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ @@ -91,14 +92,14 @@ ULIBS = AOPT = # THUMB-specific options here -TOPT = -mthumb -D THUMB +TOPT = -mthumb # Common options here # NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing #OPT += -ffixed-r7 OPT += -falign-functions=16 @@ -125,10 +126,19 @@ CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms +# Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) - ASFLAGS += -mthumb-interwork -D THUMB_INTERWORK - CPFLAGS += -mthumb-interwork -D THUMB_INTERWORK - LDFLAGS += -mthumb-interwork + ifneq ($(ASRC),) + # Both ARM and THUMB case + CPFLAGS += -mthumb-interwork -D THUMB + LDFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork -D THUMB + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly + CPFLAGS += -D THUMB + LDFLAGS += -mthumb + ASFLAGS += -mthumb-interwork -D THUMB -D PURE_THUMB + endif endif # Generate dependency information diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index bf157cf43..49d1d314f 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -159,48 +159,12 @@ void _IdleThread(void *p) { void chSysHalt(void) { chSysLock(); - IO0SET = 0x80000C00; + IO0SET = 0x00000C00; IO0CLR = 0x80000000; while (TRUE) ; } -/* - * Undefined Instruction exception handler. - * Yellow LED + RED LED 2. - */ -void UndHandler(void) { - - IO0SET = 0x80000C00; - IO0CLR = 0x80000800; - while(TRUE) - ; -} - -/* - * Prefetch exception handler. - * Yellow LED + RED LED 1. - */ -void PrefetchHandler(void) { - - IO0SET = 0x80000C00; - IO0CLR = 0x80000400; - while(TRUE) - ; -} - -/* - * Abort exception handler. - * Yellow LED + both RED LEDs. - */ -void AbortHandler(void) { - - IO0SET = 0x80000C00; - IO0CLR = 0x80000C00; - while(TRUE) - ; -} - /* * Non-vectored IRQs handling here. */ diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index e29c92f5e..f81a4eeb1 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -38,52 +38,72 @@ threadstart: msr CPSR_c, #MODE_SYS mov r0, r5 -/* blx r4*/ +#ifndef PURE_THUMB mov lr, pc bx r4 bl chThdExit +#else + mov lr, pc + bx r4 +.code 16 + ldr r4, =chThdExit + bx r4 +#endif + +.globl UndHandler +UndHandler: .globl SwiHandler SwiHandler: - b SwiHandler + +.globl PrefetchHandler +PrefetchHandler: + +.globl AbortHandler +AbortHandler: .globl FiqHandler FiqHandler: - b FiqHandler +#ifdef PURE_THUMB + ldr r0, =chSysHalt + bx r0 +#else + bl chSysHalt +#endif -#ifdef THUMB_INTERWORK +#ifdef THUMB .globl chSysLock chSysLock: - msr CPSR_c, #0x9F - bx lr + msr CPSR_c, #0x9F + bx lr .globl chSysUnlock chSysUnlock: - msr CPSR_c, #0x1F - bx lr + msr CPSR_c, #0x1F + bx lr #endif .globl chSysSwitchI chSysSwitchI: #ifdef CH_CURRP_REGISTER_CACHE - stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB_INTERWORK - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - bx lr + stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] +#ifdef THUMB + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + bx lr #else - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} #endif #else - stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB_INTERWORK - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - bx lr + stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] +#ifdef THUMB + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + bx lr #else - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} #endif #endif /* CH_CURRP_REGISTER_CACHE */ @@ -115,28 +135,68 @@ chSysSwitchI: IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} +#ifdef PURE_THUMB + ldr r0, =NonVectoredIrq + mov lr, pc + bx r0 +.code 16 + mov lr, pc + bx lr +.code 32 +#else bl NonVectoredIrq +#endif b IrqCommon .globl T0IrqHandler T0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} +#ifdef PURE_THUMB + ldr r0, =Timer0Irq + mov lr, pc + bx r0 +.code 16 + mov lr, pc + bx lr +.code 32 +#else bl Timer0Irq +#endif b IrqCommon .globl UART0IrqHandler UART0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} +#ifdef PURE_THUMB + ldr r0, =UART0Irq + mov lr, pc + bx r0 +.code 16 + mov lr, pc + bx lr +.code 32 +#else bl UART0Irq +#endif b IrqCommon .globl UART1IrqHandler UART1IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} +#ifdef PURE_THUMB + ldr r0, =UART1Irq + mov lr, pc + bx r0 +.code 16 + mov lr, pc + bx lr +.code 32 +#else bl UART1Irq +#endif b IrqCommon /* @@ -144,7 +204,17 @@ UART1IrqHandler: * required. */ IrqCommon: +#ifdef PURE_THUMB + ldr r0, =chSchRescRequiredI + mov lr, pc + bx r0 +.code 16 + mov lr, pc + bx lr +.code 32 +#else bl chSchRescRequiredI +#endif cmp r0, #0 // Simply returns if a ldmeqfd sp!, {r0-r3, r12, pc}^ // reschedule is not required. @@ -159,7 +229,17 @@ IrqCommon: stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. // Context switch. +#ifdef PURE_THUMB + ldr r0, =chSchDoRescheduleI + mov lr, pc + bx r0 +.code 16 + mov lr, pc + bx lr +.code 32 +#else bl chSchDoRescheduleI +#endif // Re-establish the IRQ conditions again. ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. diff --git a/demos/ARM7-LPC214x-GCC/crt0.s b/demos/ARM7-LPC214x-GCC/crt0.s index 9b413191b..7bf91e291 100644 --- a/demos/ARM7-LPC214x-GCC/crt0.s +++ b/demos/ARM7-LPC214x-GCC/crt0.s @@ -99,17 +99,8 @@ ResetHandler: /* System */ msr CPSR_c, #MODE_SYS | I_BIT | F_BIT mov sp, r0 - ldr r1, =__sys_stack_size__ - sub r0, r0, r1 - /* - * Check on allocated stacks size. This should never happen unless you - * don't care to verify the map file after compiling your application. - */ - ldr r1, =_bss_end - cmp r0, r1 - bge ramsizeok - bl chSysHalt -ramsizeok: +// ldr r1, =__sys_stack_size__ +// sub r0, r0, r1 /* * Data initialization. * NOTE: It assumes that the DATA size is a multiple of 4. @@ -136,11 +127,33 @@ bssloop: /* * Application-provided HW initialization routine. */ +#ifndef PURE_THUMB bl hwinit +#else + ldr r0, =hwinit + mov lr, pc + bx r0 +.code 16 + mov lr, pc + bx lr +.code 32 +#endif /* * main(0, NULL). */ mov r0, #0 mov r1, #0 +#ifndef PURE_THUMB bl main bl chSysHalt +#else + ldr r2, =main + mov lr, pc + bx r2 +.code 16 + mov lr, pc + bx lr +.code 32 + ldr r2, =chSysHalt + bx r2 +#endif -- cgit v1.2.3 From 8d478094e0b24d5ba94a4ba69cc291210ed3807f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 Nov 2007 20:39:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@103 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore2.s | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index f81a4eeb1..c9ad0c208 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -37,17 +37,21 @@ .globl threadstart threadstart: msr CPSR_c, #MODE_SYS - mov r0, r5 #ifndef PURE_THUMB + mov r0, r5 mov lr, pc bx r4 bl chThdExit #else - mov lr, pc - bx r4 + ldr r0, =.L1 + bx r0 .code 16 - ldr r4, =chThdExit +.L1: + mov r0, r5 + mov lr, pc bx r4 + bl chThdExit +.code 32 #endif .globl UndHandler -- cgit v1.2.3 From 080fb7d084f878e792563a60a255b5fc993ae0ba Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 22 Nov 2007 11:29:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@104 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/Makefile.thumb | 4 +-- demos/ARM7-LPC214x-GCC/chcore2.s | 63 ++++++++++++++++------------------- demos/ARM7-LPC214x-GCC/crt0.s | 28 +++++----------- demos/ARM7-LPC214x-GCC/main.c | 6 ---- 5 files changed, 40 insertions(+), 63 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 6c0750add..3698582e7 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -138,7 +138,7 @@ ifneq ($(TSRC),) # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly CPFLAGS += -D THUMB LDFLAGS += -mthumb - ASFLAGS += -mthumb-interwork -D THUMB -D PURE_THUMB + ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING endif endif diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 05a63460d..c08d632f9 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -135,9 +135,9 @@ ifneq ($(TSRC),) ASFLAGS += -mthumb-interwork -D THUMB else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly - CPFLAGS += -D THUMB + CPFLAGS += -D THUMB -D THUMB_NO_INTERWORKING LDFLAGS += -mthumb - ASFLAGS += -mthumb-interwork -D THUMB -D PURE_THUMB + ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING endif endif diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index c9ad0c208..a450d9b74 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -37,16 +37,15 @@ .globl threadstart threadstart: msr CPSR_c, #MODE_SYS -#ifndef PURE_THUMB +#ifndef THUMB_NO_INTERWORKING mov r0, r5 mov lr, pc bx r4 bl chThdExit #else - ldr r0, =.L1 + add r0, pc, #1 bx r0 .code 16 -.L1: mov r0, r5 mov lr, pc bx r4 @@ -68,7 +67,7 @@ AbortHandler: .globl FiqHandler FiqHandler: -#ifdef PURE_THUMB +#ifdef THUMB_NO_INTERWORKING ldr r0, =chSysHalt bx r0 #else @@ -139,80 +138,74 @@ chSysSwitchI: IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -#ifdef PURE_THUMB - ldr r0, =NonVectoredIrq - mov lr, pc +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 bx r0 .code 16 - mov lr, pc - bx lr + bl NonVectoredIrq + b IrqCommon .code 32 #else bl NonVectoredIrq -#endif b IrqCommon +#endif .globl T0IrqHandler T0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -#ifdef PURE_THUMB - ldr r0, =Timer0Irq - mov lr, pc +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 bx r0 .code 16 - mov lr, pc - bx lr + bl Timer0Irq + b IrqCommon .code 32 #else bl Timer0Irq -#endif b IrqCommon +#endif .globl UART0IrqHandler UART0IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -#ifdef PURE_THUMB - ldr r0, =UART0Irq - mov lr, pc +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 bx r0 .code 16 - mov lr, pc - bx lr + bl UART0Irq + b IrqCommon .code 32 #else bl UART0Irq -#endif b IrqCommon +#endif .globl UART1IrqHandler UART1IrqHandler: sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} -#ifdef PURE_THUMB - ldr r0, =UART1Irq - mov lr, pc +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 bx r0 .code 16 - mov lr, pc - bx lr + bl UART1Irq + b IrqCommon .code 32 #else bl UART1Irq -#endif b IrqCommon +#endif /* * Common exit point for all IRQ routines, it performs the rescheduling if * required. */ IrqCommon: -#ifdef PURE_THUMB - ldr r0, =chSchRescRequiredI - mov lr, pc - bx r0 +#ifdef THUMB_NO_INTERWORKING .code 16 + bl chSchRescRequiredI mov lr, pc bx lr .code 32 @@ -233,11 +226,11 @@ IrqCommon: stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. // Context switch. -#ifdef PURE_THUMB - ldr r0, =chSchDoRescheduleI - mov lr, pc +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 bx r0 .code 16 + bl chSchDoRescheduleI mov lr, pc bx lr .code 32 diff --git a/demos/ARM7-LPC214x-GCC/crt0.s b/demos/ARM7-LPC214x-GCC/crt0.s index 7bf91e291..a7845036d 100644 --- a/demos/ARM7-LPC214x-GCC/crt0.s +++ b/demos/ARM7-LPC214x-GCC/crt0.s @@ -127,33 +127,23 @@ bssloop: /* * Application-provided HW initialization routine. */ -#ifndef PURE_THUMB +#ifndef THUMB_NO_INTERWORKING bl hwinit -#else - ldr r0, =hwinit - mov lr, pc - bx r0 -.code 16 - mov lr, pc - bx lr -.code 32 -#endif /* * main(0, NULL). */ mov r0, #0 - mov r1, #0 -#ifndef PURE_THUMB + mov r1, r0 bl main bl chSysHalt #else - ldr r2, =main - mov lr, pc - bx r2 + add r0, pc, #1 + bx r0 .code 16 - mov lr, pc - bx lr + bl hwinit + mov r0, #0 + mov r1, r0 + bl main + bl chSysHalt .code 32 - ldr r2, =chSysHalt - bx r2 #endif diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 1829e6eb6..f84874f78 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -135,12 +135,6 @@ int main(int argc, char **argv) { chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); } - /* - * Allows the other threads to run by lowering the priority, remember, - * the priority is set to the maximum in the \p chSysInit(). - */ - chThdSetPriority(NORMALPRIO); - /* * Normal main() activity, in this demo it serves events generated by * various sources. -- cgit v1.2.3 From 97bf45204321755cf2e78a7cc7ff616edaec59c4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 22 Nov 2007 15:24:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@105 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 197 ++++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 196 ++++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/ch.ld | 85 +++++++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 167 +++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/chcore.c | 184 +++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/chcore.h | 117 ++++++++++++ demos/ARM7-LPC214x-GCC-minimal/chcore2.s | 251 ++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/chtypes.h | 47 +++++ demos/ARM7-LPC214x-GCC-minimal/crt0.s | 149 +++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/main.c | 82 +++++++++ demos/ARM7-LPC214x-GCC-minimal/readme.txt | 18 ++ demos/ARM7-LPC214x-GCC/chcore.h | 12 +- demos/ARM7-LPC214x-GCC/main.c | 4 +- demos/AVR-AT90CANx-GCC/chcore.h | 2 + demos/AVR-AT90CANx-GCC/main.c | 2 +- demos/Win32-MSVS/chcore.h | 2 + demos/Win32-MSVS/demo.c | 10 +- demos/Win32-MinGW/chcore.h | 2 + demos/Win32-MinGW/demo.c | 10 +- 19 files changed, 1519 insertions(+), 18 deletions(-) create mode 100644 demos/ARM7-LPC214x-GCC-minimal/Makefile create mode 100644 demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb create mode 100644 demos/ARM7-LPC214x-GCC-minimal/ch.ld create mode 100644 demos/ARM7-LPC214x-GCC-minimal/chconf.h create mode 100644 demos/ARM7-LPC214x-GCC-minimal/chcore.c create mode 100644 demos/ARM7-LPC214x-GCC-minimal/chcore.h create mode 100644 demos/ARM7-LPC214x-GCC-minimal/chcore2.s create mode 100644 demos/ARM7-LPC214x-GCC-minimal/chtypes.h create mode 100644 demos/ARM7-LPC214x-GCC-minimal/crt0.s create mode 100644 demos/ARM7-LPC214x-GCC-minimal/main.c create mode 100644 demos/ARM7-LPC214x-GCC-minimal/readme.txt (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile new file mode 100644 index 000000000..f440f799d --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -0,0 +1,197 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +ASRC = chcore.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ + ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c \ + main.c + + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = + +# List ASM source files here +ASMSRC = crt0.s chcore2.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT += -ffixed-r7 +OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + ifneq ($(ASRC),) + # Both ARM and THUMB case + CPFLAGS += -mthumb-interwork -D THUMB + LDFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork -D THUMB + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly + CPFLAGS += -D THUMB + LDFLAGS += -mthumb + ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING + endif +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -mthumb -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb new file mode 100644 index 000000000..03f2c7ba9 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -0,0 +1,196 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +ASRC = + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = chcore.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ + ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c \ + main.c + +# List ASM source files here +ASMSRC = crt0.s chcore2.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT += -ffixed-r7 +OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + ifneq ($(ASRC),) + # Both ARM and THUMB case + CPFLAGS += -mthumb-interwork -D THUMB + LDFLAGS += -mthumb-interwork + ASFLAGS += -mthumb-interwork -D THUMB + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly + CPFLAGS += -D THUMB -D THUMB_NO_INTERWORKING + LDFLAGS += -mthumb + ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING + endif +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld new file mode 100644 index 000000000..ace1c3b53 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -0,0 +1,85 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0100; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : + { + _text = .; + *(.text); + *(.rodata); + *(.rodata*); + *(.glue_7t); + *(.glue_7); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h new file mode 100644 index 000000000..70908e292 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -0,0 +1,167 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +//#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +//#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +//#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +//#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +//#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Semaphores APIs with priority + * shift are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES.*/ +//#define CH_USE_RT_SEMAPHORES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +//#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +//#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +//#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +//#define CH_USE_MESSAGES_TIMEOUT + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +//#define CH_USE_MESSAGES_EVENT + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +//#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +//#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +//#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +//#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +//#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +//#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.c b/demos/ARM7-LPC214x-GCC-minimal/chcore.c new file mode 100644 index 000000000..068774d17 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore.c @@ -0,0 +1,184 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "vic.h" +//#include "lpc214x_serial.h" +//#include "lpc214x_ssp.h" +//#include "mmcsd.h" + +//#include "buzzer.h" + +extern void IrqHandler(void); +extern void T0IrqHandler(void); + +#define VAL_TC0_PRESCALER 0 + +/* + * Pins configuration for Olimex LPC-P2148. + * + * PINSEL0 + * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD + * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 + * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 + * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- + * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + * + * PINSEL1 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 + * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 + * + * PINSEL2 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- + * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- + */ +#define VAL_PINSEL0 0x00055555 +#define VAL_PINSEL1 0x100840A8 +#define VAL_PINSEL2 0x00000004 +#define VAL_FIO0DIR 0xB0703C00 +#define VAL_FIO1DIR 0x00000000 + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLLBase; + pll->PLL0_CFG = 0x23; /* P and M values. */ + pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + while (!(pll->PLL0_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL0_CON = 0x3; /* Connects the PLL. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; + + /* + * I/O pins configuration. + */ + PINSEL0 = VAL_PINSEL0; + PINSEL1 = VAL_PINSEL1; + PINSEL2 = VAL_PINSEL2; + IO0DIR = VAL_FIO0DIR; + IO0SET = 0xFFFFFFFF; + IO1DIR = VAL_FIO1DIR; + IO1SET = 0xFFFFFFFF; + + /* + * Interrupt vectors assignment. + */ + InitVIC(); + VICDefVectAddr = (IOREG32)IrqHandler; + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); +// SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); +// SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); + + /* + * System Timer initialization, 1ms intervals. + */ + VICIntEnable = INTMASK(SOURCE_Timer0); + TC *timer = T0Base; + timer->TC_PR = VAL_TC0_PRESCALER; + timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); + timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ + timer->TC_TCR = 2; /* Reset counter and prescaler. */ + timer->TC_TCR = 1; /* Timer enabled. */ + + /* + * Other subsystems. + */ +// InitSerial(); +// InitSSP(); +// InitMMC(); +// InitBuzzer(); +} + +/* + * System idle thread loop. + */ +void _IdleThread(void *p) { + + while (TRUE) { +// Note, it is disabled because it causes trouble with the JTAG probe. +// Enable it in the final code only. +// PCON = 1; + } +} + +/* + * System halt. + * Yellow LED only. + */ +void chSysHalt(void) { + + chSysLock(); + IO0SET = 0x00000C00; + IO0CLR = 0x80000000; + while (TRUE) + ; +} + +/* + * Non-vectored IRQs handling here. + */ +void NonVectoredIrq(void) { + + VICVectAddr = 0; +} + +/* + * Timer 0 IRQ handling here. + */ +void Timer0Irq(void) { + + T0IR = 1; /* Clear interrupt on match MR0. */ + chSchTimerHandlerI(); + VICVectAddr = 0; +} diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.h b/demos/ARM7-LPC214x-GCC-minimal/chcore.h new file mode 100644 index 000000000..d5ad07040 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore.h @@ -0,0 +1,117 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/* + * The following values are implementation dependent. You may change them in + * order to match your HW. + */ +#define FOSC 12000000 +#define CCLK 48000000 +#define PCLK 12000000 + +typedef void *regarm; + +/* + * Interrupt saved context. + */ +struct extctx { + regarm spsr_irq; + regarm lr_irq; + regarm r0; + regarm r1; + regarm r2; + regarm r3; + regarm r12; +}; + +/* + * System saved context. + */ +struct intctx { + regarm r4; + regarm r5; + regarm r6; +#ifndef CH_CURRP_REGISTER_CACHE + regarm r7; +#endif + regarm r8; + regarm r9; + regarm r10; + regarm r11; + regarm lr; +}; + +/* + * Port dependent part of the Thread structure, you may add fields in + * this structure. + */ +typedef struct { + struct intctx *r13; +} Context; + +/* + * Platform dependent part of the \p chThdCreate() API. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = threadstart; \ +} + +#ifdef THUMB +extern void chSysLock(void); +extern void chSysUnlock(void); +#else /* !THUMB */ +#define chSysLock() asm("msr CPSR_c, #0x9F") +#define chSysUnlock() asm("msr CPSR_c, #0x1F") +#endif /* THUMB */ + +#define chSysPuts(msg) {} + +#ifdef THUMB +#define INT_REQUIRED_STACK 0x10 +#else /* !THUMB */ +#define INT_REQUIRED_STACK 0 +#endif /* THUMB */ +#define UserStackSize(n) (((sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (INT_REQUIRED_STACK) + \ + (n) - 1) | 3) + 1) + +#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; + +/* It requires zero bytes, but better be safe.*/ +#define IDLE_THREAD_STACK_SIZE 8 +void _IdleThread(void *p) __attribute__((noreturn)); + +void chSysHalt(void) __attribute__((noreturn)); +void chSysSwitchI(Context *oldp, Context *newp); +void threadstart(void); +void DefFiqHandler(void); +void DefIrqHandler(void); +void SpuriousHandler(void); + +#endif /* _CHCORE_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s new file mode 100644 index 000000000..f8906d022 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s @@ -0,0 +1,251 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "chconf.h" + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text +.code 32 +.balign 4 + +.globl threadstart +threadstart: + msr CPSR_c, #MODE_SYS +#ifndef THUMB_NO_INTERWORKING + mov r0, r5 + mov lr, pc + bx r4 + bl chThdExit +#else + add r0, pc, #1 + bx r0 +.code 16 + mov r0, r5 + mov lr, pc + bx r4 + bl chThdExit +.code 32 +#endif + +.globl UndHandler +UndHandler: + +.globl SwiHandler +SwiHandler: + +.globl PrefetchHandler +PrefetchHandler: + +.globl AbortHandler +AbortHandler: + +.globl FiqHandler +FiqHandler: +#ifdef THUMB_NO_INTERWORKING + ldr r0, =chSysHalt + bx r0 +#else + bl chSysHalt +#endif + +#ifdef THUMB +.globl chSysLock +chSysLock: + msr CPSR_c, #0x9F + bx lr + +.globl chSysUnlock +chSysUnlock: + msr CPSR_c, #0x1F + bx lr +#endif + +.globl chSysSwitchI +chSysSwitchI: +#ifdef CH_CURRP_REGISTER_CACHE + stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] +#ifdef THUMB + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} + bx lr +#else + ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} +#endif +#else + stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + str sp, [r0, #0] + ldr sp, [r1, #0] +#ifdef THUMB + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} + bx lr +#else + ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} +#endif +#endif /* CH_CURRP_REGISTER_CACHE */ + +/* + * System stack frame structure after a context switch in the + * interrupt handler: + * + * High +------------+ + * | R12 | -+ + * | R3 | | + * | R2 | | + * | R1 | | External context: IRQ handler frame + * | R0 | | + * | LR_IRQ | | (user code return address) + * | SPSR | -+ (user code status) + * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space + * | LR | -+ (system code return address) + * | R11 | | + * | R10 | | + * | R9 | | + * | R8 | | Internal context: mk_SwitchI() frame + * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) + * | R6 | | + * | R5 | | + * SP-> | R4 | -+ + * Low +------------+ + */ +.globl IrqHandler +IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 +.code 16 + bl NonVectoredIrq + b IrqCommon +.code 32 +#else + bl NonVectoredIrq + b IrqCommon +#endif + +.globl T0IrqHandler +T0IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 +.code 16 + bl Timer0Irq + b IrqCommon +.code 32 +#else + bl Timer0Irq + b IrqCommon +#endif + +/* +.globl UART0IrqHandler +UART0IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 +.code 16 + bl UART0Irq + b IrqCommon +.code 32 +#else + bl UART0Irq + b IrqCommon +#endif + +.globl UART1IrqHandler +UART1IrqHandler: + sub lr, lr, #4 + stmfd sp!, {r0-r3, r12, lr} +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 +.code 16 + bl UART1Irq + b IrqCommon +.code 32 +#else + bl UART1Irq + b IrqCommon +#endif +*/ + +/* + * Common exit point for all IRQ routines, it performs the rescheduling if + * required. + */ +IrqCommon: +#ifdef THUMB_NO_INTERWORKING +.code 16 + bl chSchRescRequiredI + mov lr, pc + bx lr +.code 32 +#else + bl chSchRescRequiredI +#endif + cmp r0, #0 // Simply returns if a + ldmeqfd sp!, {r0-r3, r12, pc}^ // reschedule is not required. + + // Saves the IRQ mode registers in the system stack. + ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0-r3, r12} // Registers on System Stack. + msr CPSR_c, #MODE_IRQ | I_BIT + mrs r0, SPSR + mov r1, lr + msr CPSR_c, #MODE_SYS | I_BIT + stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. + + // Context switch. +#ifdef THUMB_NO_INTERWORKING + add r0, pc, #1 + bx r0 +.code 16 + bl chSchDoRescheduleI + mov lr, pc + bx lr +.code 32 +#else + bl chSchDoRescheduleI +#endif + + // Re-establish the IRQ conditions again. + ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. + msr CPSR_c, #MODE_IRQ | I_BIT + msr SPSR_fsxc, r0 + mov lr, r1 + msr CPSR_c, #MODE_SYS | I_BIT + ldmfd sp!, {r0-r3, r12} + msr CPSR_c, #MODE_IRQ | I_BIT + subs pc, lr, #0 diff --git a/demos/ARM7-LPC214x-GCC-minimal/chtypes.h b/demos/ARM7-LPC214x-GCC-minimal/chtypes.h new file mode 100644 index 000000000..2ac219148 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/chtypes.h @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +/* + * Generic types often dependant on the compiler. + */ +#define BOOL char +#define BYTE8 unsigned char +#define SBYTE8 char +#define WORD16 short +#define UWORD16 unsigned short +#define LONG32 int +#define ULONG32 unsigned int + +typedef BYTE8 t_tmode; +typedef BYTE8 t_tstate; +typedef UWORD16 t_tid; +typedef ULONG32 t_prio; +typedef LONG32 t_msg; +typedef LONG32 t_eventid; +typedef ULONG32 t_eventmask; +typedef ULONG32 t_time; +typedef LONG32 t_cnt; +typedef ULONG32 t_size; + +#define INLINE inline + +#endif /* _CHTYPES_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/crt0.s b/demos/ARM7-LPC214x-GCC-minimal/crt0.s new file mode 100644 index 000000000..a7845036d --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/crt0.s @@ -0,0 +1,149 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Generic ARM startup file for ChibiOS/RT. + */ + +.extern _main + +.set MODE_USR, 0x10 +.set MODE_FIQ, 0x11 +.set MODE_IRQ, 0x12 +.set MODE_SVC, 0x13 +.set MODE_ABT, 0x17 +.set MODE_UND, 0x1B +.set MODE_SYS, 0x1F + +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 + +.text +.code 32 +.balign 4 +/* + * System entry points. + */ +_start: + b ResetHandler + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ + ldr pc, _fiq + +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler +_fiq: + .word FiqHandler + .word 0 + .word 0 + +/* + * Reset handler. + */ +ResetHandler: + /* + * Stack pointers initialization. + */ + ldr r0, =__ram_end__ + /* Undefined */ + msr CPSR_c, #MODE_UND | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__und_stack_size__ + sub r0, r0, r1 + /* Abort */ + msr CPSR_c, #MODE_ABT | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__abt_stack_size__ + sub r0, r0, r1 + /* FIQ */ + msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__fiq_stack_size__ + sub r0, r0, r1 + /* IRQ */ + msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__irq_stack_size__ + sub r0, r0, r1 + /* Supervisor */ + msr CPSR_c, #MODE_SVC | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__svc_stack_size__ + sub r0, r0, r1 + /* System */ + msr CPSR_c, #MODE_SYS | I_BIT | F_BIT + mov sp, r0 +// ldr r1, =__sys_stack_size__ +// sub r0, r0, r1 + /* + * Data initialization. + * NOTE: It assumes that the DATA size is a multiple of 4. + */ + ldr r1, =_textdata + ldr r2, =_data + ldr r3, =_edata +dataloop: + cmp r2, r3 + ldrlo r0, [r1], #4 + strlo r0, [r2], #4 + blo dataloop + /* + * BSS initialization. + * NOTE: It assumes that the BSS size is a multiple of 4. + */ + mov r0, #0 + ldr r1, =_bss_start + ldr r2, =_bss_end +bssloop: + cmp r1, r2 + strlo r0, [r1], #4 + blo bssloop + /* + * Application-provided HW initialization routine. + */ +#ifndef THUMB_NO_INTERWORKING + bl hwinit + /* + * main(0, NULL). + */ + mov r0, #0 + mov r1, r0 + bl main + bl chSysHalt +#else + add r0, pc, #1 + bx r0 +.code 16 + bl hwinit + mov r0, #0 + mov r1, r0 + bl main + bl chSysHalt +.code 32 +#endif diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c new file mode 100644 index 000000000..5a0b1e80a --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WorkingArea(waThread1, 32); +static t_msg Thread1(void *arg) { + + while (TRUE) { + IO0CLR = 0x00000800; + chThdSleep(200); + IO0SET = 0x00000C00; + chThdSleep(800); + IO0CLR = 0x00000400; + chThdSleep(200); + IO0SET = 0x00000C00; + chThdSleep(800); + } + return 0; +} + +/* + * Yellow LED blinker thread, times are in milliseconds. + */ +static WorkingArea(waThread2, 32); +static t_msg Thread2(void *arg) { + + while (TRUE) { + IO0CLR = 0x80000000; + chThdSleep(200); + IO0SET = 0x80000000; + chThdSleep(300); + } + return 0; +} + +/* + * Entry point, the interrupts are disabled on entry. + */ +int main(int argc, char **argv) { + + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ + chSysInit(); + + /* + * Creates the blinker threads. + */ + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop. + */ + while (TRUE) + chThdSleep(1000); + return 0; +} diff --git a/demos/ARM7-LPC214x-GCC-minimal/readme.txt b/demos/ARM7-LPC214x-GCC-minimal/readme.txt new file mode 100644 index 000000000..363cd8dde --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/readme.txt @@ -0,0 +1,18 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI LPC214X. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +This is a minimal demo, it just blinks the leds on the board by using multiple +threads, most subsystems are disabled. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 5217e30f6..d5ad07040 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -95,11 +95,13 @@ extern void chSysUnlock(void); #else /* !THUMB */ #define INT_REQUIRED_STACK 0 #endif /* THUMB */ -#define UserStackSize(n) (sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (INT_REQUIRED_STACK) + \ - (n)) +#define UserStackSize(n) (((sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (INT_REQUIRED_STACK) + \ + (n) - 1) | 3) + 1) + +#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; /* It requires zero bytes, but better be safe.*/ #define IDLE_THREAD_STACK_SIZE 8 diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index f84874f78..71fba60a8 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -28,7 +28,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static BYTE8 waThread1[UserStackSize(32)]; +static WorkingArea(waThread1, 32); static t_msg Thread1(void *arg) { while (TRUE) { @@ -47,7 +47,7 @@ static t_msg Thread1(void *arg) { /* * Yellow LED blinker thread, times are in milliseconds. */ -static BYTE8 waThread2[UserStackSize(32)]; +static WorkingArea(waThread2, 32); static t_msg Thread2(void *arg) { while (TRUE) { diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h index 32c939d32..07cb45f64 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.h +++ b/demos/AVR-AT90CANx-GCC/chcore.h @@ -103,6 +103,8 @@ typedef struct { EXTRA_INT_STACK + \ (n)) +#define WorkingArea(s, n) BYTE8 s[UserStackSize(n)]; + #define chSysLock() asm("cli") #define chSysUnlock() asm("sei") #define chSysPuts(msg) {} diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 61156b040..14c45cf47 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -23,7 +23,7 @@ void hwinit(void); -static BYTE8 waThread1[UserStackSize(32)]; +static WorkingArea(waThread1, 32); static t_msg Thread1(void *arg) { while (TRUE) { diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h index 6d11921cf..15a21fb40 100644 --- a/demos/Win32-MSVS/chcore.h +++ b/demos/Win32-MSVS/chcore.h @@ -65,6 +65,8 @@ typedef struct { #define UserStackSize(n) (sizeof(Thread) + sizeof(void *)*2 + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) +#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; + #define IDLE_THREAD_STACK_SIZE 16384 t_msg _IdleThread(void *p); diff --git a/demos/Win32-MSVS/demo.c b/demos/Win32-MSVS/demo.c index 1d4f4aa16..7f8bd6903 100644 --- a/demos/Win32-MSVS/demo.c +++ b/demos/Win32-MSVS/demo.c @@ -23,10 +23,10 @@ #include static ULONG32 wdguard; -static BYTE8 wdarea[UserStackSize(2048)]; +static WorkingArea(wdarea, 2048); static ULONG32 cdguard; -static BYTE8 cdarea[UserStackSize(2048)]; +static WorkingArea(cdarea, 2048); static Thread *cdtp; static t_msg WatchdogThread(void *arg); @@ -159,7 +159,7 @@ static t_msg ShellThread(void *arg) { FullDuplexDriver *sd = (FullDuplexDriver *)arg; char *lp, line[64]; Thread *tp; - BYTE8 tarea[UserStackSize(1024)]; + WorkingArea(tarea, 1024); chIQReset(&sd->sd_iqueue); chOQReset(&sd->sd_oqueue); @@ -221,7 +221,7 @@ static t_msg ShellThread(void *arg) { return 0; } -static BYTE8 s1area[UserStackSize(4096)]; +static WorkingArea(s1area, 2048); static Thread *s1; EventListener s1tel; @@ -244,7 +244,7 @@ static void COM1Handler(t_eventid id) { chIQReset(&COM1.sd_iqueue); } -static BYTE8 s2area[UserStackSize(4096)]; +static WorkingArea(s2area, 2048); static Thread *s2; EventListener s2tel; diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index a28aa2833..c79b9bf81 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -65,6 +65,8 @@ typedef struct { #define UserStackSize(n) (sizeof(Thread) + sizeof(void *) * 2 + \ sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) +#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; + #define IDLE_THREAD_STACK_SIZE 16384 t_msg _IdleThread(void *p); diff --git a/demos/Win32-MinGW/demo.c b/demos/Win32-MinGW/demo.c index 1d4f4aa16..7f8bd6903 100644 --- a/demos/Win32-MinGW/demo.c +++ b/demos/Win32-MinGW/demo.c @@ -23,10 +23,10 @@ #include static ULONG32 wdguard; -static BYTE8 wdarea[UserStackSize(2048)]; +static WorkingArea(wdarea, 2048); static ULONG32 cdguard; -static BYTE8 cdarea[UserStackSize(2048)]; +static WorkingArea(cdarea, 2048); static Thread *cdtp; static t_msg WatchdogThread(void *arg); @@ -159,7 +159,7 @@ static t_msg ShellThread(void *arg) { FullDuplexDriver *sd = (FullDuplexDriver *)arg; char *lp, line[64]; Thread *tp; - BYTE8 tarea[UserStackSize(1024)]; + WorkingArea(tarea, 1024); chIQReset(&sd->sd_iqueue); chOQReset(&sd->sd_oqueue); @@ -221,7 +221,7 @@ static t_msg ShellThread(void *arg) { return 0; } -static BYTE8 s1area[UserStackSize(4096)]; +static WorkingArea(s1area, 2048); static Thread *s1; EventListener s1tel; @@ -244,7 +244,7 @@ static void COM1Handler(t_eventid id) { chIQReset(&COM1.sd_iqueue); } -static BYTE8 s2area[UserStackSize(4096)]; +static WorkingArea(s2area, 2048); static Thread *s2; EventListener s2tel; -- cgit v1.2.3 From f2ced068fb80aa38326e1ef75eafdd5834e9017a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 23 Nov 2007 13:53:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@107 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/main.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 71fba60a8..b98747d20 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -139,13 +139,13 @@ int main(int argc, char **argv) { * Normal main() activity, in this demo it serves events generated by * various sources. */ - evtInit(&evt, 500); /* Initializes an event timer object. */ - evtRegister(&evt, &el0, 0); /* Registers on the timer event source. */ - evtStart(&evt); /* Starts the event timer. */ - mmcStartPolling(); /* Starts the MMC connector polling. */ + evtInit(&evt, 500); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + mmcStartPolling(); /* Starts the MMC connector polling. */ chEvtRegister(&MMCInsertEventSource, &el1, 1); chEvtRegister(&MMCRemoveEventSource, &el2, 2); - while (TRUE) /* Just serve events. */ + while (TRUE) /* Just serve events. */ chEvtWait(ALL_EVENTS, evhndl); return 0; } -- cgit v1.2.3 From cc85ca11fbb0b302266e09c3a85d2782ead85986 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 23 Nov 2007 14:16:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@108 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chcore2.s | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s index f8906d022..4df7c70ed 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s @@ -166,7 +166,7 @@ T0IrqHandler: b IrqCommon #endif -/* +#if 0 .globl UART0IrqHandler UART0IrqHandler: sub lr, lr, #4 @@ -182,7 +182,9 @@ UART0IrqHandler: bl UART0Irq b IrqCommon #endif +#endif +#if 0 .globl UART1IrqHandler UART1IrqHandler: sub lr, lr, #4 @@ -198,7 +200,7 @@ UART1IrqHandler: bl UART1Irq b IrqCommon #endif -*/ +#endif /* * Common exit point for all IRQ routines, it performs the rescheduling if -- cgit v1.2.3 From a134cd919ea3e6fee591bc29d360f3da74f46a8b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 27 Nov 2007 11:43:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@115 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 4 ++++ demos/ARM7-LPC214x-GCC/chconf.h | 6 +++++- demos/ARM7-LPC214x-GCC/chcore.c | 6 ++++++ demos/ARM7-LPC214x-GCC/chcore.h | 28 +++++++++++++--------------- demos/AVR-AT90CANx-GCC/chconf.h | 4 ++++ demos/AVR-AT90CANx-GCC/chcore.h | 31 +++++++++++++------------------ demos/Win32-MSVS/chconf.h | 4 ++++ demos/Win32-MinGW/chconf.h | 4 ++++ 8 files changed, 53 insertions(+), 34 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 70908e292..fc81d571f 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -162,6 +162,10 @@ */ //#define CH_USE_DEBUG +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 51aac3a64..311d6efbc 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -160,7 +160,11 @@ * @note the debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. */ -//#define CH_USE_DEBUG +#define CH_USE_DEBUG + +/** Debug option: Includes the threads context switch tracing feature. + */ +#define CH_USE_TRACE #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 49d1d314f..ad6f3a82c 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -165,6 +165,12 @@ void chSysHalt(void) { ; } +/* + * System console message (implemented via JTAG). + */ +void chSysPuts(char *msg) { +} + /* * Non-vectored IRQs handling here. */ diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index d5ad07040..5c595ae4f 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -71,13 +71,13 @@ typedef struct { /* * Platform dependent part of the \p chThdCreate() API. */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = threadstart; \ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = threadstart; \ } #ifdef THUMB @@ -88,19 +88,16 @@ extern void chSysUnlock(void); #define chSysUnlock() asm("msr CPSR_c, #0x1F") #endif /* THUMB */ -#define chSysPuts(msg) {} - #ifdef THUMB #define INT_REQUIRED_STACK 0x10 #else /* !THUMB */ #define INT_REQUIRED_STACK 0 #endif /* THUMB */ -#define UserStackSize(n) (((sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (INT_REQUIRED_STACK) + \ - (n) - 1) | 3) + 1) - +#define StackAlign(n) ((((n) - 1) | 3) + 1) +#define UserStackSize(n) StackAlign(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (INT_REQUIRED_STACK)) #define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; /* It requires zero bytes, but better be safe.*/ @@ -109,6 +106,7 @@ void _IdleThread(void *p) __attribute__((noreturn)); void chSysHalt(void) __attribute__((noreturn)); void chSysSwitchI(Context *oldp, Context *newp); +void chSysPuts(char *msg); void threadstart(void); void DefFiqHandler(void); void DefIrqHandler(void); diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index c6146f5e7..2bc89dc2f 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -163,6 +163,10 @@ */ //#define CH_USE_DEBUG +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h index 07cb45f64..9e1b95db8 100644 --- a/demos/AVR-AT90CANx-GCC/chcore.h +++ b/demos/AVR-AT90CANx-GCC/chcore.h @@ -83,26 +83,21 @@ typedef struct { /** * Platform dependent part of the \p chThdCreate() API. */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.sp--; \ - tp->p_ctx.sp->r2 = (int)pf; \ - tp->p_ctx.sp->r3 = (int)pf >> 8; \ - tp->p_ctx.sp->r4 = (int)arg; \ - tp->p_ctx.sp->r5 = (int)arg >> 8; \ - tp->p_ctx.sp->pc = (UWORD16)threadstart; \ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.sp--; \ + tp->p_ctx.sp->r2 = (int)pf; \ + tp->p_ctx.sp->r3 = (int)pf >> 8; \ + tp->p_ctx.sp->r4 = (int)arg; \ + tp->p_ctx.sp->r5 = (int)arg >> 8; \ + tp->p_ctx.sp->pc = (UWORD16)threadstart; \ } -/* - * Interrupt stack usage except for saved registers. - */ -#define EXTRA_INT_STACK 0x10 - -#define UserStackSize(n) (sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - EXTRA_INT_STACK + \ - (n)) - +#define INT_REQUIRED_STACK 0x10 +#define StackAlign(n) (n) +#define UserStackSize(n) StackAlign(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (INT_REQUIRED_STACK)) #define WorkingArea(s, n) BYTE8 s[UserStackSize(n)]; #define chSysLock() asm("cli") diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h index be1896046..5941cc856 100644 --- a/demos/Win32-MSVS/chconf.h +++ b/demos/Win32-MSVS/chconf.h @@ -167,6 +167,10 @@ */ //#define CH_USE_DEBUG +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 8ce32defa..af19dd995 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -167,6 +167,10 @@ */ //#define CH_USE_DEBUG +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + #endif /* _CHCONF_H_ */ /** @} */ -- cgit v1.2.3 From b74cb5bc1a144b1890e229cd1fc165ece4f10325 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 27 Nov 2007 13:28:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@116 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chcore.h | 28 +++++++++++++--------------- demos/ARM7-LPC214x-GCC/chconf.h | 4 ++-- demos/ARM7-LPC214x-GCC/chcore.c | 2 +- 3 files changed, 16 insertions(+), 18 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.h b/demos/ARM7-LPC214x-GCC-minimal/chcore.h index d5ad07040..5c595ae4f 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore.h @@ -71,13 +71,13 @@ typedef struct { /* * Platform dependent part of the \p chThdCreate() API. */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = threadstart; \ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = threadstart; \ } #ifdef THUMB @@ -88,19 +88,16 @@ extern void chSysUnlock(void); #define chSysUnlock() asm("msr CPSR_c, #0x1F") #endif /* THUMB */ -#define chSysPuts(msg) {} - #ifdef THUMB #define INT_REQUIRED_STACK 0x10 #else /* !THUMB */ #define INT_REQUIRED_STACK 0 #endif /* THUMB */ -#define UserStackSize(n) (((sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (INT_REQUIRED_STACK) + \ - (n) - 1) | 3) + 1) - +#define StackAlign(n) ((((n) - 1) | 3) + 1) +#define UserStackSize(n) StackAlign(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (INT_REQUIRED_STACK)) #define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; /* It requires zero bytes, but better be safe.*/ @@ -109,6 +106,7 @@ void _IdleThread(void *p) __attribute__((noreturn)); void chSysHalt(void) __attribute__((noreturn)); void chSysSwitchI(Context *oldp, Context *newp); +void chSysPuts(char *msg); void threadstart(void); void DefFiqHandler(void); void DefIrqHandler(void); diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 311d6efbc..87402547c 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -160,11 +160,11 @@ * @note the debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. */ -#define CH_USE_DEBUG +//#define CH_USE_DEBUG /** Debug option: Includes the threads context switch tracing feature. */ -#define CH_USE_TRACE +//#define CH_USE_TRACE #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index ad6f3a82c..640622e04 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -166,7 +166,7 @@ void chSysHalt(void) { } /* - * System console message (implemented via JTAG). + * System console message (not implemented). */ void chSysPuts(char *msg) { } -- cgit v1.2.3 From 6f0569444dafdae8b367a54a07a4bfaf3675f545 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 27 Nov 2007 16:02:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@117 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chcore.c | 7 +++++- demos/ARM7-LPC214x-GCC-minimal/chcore.h | 3 ++- demos/ARM7-LPC214x-GCC/chcore.h | 3 ++- demos/Win32-MSVS/chcore.c | 2 +- demos/Win32-MSVS/chcore.h | 39 ++++++++++++++++++--------------- demos/Win32-MinGW/chcore.h | 39 ++++++++++++++++++--------------- 6 files changed, 53 insertions(+), 40 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.c b/demos/ARM7-LPC214x-GCC-minimal/chcore.c index 068774d17..f844a6aa5 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore.c +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore.c @@ -24,7 +24,6 @@ //#include "lpc214x_serial.h" //#include "lpc214x_ssp.h" //#include "mmcsd.h" - //#include "buzzer.h" extern void IrqHandler(void); @@ -165,6 +164,12 @@ void chSysHalt(void) { ; } +/* + * System console message (not implemented). + */ +void chSysPuts(char *msg) { +} + /* * Non-vectored IRQs handling here. */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.h b/demos/ARM7-LPC214x-GCC-minimal/chcore.h index 5c595ae4f..941036830 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore.h @@ -97,7 +97,8 @@ extern void chSysUnlock(void); #define UserStackSize(n) StackAlign(sizeof(Thread) + \ sizeof(struct intctx) + \ sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) + (n) + \ + INT_REQUIRED_STACK) #define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; /* It requires zero bytes, but better be safe.*/ diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 5c595ae4f..941036830 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -97,7 +97,8 @@ extern void chSysUnlock(void); #define UserStackSize(n) StackAlign(sizeof(Thread) + \ sizeof(struct intctx) + \ sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) + (n) + \ + INT_REQUIRED_STACK) #define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; /* It requires zero bytes, but better be safe.*/ diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c index 0df82eec6..3915d6271 100644 --- a/demos/Win32-MSVS/chcore.c +++ b/demos/Win32-MSVS/chcore.c @@ -68,7 +68,7 @@ void ChkIntSources(void) { } } -t_msg _IdleThread(void) { +t_msg _IdleThread(void *p) { chThdSetPriority(IDLEPRIO); diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h index 15a21fb40..91fd7be9e 100644 --- a/demos/Win32-MSVS/chcore.h +++ b/demos/Win32-MSVS/chcore.h @@ -29,7 +29,7 @@ typedef void *regx86; /* * Stack saved context. */ -struct stackregs { +struct intctx { regx86 ebx; regx86 edi; regx86 esi; @@ -38,33 +38,36 @@ struct stackregs { }; typedef struct { - struct stackregs *esp; + struct intctx *esp; } Context; #define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ - BYTE8 *esp = (BYTE8 *)workspace + wsize; \ - APUSH(esp, arg); \ - APUSH(esp, threadexit); \ - esp -= sizeof(struct stackregs); \ - ((struct stackregs *)esp)->eip = pf; \ - ((struct stackregs *)esp)->ebx = 0; \ - ((struct stackregs *)esp)->edi = 0; \ - ((struct stackregs *)esp)->esi = 0; \ - ((struct stackregs *)esp)->ebp = 0; \ - tp->p_ctx.esp = (struct stackregs *)esp; \ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + BYTE8 *esp = (BYTE8 *)workspace + wsize; \ + APUSH(esp, arg); \ + APUSH(esp, threadexit); \ + esp -= sizeof(struct intctx); \ + ((struct intctx *)esp)->eip = pf; \ + ((struct intctx *)esp)->ebx = 0; \ + ((struct intctx *)esp)->edi = 0; \ + ((struct intctx *)esp)->esi = 0; \ + ((struct intctx *)esp)->ebp = 0; \ + tp->p_ctx.esp = (struct intctx *)esp; \ } #define chSysLock() #define chSysUnlock() #define chSysPuts(msg) {} -#define INT_REQUIRED_STACK 0x0 -#define UserStackSize(n) (sizeof(Thread) + sizeof(void *)*2 + \ - sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) - +#define INT_REQUIRED_STACK 0 +#define StackAlign(n) ((((n) - 1) | 3) + 1) +#define UserStackSize(n) StackAlign(sizeof(Thread) + \ + sizeof(void *) * 2 + \ + sizeof(struct intctx) + \ + (n) + \ + INT_REQUIRED_STACK) #define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; #define IDLE_THREAD_STACK_SIZE 16384 diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index c79b9bf81..2b90dd470 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -29,7 +29,7 @@ typedef void *regx86; /* * Stack saved context. */ -struct stackregs { +struct intctx { regx86 ebx; regx86 edi; regx86 esi; @@ -38,33 +38,36 @@ struct stackregs { }; typedef struct { - struct stackregs *esp; + struct intctx *esp; } Context; #define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ - BYTE8 *esp = (BYTE8 *)workspace + wsize; \ - APUSH(esp, arg); \ - APUSH(esp, threadstart); \ - esp -= sizeof(struct stackregs); \ - ((struct stackregs *)esp)->eip = pf; \ - ((struct stackregs *)esp)->ebx = 0; \ - ((struct stackregs *)esp)->edi = 0; \ - ((struct stackregs *)esp)->esi = 0; \ - ((struct stackregs *)esp)->ebp = 0; \ - tp->p_ctx.esp = (struct stackregs *)esp; \ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ +{ \ + BYTE8 *esp = (BYTE8 *)workspace + wsize; \ + APUSH(esp, arg); \ + APUSH(esp, threadstart); \ + esp -= sizeof(struct intctx); \ + ((struct intctx *)esp)->eip = pf; \ + ((struct intctx *)esp)->ebx = 0; \ + ((struct intctx *)esp)->edi = 0; \ + ((struct intctx *)esp)->esi = 0; \ + ((struct intctx *)esp)->ebp = 0; \ + tp->p_ctx.esp = (struct intctx *)esp; \ } #define chSysLock() #define chSysUnlock() #define chSysPuts(msg) {} -#define INT_REQUIRED_STACK 0x0 -#define UserStackSize(n) (sizeof(Thread) + sizeof(void *) * 2 + \ - sizeof(struct stackregs) + (n) + (INT_REQUIRED_STACK)) - +#define INT_REQUIRED_STACK 0 +#define StackAlign(n) ((((n) - 1) | 3) + 1) +#define UserStackSize(n) StackAlign(sizeof(Thread) + \ + sizeof(void *) * 2 + \ + sizeof(struct intctx) + \ + (n) + \ + INT_REQUIRED_STACK) #define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; #define IDLE_THREAD_STACK_SIZE 16384 -- cgit v1.2.3 From bef9d20d8eb9186a4f03c397ae880be7cad7efe1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 Dec 2007 14:48:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@126 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chcore.c | 2 +- demos/ARM7-LPC214x-GCC/chcore.c | 2 +- demos/AVR-AT90CANx-GCC/chcore2.S | 2 +- demos/Win32-MSVS/chcore.c | 2 +- demos/Win32-MinGW/chcore.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.c b/demos/ARM7-LPC214x-GCC-minimal/chcore.c index f844a6aa5..f4127cc8e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore.c +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore.c @@ -184,6 +184,6 @@ void NonVectoredIrq(void) { void Timer0Irq(void) { T0IR = 1; /* Clear interrupt on match MR0. */ - chSchTimerHandlerI(); + chSysTimerHandlerI(); VICVectAddr = 0; } diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 640622e04..613841437 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -185,6 +185,6 @@ void NonVectoredIrq(void) { void Timer0Irq(void) { T0IR = 1; /* Clear interrupt on match MR0. */ - chSchTimerHandlerI(); + chSysTimerHandlerI(); VICVectAddr = 0; } diff --git a/demos/AVR-AT90CANx-GCC/chcore2.S b/demos/AVR-AT90CANx-GCC/chcore2.S index 3564de521..96c17f011 100644 --- a/demos/AVR-AT90CANx-GCC/chcore2.S +++ b/demos/AVR-AT90CANx-GCC/chcore2.S @@ -97,7 +97,7 @@ __vector_17: in r0, _SFR_IO_ADDR(SREG) push r0 clr r1 - call chSchTimerHandlerI + call chSysTimerHandlerI intcommon: call chSchRescRequiredI tst r24 diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c index 3915d6271..99876b8d6 100644 --- a/demos/Win32-MSVS/chcore.c +++ b/demos/Win32-MSVS/chcore.c @@ -62,7 +62,7 @@ void ChkIntSources(void) { QueryPerformanceCounter(&n); if (n.QuadPart > nextcnt.QuadPart) { nextcnt.QuadPart += slice.QuadPart; - chSchTimerHandlerI(); + chSysTimerHandlerI(); if (chSchRescRequiredI()) chSchDoRescheduleI(); } diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index eab41ab27..866ac791e 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -85,7 +85,7 @@ void ChkIntSources(void) { QueryPerformanceCounter(&n); if (n.QuadPart > nextcnt.QuadPart) { nextcnt.QuadPart += slice.QuadPart; - chSchTimerHandlerI(); + chSysTimerHandlerI(); if (chSchRescRequiredI()) chSchDoRescheduleI(); } -- cgit v1.2.3 From f477fa23bfacbeedc2a666af056842c45417413f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 7 Dec 2007 13:28:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@127 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore2.s | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index a450d9b74..22a819c72 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -47,9 +47,9 @@ threadstart: bx r0 .code 16 mov r0, r5 - mov lr, pc - bx r4 + bl jmpr4 bl chThdExit +jmpr4: bx r4 .code 32 #endif @@ -202,14 +202,17 @@ UART1IrqHandler: * Common exit point for all IRQ routines, it performs the rescheduling if * required. */ -IrqCommon: #ifdef THUMB_NO_INTERWORKING .code 16 +.globl IrqCommon +IrqCommon: bl chSchRescRequiredI mov lr, pc bx lr .code 32 #else +.globl IrqCommon +IrqCommon: bl chSchRescRequiredI #endif cmp r0, #0 // Simply returns if a -- cgit v1.2.3 From 00ab4e1c637058ffcd98dad63cbe27727736daee Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 7 Dec 2007 15:56:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@130 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/main.c | 4 ++-- demos/ARM7-LPC214x-GCC/main.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 5a0b1e80a..18017f0b5 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -24,7 +24,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WorkingArea(waThread1, 32); +static WorkingArea(waThread1, 64); static t_msg Thread1(void *arg) { while (TRUE) { @@ -43,7 +43,7 @@ static t_msg Thread1(void *arg) { /* * Yellow LED blinker thread, times are in milliseconds. */ -static WorkingArea(waThread2, 32); +static WorkingArea(waThread2, 64); static t_msg Thread2(void *arg) { while (TRUE) { diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index b98747d20..dbc56803e 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -28,7 +28,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WorkingArea(waThread1, 32); +static WorkingArea(waThread1, 64); static t_msg Thread1(void *arg) { while (TRUE) { @@ -47,7 +47,7 @@ static t_msg Thread1(void *arg) { /* * Yellow LED blinker thread, times are in milliseconds. */ -static WorkingArea(waThread2, 32); +static WorkingArea(waThread2, 64); static t_msg Thread2(void *arg) { while (TRUE) { -- cgit v1.2.3 From 2a3327fbc686fe8ba0ea7ea4b4960df8221c6e14 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 7 Dec 2007 18:38:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@131 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore2.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index 22a819c72..3bbffe26f 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -71,7 +71,7 @@ FiqHandler: ldr r0, =chSysHalt bx r0 #else - bl chSysHalt + b chSysHalt #endif #ifdef THUMB -- cgit v1.2.3 From 1fb3d146edfcf92426cbf6ae58dcb7c69a0f97bf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Dec 2007 12:05:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@132 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/chcore2.s | 20 +++++++++----------- 5 files changed, 13 insertions(+), 15 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index f440f799d..e74d2f382 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -121,7 +121,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 03f2c7ba9..68f308449 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -120,7 +120,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 3698582e7..60c2df008 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -123,7 +123,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index c08d632f9..111fa8c7b 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -122,7 +122,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index 3bbffe26f..92d9d6d24 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -115,10 +115,11 @@ chSysSwitchI: * interrupt handler: * * High +------------+ - * | R12 | -+ + * | LR_USR | -+ + * | R12 | | * | R3 | | - * | R2 | | - * | R1 | | External context: IRQ handler frame + * | R2 | | External context: IRQ handler frame + * | R1 | | * | R0 | | * | LR_IRQ | | (user code return address) * | SPSR | -+ (user code status) @@ -136,7 +137,6 @@ chSysSwitchI: */ .globl IrqHandler IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -152,7 +152,6 @@ IrqHandler: .globl T0IrqHandler T0IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -168,7 +167,6 @@ T0IrqHandler: .globl UART0IrqHandler UART0IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -184,7 +182,6 @@ UART0IrqHandler: .globl UART1IrqHandler UART1IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -216,12 +213,13 @@ IrqCommon: bl chSchRescRequiredI #endif cmp r0, #0 // Simply returns if a - ldmeqfd sp!, {r0-r3, r12, pc}^ // reschedule is not required. + ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not + subeqs pc, lr, #4 // required. // Saves the IRQ mode registers in the system stack. ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0-r3, r12} // Registers on System Stack. + stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack. msr CPSR_c, #MODE_IRQ | I_BIT mrs r0, SPSR mov r1, lr @@ -247,6 +245,6 @@ IrqCommon: msr SPSR_fsxc, r0 mov lr, r1 msr CPSR_c, #MODE_SYS | I_BIT - ldmfd sp!, {r0-r3, r12} + ldmfd sp!, {r0-r3, r12, lr} msr CPSR_c, #MODE_IRQ | I_BIT - subs pc, lr, #0 + subs pc, lr, #4 -- cgit v1.2.3 From 62458fc5d52e57dc7ce2493b9b78f2a03319fe7c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Dec 2007 12:12:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@133 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chcore2.s | 39 +++++++++++++++----------------- 1 file changed, 18 insertions(+), 21 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s index 4df7c70ed..785765fd4 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s @@ -47,9 +47,9 @@ threadstart: bx r0 .code 16 mov r0, r5 - mov lr, pc - bx r4 + bl jmpr4 bl chThdExit +jmpr4: bx r4 .code 32 #endif @@ -71,7 +71,7 @@ FiqHandler: ldr r0, =chSysHalt bx r0 #else - bl chSysHalt + b chSysHalt #endif #ifdef THUMB @@ -115,10 +115,11 @@ chSysSwitchI: * interrupt handler: * * High +------------+ - * | R12 | -+ + * | LR_USR | -+ + * | R12 | | * | R3 | | - * | R2 | | - * | R1 | | External context: IRQ handler frame + * | R2 | | External context: IRQ handler frame + * | R1 | | * | R0 | | * | LR_IRQ | | (user code return address) * | SPSR | -+ (user code status) @@ -136,7 +137,6 @@ chSysSwitchI: */ .globl IrqHandler IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -152,7 +152,6 @@ IrqHandler: .globl T0IrqHandler T0IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -165,11 +164,9 @@ T0IrqHandler: bl Timer0Irq b IrqCommon #endif - -#if 0 +/* .globl UART0IrqHandler UART0IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -182,12 +179,9 @@ UART0IrqHandler: bl UART0Irq b IrqCommon #endif -#endif -#if 0 .globl UART1IrqHandler UART1IrqHandler: - sub lr, lr, #4 stmfd sp!, {r0-r3, r12, lr} #ifdef THUMB_NO_INTERWORKING add r0, pc, #1 @@ -200,29 +194,32 @@ UART1IrqHandler: bl UART1Irq b IrqCommon #endif -#endif - +*/ /* * Common exit point for all IRQ routines, it performs the rescheduling if * required. */ -IrqCommon: #ifdef THUMB_NO_INTERWORKING .code 16 +.globl IrqCommon +IrqCommon: bl chSchRescRequiredI mov lr, pc bx lr .code 32 #else +.globl IrqCommon +IrqCommon: bl chSchRescRequiredI #endif cmp r0, #0 // Simply returns if a - ldmeqfd sp!, {r0-r3, r12, pc}^ // reschedule is not required. + ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not + subeqs pc, lr, #4 // required. // Saves the IRQ mode registers in the system stack. ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0-r3, r12} // Registers on System Stack. + stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack. msr CPSR_c, #MODE_IRQ | I_BIT mrs r0, SPSR mov r1, lr @@ -248,6 +245,6 @@ IrqCommon: msr SPSR_fsxc, r0 mov lr, r1 msr CPSR_c, #MODE_SYS | I_BIT - ldmfd sp!, {r0-r3, r12} + ldmfd sp!, {r0-r3, r12, lr} msr CPSR_c, #MODE_IRQ | I_BIT - subs pc, lr, #0 + subs pc, lr, #4 -- cgit v1.2.3 From b797fc9591a6ea6ae11495142218e82fed5a69b2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 9 Dec 2007 09:16:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@135 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.c | 42 +++++++++++++++++++----- demos/ARM7-LPC214x-GCC/chcore2.s | 71 ++++------------------------------------ 2 files changed, 41 insertions(+), 72 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 613841437..05305b24e 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -116,13 +116,11 @@ void hwinit(void) { */ InitVIC(); VICDefVectAddr = (IOREG32)IrqHandler; - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); - SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); /* * System Timer initialization, 1ms intervals. */ + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); VICIntEnable = INTMASK(SOURCE_Timer0); TC *timer = T0Base; timer->TC_PR = VAL_TC0_PRESCALER; @@ -134,7 +132,7 @@ void hwinit(void) { /* * Other subsystems. */ - InitSerial(); + InitSerial(1, 2); InitSSP(); InitMMC(); InitBuzzer(); @@ -174,17 +172,45 @@ void chSysPuts(char *msg) { /* * Non-vectored IRQs handling here. */ -void NonVectoredIrq(void) { - +__attribute__((naked, weak)) +void IrqHandler(void) { + + asm(".code 32 \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t"); +#ifdef THUMB + asm("add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16 \n\t"); + VICVectAddr = 0; + asm("ldr r0, =IrqCommon \n\t" \ + "bx r0 \n\t"); +#else VICVectAddr = 0; + asm("b IrqCommon \n\t"); +#endif } /* * Timer 0 IRQ handling here. */ -void Timer0Irq(void) { - +__attribute__((naked, weak)) +void T0IrqHandler(void) { + + asm(".code 32 \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t"); +#ifdef THUMB + asm("add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16 \n\t"); + T0IR = 1; /* Clear interrupt on match MR0. */ + chSysTimerHandlerI(); + VICVectAddr = 0; + asm("ldr r0, =IrqCommon \n\t" \ + "bx r0 \n\t"); +#else T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); VICVectAddr = 0; + asm("b IrqCommon \n\t"); +#endif } diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index 92d9d6d24..2a7888387 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -53,18 +53,23 @@ jmpr4: bx r4 .code 32 #endif +.weak UndHandler .globl UndHandler UndHandler: +.weak SwiHandler .globl SwiHandler SwiHandler: +.weak PrefetchHandler .globl PrefetchHandler PrefetchHandler: +.weak AbortHandler .globl AbortHandler AbortHandler: +.weak FiqHandler .globl FiqHandler FiqHandler: #ifdef THUMB_NO_INTERWORKING @@ -111,6 +116,8 @@ chSysSwitchI: #endif /* CH_CURRP_REGISTER_CACHE */ /* + * Common exit point for all IRQ routines, it performs the rescheduling if + * required. * System stack frame structure after a context switch in the * interrupt handler: * @@ -135,70 +142,6 @@ chSysSwitchI: * SP-> | R4 | -+ * Low +------------+ */ -.globl IrqHandler -IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl NonVectoredIrq - b IrqCommon -.code 32 -#else - bl NonVectoredIrq - b IrqCommon -#endif - -.globl T0IrqHandler -T0IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl Timer0Irq - b IrqCommon -.code 32 -#else - bl Timer0Irq - b IrqCommon -#endif - -.globl UART0IrqHandler -UART0IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl UART0Irq - b IrqCommon -.code 32 -#else - bl UART0Irq - b IrqCommon -#endif - -.globl UART1IrqHandler -UART1IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl UART1Irq - b IrqCommon -.code 32 -#else - bl UART1Irq - b IrqCommon -#endif - -/* - * Common exit point for all IRQ routines, it performs the rescheduling if - * required. - */ #ifdef THUMB_NO_INTERWORKING .code 16 .globl IrqCommon -- cgit v1.2.3 From 9aaaebf0e2f93a70e725f9a4c0598bc636a78e38 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 11 Dec 2007 12:01:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@136 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chcore.c | 56 ++++++++++++-------- demos/ARM7-LPC214x-GCC-minimal/chcore2.s | 90 ++++++++------------------------ demos/ARM7-LPC214x-GCC/chcore.c | 13 ----- demos/ARM7-LPC214x-GCC/chcore2.s | 19 +++++-- 4 files changed, 74 insertions(+), 104 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.c b/demos/ARM7-LPC214x-GCC-minimal/chcore.c index f4127cc8e..f46b932be 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore.c +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore.c @@ -24,6 +24,7 @@ //#include "lpc214x_serial.h" //#include "lpc214x_ssp.h" //#include "mmcsd.h" + //#include "buzzer.h" extern void IrqHandler(void); @@ -115,13 +116,11 @@ void hwinit(void) { */ InitVIC(); VICDefVectAddr = (IOREG32)IrqHandler; - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); -// SetVICVector(UART0IrqHandler, 1, SOURCE_UART0); -// SetVICVector(UART1IrqHandler, 2, SOURCE_UART1); /* * System Timer initialization, 1ms intervals. */ + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); VICIntEnable = INTMASK(SOURCE_Timer0); TC *timer = T0Base; timer->TC_PR = VAL_TC0_PRESCALER; @@ -133,7 +132,7 @@ void hwinit(void) { /* * Other subsystems. */ -// InitSerial(); +// InitSerial(1, 2); // InitSSP(); // InitMMC(); // InitBuzzer(); @@ -151,19 +150,6 @@ void _IdleThread(void *p) { } } -/* - * System halt. - * Yellow LED only. - */ -void chSysHalt(void) { - - chSysLock(); - IO0SET = 0x00000C00; - IO0CLR = 0x80000000; - while (TRUE) - ; -} - /* * System console message (not implemented). */ @@ -173,17 +159,45 @@ void chSysPuts(char *msg) { /* * Non-vectored IRQs handling here. */ -void NonVectoredIrq(void) { - +__attribute__((naked, weak)) +void IrqHandler(void) { + + asm(".code 32 \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t"); +#ifdef THUMB + asm("add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16 \n\t"); VICVectAddr = 0; + asm("ldr r0, =IrqCommon \n\t" \ + "bx r0 \n\t"); +#else + VICVectAddr = 0; + asm("b IrqCommon \n\t"); +#endif } /* * Timer 0 IRQ handling here. */ -void Timer0Irq(void) { - +__attribute__((naked, weak)) +void T0IrqHandler(void) { + + asm(".code 32 \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t"); +#ifdef THUMB + asm("add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16 \n\t"); + T0IR = 1; /* Clear interrupt on match MR0. */ + chSysTimerHandlerI(); + VICVectAddr = 0; + asm("ldr r0, =IrqCommon \n\t" \ + "bx r0 \n\t"); +#else T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); VICVectAddr = 0; + asm("b IrqCommon \n\t"); +#endif } diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s index 785765fd4..7c9d1d0d7 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s +++ b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s @@ -53,26 +53,44 @@ jmpr4: bx r4 .code 32 #endif +.weak UndHandler .globl UndHandler UndHandler: +.weak SwiHandler .globl SwiHandler SwiHandler: +.weak PrefetchHandler .globl PrefetchHandler PrefetchHandler: +.weak AbortHandler .globl AbortHandler AbortHandler: +.weak FiqHandler .globl FiqHandler FiqHandler: + b halt32 + +.weak chSysHalt #ifdef THUMB_NO_INTERWORKING - ldr r0, =chSysHalt +.code 16 +.globl chSysHalt +chSysHalt: + mov r0, pc bx r0 +.code 32 #else - b chSysHalt +.globl chSysHalt +chSysHalt: #endif +halt32: + mrs r0, CPSR + orr r0, #I_BIT | F_BIT + msr CPSR_c, r0 +.loop: b .loop #ifdef THUMB .globl chSysLock @@ -111,6 +129,8 @@ chSysSwitchI: #endif /* CH_CURRP_REGISTER_CACHE */ /* + * Common exit point for all IRQ routines, it performs the rescheduling if + * required. * System stack frame structure after a context switch in the * interrupt handler: * @@ -135,70 +155,6 @@ chSysSwitchI: * SP-> | R4 | -+ * Low +------------+ */ -.globl IrqHandler -IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl NonVectoredIrq - b IrqCommon -.code 32 -#else - bl NonVectoredIrq - b IrqCommon -#endif - -.globl T0IrqHandler -T0IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl Timer0Irq - b IrqCommon -.code 32 -#else - bl Timer0Irq - b IrqCommon -#endif -/* -.globl UART0IrqHandler -UART0IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl UART0Irq - b IrqCommon -.code 32 -#else - bl UART0Irq - b IrqCommon -#endif - -.globl UART1IrqHandler -UART1IrqHandler: - stmfd sp!, {r0-r3, r12, lr} -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl UART1Irq - b IrqCommon -.code 32 -#else - bl UART1Irq - b IrqCommon -#endif -*/ -/* - * Common exit point for all IRQ routines, it performs the rescheduling if - * required. - */ #ifdef THUMB_NO_INTERWORKING .code 16 .globl IrqCommon @@ -214,7 +170,7 @@ IrqCommon: #endif cmp r0, #0 // Simply returns if a ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not - subeqs pc, lr, #4 // required. + subeqs pc, lr, #4 // required. // Saves the IRQ mode registers in the system stack. ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 05305b24e..5313ecdb4 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -150,19 +150,6 @@ void _IdleThread(void *p) { } } -/* - * System halt. - * Yellow LED only. - */ -void chSysHalt(void) { - - chSysLock(); - IO0SET = 0x00000C00; - IO0CLR = 0x80000000; - while (TRUE) - ; -} - /* * System console message (not implemented). */ diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index 2a7888387..7c9d1d0d7 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -72,12 +72,25 @@ AbortHandler: .weak FiqHandler .globl FiqHandler FiqHandler: + b halt32 + +.weak chSysHalt #ifdef THUMB_NO_INTERWORKING - ldr r0, =chSysHalt +.code 16 +.globl chSysHalt +chSysHalt: + mov r0, pc bx r0 +.code 32 #else - b chSysHalt +.globl chSysHalt +chSysHalt: #endif +halt32: + mrs r0, CPSR + orr r0, #I_BIT | F_BIT + msr CPSR_c, r0 +.loop: b .loop #ifdef THUMB .globl chSysLock @@ -157,7 +170,7 @@ IrqCommon: #endif cmp r0, #0 // Simply returns if a ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not - subeqs pc, lr, #4 // required. + subeqs pc, lr, #4 // required. // Saves the IRQ mode registers in the system stack. ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. -- cgit v1.2.3 From 430010715e7a9af17185412273165674f3b58f20 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 16 Dec 2007 19:01:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@141 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 5 +++-- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 5 +++-- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 7 +++---- demos/ARM7-LPC214x-GCC/Makefile | 5 +++-- demos/ARM7-LPC214x-GCC/Makefile.thumb | 5 +++-- demos/ARM7-LPC214x-GCC/chconf.h | 7 +++---- demos/AVR-AT90CANx-GCC/chconf.h | 7 +++---- demos/Win32-MSVS/chconf.h | 7 +++---- demos/Win32-MinGW/chconf.h | 7 +++---- 9 files changed, 27 insertions(+), 28 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index e74d2f382..ac7bb1000 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -64,8 +64,9 @@ UADEFS = # List ARM-mode C source files here ASRC = chcore.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ - ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ ../../ports/ARM7-LPC214x/GCC/vic.c \ main.c diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 68f308449..17239c741 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -69,8 +69,9 @@ ASRC = # enabled for all modules and that lowers performance. TSRC = chcore.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ - ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ ../../ports/ARM7-LPC214x/GCC/vic.c \ main.c diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index fc81d571f..11081acc4 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -77,10 +77,9 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ //#define CH_USE_SEMAPHORES_TIMEOUT -/** Configuration option: if specified then the Semaphores APIs with priority - * shift are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -//#define CH_USE_RT_SEMAPHORES +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +//#define CH_USE_MUTEXES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 60c2df008..a2f229617 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -64,8 +64,9 @@ UADEFS = # List ARM-mode C source files here ASRC = chcore.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ - ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/lib/evtimer.c ../../test/test.c \ diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 111fa8c7b..518169cd8 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -69,8 +69,9 @@ ASRC = # enabled for all modules and that lowers performance. TSRC = chcore.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c \ - ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/lib/evtimer.c ../../test/test.c \ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 87402547c..28db4b351 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -77,10 +77,9 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_SEMAPHORES_TIMEOUT -/** Configuration option: if specified then the Semaphores APIs with priority - * shift are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_RT_SEMAPHORES +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 2bc89dc2f..b4ddeeb05 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -78,10 +78,9 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_SEMAPHORES_TIMEOUT -/** Configuration option: if specified then the Semaphores APIs with priority - * shift are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_RT_SEMAPHORES +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h index 5941cc856..037e3d8a0 100644 --- a/demos/Win32-MSVS/chconf.h +++ b/demos/Win32-MSVS/chconf.h @@ -82,10 +82,9 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_SEMAPHORES_TIMEOUT -/** Configuration option: if specified then the Semaphores APIs with priority - * shift are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_RT_SEMAPHORES +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index af19dd995..3e741bb8c 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -82,10 +82,9 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_SEMAPHORES_TIMEOUT -/** Configuration option: if specified then the Semaphores APIs with priority - * shift are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_RT_SEMAPHORES +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ -- cgit v1.2.3 From 0bb20d36f4f1c8457416167b399d976d26660611 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 17 Dec 2007 14:57:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@142 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chcore.c | 169 +++++++++++++++++++++++++++++++++------ demos/ARM7-LPC214x-GCC/chcore.h | 31 +++++-- demos/ARM7-LPC214x-GCC/chcore2.s | 139 +------------------------------- demos/ARM7-LPC214x-GCC/crt0.s | 21 +++++ demos/Win32-MSVS/chcore.h | 2 + demos/Win32-MinGW/chcore.h | 2 + 6 files changed, 197 insertions(+), 167 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c index 5313ecdb4..8b9b4d464 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ b/demos/ARM7-LPC214x-GCC/chcore.c @@ -162,19 +162,11 @@ void chSysPuts(char *msg) { __attribute__((naked, weak)) void IrqHandler(void) { - asm(".code 32 \n\t" \ - "stmfd sp!, {r0-r3, r12, lr} \n\t"); -#ifdef THUMB - asm("add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16 \n\t"); - VICVectAddr = 0; - asm("ldr r0, =IrqCommon \n\t" \ - "bx r0 \n\t"); -#else - VICVectAddr = 0; - asm("b IrqCommon \n\t"); -#endif + chSysIRQEnterI(); + + /* nothing */ + + chSysIRQExitI(); } /* @@ -183,21 +175,148 @@ void IrqHandler(void) { __attribute__((naked, weak)) void T0IrqHandler(void) { - asm(".code 32 \n\t" \ - "stmfd sp!, {r0-r3, r12, lr} \n\t"); -#ifdef THUMB - asm("add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16 \n\t"); + chSysIRQEnterI(); + T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); + + chSysIRQExitI(); +} + +/* + * Common IRQ exit code, \p chSysIRQExitI() just jumps here. + * + * System stack frame structure after a context switch in the + * interrupt handler: + * + * High +------------+ + * | LR_USR | -+ + * | R12 | | + * | R3 | | + * | R2 | | External context: IRQ handler frame + * | R1 | | + * | R0 | | + * | LR_IRQ | | (user code return address) + * | SPSR | -+ (user code status) + * | .... | <- chSchDoRescheduleI() stack frame, optimize it for space + * | LR | -+ (system code return address) + * | R11 | | + * | R10 | | + * | R9 | | + * | R8 | | Internal context: chSysSwitchI() frame + * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) + * | R6 | | + * | R5 | | + * SP-> | R4 | -+ + * Low +------------+ + */ +__attribute__((naked, weak)) +void IrqCommon(void) { + register BOOL b asm("r0"); + VICVectAddr = 0; - asm("ldr r0, =IrqCommon \n\t" \ - "bx r0 \n\t"); + b = chSchRescRequiredI(); +#ifdef THUMB + asm(".p2align 2,, \n\t" \ + "mov lr, pc \n\t" \ + "bx lr \n\t" \ + ".code 32 \n\t"); +#endif + /* + * If a reschedulation is not required then just returns from the IRQ. + */ + asm("cmp r0, #0 \n\t" \ + "ldmeqfd sp!, {r0-r3, r12, lr} \n\t" \ + "subeqs pc, lr, #4 \n\t"); + /* + * Reschedulation required, saves the external context on the + * system/user stack and empties the IRQ stack. + */ + asm(".set MODE_IRQ, 0x12 \n\t" \ + ".set MODE_SYS, 0x1F \n\t" \ + ".set I_BIT, 0x80 \n\t" \ + "ldmfd sp!, {r0-r3, r12, lr} \n\t" \ + "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t" \ + "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \ + "mrs r0, SPSR \n\t" \ + "mov r1, lr \n\t" \ + "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \ + "stmfd sp!, {r0, r1} \n\t"); + +#ifdef THUMB_NO_INTERWORKING + asm("add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16 \n\t" \ + "bl chSchDoRescheduleI \n\t" \ + ".p2align 2,, \n\t" \ + "mov lr, pc \n\t" \ + "bx lr \n\t" \ + ".code 32 \n\t"); #else - T0IR = 1; /* Clear interrupt on match MR0. */ - chSysTimerHandlerI(); - VICVectAddr = 0; - asm("b IrqCommon \n\t"); + asm("bl chSchDoRescheduleI \n\t"); +#endif + + /* + * Restores the external context. + */ + asm("ldmfd sp!, {r0, r1} \n\t" \ + "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \ + "msr SPSR_fsxc, r0 \n\t" \ + "mov lr, r1 \n\t" \ + "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \ + "ldmfd sp!, {r0-r3, r12, lr} \n\t" \ + "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \ + "subs pc, lr, #4 \n\t"); + + /* + * Threads entry/exit code. It is declared weak so you can easily replace it. + * NOTE: It is always invoked in ARM mode, it does the mode switching. + * NOTE: It is included into IrqCommon to make sure the symbol refers to + * 32 bit code. + */ + asm(".set F_BIT, 0x40 \n\t" \ + ".weak threadstart \n\t" \ + ".globl threadstart \n\t" \ + "threadstart: \n\t" \ + "msr CPSR_c, #MODE_SYS \n\t"); +#ifndef THUMB_NO_INTERWORKING + asm("mov r0, r5 \n\t" \ + "mov lr, pc \n\t" \ + "bx r4 \n\t" \ + "bl chThdExit \n\t"); +#else + asm("add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16 \n\t" \ + "mov r0, r5 \n\t" \ + "bl jmpr4 \n\t" \ + "bl chThdExit \n\t" \ + "jmpr4: \n\t" \ + "bx r4 \n\t"); +#endif +} + +/* + * System halt. + */ +__attribute__((naked, weak)) +void chSysHalt(void) { + + asm(".set F_BIT, 0x40 \n\t" \ + ".set I_BIT, 0x80 \n\t"); +#ifdef THUMB + asm(".p2align 2,, \n\t" \ + "mov r0, pc \n\t" \ + "bx r0 \n\t"); #endif + asm(".code 32 \n\t" \ + ".weak _halt32 \n\t" \ + ".globl _halt32 \n\t" \ + "_halt32: \n\t" \ + "mrs r0, CPSR \n\t" \ + "orr r0, #I_BIT | F_BIT \n\t" \ + "msr CPSR_c, r0 \n\t" \ + ".loop: \n\t" \ + "b .loop \n\t"); } diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h index 941036830..cc1113c18 100644 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ b/demos/ARM7-LPC214x-GCC/chcore.h @@ -92,7 +92,7 @@ extern void chSysUnlock(void); #define INT_REQUIRED_STACK 0x10 #else /* !THUMB */ #define INT_REQUIRED_STACK 0 -#endif /* THUMB */ +#endif /* !THUMB */ #define StackAlign(n) ((((n) - 1) | 3) + 1) #define UserStackSize(n) StackAlign(sizeof(Thread) + \ sizeof(struct intctx) + \ @@ -101,16 +101,37 @@ extern void chSysUnlock(void); INT_REQUIRED_STACK) #define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; +#ifdef THUMB +#define chSysIRQEnterI() { \ + asm(".code 32 \n\t" \ + "stmfd sp!, {r0-r3, r12, lr} \n\t" \ + "add r0, pc, #1 \n\t" \ + "bx r0 \n\t" \ + ".code 16 \n\t"); \ +} + +#define chSysIRQExitI() { \ + VICVectAddr = 0; \ + asm("ldr r0, =IrqCommon \n\t" \ + "bx r0 \n\t"); \ +} +#else /* !THUMB */ +#define chSysIRQEnterI() { \ + asm("stmfd sp!, {r0-r3, r12, lr} \n\t"); \ +} + +#define chSysIRQExitI() { \ + asm("b IrqCommon \n\t"); \ +} +#endif /* !THUMB */ + /* It requires zero bytes, but better be safe.*/ #define IDLE_THREAD_STACK_SIZE 8 void _IdleThread(void *p) __attribute__((noreturn)); -void chSysHalt(void) __attribute__((noreturn)); +void chSysHalt(void); void chSysSwitchI(Context *oldp, Context *newp); void chSysPuts(char *msg); void threadstart(void); -void DefFiqHandler(void); -void DefIrqHandler(void); -void SpuriousHandler(void); #endif /* _CHCORE_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s index 7c9d1d0d7..35dd49597 100644 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ b/demos/ARM7-LPC214x-GCC/chcore2.s @@ -34,73 +34,15 @@ .code 32 .balign 4 -.globl threadstart -threadstart: - msr CPSR_c, #MODE_SYS -#ifndef THUMB_NO_INTERWORKING - mov r0, r5 - mov lr, pc - bx r4 - bl chThdExit -#else - add r0, pc, #1 - bx r0 -.code 16 - mov r0, r5 - bl jmpr4 - bl chThdExit -jmpr4: bx r4 -.code 32 -#endif - -.weak UndHandler -.globl UndHandler -UndHandler: - -.weak SwiHandler -.globl SwiHandler -SwiHandler: - -.weak PrefetchHandler -.globl PrefetchHandler -PrefetchHandler: - -.weak AbortHandler -.globl AbortHandler -AbortHandler: - -.weak FiqHandler -.globl FiqHandler -FiqHandler: - b halt32 - -.weak chSysHalt -#ifdef THUMB_NO_INTERWORKING -.code 16 -.globl chSysHalt -chSysHalt: - mov r0, pc - bx r0 -.code 32 -#else -.globl chSysHalt -chSysHalt: -#endif -halt32: - mrs r0, CPSR - orr r0, #I_BIT | F_BIT - msr CPSR_c, r0 -.loop: b .loop - #ifdef THUMB .globl chSysLock chSysLock: - msr CPSR_c, #0x9F + msr CPSR_c, #MODE_SYS | I_BIT bx lr .globl chSysUnlock chSysUnlock: - msr CPSR_c, #0x1F + msr CPSR_c, #MODE_SYS bx lr #endif @@ -127,80 +69,3 @@ chSysSwitchI: ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} #endif #endif /* CH_CURRP_REGISTER_CACHE */ - -/* - * Common exit point for all IRQ routines, it performs the rescheduling if - * required. - * System stack frame structure after a context switch in the - * interrupt handler: - * - * High +------------+ - * | LR_USR | -+ - * | R12 | | - * | R3 | | - * | R2 | | External context: IRQ handler frame - * | R1 | | - * | R0 | | - * | LR_IRQ | | (user code return address) - * | SPSR | -+ (user code status) - * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space - * | LR | -+ (system code return address) - * | R11 | | - * | R10 | | - * | R9 | | - * | R8 | | Internal context: mk_SwitchI() frame - * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) - * | R6 | | - * | R5 | | - * SP-> | R4 | -+ - * Low +------------+ - */ -#ifdef THUMB_NO_INTERWORKING -.code 16 -.globl IrqCommon -IrqCommon: - bl chSchRescRequiredI - mov lr, pc - bx lr -.code 32 -#else -.globl IrqCommon -IrqCommon: - bl chSchRescRequiredI -#endif - cmp r0, #0 // Simply returns if a - ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not - subeqs pc, lr, #4 // required. - - // Saves the IRQ mode registers in the system stack. - ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack. - msr CPSR_c, #MODE_IRQ | I_BIT - mrs r0, SPSR - mov r1, lr - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. - - // Context switch. -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl chSchDoRescheduleI - mov lr, pc - bx lr -.code 32 -#else - bl chSchDoRescheduleI -#endif - - // Re-establish the IRQ conditions again. - ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. - msr CPSR_c, #MODE_IRQ | I_BIT - msr SPSR_fsxc, r0 - mov lr, r1 - msr CPSR_c, #MODE_SYS | I_BIT - ldmfd sp!, {r0-r3, r12, lr} - msr CPSR_c, #MODE_IRQ | I_BIT - subs pc, lr, #4 diff --git a/demos/ARM7-LPC214x-GCC/crt0.s b/demos/ARM7-LPC214x-GCC/crt0.s index a7845036d..9032b0742 100644 --- a/demos/ARM7-LPC214x-GCC/crt0.s +++ b/demos/ARM7-LPC214x-GCC/crt0.s @@ -147,3 +147,24 @@ bssloop: bl chSysHalt .code 32 #endif + +.weak UndHandler +.globl UndHandler +UndHandler: + +.weak SwiHandler +.globl SwiHandler +SwiHandler: + +.weak PrefetchHandler +.globl PrefetchHandler +PrefetchHandler: + +.weak AbortHandler +.globl AbortHandler +AbortHandler: + +.weak FiqHandler +.globl FiqHandler +FiqHandler: + b _halt32 diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h index 91fd7be9e..b9fbb0147 100644 --- a/demos/Win32-MSVS/chcore.h +++ b/demos/Win32-MSVS/chcore.h @@ -60,6 +60,8 @@ typedef struct { #define chSysLock() #define chSysUnlock() #define chSysPuts(msg) {} +#define chSysIRQEnterI() +#define chSysIRQExitI() #define INT_REQUIRED_STACK 0 #define StackAlign(n) ((((n) - 1) | 3) + 1) diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 2b90dd470..43265326b 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -60,6 +60,8 @@ typedef struct { #define chSysLock() #define chSysUnlock() #define chSysPuts(msg) {} +#define chSysIRQEnterI() +#define chSysIRQExitI() #define INT_REQUIRED_STACK 0 #define StackAlign(n) ((((n) - 1) | 3) + 1) -- cgit v1.2.3 From cae69c784f75c1d2ace5465aff052d2d4a1b5a42 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Dec 2007 09:41:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@143 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 14 +- demos/ARM7-LPC214x-GCC/buzzer.c | 1 + demos/ARM7-LPC214x-GCC/chcore.c | 322 --------------------------------------- demos/ARM7-LPC214x-GCC/chcore.h | 137 ----------------- demos/ARM7-LPC214x-GCC/chcore2.s | 71 --------- demos/ARM7-LPC214x-GCC/crt0.s | 170 --------------------- 6 files changed, 8 insertions(+), 707 deletions(-) delete mode 100644 demos/ARM7-LPC214x-GCC/chcore.c delete mode 100644 demos/ARM7-LPC214x-GCC/chcore.h delete mode 100644 demos/ARM7-LPC214x-GCC/chcore2.s delete mode 100644 demos/ARM7-LPC214x-GCC/crt0.s (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index a2f229617..a267ac184 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -62,16 +62,16 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = chcore.c \ +ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/lib/evtimer.c ../../test/test.c \ - buzzer.c mmcsd.c main.c - + board.c buzzer.c mmcsd.c main.c # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is @@ -79,7 +79,7 @@ ASRC = chcore.c \ TSRC = # List ASM source files here -ASMSRC = crt0.s chcore2.s +ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s ../../ports/ARM7-LPC214x/GCC/chcore2.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC @@ -162,7 +162,7 @@ $(TOBJS) : %.o : %.c $(ASMOBJS) : %.o : %.s @echo - $(AS) -c $(ASFLAGS) $< -o $@ + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ %elf: $(OBJS) @echo diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index 7d80d8881..9ee122fe1 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -27,6 +27,7 @@ #include #include "lpc214x.h" +#include "board.h" #include "buzzer.h" EventSource BuzzerSilentEventSource; diff --git a/demos/ARM7-LPC214x-GCC/chcore.c b/demos/ARM7-LPC214x-GCC/chcore.c deleted file mode 100644 index 8b9b4d464..000000000 --- a/demos/ARM7-LPC214x-GCC/chcore.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include "lpc214x.h" -#include "vic.h" -#include "lpc214x_serial.h" -#include "lpc214x_ssp.h" -#include "mmcsd.h" - -#include "buzzer.h" - -extern void IrqHandler(void); -extern void T0IrqHandler(void); - -#define VAL_TC0_PRESCALER 0 - -/* - * Pins configuration for Olimex LPC-P2148. - * - * PINSEL0 - * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD - * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 - * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 - * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- - * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - * - * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 - * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 - * - * PINSEL2 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- - * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- - */ -#define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100840A8 -#define VAL_PINSEL2 0x00000004 -#define VAL_FIO0DIR 0xB0703C00 -#define VAL_FIO1DIR 0x00000000 - -/* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. - */ -void hwinit(void) { - - /* - * All peripherals clock disabled by default in order to save power. - */ - PCONP = PCRTC | PCTIM0; - - /* - * MAM setup. - */ - MAMTIM = 0x3; /* 3 cycles for flash accesses. */ - MAMCR = 0x2; /* MAM fully enabled. */ - - /* - * PLL setup for Fosc=12MHz and CCLK=48MHz. - * P=2 M=3. - */ - PLL *pll = PLLBase; - pll->PLL0_CFG = 0x23; /* P and M values. */ - pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - while (!(pll->PLL0_STAT & 0x400)) - ; /* Wait for PLL lock. */ - - pll->PLL0_CON = 0x3; /* Connects the PLL. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - - /* - * VPB setup. - * PCLK = CCLK / 4. - */ - VPBDIV = VPD_D4; - - /* - * I/O pins configuration. - */ - PINSEL0 = VAL_PINSEL0; - PINSEL1 = VAL_PINSEL1; - PINSEL2 = VAL_PINSEL2; - IO0DIR = VAL_FIO0DIR; - IO0SET = 0xFFFFFFFF; - IO1DIR = VAL_FIO1DIR; - IO1SET = 0xFFFFFFFF; - - /* - * Interrupt vectors assignment. - */ - InitVIC(); - VICDefVectAddr = (IOREG32)IrqHandler; - - /* - * System Timer initialization, 1ms intervals. - */ - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - VICIntEnable = INTMASK(SOURCE_Timer0); - TC *timer = T0Base; - timer->TC_PR = VAL_TC0_PRESCALER; - timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); - timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ - timer->TC_TCR = 2; /* Reset counter and prescaler. */ - timer->TC_TCR = 1; /* Timer enabled. */ - - /* - * Other subsystems. - */ - InitSerial(1, 2); - InitSSP(); - InitMMC(); - InitBuzzer(); -} - -/* - * System idle thread loop. - */ -void _IdleThread(void *p) { - - while (TRUE) { -// Note, it is disabled because it causes trouble with the JTAG probe. -// Enable it in the final code only. -// PCON = 1; - } -} - -/* - * System console message (not implemented). - */ -void chSysPuts(char *msg) { -} - -/* - * Non-vectored IRQs handling here. - */ -__attribute__((naked, weak)) -void IrqHandler(void) { - - chSysIRQEnterI(); - - /* nothing */ - - chSysIRQExitI(); -} - -/* - * Timer 0 IRQ handling here. - */ -__attribute__((naked, weak)) -void T0IrqHandler(void) { - - chSysIRQEnterI(); - - T0IR = 1; /* Clear interrupt on match MR0. */ - chSysTimerHandlerI(); - - chSysIRQExitI(); -} - -/* - * Common IRQ exit code, \p chSysIRQExitI() just jumps here. - * - * System stack frame structure after a context switch in the - * interrupt handler: - * - * High +------------+ - * | LR_USR | -+ - * | R12 | | - * | R3 | | - * | R2 | | External context: IRQ handler frame - * | R1 | | - * | R0 | | - * | LR_IRQ | | (user code return address) - * | SPSR | -+ (user code status) - * | .... | <- chSchDoRescheduleI() stack frame, optimize it for space - * | LR | -+ (system code return address) - * | R11 | | - * | R10 | | - * | R9 | | - * | R8 | | Internal context: chSysSwitchI() frame - * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) - * | R6 | | - * | R5 | | - * SP-> | R4 | -+ - * Low +------------+ - */ -__attribute__((naked, weak)) -void IrqCommon(void) { - register BOOL b asm("r0"); - - VICVectAddr = 0; - b = chSchRescRequiredI(); -#ifdef THUMB - asm(".p2align 2,, \n\t" \ - "mov lr, pc \n\t" \ - "bx lr \n\t" \ - ".code 32 \n\t"); -#endif - /* - * If a reschedulation is not required then just returns from the IRQ. - */ - asm("cmp r0, #0 \n\t" \ - "ldmeqfd sp!, {r0-r3, r12, lr} \n\t" \ - "subeqs pc, lr, #4 \n\t"); - /* - * Reschedulation required, saves the external context on the - * system/user stack and empties the IRQ stack. - */ - asm(".set MODE_IRQ, 0x12 \n\t" \ - ".set MODE_SYS, 0x1F \n\t" \ - ".set I_BIT, 0x80 \n\t" \ - "ldmfd sp!, {r0-r3, r12, lr} \n\t" \ - "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \ - "stmfd sp!, {r0-r3, r12, lr} \n\t" \ - "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \ - "mrs r0, SPSR \n\t" \ - "mov r1, lr \n\t" \ - "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \ - "stmfd sp!, {r0, r1} \n\t"); - -#ifdef THUMB_NO_INTERWORKING - asm("add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16 \n\t" \ - "bl chSchDoRescheduleI \n\t" \ - ".p2align 2,, \n\t" \ - "mov lr, pc \n\t" \ - "bx lr \n\t" \ - ".code 32 \n\t"); -#else - asm("bl chSchDoRescheduleI \n\t"); -#endif - - /* - * Restores the external context. - */ - asm("ldmfd sp!, {r0, r1} \n\t" \ - "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \ - "msr SPSR_fsxc, r0 \n\t" \ - "mov lr, r1 \n\t" \ - "msr CPSR_c, #MODE_SYS | I_BIT \n\t" \ - "ldmfd sp!, {r0-r3, r12, lr} \n\t" \ - "msr CPSR_c, #MODE_IRQ | I_BIT \n\t" \ - "subs pc, lr, #4 \n\t"); - - /* - * Threads entry/exit code. It is declared weak so you can easily replace it. - * NOTE: It is always invoked in ARM mode, it does the mode switching. - * NOTE: It is included into IrqCommon to make sure the symbol refers to - * 32 bit code. - */ - asm(".set F_BIT, 0x40 \n\t" \ - ".weak threadstart \n\t" \ - ".globl threadstart \n\t" \ - "threadstart: \n\t" \ - "msr CPSR_c, #MODE_SYS \n\t"); -#ifndef THUMB_NO_INTERWORKING - asm("mov r0, r5 \n\t" \ - "mov lr, pc \n\t" \ - "bx r4 \n\t" \ - "bl chThdExit \n\t"); -#else - asm("add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16 \n\t" \ - "mov r0, r5 \n\t" \ - "bl jmpr4 \n\t" \ - "bl chThdExit \n\t" \ - "jmpr4: \n\t" \ - "bx r4 \n\t"); -#endif -} - -/* - * System halt. - */ -__attribute__((naked, weak)) -void chSysHalt(void) { - - asm(".set F_BIT, 0x40 \n\t" \ - ".set I_BIT, 0x80 \n\t"); -#ifdef THUMB - asm(".p2align 2,, \n\t" \ - "mov r0, pc \n\t" \ - "bx r0 \n\t"); -#endif - asm(".code 32 \n\t" \ - ".weak _halt32 \n\t" \ - ".globl _halt32 \n\t" \ - "_halt32: \n\t" \ - "mrs r0, CPSR \n\t" \ - "orr r0, #I_BIT | F_BIT \n\t" \ - "msr CPSR_c, r0 \n\t" \ - ".loop: \n\t" \ - "b .loop \n\t"); -} diff --git a/demos/ARM7-LPC214x-GCC/chcore.h b/demos/ARM7-LPC214x-GCC/chcore.h deleted file mode 100644 index cc1113c18..000000000 --- a/demos/ARM7-LPC214x-GCC/chcore.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/* - * The following values are implementation dependent. You may change them in - * order to match your HW. - */ -#define FOSC 12000000 -#define CCLK 48000000 -#define PCLK 12000000 - -typedef void *regarm; - -/* - * Interrupt saved context. - */ -struct extctx { - regarm spsr_irq; - regarm lr_irq; - regarm r0; - regarm r1; - regarm r2; - regarm r3; - regarm r12; -}; - -/* - * System saved context. - */ -struct intctx { - regarm r4; - regarm r5; - regarm r6; -#ifndef CH_CURRP_REGISTER_CACHE - regarm r7; -#endif - regarm r8; - regarm r9; - regarm r10; - regarm r11; - regarm lr; -}; - -/* - * Port dependent part of the Thread structure, you may add fields in - * this structure. - */ -typedef struct { - struct intctx *r13; -} Context; - -/* - * Platform dependent part of the \p chThdCreate() API. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = threadstart; \ -} - -#ifdef THUMB -extern void chSysLock(void); -extern void chSysUnlock(void); -#else /* !THUMB */ -#define chSysLock() asm("msr CPSR_c, #0x9F") -#define chSysUnlock() asm("msr CPSR_c, #0x1F") -#endif /* THUMB */ - -#ifdef THUMB -#define INT_REQUIRED_STACK 0x10 -#else /* !THUMB */ -#define INT_REQUIRED_STACK 0 -#endif /* !THUMB */ -#define StackAlign(n) ((((n) - 1) | 3) + 1) -#define UserStackSize(n) StackAlign(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + \ - INT_REQUIRED_STACK) -#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; - -#ifdef THUMB -#define chSysIRQEnterI() { \ - asm(".code 32 \n\t" \ - "stmfd sp!, {r0-r3, r12, lr} \n\t" \ - "add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16 \n\t"); \ -} - -#define chSysIRQExitI() { \ - VICVectAddr = 0; \ - asm("ldr r0, =IrqCommon \n\t" \ - "bx r0 \n\t"); \ -} -#else /* !THUMB */ -#define chSysIRQEnterI() { \ - asm("stmfd sp!, {r0-r3, r12, lr} \n\t"); \ -} - -#define chSysIRQExitI() { \ - asm("b IrqCommon \n\t"); \ -} -#endif /* !THUMB */ - -/* It requires zero bytes, but better be safe.*/ -#define IDLE_THREAD_STACK_SIZE 8 -void _IdleThread(void *p) __attribute__((noreturn)); - -void chSysHalt(void); -void chSysSwitchI(Context *oldp, Context *newp); -void chSysPuts(char *msg); -void threadstart(void); - -#endif /* _CHCORE_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chcore2.s b/demos/ARM7-LPC214x-GCC/chcore2.s deleted file mode 100644 index 35dd49597..000000000 --- a/demos/ARM7-LPC214x-GCC/chcore2.s +++ /dev/null @@ -1,71 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "chconf.h" - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text -.code 32 -.balign 4 - -#ifdef THUMB -.globl chSysLock -chSysLock: - msr CPSR_c, #MODE_SYS | I_BIT - bx lr - -.globl chSysUnlock -chSysUnlock: - msr CPSR_c, #MODE_SYS - bx lr -#endif - -.globl chSysSwitchI -chSysSwitchI: -#ifdef CH_CURRP_REGISTER_CACHE - stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - bx lr -#else - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} -#endif -#else - stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - bx lr -#else - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} -#endif -#endif /* CH_CURRP_REGISTER_CACHE */ diff --git a/demos/ARM7-LPC214x-GCC/crt0.s b/demos/ARM7-LPC214x-GCC/crt0.s deleted file mode 100644 index 9032b0742..000000000 --- a/demos/ARM7-LPC214x-GCC/crt0.s +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Generic ARM startup file for ChibiOS/RT. - */ - -.extern _main - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text -.code 32 -.balign 4 -/* - * System entry points. - */ -_start: - b ResetHandler - ldr pc, _undefined - ldr pc, _swi - ldr pc, _prefetch - ldr pc, _abort - nop - ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ - ldr pc, _fiq - -_undefined: - .word UndHandler -_swi: - .word SwiHandler -_prefetch: - .word PrefetchHandler -_abort: - .word AbortHandler -_fiq: - .word FiqHandler - .word 0 - .word 0 - -/* - * Reset handler. - */ -ResetHandler: - /* - * Stack pointers initialization. - */ - ldr r0, =__ram_end__ - /* Undefined */ - msr CPSR_c, #MODE_UND | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__und_stack_size__ - sub r0, r0, r1 - /* Abort */ - msr CPSR_c, #MODE_ABT | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__abt_stack_size__ - sub r0, r0, r1 - /* FIQ */ - msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__fiq_stack_size__ - sub r0, r0, r1 - /* IRQ */ - msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__irq_stack_size__ - sub r0, r0, r1 - /* Supervisor */ - msr CPSR_c, #MODE_SVC | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__svc_stack_size__ - sub r0, r0, r1 - /* System */ - msr CPSR_c, #MODE_SYS | I_BIT | F_BIT - mov sp, r0 -// ldr r1, =__sys_stack_size__ -// sub r0, r0, r1 - /* - * Data initialization. - * NOTE: It assumes that the DATA size is a multiple of 4. - */ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata -dataloop: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dataloop - /* - * BSS initialization. - * NOTE: It assumes that the BSS size is a multiple of 4. - */ - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bssloop: - cmp r1, r2 - strlo r0, [r1], #4 - blo bssloop - /* - * Application-provided HW initialization routine. - */ -#ifndef THUMB_NO_INTERWORKING - bl hwinit - /* - * main(0, NULL). - */ - mov r0, #0 - mov r1, r0 - bl main - bl chSysHalt -#else - add r0, pc, #1 - bx r0 -.code 16 - bl hwinit - mov r0, #0 - mov r1, r0 - bl main - bl chSysHalt -.code 32 -#endif - -.weak UndHandler -.globl UndHandler -UndHandler: - -.weak SwiHandler -.globl SwiHandler -SwiHandler: - -.weak PrefetchHandler -.globl PrefetchHandler -PrefetchHandler: - -.weak AbortHandler -.globl AbortHandler -AbortHandler: - -.weak FiqHandler -.globl FiqHandler -FiqHandler: - b _halt32 -- cgit v1.2.3 From 63508437a31f19b5f5612bb3e1f3820e9edb1be1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Dec 2007 09:42:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@144 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/board.c | 109 +++++++++++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/board.h | 64 ++++++++++++++++++++++++ 2 files changed, 173 insertions(+) create mode 100644 demos/ARM7-LPC214x-GCC/board.c create mode 100644 demos/ARM7-LPC214x-GCC/board.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c new file mode 100644 index 000000000..d6b92f842 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "vic.h" +#include "lpc214x_serial.h" +#include "lpc214x_ssp.h" + +#include "board.h" +#include "mmcsd.h" +#include "buzzer.h" + +extern void IrqHandler(void); +extern void T0IrqHandler(void); + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLLBase; + pll->PLL0_CFG = 0x23; /* P and M values. */ + pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + while (!(pll->PLL0_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL0_CON = 0x3; /* Connects the PLL. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; + + /* + * I/O pins configuration. + */ + PINSEL0 = VAL_PINSEL0; + PINSEL1 = VAL_PINSEL1; + PINSEL2 = VAL_PINSEL2; + IO0DIR = VAL_FIO0DIR; + IO0SET = 0xFFFFFFFF; + IO1DIR = VAL_FIO1DIR; + IO1SET = 0xFFFFFFFF; + + /* + * Interrupt vectors assignment. + */ + InitVIC(); + VICDefVectAddr = (IOREG32)IrqHandler; + + /* + * System Timer initialization, 1ms intervals. + */ + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); + VICIntEnable = INTMASK(SOURCE_Timer0); + TC *timer = T0Base; + timer->TC_PR = VAL_TC0_PRESCALER; + timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); + timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ + timer->TC_TCR = 2; /* Reset counter and prescaler. */ + timer->TC_TCR = 1; /* Timer enabled. */ + + /* + * Other subsystems. + */ + InitSerial(1, 2); + InitSSP(); + InitMMC(); + InitBuzzer(); +} diff --git a/demos/ARM7-LPC214x-GCC/board.h b/demos/ARM7-LPC214x-GCC/board.h new file mode 100644 index 000000000..c9d3f01b3 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/board.h @@ -0,0 +1,64 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define BOARD_OLIMEX_LCP_P2148 + +/* + * The following values are implementation dependent. You may change them in + * order to match your HW. + */ +#define FOSC 12000000 +#define CCLK 48000000 +#define PCLK 12000000 + +#define VAL_TC0_PRESCALER 0 + +/* + * Pins configuration for Olimex LPC-P2148. + * + * PINSEL0 + * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD + * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 + * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 + * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- + * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + * + * PINSEL1 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 + * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 + * + * PINSEL2 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- + * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- + */ +#define VAL_PINSEL0 0x00055555 +#define VAL_PINSEL1 0x100840A8 +#define VAL_PINSEL2 0x00000004 +#define VAL_FIO0DIR 0xB0703C00 +#define VAL_FIO1DIR 0x00000000 + +#endif /* _BOARD_H_ */ -- cgit v1.2.3 From d34507ec44db7333c8a81ae23ffd89a05ef3293d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Dec 2007 10:10:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@145 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile.thumb | 13 +++++++------ demos/ARM7-LPC214x-GCC/board.c | 28 ++++++++++++++++++++++++++-- 2 files changed, 33 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 518169cd8..4b14088c8 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -67,18 +67,19 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = chcore.c \ +TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ ../../src/lib/evtimer.c ../../test/test.c \ - buzzer.c mmcsd.c main.c + board.c buzzer.c mmcsd.c main.c # List ASM source files here -ASMSRC = crt0.s chcore2.s +ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s ../../ports/ARM7-LPC214x/GCC/chcore2.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC @@ -161,7 +162,7 @@ $(TOBJS) : %.o : %.c $(ASMOBJS) : %.o : %.s @echo - $(AS) -c $(ASFLAGS) $< -o $@ + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ %elf: $(OBJS) @echo diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index d6b92f842..23e642f01 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -28,8 +28,32 @@ #include "mmcsd.h" #include "buzzer.h" -extern void IrqHandler(void); -extern void T0IrqHandler(void); +/* + * Non-vectored IRQs handling here. + */ +__attribute__((naked)) +static void IrqHandler(void) { + + chSysIRQEnterI(); + + /* nothing */ + + chSysIRQExitI(); +} + +/* + * Timer 0 IRQ handling here. + */ +__attribute__((naked)) +static void T0IrqHandler(void) { + + chSysIRQEnterI(); + + T0IR = 1; /* Clear interrupt on match MR0. */ + chSysTimerHandlerI(); + + chSysIRQExitI(); +} /* * Hardware initialization goes here. -- cgit v1.2.3 From 2c91f58d0f0baf6b75a20b46d20bdeb524aa356f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Dec 2007 10:46:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@146 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/Makefile.thumb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index a267ac184..13c32b4dc 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -79,7 +79,7 @@ ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s ../../ports/ARM7-LPC214x/GCC/chcore2.s +ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 4b14088c8..93188a528 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -79,7 +79,7 @@ TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ board.c buzzer.c mmcsd.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s ../../ports/ARM7-LPC214x/GCC/chcore2.s +ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC -- cgit v1.2.3 From b1bba5833e6f4476c8fb81b364c3f30996e94cc6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Dec 2007 11:11:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@147 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 11 +- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 10 +- demos/ARM7-LPC214x-GCC-minimal/chcore.c | 203 ------------------------- demos/ARM7-LPC214x-GCC-minimal/chcore.h | 116 --------------- demos/ARM7-LPC214x-GCC-minimal/chcore2.s | 206 -------------------------- demos/ARM7-LPC214x-GCC-minimal/chtypes.h | 47 ------ demos/ARM7-LPC214x-GCC-minimal/crt0.s | 149 ------------------- demos/ARM7-LPC214x-GCC/chtypes.h | 47 ------ 8 files changed, 10 insertions(+), 779 deletions(-) delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/chcore.c delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/chcore.h delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/chcore2.s delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/chtypes.h delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/crt0.s delete mode 100644 demos/ARM7-LPC214x-GCC/chtypes.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index ac7bb1000..3514a9090 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -62,14 +62,13 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = chcore.c \ +ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c \ - main.c - + board.c main.c # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is @@ -77,7 +76,7 @@ ASRC = chcore.c \ TSRC = # List ASM source files here -ASMSRC = crt0.s chcore2.s +ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC @@ -160,7 +159,7 @@ $(TOBJS) : %.o : %.c $(ASMOBJS) : %.o : %.s @echo - $(AS) -c $(ASFLAGS) $< -o $@ + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ %elf: $(OBJS) @echo diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 17239c741..76b3fd296 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -67,16 +67,16 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = chcore.c \ +TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ + ../../ports/ARM7-LPC214x/GCC/vic.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c \ - main.c + board.c main.c # List ASM source files here -ASMSRC = crt0.s chcore2.s +ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC @@ -159,7 +159,7 @@ $(TOBJS) : %.o : %.c $(ASMOBJS) : %.o : %.s @echo - $(AS) -c $(ASFLAGS) $< -o $@ + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ %elf: $(OBJS) @echo diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.c b/demos/ARM7-LPC214x-GCC-minimal/chcore.c deleted file mode 100644 index f46b932be..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include "lpc214x.h" -#include "vic.h" -//#include "lpc214x_serial.h" -//#include "lpc214x_ssp.h" -//#include "mmcsd.h" - -//#include "buzzer.h" - -extern void IrqHandler(void); -extern void T0IrqHandler(void); - -#define VAL_TC0_PRESCALER 0 - -/* - * Pins configuration for Olimex LPC-P2148. - * - * PINSEL0 - * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD - * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 - * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 - * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- - * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - * - * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 - * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 - * - * PINSEL2 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- - * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- - */ -#define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100840A8 -#define VAL_PINSEL2 0x00000004 -#define VAL_FIO0DIR 0xB0703C00 -#define VAL_FIO1DIR 0x00000000 - -/* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. - */ -void hwinit(void) { - - /* - * All peripherals clock disabled by default in order to save power. - */ - PCONP = PCRTC | PCTIM0; - - /* - * MAM setup. - */ - MAMTIM = 0x3; /* 3 cycles for flash accesses. */ - MAMCR = 0x2; /* MAM fully enabled. */ - - /* - * PLL setup for Fosc=12MHz and CCLK=48MHz. - * P=2 M=3. - */ - PLL *pll = PLLBase; - pll->PLL0_CFG = 0x23; /* P and M values. */ - pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - while (!(pll->PLL0_STAT & 0x400)) - ; /* Wait for PLL lock. */ - - pll->PLL0_CON = 0x3; /* Connects the PLL. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - - /* - * VPB setup. - * PCLK = CCLK / 4. - */ - VPBDIV = VPD_D4; - - /* - * I/O pins configuration. - */ - PINSEL0 = VAL_PINSEL0; - PINSEL1 = VAL_PINSEL1; - PINSEL2 = VAL_PINSEL2; - IO0DIR = VAL_FIO0DIR; - IO0SET = 0xFFFFFFFF; - IO1DIR = VAL_FIO1DIR; - IO1SET = 0xFFFFFFFF; - - /* - * Interrupt vectors assignment. - */ - InitVIC(); - VICDefVectAddr = (IOREG32)IrqHandler; - - /* - * System Timer initialization, 1ms intervals. - */ - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - VICIntEnable = INTMASK(SOURCE_Timer0); - TC *timer = T0Base; - timer->TC_PR = VAL_TC0_PRESCALER; - timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); - timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ - timer->TC_TCR = 2; /* Reset counter and prescaler. */ - timer->TC_TCR = 1; /* Timer enabled. */ - - /* - * Other subsystems. - */ -// InitSerial(1, 2); -// InitSSP(); -// InitMMC(); -// InitBuzzer(); -} - -/* - * System idle thread loop. - */ -void _IdleThread(void *p) { - - while (TRUE) { -// Note, it is disabled because it causes trouble with the JTAG probe. -// Enable it in the final code only. -// PCON = 1; - } -} - -/* - * System console message (not implemented). - */ -void chSysPuts(char *msg) { -} - -/* - * Non-vectored IRQs handling here. - */ -__attribute__((naked, weak)) -void IrqHandler(void) { - - asm(".code 32 \n\t" \ - "stmfd sp!, {r0-r3, r12, lr} \n\t"); -#ifdef THUMB - asm("add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16 \n\t"); - VICVectAddr = 0; - asm("ldr r0, =IrqCommon \n\t" \ - "bx r0 \n\t"); -#else - VICVectAddr = 0; - asm("b IrqCommon \n\t"); -#endif -} - -/* - * Timer 0 IRQ handling here. - */ -__attribute__((naked, weak)) -void T0IrqHandler(void) { - - asm(".code 32 \n\t" \ - "stmfd sp!, {r0-r3, r12, lr} \n\t"); -#ifdef THUMB - asm("add r0, pc, #1 \n\t" \ - "bx r0 \n\t" \ - ".code 16 \n\t"); - T0IR = 1; /* Clear interrupt on match MR0. */ - chSysTimerHandlerI(); - VICVectAddr = 0; - asm("ldr r0, =IrqCommon \n\t" \ - "bx r0 \n\t"); -#else - T0IR = 1; /* Clear interrupt on match MR0. */ - chSysTimerHandlerI(); - VICVectAddr = 0; - asm("b IrqCommon \n\t"); -#endif -} diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore.h b/demos/ARM7-LPC214x-GCC-minimal/chcore.h deleted file mode 100644 index 941036830..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/* - * The following values are implementation dependent. You may change them in - * order to match your HW. - */ -#define FOSC 12000000 -#define CCLK 48000000 -#define PCLK 12000000 - -typedef void *regarm; - -/* - * Interrupt saved context. - */ -struct extctx { - regarm spsr_irq; - regarm lr_irq; - regarm r0; - regarm r1; - regarm r2; - regarm r3; - regarm r12; -}; - -/* - * System saved context. - */ -struct intctx { - regarm r4; - regarm r5; - regarm r6; -#ifndef CH_CURRP_REGISTER_CACHE - regarm r7; -#endif - regarm r8; - regarm r9; - regarm r10; - regarm r11; - regarm lr; -}; - -/* - * Port dependent part of the Thread structure, you may add fields in - * this structure. - */ -typedef struct { - struct intctx *r13; -} Context; - -/* - * Platform dependent part of the \p chThdCreate() API. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->r4 = pf; \ - tp->p_ctx.r13->r5 = arg; \ - tp->p_ctx.r13->lr = threadstart; \ -} - -#ifdef THUMB -extern void chSysLock(void); -extern void chSysUnlock(void); -#else /* !THUMB */ -#define chSysLock() asm("msr CPSR_c, #0x9F") -#define chSysUnlock() asm("msr CPSR_c, #0x1F") -#endif /* THUMB */ - -#ifdef THUMB -#define INT_REQUIRED_STACK 0x10 -#else /* !THUMB */ -#define INT_REQUIRED_STACK 0 -#endif /* THUMB */ -#define StackAlign(n) ((((n) - 1) | 3) + 1) -#define UserStackSize(n) StackAlign(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + \ - INT_REQUIRED_STACK) -#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; - -/* It requires zero bytes, but better be safe.*/ -#define IDLE_THREAD_STACK_SIZE 8 -void _IdleThread(void *p) __attribute__((noreturn)); - -void chSysHalt(void) __attribute__((noreturn)); -void chSysSwitchI(Context *oldp, Context *newp); -void chSysPuts(char *msg); -void threadstart(void); -void DefFiqHandler(void); -void DefIrqHandler(void); -void SpuriousHandler(void); - -#endif /* _CHCORE_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s b/demos/ARM7-LPC214x-GCC-minimal/chcore2.s deleted file mode 100644 index 7c9d1d0d7..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/chcore2.s +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "chconf.h" - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text -.code 32 -.balign 4 - -.globl threadstart -threadstart: - msr CPSR_c, #MODE_SYS -#ifndef THUMB_NO_INTERWORKING - mov r0, r5 - mov lr, pc - bx r4 - bl chThdExit -#else - add r0, pc, #1 - bx r0 -.code 16 - mov r0, r5 - bl jmpr4 - bl chThdExit -jmpr4: bx r4 -.code 32 -#endif - -.weak UndHandler -.globl UndHandler -UndHandler: - -.weak SwiHandler -.globl SwiHandler -SwiHandler: - -.weak PrefetchHandler -.globl PrefetchHandler -PrefetchHandler: - -.weak AbortHandler -.globl AbortHandler -AbortHandler: - -.weak FiqHandler -.globl FiqHandler -FiqHandler: - b halt32 - -.weak chSysHalt -#ifdef THUMB_NO_INTERWORKING -.code 16 -.globl chSysHalt -chSysHalt: - mov r0, pc - bx r0 -.code 32 -#else -.globl chSysHalt -chSysHalt: -#endif -halt32: - mrs r0, CPSR - orr r0, #I_BIT | F_BIT - msr CPSR_c, r0 -.loop: b .loop - -#ifdef THUMB -.globl chSysLock -chSysLock: - msr CPSR_c, #0x9F - bx lr - -.globl chSysUnlock -chSysUnlock: - msr CPSR_c, #0x1F - bx lr -#endif - -.globl chSysSwitchI -chSysSwitchI: -#ifdef CH_CURRP_REGISTER_CACHE - stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr} - bx lr -#else - ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc} -#endif -#else - stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - str sp, [r0, #0] - ldr sp, [r1, #0] -#ifdef THUMB - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr} - bx lr -#else - ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc} -#endif -#endif /* CH_CURRP_REGISTER_CACHE */ - -/* - * Common exit point for all IRQ routines, it performs the rescheduling if - * required. - * System stack frame structure after a context switch in the - * interrupt handler: - * - * High +------------+ - * | LR_USR | -+ - * | R12 | | - * | R3 | | - * | R2 | | External context: IRQ handler frame - * | R1 | | - * | R0 | | - * | LR_IRQ | | (user code return address) - * | SPSR | -+ (user code status) - * | .... | <- mk_DoRescheduleI() stack frame, optimize it for space - * | LR | -+ (system code return address) - * | R11 | | - * | R10 | | - * | R9 | | - * | R8 | | Internal context: mk_SwitchI() frame - * | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE) - * | R6 | | - * | R5 | | - * SP-> | R4 | -+ - * Low +------------+ - */ -#ifdef THUMB_NO_INTERWORKING -.code 16 -.globl IrqCommon -IrqCommon: - bl chSchRescRequiredI - mov lr, pc - bx lr -.code 32 -#else -.globl IrqCommon -IrqCommon: - bl chSchRescRequiredI -#endif - cmp r0, #0 // Simply returns if a - ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not - subeqs pc, lr, #4 // required. - - // Saves the IRQ mode registers in the system stack. - ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty. - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack. - msr CPSR_c, #MODE_IRQ | I_BIT - mrs r0, SPSR - mov r1, lr - msr CPSR_c, #MODE_SYS | I_BIT - stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ. - - // Context switch. -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 -.code 16 - bl chSchDoRescheduleI - mov lr, pc - bx lr -.code 32 -#else - bl chSchDoRescheduleI -#endif - - // Re-establish the IRQ conditions again. - ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ. - msr CPSR_c, #MODE_IRQ | I_BIT - msr SPSR_fsxc, r0 - mov lr, r1 - msr CPSR_c, #MODE_SYS | I_BIT - ldmfd sp!, {r0-r3, r12, lr} - msr CPSR_c, #MODE_IRQ | I_BIT - subs pc, lr, #4 diff --git a/demos/ARM7-LPC214x-GCC-minimal/chtypes.h b/demos/ARM7-LPC214x-GCC-minimal/chtypes.h deleted file mode 100644 index 2ac219148..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/chtypes.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -/* - * Generic types often dependant on the compiler. - */ -#define BOOL char -#define BYTE8 unsigned char -#define SBYTE8 char -#define WORD16 short -#define UWORD16 unsigned short -#define LONG32 int -#define ULONG32 unsigned int - -typedef BYTE8 t_tmode; -typedef BYTE8 t_tstate; -typedef UWORD16 t_tid; -typedef ULONG32 t_prio; -typedef LONG32 t_msg; -typedef LONG32 t_eventid; -typedef ULONG32 t_eventmask; -typedef ULONG32 t_time; -typedef LONG32 t_cnt; -typedef ULONG32 t_size; - -#define INLINE inline - -#endif /* _CHTYPES_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/crt0.s b/demos/ARM7-LPC214x-GCC-minimal/crt0.s deleted file mode 100644 index a7845036d..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/crt0.s +++ /dev/null @@ -1,149 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Generic ARM startup file for ChibiOS/RT. - */ - -.extern _main - -.set MODE_USR, 0x10 -.set MODE_FIQ, 0x11 -.set MODE_IRQ, 0x12 -.set MODE_SVC, 0x13 -.set MODE_ABT, 0x17 -.set MODE_UND, 0x1B -.set MODE_SYS, 0x1F - -.equ I_BIT, 0x80 -.equ F_BIT, 0x40 - -.text -.code 32 -.balign 4 -/* - * System entry points. - */ -_start: - b ResetHandler - ldr pc, _undefined - ldr pc, _swi - ldr pc, _prefetch - ldr pc, _abort - nop - ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */ - ldr pc, _fiq - -_undefined: - .word UndHandler -_swi: - .word SwiHandler -_prefetch: - .word PrefetchHandler -_abort: - .word AbortHandler -_fiq: - .word FiqHandler - .word 0 - .word 0 - -/* - * Reset handler. - */ -ResetHandler: - /* - * Stack pointers initialization. - */ - ldr r0, =__ram_end__ - /* Undefined */ - msr CPSR_c, #MODE_UND | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__und_stack_size__ - sub r0, r0, r1 - /* Abort */ - msr CPSR_c, #MODE_ABT | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__abt_stack_size__ - sub r0, r0, r1 - /* FIQ */ - msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__fiq_stack_size__ - sub r0, r0, r1 - /* IRQ */ - msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__irq_stack_size__ - sub r0, r0, r1 - /* Supervisor */ - msr CPSR_c, #MODE_SVC | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__svc_stack_size__ - sub r0, r0, r1 - /* System */ - msr CPSR_c, #MODE_SYS | I_BIT | F_BIT - mov sp, r0 -// ldr r1, =__sys_stack_size__ -// sub r0, r0, r1 - /* - * Data initialization. - * NOTE: It assumes that the DATA size is a multiple of 4. - */ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata -dataloop: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dataloop - /* - * BSS initialization. - * NOTE: It assumes that the BSS size is a multiple of 4. - */ - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -bssloop: - cmp r1, r2 - strlo r0, [r1], #4 - blo bssloop - /* - * Application-provided HW initialization routine. - */ -#ifndef THUMB_NO_INTERWORKING - bl hwinit - /* - * main(0, NULL). - */ - mov r0, #0 - mov r1, r0 - bl main - bl chSysHalt -#else - add r0, pc, #1 - bx r0 -.code 16 - bl hwinit - mov r0, #0 - mov r1, r0 - bl main - bl chSysHalt -.code 32 -#endif diff --git a/demos/ARM7-LPC214x-GCC/chtypes.h b/demos/ARM7-LPC214x-GCC/chtypes.h deleted file mode 100644 index 2ac219148..000000000 --- a/demos/ARM7-LPC214x-GCC/chtypes.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -/* - * Generic types often dependant on the compiler. - */ -#define BOOL char -#define BYTE8 unsigned char -#define SBYTE8 char -#define WORD16 short -#define UWORD16 unsigned short -#define LONG32 int -#define ULONG32 unsigned int - -typedef BYTE8 t_tmode; -typedef BYTE8 t_tstate; -typedef UWORD16 t_tid; -typedef ULONG32 t_prio; -typedef LONG32 t_msg; -typedef LONG32 t_eventid; -typedef ULONG32 t_eventmask; -typedef ULONG32 t_time; -typedef LONG32 t_cnt; -typedef ULONG32 t_size; - -#define INLINE inline - -#endif /* _CHTYPES_H_ */ -- cgit v1.2.3 From 51d9a97993bca9924419ba9d62b4c79c8426c91b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Dec 2007 11:13:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@148 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/board.c | 133 +++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/board.h | 64 ++++++++++++++++ 2 files changed, 197 insertions(+) create mode 100644 demos/ARM7-LPC214x-GCC-minimal/board.c create mode 100644 demos/ARM7-LPC214x-GCC-minimal/board.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c new file mode 100644 index 000000000..ef86d8217 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -0,0 +1,133 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "lpc214x.h" +#include "vic.h" +//#include "lpc214x_serial.h" +//#include "lpc214x_ssp.h" + +#include "board.h" +//#include "mmcsd.h" +//#include "buzzer.h" + +/* + * Non-vectored IRQs handling here. + */ +__attribute__((naked)) +static void IrqHandler(void) { + + chSysIRQEnterI(); + + /* nothing */ + + chSysIRQExitI(); +} + +/* + * Timer 0 IRQ handling here. + */ +__attribute__((naked)) +static void T0IrqHandler(void) { + + chSysIRQEnterI(); + + T0IR = 1; /* Clear interrupt on match MR0. */ + chSysTimerHandlerI(); + + chSysIRQExitI(); +} + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLLBase; + pll->PLL0_CFG = 0x23; /* P and M values. */ + pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + while (!(pll->PLL0_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL0_CON = 0x3; /* Connects the PLL. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; + + /* + * I/O pins configuration. + */ + PINSEL0 = VAL_PINSEL0; + PINSEL1 = VAL_PINSEL1; + PINSEL2 = VAL_PINSEL2; + IO0DIR = VAL_FIO0DIR; + IO0SET = 0xFFFFFFFF; + IO1DIR = VAL_FIO1DIR; + IO1SET = 0xFFFFFFFF; + + /* + * Interrupt vectors assignment. + */ + InitVIC(); + VICDefVectAddr = (IOREG32)IrqHandler; + + /* + * System Timer initialization, 1ms intervals. + */ + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); + VICIntEnable = INTMASK(SOURCE_Timer0); + TC *timer = T0Base; + timer->TC_PR = VAL_TC0_PRESCALER; + timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); + timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ + timer->TC_TCR = 2; /* Reset counter and prescaler. */ + timer->TC_TCR = 1; /* Timer enabled. */ + + /* + * Other subsystems. + */ +// InitSerial(1, 2); +// InitSSP(); +// InitMMC(); +// InitBuzzer(); +} diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h new file mode 100644 index 000000000..c9d3f01b3 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/board.h @@ -0,0 +1,64 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define BOARD_OLIMEX_LCP_P2148 + +/* + * The following values are implementation dependent. You may change them in + * order to match your HW. + */ +#define FOSC 12000000 +#define CCLK 48000000 +#define PCLK 12000000 + +#define VAL_TC0_PRESCALER 0 + +/* + * Pins configuration for Olimex LPC-P2148. + * + * PINSEL0 + * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD + * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 + * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 + * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- + * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + * + * PINSEL1 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 + * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 + * + * PINSEL2 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- + * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- + */ +#define VAL_PINSEL0 0x00055555 +#define VAL_PINSEL1 0x100840A8 +#define VAL_PINSEL2 0x00000004 +#define VAL_FIO0DIR 0xB0703C00 +#define VAL_FIO1DIR 0x00000000 + +#endif /* _BOARD_H_ */ -- cgit v1.2.3 From 8afb5785a131d255523593d6ec393cada25b8e7f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Dec 2007 14:00:01 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@149 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 12 ++++++------ demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 14 +++++++------- demos/ARM7-LPC214x-GCC/Makefile | 14 +++++++------- demos/ARM7-LPC214x-GCC/Makefile.thumb | 14 +++++++------- 4 files changed, 27 insertions(+), 27 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 3514a9090..1fe22d71a 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -127,16 +127,16 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) - # Both ARM and THUMB case - CPFLAGS += -mthumb-interwork -D THUMB + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork LDFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork -D THUMB else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly - CPFLAGS += -D THUMB + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -D THUMB_NO_INTERWORKING LDFLAGS += -mthumb - ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING + ASFLAGS += -D THUMB_NO_INTERWORKING endif endif diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 76b3fd296..b00adef75 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -91,7 +91,7 @@ ULIBS = AOPT = # THUMB-specific options here -TOPT = -mthumb +TOPT = -mthumb -D THUMB # Common options here # NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in @@ -127,16 +127,16 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) - # Both ARM and THUMB case - CPFLAGS += -mthumb-interwork -D THUMB + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork LDFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork -D THUMB else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly - CPFLAGS += -D THUMB -D THUMB_NO_INTERWORKING + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -D THUMB_NO_INTERWORKING LDFLAGS += -mthumb - ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING + ASFLAGS += -D THUMB_NO_INTERWORKING endif endif diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 13c32b4dc..5e49defda 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -130,16 +130,16 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) - # Both ARM and THUMB case - CPFLAGS += -mthumb-interwork -D THUMB + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork LDFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork -D THUMB else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly - CPFLAGS += -D THUMB + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -D THUMB_NO_INTERWORKING LDFLAGS += -mthumb - ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING + ASFLAGS += -D THUMB_NO_INTERWORKING endif endif @@ -158,7 +158,7 @@ $(AOBJS) : %.o : %.c $(TOBJS) : %.o : %.c @echo - $(CC) -c $(CPFLAGS) $(TOPT) -mthumb -I . $(INCDIR) $< -o $@ + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ $(ASMOBJS) : %.o : %.s @echo diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 93188a528..89ccdfdc2 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -94,7 +94,7 @@ ULIBS = AOPT = # THUMB-specific options here -TOPT = -mthumb +TOPT = -mthumb -D THUMB # Common options here # NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in @@ -130,16 +130,16 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) - # Both ARM and THUMB case - CPFLAGS += -mthumb-interwork -D THUMB + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork LDFLAGS += -mthumb-interwork - ASFLAGS += -mthumb-interwork -D THUMB else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly - CPFLAGS += -D THUMB -D THUMB_NO_INTERWORKING + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -D THUMB_NO_INTERWORKING LDFLAGS += -mthumb - ASFLAGS += -mthumb-interwork -D THUMB -D THUMB_NO_INTERWORKING + ASFLAGS += -D THUMB_NO_INTERWORKING endif endif -- cgit v1.2.3 From 398c024927d7fb31d86c50e081a74a9c8fd45769 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 23 Dec 2007 09:40:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@159 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 7 ++++--- demos/Win32-MinGW/demo.c | 6 +++--- 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 9ee9dfb77..8d4edec7e 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -58,9 +58,10 @@ UADEFS = # List C source files here SRC = chcore.c demo.c \ ../../test/test.c ../../ports/win32/simcom.c \ - ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c \ - ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c \ - ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ # List ASM source files here ASRC = chcore2.s diff --git a/demos/Win32-MinGW/demo.c b/demos/Win32-MinGW/demo.c index 7f8bd6903..acf17e7fd 100644 --- a/demos/Win32-MinGW/demo.c +++ b/demos/Win32-MinGW/demo.c @@ -159,7 +159,7 @@ static t_msg ShellThread(void *arg) { FullDuplexDriver *sd = (FullDuplexDriver *)arg; char *lp, line[64]; Thread *tp; - WorkingArea(tarea, 1024); + WorkingArea(tarea, 2048); chIQReset(&sd->sd_iqueue); chOQReset(&sd->sd_oqueue); @@ -221,7 +221,7 @@ static t_msg ShellThread(void *arg) { return 0; } -static WorkingArea(s1area, 2048); +static WorkingArea(s1area, 4096); static Thread *s1; EventListener s1tel; @@ -244,7 +244,7 @@ static void COM1Handler(t_eventid id) { chIQReset(&COM1.sd_iqueue); } -static WorkingArea(s2area, 2048); +static WorkingArea(s2area, 4096); static Thread *s2; EventListener s2tel; -- cgit v1.2.3 From e9fd3ba81330391dbb28181a98ec1e364736b6e5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 1 Jan 2008 17:45:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@163 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/ch.ld | 2 ++ demos/ARM7-LPC214x-GCC/ch.ld | 2 ++ 2 files changed, 4 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld index ace1c3b53..a71fac21b 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -64,6 +64,8 @@ SECTIONS _data = .; *(.data) . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); _edata = .; } > ram AT > flash diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index ace1c3b53..a71fac21b 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -64,6 +64,8 @@ SECTIONS _data = .; *(.data) . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); _edata = .; } > ram AT > flash -- cgit v1.2.3 From 14d3b059c225769038a0f3538f491cf6099dbb3e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 7 Jan 2008 10:49:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@165 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MSVS/ch.vcproj | 13 ++++++------- demos/Win32-MSVS/demo.c | 9 --------- 2 files changed, 6 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MSVS/ch.vcproj b/demos/Win32-MSVS/ch.vcproj index 3490c810b..0b27e2ffb 100644 --- a/demos/Win32-MSVS/ch.vcproj +++ b/demos/Win32-MSVS/ch.vcproj @@ -159,6 +159,9 @@ + + @@ -185,13 +188,6 @@ RelativePath="..\..\ports\Win32\simcom.c"> - - - - + + diff --git a/demos/Win32-MSVS/demo.c b/demos/Win32-MSVS/demo.c index 7f8bd6903..5a3bf167c 100644 --- a/demos/Win32-MSVS/demo.c +++ b/demos/Win32-MSVS/demo.c @@ -182,7 +182,6 @@ static t_msg ShellThread(void *arg) { PrintLineFDD(sd, " exit - Logout from ChibiOS/RT\r\n"); PrintLineFDD(sd, " time - Prints the system timer value\r\n"); PrintLineFDD(sd, " hello - Runs the Hello World demo thread\r\n"); - PrintLineFDD(sd, " test - Runs the System Test thread\r\n"); } else if (stricmp(lp, "exit") == 0) { if (checkend(sd)) @@ -204,14 +203,6 @@ static t_msg ShellThread(void *arg) { if (chThdWait(tp)) break; // Lost connection while executing the hello thread. } - else if (stricmp(lp, "test") == 0) { - if (checkend(sd)) - continue; - tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), - TestThread, arg); - if (chThdWait(tp)) - break; // Lost connection while executing the hello thread. - } else { PrintLineFDD(sd, lp); PrintLineFDD(sd, " ?\r\n"); -- cgit v1.2.3 From b1db8a9f7fe3bc2cd48c52e7c2c50e0e118f8889 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 7 Jan 2008 14:06:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@166 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 5 +++++ demos/ARM7-LPC214x-GCC/chconf.h | 5 +++++ demos/AVR-AT90CANx-GCC/chconf.h | 5 +++++ demos/Win32-MSVS/chconf.h | 5 +++++ demos/Win32-MinGW/chconf.h | 5 +++++ 5 files changed, 25 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 11081acc4..7db7c3618 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -107,6 +107,11 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ //#define CH_USE_MESSAGES_EVENT +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +//#define CH_USE_MESSAGES_PRIORITY + /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 28db4b351..4889fb590 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -107,6 +107,11 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_MESSAGES_EVENT +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +#define CH_USE_MESSAGES_PRIORITY + /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index b4ddeeb05..d3f4491b2 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -108,6 +108,11 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_MESSAGES_EVENT +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +#define CH_USE_MESSAGES_PRIORITY + /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h index 037e3d8a0..e4710e575 100644 --- a/demos/Win32-MSVS/chconf.h +++ b/demos/Win32-MSVS/chconf.h @@ -112,6 +112,11 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_MESSAGES_EVENT +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +#define CH_USE_MESSAGES_PRIORITY + /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 3e741bb8c..115db4325 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -112,6 +112,11 @@ * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ #define CH_USE_MESSAGES_EVENT +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +#define CH_USE_MESSAGES_PRIORITY + /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. * @note requires \p CH_USE_MESSAGES. -- cgit v1.2.3 From 7c184cf08e65dc65e060c8c913219c96bde0fd41 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 7 Jan 2008 14:11:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@167 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 4889fb590..eb1ebf7ea 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -110,7 +110,7 @@ /** Configuration option: If enabled then the threads have an option to serve * messages by priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_PRIORITY +//#define CH_USE_MESSAGES_PRIORITY /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. -- cgit v1.2.3 From 29feb9855078f659c1ff9c9459c0a013a9be4daf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 7 Jan 2008 14:16:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@168 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chconf.h | 2 +- demos/Win32-MSVS/chconf.h | 2 +- demos/Win32-MinGW/chconf.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index d3f4491b2..f0f3caf26 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -111,7 +111,7 @@ /** Configuration option: If enabled then the threads have an option to serve * messages by priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_PRIORITY +//#define CH_USE_MESSAGES_PRIORITY /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h index e4710e575..b6d8e4c98 100644 --- a/demos/Win32-MSVS/chconf.h +++ b/demos/Win32-MSVS/chconf.h @@ -115,7 +115,7 @@ /** Configuration option: If enabled then the threads have an option to serve * messages by priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_PRIORITY +//#define CH_USE_MESSAGES_PRIORITY /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 115db4325..b913a6cc4 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -115,7 +115,7 @@ /** Configuration option: If enabled then the threads have an option to serve * messages by priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_PRIORITY +//#define CH_USE_MESSAGES_PRIORITY /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. -- cgit v1.2.3 From 8fb01ac78308d1fdb0efad351a5ffd5f48981a2f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 17 Jan 2008 09:44:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@179 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MSVS/chcore.c | 6 +++--- demos/Win32-MSVS/chcore.h | 2 +- demos/Win32-MinGW/chcore.h | 2 +- demos/Win32-MinGW/chcore2.s | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c index 99876b8d6..facdea31c 100644 --- a/demos/Win32-MSVS/chcore.c +++ b/demos/Win32-MSVS/chcore.c @@ -84,7 +84,7 @@ __declspec(naked) void __fastcall chSysHalt(void) { exit(2); } -__declspec(naked) void __fastcall chSysSwitchI(Context *oldp, Context *newp) { +__declspec(naked) void __fastcall chSysSwitchI(Thread *otp, Thread *ntp) { __asm { // Switch out code @@ -92,9 +92,9 @@ __declspec(naked) void __fastcall chSysSwitchI(Context *oldp, Context *newp) { push esi push edi push ebx - mov dword ptr [ecx],esp + mov dword ptr 16[ecx],esp // Switch in code - mov esp,[edx] + mov esp,16[edx] pop ebx pop edi pop esi diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h index b9fbb0147..18e96dc13 100644 --- a/demos/Win32-MSVS/chcore.h +++ b/demos/Win32-MSVS/chcore.h @@ -76,7 +76,7 @@ typedef struct { t_msg _IdleThread(void *p); void __fastcall chSysHalt(void); -void __fastcall chSysSwitchI(Context *oldp, Context *newp); +void __fastcall chSysSwitchI(Thread *otp, Thread *ntp); void __fastcall threadexit(void); #endif /* _CHCORE_H_ */ diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 43265326b..6bb2664f5 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -76,7 +76,7 @@ typedef struct { t_msg _IdleThread(void *p); __attribute__((fastcall)) void chSysHalt(void); -__attribute__((fastcall)) void chSysSwitchI(Context *oldp, Context *newp); +__attribute__((fastcall)) void chSysSwitchI(Thread *otp, Thread *ntp); __attribute__((fastcall)) void threadstart(void); #endif /* _CHCORE_H_ */ diff --git a/demos/Win32-MinGW/chcore2.s b/demos/Win32-MinGW/chcore2.s index c8260e3e6..9334fbfdc 100644 --- a/demos/Win32-MinGW/chcore2.s +++ b/demos/Win32-MinGW/chcore2.s @@ -27,9 +27,9 @@ push %esi push %edi push %ebx - movl %esp,(%ecx) + movl %esp,16(%ecx) # Switch in - movl (%edx),%esp + movl 16(%edx),%esp pop %ebx pop %edi pop %esi -- cgit v1.2.3 From 68003a03c299850f0b66adfa4df6c9d6b6ba6ab2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Jan 2008 14:50:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@182 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 6 ------ demos/ARM7-LPC214x-GCC/chconf.h | 6 ------ demos/AVR-AT90CANx-GCC/chconf.h | 6 ------ demos/Win32-MSVS/chconf.h | 6 ------ demos/Win32-MinGW/chconf.h | 6 ------ 5 files changed, 30 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 7db7c3618..d12a1827e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -95,12 +95,6 @@ * included in the kernel.*/ //#define CH_USE_MESSAGES -/** Configuration option: if specified then the \p chMsgSendTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -//#define CH_USE_MESSAGES_TIMEOUT - /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index eb1ebf7ea..c8817f85c 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -95,12 +95,6 @@ * included in the kernel.*/ #define CH_USE_MESSAGES -/** Configuration option: if specified then the \p chMsgSendTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_TIMEOUT - /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index f0f3caf26..162255af5 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -96,12 +96,6 @@ * included in the kernel.*/ #define CH_USE_MESSAGES -/** Configuration option: if specified then the \p chMsgSendTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_TIMEOUT - /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h index b6d8e4c98..075f829d3 100644 --- a/demos/Win32-MSVS/chconf.h +++ b/demos/Win32-MSVS/chconf.h @@ -100,12 +100,6 @@ * included in the kernel.*/ #define CH_USE_MESSAGES -/** Configuration option: if specified then the \p chMsgSendTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_TIMEOUT - /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index b913a6cc4..15cf3d323 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -100,12 +100,6 @@ * included in the kernel.*/ #define CH_USE_MESSAGES -/** Configuration option: if specified then the \p chMsgSendTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_TIMEOUT - /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. * @note requires \p CH_USE_MESSAGES. -- cgit v1.2.3 From 4fb21e032efb6898b89328daa3d6e4c0d4b6bbef Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 6 Feb 2008 14:41:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@190 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 197 ++ demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h | 2918 +++++++++++++++++++++++ demos/ARM7-AT91SAM7X-GCC/board.c | 25 + demos/ARM7-AT91SAM7X-GCC/board.h | 26 + demos/ARM7-AT91SAM7X-GCC/ch.ld | 87 + demos/ARM7-AT91SAM7X-GCC/chconf.h | 169 ++ demos/ARM7-AT91SAM7X-GCC/main.c | 39 + demos/ARM7-AT91SAM7X-GCC/readme.txt | 26 + 8 files changed, 3487 insertions(+) create mode 100644 demos/ARM7-AT91SAM7X-GCC/Makefile create mode 100644 demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h create mode 100644 demos/ARM7-AT91SAM7X-GCC/board.c create mode 100644 demos/ARM7-AT91SAM7X-GCC/board.h create mode 100644 demos/ARM7-AT91SAM7X-GCC/ch.ld create mode 100644 demos/ARM7-AT91SAM7X-GCC/chconf.h create mode 100644 demos/ARM7-AT91SAM7X-GCC/main.c create mode 100644 demos/ARM7-AT91SAM7X-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile new file mode 100644 index 000000000..87f1db472 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -0,0 +1,197 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +ASRC = \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + board.c main.c + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = + +# List ASM source files here +ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-AT91SAM7X/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT += -ffixed-r7 +OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -D THUMB_NO_INTERWORKING + LDFLAGS += -mthumb + ASFLAGS += -D THUMB_NO_INTERWORKING + endif +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h b/demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h new file mode 100644 index 000000000..20b0e747d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h @@ -0,0 +1,2918 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the disclaimer below in the documentation and/or +// other materials provided with the distribution. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 06/19/2007 (15:41:06) +// +// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c new file mode 100644 index 000000000..2ebad09e2 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -0,0 +1,25 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "at91lib/AT91SAM7X256.h" + +void hwinit(void) { +} diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h new file mode 100644 index 000000000..e6b529df6 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -0,0 +1,26 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define BOARD_OLIMEX_SAM7_EX256 + + +#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld new file mode 100644 index 000000000..10ce4b2f5 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0100; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : + { + _text = .; + *(.text); + *(.rodata); + *(.rodata*); + *(.glue_7t); + *(.glue_7); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h new file mode 100644 index 000000000..c8817f85c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +//#define CH_USE_MESSAGES_PRIORITY + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c new file mode 100644 index 000000000..24c96519f --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -0,0 +1,39 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "at91lib/AT91SAM7X256.h" + +/* + * Entry point, the interrupts are disabled on entry. + */ +int main(int argc, char **argv) { + + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ + chSysInit(); + + while (TRUE) + chThdSleep(1000); + + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-GCC/readme.txt b/demos/ARM7-AT91SAM7X-GCC/readme.txt new file mode 100644 index 000000000..5c0317e65 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-EX256 board. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/AT91SAM7X256/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com -- cgit v1.2.3 From d88047aa532f2416c3d3bec2db322b503e2e4585 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 6 Feb 2008 16:48:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@191 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/ch.ld | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 87f1db472..e4fd03fce 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -62,7 +62,7 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = \ +ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 10ce4b2f5..0cbe11eca 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -31,7 +31,7 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { flash : org = 0x100000, len = 256k - ram : org = 0x200000, len = 64k + ram : org = 0x200020, len = 64k - 0x20 } __ram_start__ = ORIGIN(ram); -- cgit v1.2.3 From fd63d45d5f642ae22e8de45faa09a795231fea1b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 15 Feb 2008 16:12:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@192 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 61 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 2ebad09e2..bc0d46189 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -21,5 +21,66 @@ #include "at91lib/AT91SAM7X256.h" +extern void FiqHandler(void); + +__attribute__((interrupt("IRQ"))) +static void SpuriousHandler(void) { + + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)AT91C_BASE_AIC; +} + void hwinit(void) { + int i; + AT91PS_PMC pmcp = AT91C_BASE_PMC; + AT91PS_AIC aicp = AT91C_BASE_AIC; + + /* + * Flash Memory: 1 wait state, about 50 cycles in a microsecond. + */ + AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; + + /* + * Watchdog disabled. + */ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + /* + * Enables the main oscillator and waits 56 slow cycles as startup time. + */ + pmcp->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; + while (!(pmcp->PMC_SR & AT91C_PMC_MOSCS)) + ; + + /* + * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 + * PLLfreq = 96109714 Hz (rounded) + */ + pmcp->PMC_PLLR = (AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (10 << 8)) | + (AT91C_CKGR_MUL & (72 << 16)); + while (!(pmcp->PMC_SR & (AT91C_PMC_LOCK))) + ; + + /* + * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) + */ + pmcp->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; + while (!(pmcp->PMC_SR & (AT91C_PMC_MCKRDY))) + ; + + /* + * Default AIC setup, the device drivers will modify it as needed. + */ + aicp->AIC_SVR[0] = (AT91_REG)FiqHandler; + for (i = 1; i < 31; i++) { + aicp->AIC_SVR[i] = (AT91_REG)NULL; + aicp->AIC_EOICR = (AT91_REG)i; + } + aicp->AIC_SPU = (AT91_REG)SpuriousHandler; + + /* + * I/O setup, enable clocks, initially all pins are inputs with pullups. + */ + pmcp->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); + AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; } -- cgit v1.2.3 From 53b6f6d8df525c3f71d230c6ed2be39c64c871a5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 18 Feb 2008 15:53:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@193 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 1 + demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c | 84 ++++++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h | 78 +++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-GCC/board.c | 82 +++++++++++++++++++++++++-------- demos/ARM7-AT91SAM7X-GCC/board.h | 35 ++++++++++++++ 5 files changed, 262 insertions(+), 18 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c create mode 100644 demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index e4fd03fce..a50ecb387 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -68,6 +68,7 @@ ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ ../../src/lib/evtimer.c ../../test/test.c \ + at91lib\aic.c \ board.c main.c # List THUMB-mode C sources here diff --git a/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c b/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c new file mode 100644 index 000000000..66eebf94e --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "aic.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the interrupt associated with the given source, using the +/// specified mode and interrupt handler. +/// \param source Interrupt source to configure. +/// \param mode Triggering mode of the interrupt. +/// \param handler Interrupt handler function. +//------------------------------------------------------------------------------ +void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )) +{ + // Disable the interrupt first + AT91C_BASE_AIC->AIC_IDCR = 1 << source; + + // Configure mode and handler + AT91C_BASE_AIC->AIC_SMR[source] = mode; + AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; + + // Clear interrupt + AT91C_BASE_AIC->AIC_ICCR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Enables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_EnableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IECR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Disables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_DisableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IDCR = 1 << source; +} + diff --git a/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h b/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h new file mode 100644 index 000000000..e8e52c78a --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Methods and definitions for configuring interrupts using the Advanced +/// Interrupt Controller (AIC). +/// +/// !Usage +/// -# Configure an interrupt source using AIC_ConfigureIT +/// -# Enable or disable interrupt generation of a particular source with +/// AIC_EnableIT and AIC_DisableIT. +//------------------------------------------------------------------------------ + +#ifndef AIC_H +#define AIC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL + /// Redefinition of missing constant. + #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )); + +extern void AIC_EnableIT(unsigned int source); + +extern void AIC_DisableIT(unsigned int source); + +#endif //#ifndef AIC_H + diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index bc0d46189..fac56f18d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -19,7 +19,8 @@ #include -#include "at91lib/AT91SAM7X256.h" +#include "board.h" +#include "at91lib/aic.h" extern void FiqHandler(void); @@ -29,10 +30,24 @@ static void SpuriousHandler(void) { AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)AT91C_BASE_AIC; } +/* + * Timer 0 IRQ handling here. + */ +__attribute__((naked)) +static void SYSIrqHandler(void) { + + chSysIRQEnterI(); + + if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { + chSysTimerHandlerI(); + (void) AT91C_BASE_PITC->PITC_PIVR; + } + + chSysIRQExitI(); +} + void hwinit(void) { int i; - AT91PS_PMC pmcp = AT91C_BASE_PMC; - AT91PS_AIC aicp = AT91C_BASE_AIC; /* * Flash Memory: 1 wait state, about 50 cycles in a microsecond. @@ -47,40 +62,71 @@ void hwinit(void) { /* * Enables the main oscillator and waits 56 slow cycles as startup time. */ - pmcp->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; - while (!(pmcp->PMC_SR & AT91C_PMC_MOSCS)) + AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) ; /* * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 * PLLfreq = 96109714 Hz (rounded) */ - pmcp->PMC_PLLR = (AT91C_CKGR_DIV & 14) | - (AT91C_CKGR_PLLCOUNT & (10 << 8)) | - (AT91C_CKGR_MUL & (72 << 16)); - while (!(pmcp->PMC_SR & (AT91C_PMC_LOCK))) + AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (10 << 8)) | + (AT91C_CKGR_MUL & (72 << 16)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) ; /* * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) */ - pmcp->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; - while (!(pmcp->PMC_SR & (AT91C_PMC_MCKRDY))) + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) ; + /* + * I/O setup, enable clocks, initially all pins are inputs with pullups. + */ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); + AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; + AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; + /* * Default AIC setup, the device drivers will modify it as needed. */ - aicp->AIC_SVR[0] = (AT91_REG)FiqHandler; + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; for (i = 1; i < 31; i++) { - aicp->AIC_SVR[i] = (AT91_REG)NULL; - aicp->AIC_EOICR = (AT91_REG)i; + AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; } - aicp->AIC_SPU = (AT91_REG)SpuriousHandler; + AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; /* - * I/O setup, enable clocks, initially all pins are inputs with pullups. + * LCD pins setup. */ - pmcp->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); - AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; + AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // Set to high. + AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL; // Configure as output. + AT91C_BASE_SYS->PIOA_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. + + AT91C_BASE_PIOA->PIO_SODR = PIOA_LCD_RESET; // Set to high. + AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET; // Configure as output. + AT91C_BASE_SYS->PIOB_PPUDR = PIOA_LCD_RESET; // Disable internal pullup resistor. + + /* + * Joystick and buttons, disable pullups, already inputs. + */ + AT91C_BASE_SYS->PIOA_PPUDR = PIOA_B1 | PIOA_B2 | PIOA_B3 | PIOA_B4 | PIOA_B5; + AT91C_BASE_SYS->PIOB_PPUDR = PIOB_SW1 | PIOB_SW2; + + /* + * MMC/SD slot, disable pullups, already inputs. + */ + AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP | PIOB_MMC_CP; + + /* + * PIT Initialization. + */ + AIC_ConfigureIT(AT91C_ID_SYS, AT91C_AIC_SRCTYPE_POSITIVE_EDGE, SYSIrqHandler); + AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; } diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h index e6b529df6..c1a900890 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -20,7 +20,42 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#ifndef AT91SAM7X256_H +#include "at91lib/AT91SAM7X256.h" +#endif + #define BOARD_OLIMEX_SAM7_EX256 +#define MCK 18432000 + +/* + * I/O definitions. + */ +#define PIOA_LCD_RESET (1 << 2) +#define PIOA_B1 (1 << 7) +#define PIOA_B2 (1 << 8) +#define PIOA_B3 (1 << 9) +#define PIOA_B4 (1 << 14) +#define PIOA_B5 (1 << 15) +#define PIOA_USB_PUP (1 << 25) +#define PIOA_USB_PR (1 << 26) +#define PIOA_PA27 (1 << 27) +#define PIOA_PA28 (1 << 28) +#define PIOA_PA29 (1 << 29) +#define PIOA_PA30 (1 << 30) + +#define PIOB_PHY_PD (1 << 18) +#define PIOB_AUDIO_OUT (1 << 19) +#define PIOB_LCD_BL (1 << 20) +#define PIOB_PB21 (1 << 21) +#define PIOB_MMC_WP (1 << 22) +#define PIOB_MMC_CP (1 << 23) +#define PIOB_SW1 (1 << 24) +#define PIOB_SW2 (1 << 25) +#define PIOB_PHY_IRQ (1 << 26) +#define PIOB_PB27_AD0 (1 << 27) +#define PIOB_PB27_AD1 (1 << 28) +#define PIOB_PB27_AD2 (1 << 29) +#define PIOB_PB27_AD3 (1 << 30) #endif /* _BOARD_H_ */ -- cgit v1.2.3 From dcd80dadf36c91ac337030eea3e2d7bbf7a7d0f5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 19 Feb 2008 15:34:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@194 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/board.c | 13 ++++++++++--- demos/ARM7-AT91SAM7X-GCC/board.h | 3 ++- demos/ARM7-AT91SAM7X-GCC/ch.ld | 3 --- demos/ARM7-AT91SAM7X-GCC/main.c | 19 +++++++++++++++++-- 5 files changed, 30 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index a50ecb387..737752687 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -62,7 +62,7 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ +ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index fac56f18d..aef835ffa 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -31,7 +31,7 @@ static void SpuriousHandler(void) { } /* - * Timer 0 IRQ handling here. + * SYS IRQ handling here. */ __attribute__((naked)) static void SYSIrqHandler(void) { @@ -39,6 +39,7 @@ static void SYSIrqHandler(void) { chSysIRQEnterI(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { +// AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. chSysTimerHandlerI(); (void) AT91C_BASE_PITC->PITC_PIVR; } @@ -46,6 +47,9 @@ static void SYSIrqHandler(void) { chSysIRQExitI(); } +/* + * Board initialization code. + */ void hwinit(void) { int i; @@ -104,7 +108,7 @@ void hwinit(void) { /* * LCD pins setup. */ - AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // Set to high. + AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // Set to low. AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL; // Configure as output. AT91C_BASE_SYS->PIOA_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. @@ -126,7 +130,10 @@ void hwinit(void) { /* * PIT Initialization. */ - AIC_ConfigureIT(AT91C_ID_SYS, AT91C_AIC_SRCTYPE_POSITIVE_EDGE, SYSIrqHandler); + AIC_ConfigureIT(AT91C_ID_SYS, + AT91C_AIC_SRCTYPE_POSITIVE_EDGE | (AT91C_AIC_PRIOR_HIGHEST -1), + SYSIrqHandler); + AIC_EnableIT(AT91C_ID_SYS); AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; } diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h index c1a900890..c5dc4728f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -26,7 +26,8 @@ #define BOARD_OLIMEX_SAM7_EX256 -#define MCK 18432000 +#define CLK 18432000 +#define MCK 48054857 /* * I/O definitions. diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 0cbe11eca..541c73b5b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -37,9 +37,6 @@ MEMORY __ram_start__ = ORIGIN(ram); __ram_size__ = LENGTH(ram); __ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; SECTIONS { diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 24c96519f..80eab874e 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -19,7 +19,19 @@ #include -#include "at91lib/AT91SAM7X256.h" +#include "board.h" + +static WorkingArea(waThread1, 64); +static t_msg Thread1(void *arg) { + + while (TRUE) { + AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. + chThdSleep(500); + AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // LCD off. + chThdSleep(500); + } + return 0; +} /* * Entry point, the interrupts are disabled on entry. @@ -32,8 +44,11 @@ int main(int argc, char **argv) { */ chSysInit(); - while (TRUE) + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + + while (TRUE) { chThdSleep(1000); + } return 0; } -- cgit v1.2.3 From fd1fdffd2aae564779bc5d220dcb2cdbc9064e34 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 19 Feb 2008 16:32:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@196 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/readme.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/readme.txt b/demos/ARM7-AT91SAM7X-GCC/readme.txt index 5c0317e65..71f8ee51a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-GCC/readme.txt @@ -8,7 +8,7 @@ The demo runs on an Olimex SAM7-EX256 board. ** The Demo ** -The demo blinks the leds on the board by using multiple threads. +The demo currently just flashes the LCD background using a thread. ** Build Procedure ** -- cgit v1.2.3 From f87e32d85c6fc2b400c4dc8db15af1cb4c626907 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 20 Feb 2008 16:29:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@197 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/board.c | 28 ++++++++++++++++++---------- demos/ARM7-AT91SAM7X-GCC/main.c | 8 +++++++- 3 files changed, 26 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 737752687..b5768f619 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -62,7 +62,7 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ +ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c ../../ports\ARM7-AT91SAM7X\GCC\sam7x_serial.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index aef835ffa..4231780bf 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -20,6 +20,7 @@ #include #include "board.h" +#include "sam7x_serial.h" #include "at91lib/aic.h" extern void FiqHandler(void); @@ -39,7 +40,6 @@ static void SYSIrqHandler(void) { chSysIRQEnterI(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { -// AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. chSysTimerHandlerI(); (void) AT91C_BASE_PITC->PITC_PIVR; } @@ -90,9 +90,9 @@ void hwinit(void) { /* * I/O setup, enable clocks, initially all pins are inputs with pullups. */ - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); - AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; - AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); + AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; + AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; /* * Default AIC setup, the device drivers will modify it as needed. @@ -110,30 +110,38 @@ void hwinit(void) { */ AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // Set to low. AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL; // Configure as output. - AT91C_BASE_SYS->PIOA_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. + AT91C_BASE_PIOA->PIO_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. AT91C_BASE_PIOA->PIO_SODR = PIOA_LCD_RESET; // Set to high. AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET; // Configure as output. - AT91C_BASE_SYS->PIOB_PPUDR = PIOA_LCD_RESET; // Disable internal pullup resistor. + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET; // Disable internal pullup resistor. /* * Joystick and buttons, disable pullups, already inputs. */ - AT91C_BASE_SYS->PIOA_PPUDR = PIOA_B1 | PIOA_B2 | PIOA_B3 | PIOA_B4 | PIOA_B5; - AT91C_BASE_SYS->PIOB_PPUDR = PIOB_SW1 | PIOB_SW2; + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1 | PIOA_B2 | PIOA_B3 | PIOA_B4 | PIOA_B5; + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1 | PIOB_SW2; /* * MMC/SD slot, disable pullups, already inputs. */ - AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP | PIOB_MMC_CP; + AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP | PIOB_MMC_CP; /* * PIT Initialization. */ AIC_ConfigureIT(AT91C_ID_SYS, - AT91C_AIC_SRCTYPE_POSITIVE_EDGE | (AT91C_AIC_PRIOR_HIGHEST -1), + AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), SYSIrqHandler); AIC_EnableIT(AT91C_ID_SYS); AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + + /* + * Serial driver initialization, RTS/CTS pins enabled for USART0 only. + */ + InitSerial(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; } diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 80eab874e..67031c421 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -20,6 +20,7 @@ #include #include "board.h" +#include "sam7x_serial.h" static WorkingArea(waThread1, 64); static t_msg Thread1(void *arg) { @@ -37,6 +38,7 @@ static t_msg Thread1(void *arg) { * Entry point, the interrupts are disabled on entry. */ int main(int argc, char **argv) { + t_msg TestThread(void *p); /* * The main() function becomes a thread here then the interrupts are @@ -47,7 +49,11 @@ int main(int argc, char **argv) { chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); while (TRUE) { - chThdSleep(1000); + chThdSleep(500); + if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) + chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW2)) + TestThread(&COM1); } return 0; -- cgit v1.2.3 From 05c3be1b2c214a8dd8dcb47c5a615fb1b6406719 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 21 Feb 2008 13:31:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@198 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 2 +- demos/ARM7-AT91SAM7X-GCC/readme.txt | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 4231780bf..3a5539587 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -40,8 +40,8 @@ static void SYSIrqHandler(void) { chSysIRQEnterI(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { - chSysTimerHandlerI(); (void) AT91C_BASE_PITC->PITC_PIVR; + chSysTimerHandlerI(); } chSysIRQExitI(); diff --git a/demos/ARM7-AT91SAM7X-GCC/readme.txt b/demos/ARM7-AT91SAM7X-GCC/readme.txt index 71f8ee51a..986d5ec7c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-GCC/readme.txt @@ -9,6 +9,8 @@ The demo runs on an Olimex SAM7-EX256 board. ** The Demo ** The demo currently just flashes the LCD background using a thread. +The button SW1 prints an "Hello World!" string on COM1, the button SW2 +activates che ChibiOS/RT test suite, output on COM1. ** Build Procedure ** -- cgit v1.2.3 From 9d95345fd750466563a0fd95a35ab20e425018b9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 21 Feb 2008 15:10:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@199 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 5 +- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 199 ++++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-GCC/board.c | 6 +- 3 files changed, 207 insertions(+), 3 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-GCC/Makefile.thumb (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index b5768f619..b419f525f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -62,13 +62,14 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c ../../ports\ARM7-AT91SAM7X\GCC\sam7x_serial.c \ +ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ + ../../ports/ARM7-AT91SAM7X/GCC/sam7x_serial.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ ../../src/lib/evtimer.c ../../test/test.c \ - at91lib\aic.c \ + at91lib/aic.c \ board.c main.c # List THUMB-mode C sources here diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb new file mode 100644 index 000000000..bb33297ca --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -0,0 +1,199 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +ASRC = + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ + ../../ports/ARM7-AT91SAM7X/GCC/sam7x_serial.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + at91lib/aic.c \ + board.c main.c + +# List ASM source files here +ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-AT91SAM7X/GCC + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +#OPT += -ffixed-r7 +OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -D THUMB_NO_INTERWORKING + LDFLAGS += -mthumb + ASFLAGS += -D THUMB_NO_INTERWORKING + endif +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 3a5539587..8d0851329 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -25,10 +25,14 @@ extern void FiqHandler(void); -__attribute__((interrupt("IRQ"))) +__attribute__((naked)) static void SpuriousHandler(void) { + chSysIRQEnterI(); + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)AT91C_BASE_AIC; + + chSysIRQExitI(); } /* -- cgit v1.2.3 From 58ab6d53dd54635ef8d53166234c192312bb6854 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 22 Feb 2008 10:53:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@201 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 6 ++++-- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 6 ++++-- demos/ARM7-AT91SAM7X-GCC/board.c | 3 ++- 3 files changed, 10 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index b419f525f..9c2006fe2 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -78,10 +78,11 @@ ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s +ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-AT91SAM7X/GCC +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X/GCC # List the user directory to look for the libraries here ULIBDIR = @@ -130,6 +131,7 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB case. CPFLAGS += -mthumb-interwork diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index bb33297ca..5dd2f33c6 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -78,10 +78,11 @@ TSRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s +ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-AT91SAM7X/GCC +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X/GCC # List the user directory to look for the libraries here ULIBDIR = @@ -130,6 +131,7 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB case. CPFLAGS += -mthumb-interwork diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 8d0851329..236e1100e 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -30,7 +30,7 @@ static void SpuriousHandler(void) { chSysIRQEnterI(); - AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)AT91C_BASE_AIC; + AT91C_BASE_AIC->AIC_EOICR = 0; chSysIRQExitI(); } @@ -47,6 +47,7 @@ static void SYSIrqHandler(void) { (void) AT91C_BASE_PITC->PITC_PIVR; chSysTimerHandlerI(); } + AT91C_BASE_AIC->AIC_EOICR = 0; \ chSysIRQExitI(); } -- cgit v1.2.3 From 0ea8e4c99fb2626c26136fc7260482b272f03d11 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 22 Feb 2008 11:09:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@202 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 8 ++++---- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 8 ++++---- demos/ARM7-LPC214x-GCC/Makefile | 14 ++++++++------ demos/ARM7-LPC214x-GCC/Makefile.thumb | 14 ++++++++------ 4 files changed, 24 insertions(+), 20 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 9c2006fe2..c94b88fdb 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -62,8 +62,8 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ - ../../ports/ARM7-AT91SAM7X/GCC/sam7x_serial.c \ +ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -78,11 +78,11 @@ ASRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s # List all user directories here UINCDIR = ../../src/include ../../src/lib \ - ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X/GCC + ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 5dd2f33c6..76a4459fd 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -67,8 +67,8 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ - ../../ports/ARM7-AT91SAM7X/GCC/sam7x_serial.c \ +TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -78,11 +78,11 @@ TSRC = ../../ports/ARM7-AT91SAM7X/GCC/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/GCC/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s # List all user directories here UINCDIR = ../../src/include ../../src/lib \ - ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X/GCC + ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 5e49defda..c7177b094 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -62,10 +62,10 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ +ASRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -79,10 +79,11 @@ ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here ULIBDIR = @@ -131,6 +132,7 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB case. CPFLAGS += -mthumb-interwork diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 89ccdfdc2..66d799ad9 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -67,10 +67,10 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/GCC/lpc214x_ssp.c \ +TSRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -79,10 +79,11 @@ TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ board.c buzzer.c mmcsd.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here ULIBDIR = @@ -131,6 +132,7 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB case. CPFLAGS += -mthumb-interwork -- cgit v1.2.3 From fe3c49452942316792f892479c6f3389f0c518a8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 22 Feb 2008 11:17:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@203 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 12 +++++++----- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 10 ++++++---- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/board.c | 2 ++ 5 files changed, 17 insertions(+), 11 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 1fe22d71a..d8ed9ed9b 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -62,8 +62,8 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c \ +ASRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -76,10 +76,11 @@ ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here ULIBDIR = @@ -128,6 +129,7 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB case. CPFLAGS += -mthumb-interwork @@ -155,7 +157,7 @@ $(AOBJS) : %.o : %.c $(TOBJS) : %.o : %.c @echo - $(CC) -c $(CPFLAGS) $(TOPT) -mthumb -I . $(INCDIR) $< -o $@ + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ $(ASMOBJS) : %.o : %.s @echo diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index b00adef75..621e71853 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -67,8 +67,8 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ - ../../ports/ARM7-LPC214x/GCC/vic.c \ +TSRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -76,10 +76,11 @@ TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here ULIBDIR = @@ -128,6 +129,7 @@ ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB case. CPFLAGS += -mthumb-interwork diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index c7177b094..5168f764a 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -79,7 +79,7 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here UINCDIR = ../../src/include ../../src/lib \ diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 66d799ad9..a8840a293 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -79,7 +79,7 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ board.c buzzer.c mmcsd.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here UINCDIR = ../../src/include ../../src/lib \ diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 23e642f01..94bc21336 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -37,6 +37,7 @@ static void IrqHandler(void) { chSysIRQEnterI(); /* nothing */ + VICVectAddr = 0; chSysIRQExitI(); } @@ -51,6 +52,7 @@ static void T0IrqHandler(void) { T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); + VICVectAddr = 0; chSysIRQExitI(); } -- cgit v1.2.3 From 1d8c29c017b98aa823230ce49e9dbae2911b1e02 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 27 Feb 2008 15:36:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@206 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/Makefile | 640 +++++++++++++++++++++++++++++++++++++++ demos/AVR-ATmega128-GCC/board.c | 81 +++++ demos/AVR-ATmega128-GCC/board.h | 89 ++++++ demos/AVR-ATmega128-GCC/chconf.h | 169 +++++++++++ demos/AVR-ATmega128-GCC/main.c | 54 ++++ 5 files changed, 1033 insertions(+) create mode 100644 demos/AVR-ATmega128-GCC/Makefile create mode 100644 demos/AVR-ATmega128-GCC/board.c create mode 100644 demos/AVR-ATmega128-GCC/board.h create mode 100644 demos/AVR-ATmega128-GCC/chconf.h create mode 100644 demos/AVR-ATmega128-GCC/main.c (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile new file mode 100644 index 000000000..42104bc7a --- /dev/null +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -0,0 +1,640 @@ +# Hey Emacs, this is a -*- makefile -*- +#---------------------------------------------------------------------------- +# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al. +# +# Released to the Public Domain +# +# Additional material for this makefile was written by: +# Peter Fleury +# Tim Henigan +# Colin O'Flynn +# Reiner Patommel +# Markus Pfaff +# Sander Pool +# Frederik Rouleau +# Carlos Lamas +# +#---------------------------------------------------------------------------- +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make coff = Convert ELF to AVR COFF. +# +# make extcoff = Convert ELF to AVR Extended COFF. +# +# make program = Download the hex file to the device, using avrdude. +# Please customize the avrdude settings below first! +# +# make debug = Start either simulavr or avarice as specified for debugging, +# with avr-gdb or avr-insight as the front end for debugging. +# +# make filename.s = Just compile filename.c into the assembler code only. +# +# make filename.i = Create a preprocessed source file for use in submitting +# bug reports to the GCC project. +# +# To rebuild project do "make clean" then "make all". +#---------------------------------------------------------------------------- + + +# MCU name +MCU = atmega128 + + +# Processor frequency. +# This will define a symbol, F_CPU, in all source code files equal to the +# processor frequency. You can then use this symbol in your source code to +# calculate timings. Do NOT tack on a 'UL' at the end, this will be done +# automatically to create a 32-bit value in your source code. +# Typical values are: +# F_CPU = 1000000 +# F_CPU = 1843200 +# F_CPU = 2000000 +# F_CPU = 3686400 +# F_CPU = 4000000 +# F_CPU = 7372800 +# F_CPU = 8000000 +# F_CPU = 11059200 +# F_CPU = 14745600 +# F_CPU = 16000000 +# F_CPU = 18432000 +# F_CPU = 20000000 +F_CPU = 16000000 + + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + + +# Target file name (without extension). +TARGET = ch + + +# Object files directory +# To put object files in current directory, use a dot (.), do NOT make +# this an empty or blank macro! +OBJDIR = . + + +# List C source files here. (C dependencies are automatically generated.) +SRC = ../../ports/AVR/chcore.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + board.c main.c + + + +# List C++ source files here. (C dependencies are automatically generated.) +CPPSRC = + + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = s + + +# Debugging format. +# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs. +# AVR Studio 4.10 requires dwarf-2. +# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run. +DEBUG = dwarf-2 + + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRAINCDIRS = ../../src/include ../../src/lib ../../ports/AVR + + +# Compiler flag to set the C Standard level. +# c89 = "ANSI" C +# gnu89 = c89 plus GCC extensions +# c99 = ISO C99 standard (not yet fully implemented) +# gnu99 = c99 plus GCC extensions +CSTANDARD = -std=gnu99 + + +# Place -D or -U options here for C sources +CDEFS = -DF_CPU=$(F_CPU)UL + + +# Place -D or -U options here for ASM sources +ADEFS = -DF_CPU=$(F_CPU) + + +# Place -D or -U options here for C++ sources +CPPDEFS = -DF_CPU=$(F_CPU)UL +#CPPDEFS += -D__STDC_LIMIT_MACROS +#CPPDEFS += -D__STDC_CONSTANT_MACROS + + + +#---------------- Compiler Options C ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) +CFLAGS += -O$(OPT) +CFLAGS += -funsigned-char +CFLAGS += -funsigned-bitfields +CFLAGS += -fpack-struct +CFLAGS += -fshort-enums +CFLAGS += -fno-strict-aliasing +CFLAGS += -Wall +CFLAGS += -Wstrict-prototypes +#CFLAGS += -mshort-calls +#CFLAGS += -fno-unit-at-a-time +#CFLAGS += -Wundef +#CFLAGS += -Wunreachable-code +#CFLAGS += -Wsign-compare +CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +CFLAGS += $(CSTANDARD) + + +#---------------- Compiler Options C++ ---------------- +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +CPPFLAGS = -g$(DEBUG) +CPPFLAGS += $(CPPDEFS) +CPPFLAGS += -O$(OPT) +CPPFLAGS += -funsigned-char +CPPFLAGS += -funsigned-bitfields +CPPFLAGS += -fpack-struct +CPPFLAGS += -fshort-enums +CPPFLAGS += -fno-exceptions +CPPFLAGS += -Wall +CFLAGS += -Wundef +#CPPFLAGS += -mshort-calls +#CPPFLAGS += -fno-unit-at-a-time +#CPPFLAGS += -Wstrict-prototypes +#CPPFLAGS += -Wunreachable-code +#CPPFLAGS += -Wsign-compare +CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst) +CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) +#CPPFLAGS += $(CSTANDARD) + + +#---------------- Assembler Options ---------------- +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +# -listing-cont-lines: Sets the maximum number of continuation lines of hex +# dump that will be displayed for a given single line of source input. +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100 + + +#---------------- Library Options ---------------- +# Minimalistic printf version +PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min + +# Floating point printf version (requires MATH_LIB = -lm below) +PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt + +# If this is left blank, then it will use the Standard printf version. +PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_MIN) +#PRINTF_LIB = $(PRINTF_LIB_FLOAT) + + +# Minimalistic scanf version +SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min + +# Floating point + %[ scanf version (requires MATH_LIB = -lm below) +SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt + +# If this is left blank, then it will use the Standard scanf version. +SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_MIN) +#SCANF_LIB = $(SCANF_LIB_FLOAT) + + +MATH_LIB = -lm + + +# List any extra directories to look for libraries here. +# Each directory must be seperated by a space. +# Use forward slashes for directory separators. +# For a directory that has spaces, enclose it in quotes. +EXTRALIBDIRS = + + + +#---------------- External Memory Options ---------------- + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# used for variables (.data/.bss) and heap (malloc()). +#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff + +# 64 KB of external RAM, starting after internal RAM (ATmega128!), +# only used for heap (malloc()). +#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff + +EXTMEMOPTS = + + + +#---------------- Linker Options ---------------- +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += $(EXTMEMOPTS) +LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS)) +LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB) +#LDFLAGS += -T linker_script.x + + + +#---------------- Programming Options (avrdude) ---------------- + +# Programming hardware: alf avr910 avrisp bascom bsd +# dt006 pavr picoweb pony-stk200 sp12 stk200 stk500 +# +# Type: avrdude -c ? +# to get a full listing. +# +AVRDUDE_PROGRAMMER = stk500 + +# com1 = serial port. Use lpt1 to connect to parallel port. +AVRDUDE_PORT = com1 # programmer connected to serial device + +AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex +#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep + + +# Uncomment the following if you want avrdude's erase cycle counter. +# Note that this counter needs to be initialized first using -Yn, +# see avrdude manual. +#AVRDUDE_ERASE_COUNTER = -y + +# Uncomment the following if you do /not/ wish a verification to be +# performed after programming the device. +#AVRDUDE_NO_VERIFY = -V + +# Increase verbosity level. Please use this when submitting bug +# reports about avrdude. See +# to submit bug reports. +#AVRDUDE_VERBOSE = -v -v + +AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER) +AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY) +AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE) +AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER) + + + +#---------------- Debugging Options ---------------- + +# For simulavr only - target MCU frequency. +DEBUG_MFREQ = $(F_CPU) + +# Set the DEBUG_UI to either gdb or insight. +# DEBUG_UI = gdb +DEBUG_UI = insight + +# Set the debugging back-end to either avarice, simulavr. +DEBUG_BACKEND = avarice +#DEBUG_BACKEND = simulavr + +# GDB Init Filename. +GDBINIT_FILE = __avr_gdbinit + +# When using avarice settings for the JTAG +JTAG_DEV = /dev/com1 + +# Debugging port used to communicate between GDB / avarice / simulavr. +DEBUG_PORT = 4242 + +# Debugging host used to communicate between GDB / avarice / simulavr, normally +# just set to localhost unless doing some sort of crazy debugging when +# avarice is running on a different computer. +DEBUG_HOST = localhost + + + +#============================================================================ + + +# Define programs and commands. +SHELL = sh +CC = avr-gcc +OBJCOPY = avr-objcopy +OBJDUMP = avr-objdump +SIZE = avr-size +AR = avr-ar rcs +NM = avr-nm +AVRDUDE = avrdude +REMOVE = rm -f +REMOVEDIR = rm -rf +COPY = cp +WINSHELL = cmd + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_COFF = Converting to AVR COFF: +MSG_EXTENDED_COFF = Converting to AVR Extended COFF: +MSG_FLASH = Creating load file for Flash: +MSG_EEPROM = Creating load file for EEPROM: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_CPP = Compiling C++: +MSG_ASSEMBLING = Assembling: +MSG_CLEANING = Cleaning project: +MSG_CREATING_LIBRARY = Creating library: + + + + +# Define all object files. +OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o) + +# Define all listing files. +LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst) + + +# Compiler flags to generate dependency files. +GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d + + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) + + + + + +# Default target. +all: begin gccversion sizebefore build sizeafter end + +# Change the build target to build a HEX file or a library. +build: elf hex bin eep lss sym +#build: lib + + +elf: $(TARGET).elf +hex: $(TARGET).hex +bin: $(TARGET).bin +eep: $(TARGET).eep +lss: $(TARGET).lss +sym: $(TARGET).sym +LIBNAME=lib$(TARGET).a +lib: $(LIBNAME) + + + +# Eye candy. +# AVR Studio 3.x does not check make's exit code but relies on +# the following magic strings to be generated by the compile job. +begin: + @echo + @echo $(MSG_BEGIN) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf + +sizebefore: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \ + 2>/dev/null; echo; fi + +sizeafter: + @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \ + 2>/dev/null; echo; fi + + + +# Display compiler version information. +gccversion : + @$(CC) --version + + + +# Program the device. +program: $(TARGET).hex $(TARGET).eep + $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM) + + +# Generate avr-gdb config/init file which does the following: +# define the reset signal, load the target file, connect to target, and set +# a breakpoint at main(). +gdb-config: + @$(REMOVE) $(GDBINIT_FILE) + @echo define reset >> $(GDBINIT_FILE) + @echo SIGNAL SIGHUP >> $(GDBINIT_FILE) + @echo end >> $(GDBINIT_FILE) + @echo file $(TARGET).elf >> $(GDBINIT_FILE) + @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE) +ifeq ($(DEBUG_BACKEND),simulavr) + @echo load >> $(GDBINIT_FILE) +endif + @echo break main >> $(GDBINIT_FILE) + +debug: gdb-config $(TARGET).elf +ifeq ($(DEBUG_BACKEND), avarice) + @echo Starting AVaRICE - Press enter when "waiting to connect" message displays. + @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \ + $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT) + @$(WINSHELL) /c pause + +else + @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \ + $(DEBUG_MFREQ) --port $(DEBUG_PORT) +endif + @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE) + + + + +# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB. +COFFCONVERT = $(OBJCOPY) --debugging +COFFCONVERT += --change-section-address .data-0x800000 +COFFCONVERT += --change-section-address .bss-0x800000 +COFFCONVERT += --change-section-address .noinit-0x800000 +COFFCONVERT += --change-section-address .eeprom-0x810000 + + + +coff: $(TARGET).elf + @echo + @echo $(MSG_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-avr $< $(TARGET).cof + + +extcoff: $(TARGET).elf + @echo + @echo $(MSG_EXTENDED_COFF) $(TARGET).cof + $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof + + + +# Create final output files (.hex, .eep) from ELF output file. +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ + +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary -R .eeprom $< $@ + +%.eep: %.elf + @echo + @echo $(MSG_EEPROM) $@ + -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \ + --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0 + +# Create extended listing file from ELF output file. +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S $< > $@ + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + + +# Create library from object files. +.SECONDARY : $(TARGET).a +.PRECIOUS : $(OBJ) +%.a: $(OBJ) + @echo + @echo $(MSG_CREATING_LIBRARY) $@ + $(AR) $@ $(OBJ) + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(OBJ) +%.elf: $(OBJ) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS) + + +# Compile: create object files from C source files. +$(OBJDIR)/%.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(ALL_CFLAGS) $< -o $@ + + +# Compile: create object files from C++ source files. +$(OBJDIR)/%.o : %.cpp + @echo + @echo $(MSG_COMPILING_CPP) $< + $(CC) -c $(ALL_CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. +%.s : %.c + $(CC) -S $(ALL_CFLAGS) $< -o $@ + + +# Compile: create assembler files from C++ source files. +%.s : %.cpp + $(CC) -S $(ALL_CPPFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. +$(OBJDIR)/%.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Create preprocessed source for use in sending a bug report. +%.i : %.c + $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list end + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin + $(REMOVE) $(TARGET).eep + $(REMOVE) $(TARGET).cof + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lss + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) + $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRC:.c=.i) + $(REMOVEDIR) .dep + + +# Create object files directory +$(shell mkdir $(OBJDIR) 2>/dev/null) + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex bin eep lss sym coff extcoff \ +clean clean_list program debug gdb-config + + + + + + diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c new file mode 100644 index 000000000..b0907d6c4 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/board.c @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include +#include + +#include "board.h" + +ISR(TIMER0_OVF_vect) { + + chSysIRQEnterI(); + + chSysTimerHandlerI(); + + chSysIRQExitI(); +} + +/* + * Board initialization code. + */ +void hwinit(void) { + + /* + * I/O ports setup. + */ + DDRA = VAL_DDRA; + PORTA = VAL_PORTA; + DDRB = VAL_DDRB; + PORTB = VAL_PORTB; + DDRC = VAL_DDRC; + PORTC = VAL_PORTC; + DDRD = VAL_DDRD; + PORTD = VAL_PORTD; + DDRE = VAL_DDRE; + PORTE = VAL_PORTE; + DDRF = VAL_DDRF; + PORTF = VAL_PORTF; + DDRG = VAL_DDRG; + PORTG = VAL_PORTG; + + /* + * External interrupts setup, all disabled initially. + */ + EICRA = 0x00; + EICRB = 0x00; + EIMSK = 0x00; + + /* + * Enables Idle mode for SLEEP instruction. + */ + MCUCR = (1 << SE); + + /* + * Timer 0 setup. + */ + TCCR0 = (1 << WGM01) | (0 << WGM00) | // CTC mode. + (0 << COM01) | (0 << COM00) | // OC0A disabled (normal I/O). + (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. + OCR0 = F_CPU / 64 / CH_FREQUENCY - 1; + TCNT0 = 0; // Reset counter. + TIFR = (1 << OCF0); // Reset pending (if any). + TIMSK = (1 << OCIE0); // Interrupt on compare. +} diff --git a/demos/AVR-ATmega128-GCC/board.h b/demos/AVR-ATmega128-GCC/board.h new file mode 100644 index 000000000..ee0e9b624 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/board.h @@ -0,0 +1,89 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define BOARD_OLIMEX_AVR_MT_128 + +/* PA7 RLY DS B5 B4 B3 B2 B1 + * IN OUT IN IN IN IN IN IN + * DDRA 0 1 0 0 0 0 0 0 + * PU VAL HiZ HiZ HiZ HiZ HiZ HiZ + * PORTA 1 0 0 0 0 0 0 0 + */ +#define VAL_DDRA 0x40 +#define VAL_PORTA 0x80 + +/* + * All inputs with pullups. + */ +#define VAL_DDRB 0x00 +#define VAL_PORTB 0xFF + +/* D7 D6 D5 D4 PC3 E R/W RS + * IN IN IN IN IN OUT OUT OUT + * DDRC 0 0 0 0 0 1 1 1 + * PU PU PU PU PU VAL VAL VAL + * PORTC 1 1 1 1 1 0 0 0 + */ +#define VAL_DDRC 0x03 +#define VAL_PORTC 0xF8 + +/* PD7 PD6 PD5 PD4 TXD RXD PD1 PD0 + * IN IN IN IN OUT IN IN IN + * DDRD 0 0 0 0 1 0 0 0 + * PU PU PU PU VAL HiZ HiZ HiZ + * PORTD 1 1 1 1 1 0 0 0 + */ +#define VAL_DDRD 0x08 +#define VAL_PORTD 0xF8 + +/* PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0 + * IN IN OUT OUT IN IN OUT IN + * DDRE 0 0 1 1 0 0 1 0 + * PU PU VAL VAL PU PU VAL PU + * PORTE 1 1 1 1 1 1 1 1 + */ +#define VAL_DDRE 0x32 +#define VAL_PORTE 0xFF + +/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 + * x x x x IN IN IN IN + * DDRF 0 0 0 0 0 0 0 0 + * PU PU PU PU PU PU PU PU + * PORTF 1 1 1 1 1 1 1 1 + * + */ +#define VAL_DDRF 0x00 +#define VAL_PORTF 0xFF + +/* x x x x x PG2 PG1 PG0 + * x x x x x IN IN IN + * DDRG 0 0 0 0 0 0 0 0 + * x x x x x PU PU PU + * PORTG 0 0 0 0 0 1 1 1 + * + */ +#define VAL_DDRG 0x00 +#define VAL_PORTG 0x07 + +void hwinit(void); + +#endif /* _BOARD_H_ */ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h new file mode 100644 index 000000000..c8817f85c --- /dev/null +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +//#define CH_USE_MESSAGES_PRIORITY + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c new file mode 100644 index 000000000..14c45cf47 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/main.c @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include + +void hwinit(void); + +static WorkingArea(waThread1, 32); +static t_msg Thread1(void *arg) { + + while (TRUE) { + chThdSleep(800); + } + return 0; +} + +int main(int argc, char **argv) { + + hwinit(); + + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ + chSysInit(); + + /* + * Starts the LED blinker thread. + */ + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + + while(TRUE) + /* Do stuff*/ ; + + return 0; +} -- cgit v1.2.3 From 64e798c8cd4ae5e6ce18290f8452099ec90ebd14 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 27 Feb 2008 15:53:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@207 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index c8817f85c..17c2c3d38 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -152,7 +152,7 @@ * ChibiOS/RT code must be recompiled with the GCC option \p * -ffixed-. */ -//#define CH_CURRP_REGISTER_CACHE "r7" +//#define CH_CURRP_REGISTER_CACHE "r8" /** Configuration option: Includes basic debug support to the kernel. * @note the debug support is port-dependent, it may be not present on some -- cgit v1.2.3 From 4ea04cc357408d68750e5b4a9d834c5a5d015fa7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 29 Feb 2008 14:55:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@208 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/Makefile | 3 +-- demos/AVR-ATmega128-GCC/board.c | 4 ++-- demos/AVR-ATmega128-GCC/board.h | 19 +++++++++++++++++++ demos/AVR-ATmega128-GCC/main.c | 7 +++++-- 4 files changed, 27 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index 42104bc7a..dea57ee61 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -85,11 +85,10 @@ SRC = ../../ports/AVR/chcore.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ../../src/lib/evtimer.c \ board.c main.c - # List C++ source files here. (C dependencies are automatically generated.) CPPSRC = diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index b0907d6c4..6ac43a218 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -24,7 +24,7 @@ #include "board.h" -ISR(TIMER0_OVF_vect) { +ISR(TIMER0_COMP_vect) { chSysIRQEnterI(); @@ -73,7 +73,7 @@ void hwinit(void) { */ TCCR0 = (1 << WGM01) | (0 << WGM00) | // CTC mode. (0 << COM01) | (0 << COM00) | // OC0A disabled (normal I/O). - (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. + (1 << CS02) | (0 << CS01) | (0 << CS00); // CLK/64 clock source. OCR0 = F_CPU / 64 / CH_FREQUENCY - 1; TCNT0 = 0; // Reset counter. TIFR = (1 << OCF0); // Reset pending (if any). diff --git a/demos/AVR-ATmega128-GCC/board.h b/demos/AVR-ATmega128-GCC/board.h index ee0e9b624..a29ee8664 100644 --- a/demos/AVR-ATmega128-GCC/board.h +++ b/demos/AVR-ATmega128-GCC/board.h @@ -84,6 +84,25 @@ #define VAL_DDRG 0x00 #define VAL_PORTG 0x07 +#define PORTA_BUTTON1 (1 << 0) +#define PORTA_BUTTON2 (1 << 1) +#define PORTA_BUTTON3 (1 << 2) +#define PORTA_BUTTON4 (1 << 3) +#define PORTA_BUTTON5 (1 << 4) +#define PORTA_DALLAS (1 << 5) +#define PORTA_RELAY (1 << 6) + +#define PORTC_44780_RS (1 << 0) +#define PORTC_44780_RW (1 << 1) +#define PORTC_44780_E (1 << 2) +#define PORTC_44780_D4 (1 << 4) +#define PORTC_44780_D5 (1 << 5) +#define PORTC_44780_D6 (1 << 6) +#define PORTC_44780_D7 (1 << 7) + +#define PORTE_BUZZ1 (1 << 4) +#define PORTE_BUZZ2 (1 << 5) + void hwinit(void); #endif /* _BOARD_H_ */ diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 14c45cf47..b5103521e 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -21,13 +21,16 @@ #include +#include "board.h" + void hwinit(void); static WorkingArea(waThread1, 32); static t_msg Thread1(void *arg) { while (TRUE) { - chThdSleep(800); + PORTA ^= PORTA_RELAY; + chThdSleep(1000); } return 0; } @@ -48,7 +51,7 @@ int main(int argc, char **argv) { chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); while(TRUE) - /* Do stuff*/ ; + chThdSleep(1000); return 0; } -- cgit v1.2.3 From 2680f87b476671ef8af6314bfbf115b31daf0f50 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 29 Feb 2008 15:02:45 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@209 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/readme.txt | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 demos/AVR-ATmega128-GCC/readme.txt (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/readme.txt b/demos/AVR-ATmega128-GCC/readme.txt new file mode 100644 index 000000000..b580dbc6e --- /dev/null +++ b/demos/AVR-ATmega128-GCC/readme.txt @@ -0,0 +1,23 @@ +***************************************************************************** +** ChibiOS/RT port for Atmel AVRmega128. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex AVR-MT-128 board. + +** The Demo ** + +The demo currently just toggles the relay using a thread. It will be expanded +in next releases. + +** Build Procedure ** + +The demo was built using the WinAVR toolchain. + +** Notes ** + +The demo requires include files from WinAVR that are not part of the ChibiOS/RT +distribution, please install WinAVR. + + http://winavr.sourceforge.net/ -- cgit v1.2.3 From ec0a917ae1bef32f1848161e759ef98542327523 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 3 Mar 2008 15:52:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@212 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/main.c | 2 +- demos/ARM7-LPC214x-GCC/main.c | 4 +-- demos/ARM7-LPC214x-GCC/mmcsd.c | 54 ++++++++++++++++++++--------------------- demos/ARM7-LPC214x-GCC/mmcsd.h | 20 +++++++-------- 4 files changed, 40 insertions(+), 40 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 67031c421..f2a3f3737 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -51,7 +51,7 @@ int main(int argc, char **argv) { while (TRUE) { chThdSleep(500); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) - chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW2)) TestThread(&COM1); } diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index dbc56803e..fe0b9342c 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -73,7 +73,7 @@ static void TimerHandler(t_eventid id) { if (!(IO0PIN & 0x00008000)) // Button 1 PlaySound(1000, 100); if (!(IO0PIN & 0x00010000)) { // Button 2 - chFDDWrite(&COM1, (BYTE8 *)"Hello World!\r\n", 14); + chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); PlaySound(2000, 100); } } @@ -84,7 +84,7 @@ static void TimerHandler(t_eventid id) { * driver and reads a sector. */ static void InsertHandler(t_eventid id) { - static BYTE8 rwbuf[512]; + static uint8_t rwbuf[512]; MMCCSD data; PlaySoundWait(1000, 100); diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 8723d8d96..febfca237 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -91,14 +91,14 @@ void mmcStopPolling(void) { /* * Returns TRUE if the card is safely inserted in the reader. */ -BOOL mmcCardInserted (void) { +t_bool mmcCardInserted (void) { return cnt == 0; } static void wait(void) { int i; - BYTE8 buf[4]; + uint8_t buf[4]; for (i = 0; i < 16; i++) { sspRW(buf, NULL, 1); @@ -116,8 +116,8 @@ static void wait(void) { } } -static void sendhdr(BYTE8 cmd, ULONG32 arg) { - BYTE8 buf[6]; +static void sendhdr(uint8_t cmd, uint32_t arg) { + uint8_t buf[6]; /* * Wait for the bus to become idle if a write operation was in progress. @@ -133,9 +133,9 @@ static void sendhdr(BYTE8 cmd, ULONG32 arg) { sspRW(NULL, buf, 6); } -static BYTE8 recvr1(void) { +static uint8_t recvr1(void) { int i; - BYTE8 r1[1]; + uint8_t r1[1]; for (i = 0; i < 9; i++) { sspRW(r1, NULL, 1); @@ -145,7 +145,7 @@ static BYTE8 recvr1(void) { return 0xFF; /* Timeout.*/ } -static BOOL getdata(BYTE8 *buf, ULONG32 n) { +static t_bool getdata(uint8_t *buf, uint32_t n) { int i; for (i = 0; i < MMC_WAIT_DATA; i++) { @@ -162,7 +162,7 @@ static BOOL getdata(BYTE8 *buf, ULONG32 n) { /* * Initializes a card after the power up by selecting the SPI mode. */ -BOOL mmcInit(void) { +t_bool mmcInit(void) { /* * Starting initialization with slow clock mode. @@ -187,7 +187,7 @@ BOOL mmcInit(void) { */ i = 0; while (TRUE) { - BYTE8 b = mmcSendCommand(CMDINIT, 0); + uint8_t b = mmcSendCommand(CMDINIT, 0); if (b == 0x00) break; if (b != 0x01) @@ -207,8 +207,8 @@ BOOL mmcInit(void) { /* * Sends a simple command and returns a R1-type response. */ -BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg) { - BYTE8 r1; +uint8_t mmcSendCommand(uint8_t cmd, uint32_t arg) { + uint8_t r1; sspAcquireBus(); sendhdr(cmd, arg); @@ -222,8 +222,8 @@ BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg) { * @param data the pointer to a \p MMCCSD structure * @return \p TRUE if an error happened */ -BOOL mmcGetSize(MMCCSD *data) { - BYTE8 buf[16]; +t_bool mmcGetSize(MMCCSD *data) { + uint8_t buf[16]; sspAcquireBus(); sendhdr(CMDREADCSD, 0); @@ -250,7 +250,7 @@ BOOL mmcGetSize(MMCCSD *data) { * @param buf the pointer to the read buffer * @return \p TRUE if an error happened */ -BOOL mmcRead(BYTE8 *buf, ULONG32 blknum) { +t_bool mmcRead(uint8_t *buf, uint32_t blknum) { sspAcquireBus(); sendhdr(CMDREAD, blknum << 8); @@ -273,8 +273,8 @@ BOOL mmcRead(BYTE8 *buf, ULONG32 blknum) { * @param buf the pointer to the read buffer * @return \p TRUE if an error happened */ -BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { - static const BYTE8 stopcmd[] = {0x40 | CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; +t_bool mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { + static const uint8_t stopcmd[] = {0x40 | CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; sspAcquireBus(); sendhdr(CMDREADMULTIPLE, blknum << 8); @@ -290,7 +290,7 @@ BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { buf += 512; n--; } - sspRW(NULL, (BYTE8 *)stopcmd, sizeof(stopcmd)); + sspRW(NULL, (uint8_t *)stopcmd, sizeof(stopcmd)); if (recvr1() != 0x00) { sspReleaseBus(); return TRUE; @@ -309,9 +309,9 @@ BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { * the card, this allows to not make useless busy waiting. The invoking * thread can do other things while the data is being written. */ -BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum) { - static const BYTE8 start[] = {0xFF, 0xFE}; - BYTE8 b[4]; +t_bool mmcWrite(uint8_t *buf, uint32_t blknum) { + static const uint8_t start[] = {0xFF, 0xFE}; + uint8_t b[4]; sspAcquireBus(); sendhdr(CMDWRITE, blknum << 8); @@ -319,7 +319,7 @@ BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum) { sspReleaseBus(); return TRUE; } - sspRW(NULL, (BYTE8 *)start, 2); /* Data prologue.*/ + sspRW(NULL, (uint8_t *)start, 2); /* Data prologue.*/ sspRW(NULL, buf, 512); /* Data.*/ sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ sspRW(b, NULL, 1); @@ -340,10 +340,10 @@ BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum) { * the card, this allows to not make useless busy waiting. The invoking * thread can do other things while the data is being written. */ -BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { - static const BYTE8 start[] = {0xFF, 0xFC}, +t_bool mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { + static const uint8_t start[] = {0xFF, 0xFC}, stop[] = {0xFD, 0xFF}; - BYTE8 b[4]; + uint8_t b[4]; sspAcquireBus(); sendhdr(CMDWRITEMULTIPLE, blknum << 8); @@ -352,7 +352,7 @@ BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { return TRUE; } while (n) { - sspRW(NULL, (BYTE8 *)start, sizeof(start)); /* Data prologue.*/ + sspRW(NULL, (uint8_t *)start, sizeof(start)); /* Data prologue.*/ sspRW(NULL, buf, 512); /* Data.*/ sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ sspRW(b, NULL, 1); @@ -364,7 +364,7 @@ BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { buf += 512; n--; } - sspRW(NULL, (BYTE8 *)stop, sizeof(stop)); /* Stops the transfer.*/ + sspRW(NULL, (uint8_t *)stop, sizeof(stop)); /* Stops the transfer.*/ sspReleaseBus(); return FALSE; } @@ -373,7 +373,7 @@ BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n) { * Makes sure that pending operations are completed before returning. */ void mmcSynch(void) { - BYTE8 buf[4]; + uint8_t buf[4]; sspAcquireBus(); while (TRUE) { diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index b5f0ea57c..60396dafb 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -37,8 +37,8 @@ #define CMDWRITEMULTIPLE 25 typedef struct { - ULONG32 csize; - ULONG32 rdblklen; + uint32_t csize; + uint32_t rdblklen; } MMCCSD; extern EventSource MMCInsertEventSource, MMCRemoveEventSource; @@ -48,16 +48,16 @@ extern EventSource MMCInsertEventSource, MMCRemoveEventSource; #endif void InitMMC(void); - BOOL mmcInit(void); + t_bool mmcInit(void); void mmcStartPolling(void); void mmcStopPolling(void); - BOOL mmcCardInserted (void); - BYTE8 mmcSendCommand(BYTE8 cmd, ULONG32 arg); - BOOL mmcGetSize(MMCCSD *data); - BOOL mmcRead(BYTE8 *buf, ULONG32 blknum); - BOOL mmcReadMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); - BOOL mmcWrite(BYTE8 *buf, ULONG32 blknum); - BOOL mmcWriteMultiple(BYTE8 *buf, ULONG32 blknum, ULONG32 n); + t_bool mmcCardInserted (void); + uint8_t mmcSendCommand(uint8_t cmd, uint32_t arg); + t_bool mmcGetSize(MMCCSD *data); + t_bool mmcRead(uint8_t *buf, uint32_t blknum); + t_bool mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); + t_bool mmcWrite(uint8_t *buf, uint32_t blknum); + t_bool mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); void mmcSynch(void); #ifdef __cplusplus } -- cgit v1.2.3 From 99ac65be2ac3d59a4de3b5adaa4dd9adeb80c1e2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 Mar 2008 10:33:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@213 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MSVS/ch.sln | 21 ---- demos/Win32-MSVS/ch.vcproj | 267 ---------------------------------------- demos/Win32-MSVS/chconf.h | 174 -------------------------- demos/Win32-MSVS/chcore.c | 115 ----------------- demos/Win32-MSVS/chcore.h | 82 ------------- demos/Win32-MSVS/chtypes.h | 47 ------- demos/Win32-MSVS/demo.c | 292 -------------------------------------------- demos/Win32-MSVS/readme.txt | 22 ---- demos/Win32-MinGW/chcore.h | 4 +- demos/Win32-MinGW/chtypes.h | 36 +++--- demos/Win32-MinGW/demo.c | 16 +-- 11 files changed, 25 insertions(+), 1051 deletions(-) delete mode 100644 demos/Win32-MSVS/ch.sln delete mode 100644 demos/Win32-MSVS/ch.vcproj delete mode 100644 demos/Win32-MSVS/chconf.h delete mode 100644 demos/Win32-MSVS/chcore.c delete mode 100644 demos/Win32-MSVS/chcore.h delete mode 100644 demos/Win32-MSVS/chtypes.h delete mode 100644 demos/Win32-MSVS/demo.c delete mode 100644 demos/Win32-MSVS/readme.txt (limited to 'demos') diff --git a/demos/Win32-MSVS/ch.sln b/demos/Win32-MSVS/ch.sln deleted file mode 100644 index cb9406206..000000000 --- a/demos/Win32-MSVS/ch.sln +++ /dev/null @@ -1,21 +0,0 @@ -Microsoft Visual Studio Solution File, Format Version 8.00 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ch", "ch.vcproj", "{0A528619-7F3F-4459-AAC5-DE8BA570D51D}" - ProjectSection(ProjectDependencies) = postProject - EndProjectSection -EndProject -Global - GlobalSection(SolutionConfiguration) = preSolution - Debug = Debug - Release = Release - EndGlobalSection - GlobalSection(ProjectConfiguration) = postSolution - {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Debug.ActiveCfg = Debug|Win32 - {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Debug.Build.0 = Debug|Win32 - {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Release.ActiveCfg = Release|Win32 - {0A528619-7F3F-4459-AAC5-DE8BA570D51D}.Release.Build.0 = Release|Win32 - EndGlobalSection - GlobalSection(ExtensibilityGlobals) = postSolution - EndGlobalSection - GlobalSection(ExtensibilityAddIns) = postSolution - EndGlobalSection -EndGlobal diff --git a/demos/Win32-MSVS/ch.vcproj b/demos/Win32-MSVS/ch.vcproj deleted file mode 100644 index 0b27e2ffb..000000000 --- a/demos/Win32-MSVS/ch.vcproj +++ /dev/null @@ -1,267 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/demos/Win32-MSVS/chconf.h b/demos/Win32-MSVS/chconf.h deleted file mode 100644 index 075f829d3..000000000 --- a/demos/Win32-MSVS/chconf.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Configuration file for Visual Studio 7 demo project. - */ - -/** - * @addtogroup Config - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/* - * NOTE: this is just documentation for doxigen, the real configuration file - * is the one into the project directories. - */ - -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 - -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ -#define CH_TIME_QUANTUM 20 - -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-\. - */ -//#define CH_CURRP_REGISTER_CACHE "reg" - -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. - */ -//#define CH_USE_DEBUG - -/** Debug option: Includes the threads context switch tracing feature. - */ -//#define CH_USE_TRACE - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/Win32-MSVS/chcore.c b/demos/Win32-MSVS/chcore.c deleted file mode 100644 index facdea31c..000000000 --- a/demos/Win32-MSVS/chcore.c +++ /dev/null @@ -1,115 +0,0 @@ -#include -#include - -#undef CDECL - -#include - -static LARGE_INTEGER nextcnt; -static LARGE_INTEGER slice; - -void InitSimCom1(void); -void InitSimCom2(void); -BOOL Com1ConnInterruptSimCom(void); -BOOL Com2ConnInterruptSimCom(void); -BOOL Com1InInterruptSimCom(void); -BOOL Com2InInterruptSimCom(void); -BOOL Com1OutInterruptSimCom(void); -BOOL Com2OutInterruptSimCom(void); - -/* - * Simulated HW initialization. - */ -void InitCore(void) { - WSADATA wsaData; - - // Initialization. - if (WSAStartup(2, &wsaData) != 0) { - printf("Unable to locate a winsock DLL\n"); - exit(1); - } - - printf("Win32 ChibiOS/RT simulator\n\n"); - printf("Thread structure %d bytes\n", sizeof(Thread)); - if (!QueryPerformanceFrequency(&slice)) { - printf("QueryPerformanceFrequency() error"); - exit(1); - } - printf("Core Frequency %u Hz\n", slice.LowPart); - slice.QuadPart /= CH_FREQUENCY; - QueryPerformanceCounter(&nextcnt); - nextcnt.QuadPart += slice.QuadPart; - - InitSimCom1(); - InitSimCom2(); -} - -/* - * Interrupt simulation. - */ -void ChkIntSources(void) { - LARGE_INTEGER n; - - if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || - Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || - Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { - if (chSchRescRequiredI()) - chSchDoRescheduleI(); - return; - } - - // Interrupt Timer simulation (10ms interval). - QueryPerformanceCounter(&n); - if (n.QuadPart > nextcnt.QuadPart) { - nextcnt.QuadPart += slice.QuadPart; - chSysTimerHandlerI(); - if (chSchRescRequiredI()) - chSchDoRescheduleI(); - } -} - -t_msg _IdleThread(void *p) { - - chThdSetPriority(IDLEPRIO); - - while (TRUE) { - - ChkIntSources(); - Sleep(0); - } -} - -__declspec(naked) void __fastcall chSysHalt(void) { - - exit(2); -} - -__declspec(naked) void __fastcall chSysSwitchI(Thread *otp, Thread *ntp) { - - __asm { - // Switch out code - push ebp - push esi - push edi - push ebx - mov dword ptr 16[ecx],esp - // Switch in code - mov esp,16[edx] - pop ebx - pop edi - pop esi - pop ebp - ret - } -} - -__declspec(naked) void __fastcall threadexit(void) { - - __asm { -// add esp,4 ; The thread parameter - push eax ; The exit code returned by the thread - call chThdExit - add esp,4 - call chSysHalt ; Should *never* happen - } -} diff --git a/demos/Win32-MSVS/chcore.h b/demos/Win32-MSVS/chcore.h deleted file mode 100644 index 18e96dc13..000000000 --- a/demos/Win32-MSVS/chcore.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Core file for Visual Studio 7 demo project. - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -typedef void *regx86; - -/* - * Stack saved context. - */ -struct intctx { - regx86 ebx; - regx86 edi; - regx86 esi; - regx86 ebp; - regx86 eip; -}; - -typedef struct { - struct intctx *esp; -} Context; - -#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) - -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ - BYTE8 *esp = (BYTE8 *)workspace + wsize; \ - APUSH(esp, arg); \ - APUSH(esp, threadexit); \ - esp -= sizeof(struct intctx); \ - ((struct intctx *)esp)->eip = pf; \ - ((struct intctx *)esp)->ebx = 0; \ - ((struct intctx *)esp)->edi = 0; \ - ((struct intctx *)esp)->esi = 0; \ - ((struct intctx *)esp)->ebp = 0; \ - tp->p_ctx.esp = (struct intctx *)esp; \ -} - -#define chSysLock() -#define chSysUnlock() -#define chSysPuts(msg) {} -#define chSysIRQEnterI() -#define chSysIRQExitI() - -#define INT_REQUIRED_STACK 0 -#define StackAlign(n) ((((n) - 1) | 3) + 1) -#define UserStackSize(n) StackAlign(sizeof(Thread) + \ - sizeof(void *) * 2 + \ - sizeof(struct intctx) + \ - (n) + \ - INT_REQUIRED_STACK) -#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; - -#define IDLE_THREAD_STACK_SIZE 16384 -t_msg _IdleThread(void *p); - -void __fastcall chSysHalt(void); -void __fastcall chSysSwitchI(Thread *otp, Thread *ntp); -void __fastcall threadexit(void); - -#endif /* _CHCORE_H_ */ diff --git a/demos/Win32-MSVS/chtypes.h b/demos/Win32-MSVS/chtypes.h deleted file mode 100644 index 5ab9a06e1..000000000 --- a/demos/Win32-MSVS/chtypes.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -/* - * Generic types often dependant on the compiler. - */ -#define BOOL char -#define BYTE8 unsigned char -#define SBYTE8 char -#define WORD16 short -#define UWORD16 unsigned short -#define LONG32 int -#define ULONG32 unsigned int - -typedef BYTE8 t_tmode; -typedef BYTE8 t_tstate; -typedef UWORD16 t_tid; -typedef ULONG32 t_prio; -typedef LONG32 t_msg; -typedef LONG32 t_eventid; -typedef ULONG32 t_eventmask; -typedef ULONG32 t_time; -typedef LONG32 t_cnt; -typedef ULONG32 t_size; - -#define INLINE __inline - -#endif /* _CHTYPES_H_ */ diff --git a/demos/Win32-MSVS/demo.c b/demos/Win32-MSVS/demo.c deleted file mode 100644 index 5a3bf167c..000000000 --- a/demos/Win32-MSVS/demo.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include - -#include - -static ULONG32 wdguard; -static WorkingArea(wdarea, 2048); - -static ULONG32 cdguard; -static WorkingArea(cdarea, 2048); -static Thread *cdtp; - -static t_msg WatchdogThread(void *arg); -static t_msg ConsoleThread(void *arg); - -t_msg TestThread(void *p); - -void InitCore(void); -extern FullDuplexDriver COM1, COM2; - -#define cprint(msg) chMsgSend(cdtp, (t_msg)msg) - -/* - * Watchdog thread, it checks magic values located under the various stack - * areas. The system is halted if something is wrong. - */ -static t_msg WatchdogThread(void *arg) { - wdguard = 0xA51F2E3D; - cdguard = 0xA51F2E3D; - while (TRUE) { - - if ((wdguard != 0xA51F2E3D) || - (cdguard != 0xA51F2E3D)) { - printf("Halted by watchdog"); - chSysHalt(); - } - chThdSleep(50); - } - return 0; -} - -/* - * Console print server done using synchronous messages. This makes the access - * to the C printf() thread safe and the print operation atomic among threads. - * In this example the message is the zero termitated string itself. - */ -static t_msg ConsoleThread(void *arg) { - - while (!chThdShouldTerminate()) { - printf((char *)chMsgWait()); - chMsgRelease(RDY_OK); - } - return 0; -} - -static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { - - while (*msg) - chFDDPut(sd, *msg++); -} - -static BOOL GetLineFDD(FullDuplexDriver *sd, char *line, int size) { - char *p = line; - - while (TRUE) { - short c = chIQGet(&sd->sd_iqueue); - if (c < 0) - return TRUE; - if (c == 4) { - PrintLineFDD(sd, "^D\r\n"); - return TRUE; - } - if (c == 8) { - if (p != line) { - chFDDPut(sd, (BYTE8)c); - chFDDPut(sd, 0x20); - chFDDPut(sd, (BYTE8)c); - p--; - } - continue; - } - if (c == '\r') { - PrintLineFDD(sd, "\r\n"); - *p = 0; - return FALSE; - } - if (c < 0x20) - continue; - if (p < line + size - 1) { - chFDDPut(sd, (BYTE8)c); - *p++ = (BYTE8)c; - } - } -} - -/* - * Example thread, not much to see here. It simulates the CTRL-C but there - * are no real signals involved. - */ -static t_msg HelloWorldThread(void *arg) { - int i; - short c; - FullDuplexDriver *sd = (FullDuplexDriver *)arg; - - for (i = 0; i < 100; i++) { - - PrintLineFDD(sd, "Hello World\r\n"); - c = chFDDGetTimeout(sd, 333); - switch (c) { - case -1: - continue; - case -2: - return 1; - case 3: - PrintLineFDD(sd, "^C\r\n"); - return 0; - default: - chThdSleep(333); - } - } - return 0; -} - -static BOOL checkend(FullDuplexDriver *sd) { - - char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ - if (lp) { - PrintLineFDD(sd, lp); - PrintLineFDD(sd, " ?\r\n"); - return TRUE; - } - return FALSE; -} - -/* - * Simple command shell thread, the argument is the serial line for the - * standard input and output. It recognizes few simple commands. - */ -static t_msg ShellThread(void *arg) { - FullDuplexDriver *sd = (FullDuplexDriver *)arg; - char *lp, line[64]; - Thread *tp; - WorkingArea(tarea, 1024); - - chIQReset(&sd->sd_iqueue); - chOQReset(&sd->sd_oqueue); - PrintLineFDD(sd, "ChibiOS/RT Command Shell\r\n\n"); - while (TRUE) { - PrintLineFDD(sd, "ch> "); - if (GetLineFDD(sd, line, sizeof(line))) { - PrintLineFDD(sd, "\nlogout"); - break; - } - lp = strtok(line, " \009"); // Note: not thread safe but it is just a demo. - if (lp) { - if ((stricmp(lp, "help") == 0) || - (stricmp(lp, "h") == 0) || - (stricmp(lp, "?") == 0)) { - if (checkend(sd)) - continue; - PrintLineFDD(sd, "Commands:\r\n"); - PrintLineFDD(sd, " help,h,? - This help\r\n"); - PrintLineFDD(sd, " exit - Logout from ChibiOS/RT\r\n"); - PrintLineFDD(sd, " time - Prints the system timer value\r\n"); - PrintLineFDD(sd, " hello - Runs the Hello World demo thread\r\n"); - } - else if (stricmp(lp, "exit") == 0) { - if (checkend(sd)) - continue; - PrintLineFDD(sd, "\nlogout"); - break; - } - else if (stricmp(lp, "time") == 0) { - if (checkend(sd)) - continue; - sprintf(line, "Time: %d\r\n", chSysGetTime()); - PrintLineFDD(sd, line); - } - else if (stricmp(lp, "hello") == 0) { - if (checkend(sd)) - continue; - tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), - HelloWorldThread, sd); - if (chThdWait(tp)) - break; // Lost connection while executing the hello thread. - } - else { - PrintLineFDD(sd, lp); - PrintLineFDD(sd, " ?\r\n"); - } - } - } - return 0; -} - -static WorkingArea(s1area, 2048); -static Thread *s1; -EventListener s1tel; - -static void COM1Handler(t_eventid id) { - t_dflags flags; - - if (s1 && chThdTerminated(s1)) { - s1 = NULL; - cprint("Init: disconnection on COM1\n"); - } - flags = chFDDGetAndClearFlags(&COM1); - if ((flags & SD_CONNECTED) && (s1 == NULL)) { - cprint("Init: connection on COM1\n"); - s1 = chThdCreate(NORMALPRIO, P_SUSPENDED, s1area, sizeof(s1area), - ShellThread, &COM1); - chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); - chThdResume(s1); - } - if ((flags & SD_DISCONNECTED) && (s1 != NULL)) - chIQReset(&COM1.sd_iqueue); -} - -static WorkingArea(s2area, 2048); -static Thread *s2; -EventListener s2tel; - -static void COM2Handler(t_eventid id) { - t_dflags flags; - - if (s2 && chThdTerminated(s2)) { - s2 = NULL; - cprint("Init: disconnection on COM2\n"); - } - flags = chFDDGetAndClearFlags(&COM2); - if ((flags & SD_CONNECTED) && (s2 == NULL)) { - cprint("Init: connection on COM2\n"); - s2 = chThdCreate(NORMALPRIO, P_SUSPENDED, s2area, sizeof(s1area), - ShellThread, &COM2); - chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); - chThdResume(s2); - } - if ((flags & SD_DISCONNECTED) && (s2 != NULL)) - chIQReset(&COM2.sd_iqueue); -} - -static t_evhandler fhandlers[2] = { - COM1Handler, - COM2Handler -}; - -/*------------------------------------------------------------------------* - * Simulator main, start here your threads, examples inside. * - *------------------------------------------------------------------------*/ -int main(void) { - EventListener c1fel, c2fel; - - InitCore(); - - // Startup ChibiOS/RT. - chSysInit(); - - chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); - cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); - - cprint("Console service started on COM1, COM2\n"); - cprint(" - Listening for connections on COM1\n"); - chFDDGetAndClearFlags(&COM1); - chEvtRegister(&COM1.sd_sevent, &c1fel, 0); - cprint(" - Listening for connections on COM2\n"); - chFDDGetAndClearFlags(&COM2); - chEvtRegister(&COM2.sd_sevent, &c2fel, 1); - while (!chThdShouldTerminate()) - chEvtWait(ALL_EVENTS, fhandlers); - chEvtUnregister(&COM2.sd_sevent, &c2fel); // Never invoked but this is an example... - chEvtUnregister(&COM1.sd_sevent, &c1fel); // Never invoked but this is an example... - return 0; -} diff --git a/demos/Win32-MSVS/readme.txt b/demos/Win32-MSVS/readme.txt deleted file mode 100644 index 6025e4879..000000000 --- a/demos/Win32-MSVS/readme.txt +++ /dev/null @@ -1,22 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for x86 into a Win32 process ** -***************************************************************************** - -** TARGET ** - -The demo runs under any Windows version as an application program. The serial -I/O is simulated over TCP/IP sockets. - -** The Demo ** - -The demo listens on the two serial ports, when a connection is detected a -thread is started that serves a small command shell. -The demo shows how create/terminate threads at runtime, how listen to events, -how ho work with serial ports, how use the messages. -You can develop your ChibiOS/RT application using this demo as a simulator -then you can recompile it for a different architecture. -See demo.c for details. - -** Build Procedure ** - -The demo was built using the Visual Studio 7, any later version should work. diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 6bb2664f5..fed88c171 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -45,7 +45,7 @@ typedef struct { #define SETUP_CONTEXT(workspace, wsize, pf, arg) \ { \ - BYTE8 *esp = (BYTE8 *)workspace + wsize; \ + uint8_t *esp = (uint8_t *)workspace + wsize; \ APUSH(esp, arg); \ APUSH(esp, threadstart); \ esp -= sizeof(struct intctx); \ @@ -70,7 +70,7 @@ typedef struct { sizeof(struct intctx) + \ (n) + \ INT_REQUIRED_STACK) -#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2]; +#define WorkingArea(s, n) uint32_t s[UserStackSize(n) >> 2]; #define IDLE_THREAD_STACK_SIZE 16384 t_msg _IdleThread(void *p); diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 2ac219148..c8a1dc69c 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -20,27 +20,21 @@ #ifndef _CHTYPES_H_ #define _CHTYPES_H_ -/* - * Generic types often dependant on the compiler. - */ -#define BOOL char -#define BYTE8 unsigned char -#define SBYTE8 char -#define WORD16 short -#define UWORD16 unsigned short -#define LONG32 int -#define ULONG32 unsigned int - -typedef BYTE8 t_tmode; -typedef BYTE8 t_tstate; -typedef UWORD16 t_tid; -typedef ULONG32 t_prio; -typedef LONG32 t_msg; -typedef LONG32 t_eventid; -typedef ULONG32 t_eventmask; -typedef ULONG32 t_time; -typedef LONG32 t_cnt; -typedef ULONG32 t_size; +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +typedef int8_t t_bool; +typedef uint8_t t_tmode; +typedef uint8_t t_tstate; +typedef uint16_t t_tid; +typedef uint32_t t_prio; +typedef int32_t t_msg; +typedef int32_t t_eventid; +typedef uint32_t t_eventmask; +typedef uint32_t t_time; +typedef int32_t t_cnt; +typedef uint32_t t_size; #define INLINE inline diff --git a/demos/Win32-MinGW/demo.c b/demos/Win32-MinGW/demo.c index acf17e7fd..0b646a50b 100644 --- a/demos/Win32-MinGW/demo.c +++ b/demos/Win32-MinGW/demo.c @@ -22,10 +22,10 @@ #include -static ULONG32 wdguard; +static uint32_t wdguard; static WorkingArea(wdarea, 2048); -static ULONG32 cdguard; +static uint32_t cdguard; static WorkingArea(cdarea, 2048); static Thread *cdtp; @@ -78,7 +78,7 @@ static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { chFDDPut(sd, *msg++); } -static BOOL GetLineFDD(FullDuplexDriver *sd, char *line, int size) { +static t_bool GetLineFDD(FullDuplexDriver *sd, char *line, int size) { char *p = line; while (TRUE) { @@ -91,9 +91,9 @@ static BOOL GetLineFDD(FullDuplexDriver *sd, char *line, int size) { } if (c == 8) { if (p != line) { - chFDDPut(sd, (BYTE8)c); + chFDDPut(sd, (uint8_t)c); chFDDPut(sd, 0x20); - chFDDPut(sd, (BYTE8)c); + chFDDPut(sd, (uint8_t)c); p--; } continue; @@ -106,8 +106,8 @@ static BOOL GetLineFDD(FullDuplexDriver *sd, char *line, int size) { if (c < 0x20) continue; if (p < line + size - 1) { - chFDDPut(sd, (BYTE8)c); - *p++ = (BYTE8)c; + chFDDPut(sd, (uint8_t)c); + *p++ = (uint8_t)c; } } } @@ -140,7 +140,7 @@ static t_msg HelloWorldThread(void *arg) { return 0; } -static BOOL checkend(FullDuplexDriver *sd) { +static t_bool checkend(FullDuplexDriver *sd) { char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ if (lp) { -- cgit v1.2.3 From 0778745ee12a4f14c001bd205e05728cc01e9633 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 Mar 2008 16:08:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@214 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/Makefile | 2 +- demos/AVR-ATmega128-GCC/board.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index dea57ee61..66cc846c7 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -80,7 +80,7 @@ OBJDIR = . # List C source files here. (C dependencies are automatically generated.) -SRC = ../../ports/AVR/chcore.c \ +SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index 6ac43a218..03907d391 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -23,6 +23,7 @@ #include #include "board.h" +#include "avr_serial.h" ISR(TIMER0_COMP_vect) { @@ -78,4 +79,9 @@ void hwinit(void) { TCNT0 = 0; // Reset counter. TIFR = (1 << OCF0); // Reset pending (if any). TIMSK = (1 << OCIE0); // Interrupt on compare. + + /* + * Other initializations. + */ + InitSerial(); } -- cgit v1.2.3 From 5e64a9fec2e17d008b9488faa027d2beaa130a88 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 5 Mar 2008 10:59:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@215 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/main.c | 4 ++-- demos/ARM7-LPC214x-GCC-minimal/main.c | 4 ++-- demos/ARM7-LPC214x-GCC/buzzer.c | 4 ++-- demos/ARM7-LPC214x-GCC/buzzer.h | 4 ++-- demos/ARM7-LPC214x-GCC/main.c | 14 +++++++------- demos/ARM7-LPC214x-GCC/mmcsd.c | 16 ++++++++-------- demos/ARM7-LPC214x-GCC/mmcsd.h | 14 +++++++------- demos/AVR-ATmega128-GCC/main.c | 2 +- demos/Win32-MinGW/chcore.c | 2 +- demos/Win32-MinGW/chcore.h | 2 +- demos/Win32-MinGW/chtypes.h | 25 ++++++++++++++----------- demos/Win32-MinGW/demo.c | 30 +++++++++++++++--------------- 12 files changed, 62 insertions(+), 59 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index f2a3f3737..a255c9939 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -23,7 +23,7 @@ #include "sam7x_serial.h" static WorkingArea(waThread1, 64); -static t_msg Thread1(void *arg) { +static msg_t Thread1(void *arg) { while (TRUE) { AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. @@ -38,7 +38,7 @@ static t_msg Thread1(void *arg) { * Entry point, the interrupts are disabled on entry. */ int main(int argc, char **argv) { - t_msg TestThread(void *p); + msg_t TestThread(void *p); /* * The main() function becomes a thread here then the interrupts are diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 18017f0b5..87d59dce0 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -25,7 +25,7 @@ * Red LEDs blinker thread, times are in milliseconds. */ static WorkingArea(waThread1, 64); -static t_msg Thread1(void *arg) { +static msg_t Thread1(void *arg) { while (TRUE) { IO0CLR = 0x00000800; @@ -44,7 +44,7 @@ static t_msg Thread1(void *arg) { * Yellow LED blinker thread, times are in milliseconds. */ static WorkingArea(waThread2, 64); -static t_msg Thread2(void *arg) { +static msg_t Thread2(void *arg) { while (TRUE) { IO0CLR = 0x80000000; diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index 9ee122fe1..249b1542b 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -64,7 +64,7 @@ static void stop(void *p) { chEvtSendI(&BuzzerSilentEventSource); } -void PlaySound(int freq, t_time duration) { +void PlaySound(int freq, systime_t duration) { static VirtualTimer bvt; TC *tc = T1Base; @@ -82,7 +82,7 @@ void PlaySound(int freq, t_time duration) { chSysUnlock(); } -void PlaySoundWait(int freq, t_time duration) { +void PlaySoundWait(int freq, systime_t duration) { TC *tc = T1Base; StopCounter(tc); diff --git a/demos/ARM7-LPC214x-GCC/buzzer.h b/demos/ARM7-LPC214x-GCC/buzzer.h index 464e081d8..734cb1a44 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.h +++ b/demos/ARM7-LPC214x-GCC/buzzer.h @@ -24,8 +24,8 @@ extern "C" { #endif void InitBuzzer(void); - void PlaySound(int freq, t_time duration); - void PlaySoundWait(int freq, t_time duration); + void PlaySound(int freq, systime_t duration); + void PlaySoundWait(int freq, systime_t duration); #ifdef __cplusplus } #endif diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index fe0b9342c..ad2ab2700 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -29,7 +29,7 @@ * Red LEDs blinker thread, times are in milliseconds. */ static WorkingArea(waThread1, 64); -static t_msg Thread1(void *arg) { +static msg_t Thread1(void *arg) { while (TRUE) { IO0CLR = 0x00000800; @@ -48,7 +48,7 @@ static t_msg Thread1(void *arg) { * Yellow LED blinker thread, times are in milliseconds. */ static WorkingArea(waThread2, 64); -static t_msg Thread2(void *arg) { +static msg_t Thread2(void *arg) { while (TRUE) { IO0CLR = 0x80000000; @@ -62,8 +62,8 @@ static t_msg Thread2(void *arg) { /* * Executed as event handler at 500mS intervals. */ -static void TimerHandler(t_eventid id) { - t_msg TestThread(void *p); +static void TimerHandler(eventid_t id) { + msg_t TestThread(void *p); if (!(IO0PIN & 0x00018000)) { // Both buttons TestThread(&COM1); @@ -83,7 +83,7 @@ static void TimerHandler(t_eventid id) { * Plays sounds when a MMC/SD card is inserted, then initializes the MMC * driver and reads a sector. */ -static void InsertHandler(t_eventid id) { +static void InsertHandler(eventid_t id) { static uint8_t rwbuf[512]; MMCCSD data; @@ -102,7 +102,7 @@ static void InsertHandler(t_eventid id) { /* * Plays sounds when a MMC/SD card is removed. */ -static void RemoveHandler(t_eventid id) { +static void RemoveHandler(eventid_t id) { PlaySoundWait(2000, 100); PlaySoundWait(1000, 100); @@ -112,7 +112,7 @@ static void RemoveHandler(t_eventid id) { * Entry point, the interrupts are disabled on entry. */ int main(int argc, char **argv) { - static const t_evhandler evhndl[] = { + static const evhandler_t evhndl[] = { TimerHandler, InsertHandler, RemoveHandler diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index febfca237..c06123f88 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -91,7 +91,7 @@ void mmcStopPolling(void) { /* * Returns TRUE if the card is safely inserted in the reader. */ -t_bool mmcCardInserted (void) { +bool_t mmcCardInserted (void) { return cnt == 0; } @@ -145,7 +145,7 @@ static uint8_t recvr1(void) { return 0xFF; /* Timeout.*/ } -static t_bool getdata(uint8_t *buf, uint32_t n) { +static bool_t getdata(uint8_t *buf, uint32_t n) { int i; for (i = 0; i < MMC_WAIT_DATA; i++) { @@ -162,7 +162,7 @@ static t_bool getdata(uint8_t *buf, uint32_t n) { /* * Initializes a card after the power up by selecting the SPI mode. */ -t_bool mmcInit(void) { +bool_t mmcInit(void) { /* * Starting initialization with slow clock mode. @@ -222,7 +222,7 @@ uint8_t mmcSendCommand(uint8_t cmd, uint32_t arg) { * @param data the pointer to a \p MMCCSD structure * @return \p TRUE if an error happened */ -t_bool mmcGetSize(MMCCSD *data) { +bool_t mmcGetSize(MMCCSD *data) { uint8_t buf[16]; sspAcquireBus(); @@ -250,7 +250,7 @@ t_bool mmcGetSize(MMCCSD *data) { * @param buf the pointer to the read buffer * @return \p TRUE if an error happened */ -t_bool mmcRead(uint8_t *buf, uint32_t blknum) { +bool_t mmcRead(uint8_t *buf, uint32_t blknum) { sspAcquireBus(); sendhdr(CMDREAD, blknum << 8); @@ -273,7 +273,7 @@ t_bool mmcRead(uint8_t *buf, uint32_t blknum) { * @param buf the pointer to the read buffer * @return \p TRUE if an error happened */ -t_bool mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { +bool_t mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { static const uint8_t stopcmd[] = {0x40 | CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; sspAcquireBus(); @@ -309,7 +309,7 @@ t_bool mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { * the card, this allows to not make useless busy waiting. The invoking * thread can do other things while the data is being written. */ -t_bool mmcWrite(uint8_t *buf, uint32_t blknum) { +bool_t mmcWrite(uint8_t *buf, uint32_t blknum) { static const uint8_t start[] = {0xFF, 0xFE}; uint8_t b[4]; @@ -340,7 +340,7 @@ t_bool mmcWrite(uint8_t *buf, uint32_t blknum) { * the card, this allows to not make useless busy waiting. The invoking * thread can do other things while the data is being written. */ -t_bool mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { +bool_t mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { static const uint8_t start[] = {0xFF, 0xFC}, stop[] = {0xFD, 0xFF}; uint8_t b[4]; diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h index 60396dafb..d7ab4b348 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ b/demos/ARM7-LPC214x-GCC/mmcsd.h @@ -48,16 +48,16 @@ extern EventSource MMCInsertEventSource, MMCRemoveEventSource; #endif void InitMMC(void); - t_bool mmcInit(void); + bool_t mmcInit(void); void mmcStartPolling(void); void mmcStopPolling(void); - t_bool mmcCardInserted (void); + bool_t mmcCardInserted (void); uint8_t mmcSendCommand(uint8_t cmd, uint32_t arg); - t_bool mmcGetSize(MMCCSD *data); - t_bool mmcRead(uint8_t *buf, uint32_t blknum); - t_bool mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); - t_bool mmcWrite(uint8_t *buf, uint32_t blknum); - t_bool mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); + bool_t mmcGetSize(MMCCSD *data); + bool_t mmcRead(uint8_t *buf, uint32_t blknum); + bool_t mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); + bool_t mmcWrite(uint8_t *buf, uint32_t blknum); + bool_t mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); void mmcSynch(void); #ifdef __cplusplus } diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index b5103521e..48b263f3c 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -26,7 +26,7 @@ void hwinit(void); static WorkingArea(waThread1, 32); -static t_msg Thread1(void *arg) { +static msg_t Thread1(void *arg) { while (TRUE) { PORTA ^= PORTA_RELAY; diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 866ac791e..047fe66da 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -91,7 +91,7 @@ void ChkIntSources(void) { } } -t_msg _IdleThread(void *p) { +msg_t _IdleThread(void *p) { while (TRUE) { diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index fed88c171..bc0ed3e42 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -73,7 +73,7 @@ typedef struct { #define WorkingArea(s, n) uint32_t s[UserStackSize(n) >> 2]; #define IDLE_THREAD_STACK_SIZE 16384 -t_msg _IdleThread(void *p); +msg_t _IdleThread(void *p); __attribute__((fastcall)) void chSysHalt(void); __attribute__((fastcall)) void chSysSwitchI(Thread *otp, Thread *ntp); diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index c8a1dc69c..2fd609b1f 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -20,21 +20,24 @@ #ifndef _CHTYPES_H_ #define _CHTYPES_H_ +#define __need_NULL +#define __need_size_t +#include + #if !defined(_STDINT_H) && !defined(__STDINT_H_) #include #endif -typedef int8_t t_bool; -typedef uint8_t t_tmode; -typedef uint8_t t_tstate; -typedef uint16_t t_tid; -typedef uint32_t t_prio; -typedef int32_t t_msg; -typedef int32_t t_eventid; -typedef uint32_t t_eventmask; -typedef uint32_t t_time; -typedef int32_t t_cnt; -typedef uint32_t t_size; +typedef int8_t bool_t; +typedef uint8_t tmode_t; +typedef uint8_t tstate_t; +typedef uint16_t tid_t; +typedef uint32_t tprio_t; +typedef int32_t msg_t; +typedef int32_t eventid_t; +typedef uint32_t eventmask_t; +typedef uint32_t systime_t; +typedef int32_t cnt_t; #define INLINE inline diff --git a/demos/Win32-MinGW/demo.c b/demos/Win32-MinGW/demo.c index 0b646a50b..f3d276599 100644 --- a/demos/Win32-MinGW/demo.c +++ b/demos/Win32-MinGW/demo.c @@ -29,21 +29,21 @@ static uint32_t cdguard; static WorkingArea(cdarea, 2048); static Thread *cdtp; -static t_msg WatchdogThread(void *arg); -static t_msg ConsoleThread(void *arg); +static msg_t WatchdogThread(void *arg); +static msg_t ConsoleThread(void *arg); -t_msg TestThread(void *p); +msg_t TestThread(void *p); void InitCore(void); extern FullDuplexDriver COM1, COM2; -#define cprint(msg) chMsgSend(cdtp, (t_msg)msg) +#define cprint(msg) chMsgSend(cdtp, (msg_t)msg) /* * Watchdog thread, it checks magic values located under the various stack * areas. The system is halted if something is wrong. */ -static t_msg WatchdogThread(void *arg) { +static msg_t WatchdogThread(void *arg) { wdguard = 0xA51F2E3D; cdguard = 0xA51F2E3D; while (TRUE) { @@ -63,7 +63,7 @@ static t_msg WatchdogThread(void *arg) { * to the C printf() thread safe and the print operation atomic among threads. * In this example the message is the zero termitated string itself. */ -static t_msg ConsoleThread(void *arg) { +static msg_t ConsoleThread(void *arg) { while (!chThdShouldTerminate()) { printf((char *)chMsgWait()); @@ -78,7 +78,7 @@ static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { chFDDPut(sd, *msg++); } -static t_bool GetLineFDD(FullDuplexDriver *sd, char *line, int size) { +static bool_t GetLineFDD(FullDuplexDriver *sd, char *line, int size) { char *p = line; while (TRUE) { @@ -116,7 +116,7 @@ static t_bool GetLineFDD(FullDuplexDriver *sd, char *line, int size) { * Example thread, not much to see here. It simulates the CTRL-C but there * are no real signals involved. */ -static t_msg HelloWorldThread(void *arg) { +static msg_t HelloWorldThread(void *arg) { int i; short c; FullDuplexDriver *sd = (FullDuplexDriver *)arg; @@ -140,7 +140,7 @@ static t_msg HelloWorldThread(void *arg) { return 0; } -static t_bool checkend(FullDuplexDriver *sd) { +static bool_t checkend(FullDuplexDriver *sd) { char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ if (lp) { @@ -155,7 +155,7 @@ static t_bool checkend(FullDuplexDriver *sd) { * Simple command shell thread, the argument is the serial line for the * standard input and output. It recognizes few simple commands. */ -static t_msg ShellThread(void *arg) { +static msg_t ShellThread(void *arg) { FullDuplexDriver *sd = (FullDuplexDriver *)arg; char *lp, line[64]; Thread *tp; @@ -225,8 +225,8 @@ static WorkingArea(s1area, 4096); static Thread *s1; EventListener s1tel; -static void COM1Handler(t_eventid id) { - t_dflags flags; +static void COM1Handler(eventid_t id) { + dflags_t flags; if (s1 && chThdTerminated(s1)) { s1 = NULL; @@ -248,8 +248,8 @@ static WorkingArea(s2area, 4096); static Thread *s2; EventListener s2tel; -static void COM2Handler(t_eventid id) { - t_dflags flags; +static void COM2Handler(eventid_t id) { + dflags_t flags; if (s2 && chThdTerminated(s2)) { s2 = NULL; @@ -267,7 +267,7 @@ static void COM2Handler(t_eventid id) { chIQReset(&COM2.sd_iqueue); } -static t_evhandler fhandlers[2] = { +static evhandler_t fhandlers[2] = { COM1Handler, COM2Handler }; -- cgit v1.2.3 From 8c39bfc93d6c68e5d64707916558b6316f611be2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 5 Mar 2008 15:56:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@216 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/Makefile | 1 + demos/AVR-ATmega128-GCC/main.c | 23 ++++++++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index 66cc846c7..e2b5dd8cc 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -86,6 +86,7 @@ SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ ../../src/lib/evtimer.c \ + ../../test/test.c \ board.c main.c diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 48b263f3c..29a19701b 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -18,6 +18,8 @@ */ #include +#include +#include #include @@ -35,7 +37,19 @@ static msg_t Thread1(void *arg) { return 0; } +static void TimerHandler(eventid_t id) { + msg_t TestThread(void *p); + + if (!(PORTA & PORTA_BUTTON1)) + TestThread(&SER2); +} + int main(int argc, char **argv) { + static EvTimer evt; + static evhandler_t handlers[1] = { + TimerHandler + }; + static EventListener el0; hwinit(); @@ -45,13 +59,20 @@ int main(int argc, char **argv) { */ chSysInit(); + /* + * Event Timer initialization. + */ + evtInit(&evt, 500); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + /* * Starts the LED blinker thread. */ chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); while(TRUE) - chThdSleep(1000); + chEvtWait(ALL_EVENTS, handlers); return 0; } -- cgit v1.2.3 From a6dbd7a691a6c70ebaf132cdc92fc21b3428f6f7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 6 Mar 2008 11:38:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@217 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/Makefile | 25 +++++-- demos/AVR-AT90CANx-GCC/board.c | 87 +++++++++++++++++++++++ demos/AVR-AT90CANx-GCC/board.h | 86 +++++++++++++++++++++++ demos/AVR-AT90CANx-GCC/chconf.h | 15 ++-- demos/AVR-AT90CANx-GCC/chcore.c | 137 ------------------------------------- demos/AVR-AT90CANx-GCC/chcore.h | 116 ------------------------------- demos/AVR-AT90CANx-GCC/chcore2.S | 123 --------------------------------- demos/AVR-AT90CANx-GCC/chtypes.h | 48 ------------- demos/AVR-AT90CANx-GCC/main.c | 30 +++++++- demos/AVR-AT90CANx-GCC/readme.txt | 25 +++++++ demos/AVR-ATmega128-GCC/readme.txt | 3 +- 11 files changed, 253 insertions(+), 442 deletions(-) create mode 100644 demos/AVR-AT90CANx-GCC/board.c create mode 100644 demos/AVR-AT90CANx-GCC/board.h delete mode 100644 demos/AVR-AT90CANx-GCC/chcore.c delete mode 100644 demos/AVR-AT90CANx-GCC/chcore.h delete mode 100644 demos/AVR-AT90CANx-GCC/chcore2.S delete mode 100644 demos/AVR-AT90CANx-GCC/chtypes.h create mode 100644 demos/AVR-AT90CANx-GCC/readme.txt (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index b65fb4a74..106c3c390 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -80,8 +80,14 @@ OBJDIR = . # List C source files here. (C dependencies are automatically generated.) -SRC = ./main.c ./chcore.c ../../src/chinit.c ../../src/chlists.c ../../src/chdelta.c ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c ../../src/chserial.c - +SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c \ + ../../test/test.c \ + board.c main.c # List C++ source files here. (C dependencies are automatically generated.) @@ -95,7 +101,7 @@ CPPSRC = # Even though the DOS/Win* filesystem matches both .s and .S the same, # it will preserve the spelling of the filenames, and gcc itself does # care about how the name is spelled on its command-line. -ASRC = ./chcore2.S +ASRC = # Optimization level, can be [0, 1, 2, 3, s]. @@ -115,7 +121,7 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = ../../src/include +EXTRAINCDIRS = ../../src/include ../../src/lib ../../ports/AVR # Compiler flag to set the C Standard level. @@ -402,12 +408,13 @@ ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS) all: begin gccversion sizebefore build sizeafter end # Change the build target to build a HEX file or a library. -build: elf hex eep lss sym +build: elf hex bin eep lss sym #build: lib elf: $(TARGET).elf hex: $(TARGET).hex +bin: $(TARGET).bin eep: $(TARGET).eep lss: $(TARGET).lss sym: $(TARGET).sym @@ -512,6 +519,11 @@ extcoff: $(TARGET).elf @echo $(MSG_FLASH) $@ $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@ +%.bin: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O binary -R .eeprom $< $@ + %.eep: %.elf @echo @echo $(MSG_EEPROM) $@ @@ -593,6 +605,7 @@ clean_list : @echo @echo $(MSG_CLEANING) $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).bin $(REMOVE) $(TARGET).eep $(REMOVE) $(TARGET).cof $(REMOVE) $(TARGET).elf @@ -617,7 +630,7 @@ $(shell mkdir $(OBJDIR) 2>/dev/null) # Listing of phony targets. .PHONY : all begin finish end sizebefore sizeafter gccversion \ -build elf hex eep lss sym coff extcoff \ +build elf hex bin eep lss sym coff extcoff \ clean clean_list program debug gdb-config diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c new file mode 100644 index 000000000..e78360e9a --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/board.c @@ -0,0 +1,87 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include +#include + +#include "board.h" +#include "avr_serial.h" + +ISR(TIMER0_COMP_vect) { + + chSysIRQEnterI(); + + chSysTimerHandlerI(); + + chSysIRQExitI(); +} + +/* + * Board initialization code. + */ +void hwinit(void) { + + /* + * I/O ports setup. + */ + DDRA = VAL_DDRA; + PORTA = VAL_PORTA; + DDRB = VAL_DDRB; + PORTB = VAL_PORTB; + DDRC = VAL_DDRC; + PORTC = VAL_PORTC; + DDRD = VAL_DDRD; + PORTD = VAL_PORTD; + DDRE = VAL_DDRE; + PORTE = VAL_PORTE; + DDRF = VAL_DDRF; + PORTF = VAL_PORTF; + DDRG = VAL_DDRG; + PORTG = VAL_PORTG; + + /* + * External interrupts setup, all disabled initially. + */ + EICRA = 0x00; + EICRB = 0x00; + EIMSK = 0x00; + + /* + * Enables Idle mode for SLEEP instruction. + */ + SMCR = (1 << SE); + + /* + * Timer 0 setup. + */ + TCCR0A = (1 << WGM01) | (0 << WGM00) | // CTC mode. + (0 << COM0A1) | (0 << COM0A0) | // OC0A disabled (normal I/O). + (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. + OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; + TCNT0 = 0; // Reset counter. + TIFR0 = (1 << OCF0A); // Reset pending (if any). + TIMSK0 = (1 << OCIE0A); // Interrupt on compare. + + /* + * Other initializations. + */ + InitSerial(); +} diff --git a/demos/AVR-AT90CANx-GCC/board.h b/demos/AVR-AT90CANx-GCC/board.h new file mode 100644 index 000000000..fefd6a39c --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/board.h @@ -0,0 +1,86 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define BOARD_OLIMEX_AVR_CAN + +/* + * All inputs with pullups. + */ +#define VAL_DDRA 0x00 +#define VAL_PORTA 0xFF + +/* + * All inputs with pullups. + */ +#define VAL_DDRB 0x00 +#define VAL_PORTB 0xFF + +/* + * All inputs with pullups. + */ +#define VAL_DDRC 0x00 +#define VAL_PORTC 0xFF + +/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 + * IN IN OUT IN OUT IN IN IN + * DDRD 0 0 1 0 1 0 0 0 + * PU HiZ VAL PU VAL HiZ HiZ HiZ + * PORTD 1 0 ?1 1 1 0 0 0 + */ +#define VAL_DDRD 0x28 +#define VAL_PORTD 0xB8 + +/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0 + * IN IN IN OUT IN IN OUT IN + * DDRE 0 0 0 1 0 0 1 0 + * PU PU HiZ VAL PU PU VAL HiZ + * PORTE 1 1 0 1 1 1 1 0 + */ +#define VAL_DDRE 0x12 +#define VAL_PORTE 0xDE + +/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 + * x x x x IN IN IN IN + * DDRF 0 0 0 0 0 0 0 0 + * x x x x PU PU PU PU + * PORTF 0 0 0 0 1 1 1 1 + * + */ +#define VAL_DDRF 0x00 +#define VAL_PORTF 0x0F + +/* x x x x x PG2 PG1 PG0 + * x x x x x IN IN IN + * DDRG 0 0 0 0 0 0 0 0 + * x x x x x PU PU PU + * PORTG 0 0 0 0 0 1 1 1 + * + */ +#define VAL_DDRG 0x00 +#define VAL_PORTG 0x07 + +#define PORTE_LED (1 << 4) +#define PORTE_BUTTON (1 << 5) + +void hwinit(void); + +#endif /* _BOARD_H_ */ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 162255af5..17c2c3d38 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -17,6 +17,10 @@ along with this program. If not, see . */ +/* + * Configuration file for LPC214x-GCC demo project. + */ + /** * @addtogroup Config * @{ @@ -25,15 +29,10 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/* - * NOTE: this is just documentation for doxigen, the real configuration file - * is the one into the project directories. - */ - /** Configuration option: if specified then time efficient rather than space * efficient code is used when two possible implementations exist, note * that this is not related to the compiler optimization options.*/ -//#define CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ @@ -151,9 +150,9 @@ * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-\. + * -ffixed-. */ -//#define CH_CURRP_REGISTER_CACHE "reg" +//#define CH_CURRP_REGISTER_CACHE "r8" /** Configuration option: Includes basic debug support to the kernel. * @note the debug support is port-dependent, it may be not present on some diff --git a/demos/AVR-AT90CANx-GCC/chcore.c b/demos/AVR-AT90CANx-GCC/chcore.c deleted file mode 100644 index 3bc5b027e..000000000 --- a/demos/AVR-AT90CANx-GCC/chcore.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include - -/* - * All inputs with pullups. - */ -#define VAL_DDRA 0x00 -#define VAL_PORTA 0xFF - -/* - * All inputs with pullups. - */ -#define VAL_DDRB 0x00 -#define VAL_PORTB 0xFF - -/* - * All inputs with pullups. - */ -#define VAL_DDRC 0x00 -#define VAL_PORTC 0xFF - -/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 - * IN IN OUT IN OUT IN IN IN - * DDRD 0 0 1 0 1 0 0 0 - * PU HiZ VAL PU VAL HiZ HiZ HiZ - * PORTD 1 0 ?1 1 1 0 0 0 - */ -#define VAL_DDRD 0x28 -#define VAL_PORTD 0xB8 - -/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0 - * IN IN IN OUT IN IN OUT IN - * DDRE 0 0 0 1 0 0 1 0 - * PU PU HiZ VAL PU PU VAL HiZ - * PORTE 1 1 0 1 1 1 1 0 - */ -#define VAL_DDRE 0x12 -#define VAL_PORTE 0xDE - -/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 - * x x x x IN IN IN IN - * DDRF 0 0 0 0 0 0 0 0 - * x x x x PU PU PU PU - * PORTF 0 0 0 0 1 1 1 1 - * - */ -#define VAL_DDRF 0x00 -#define VAL_PORTF 0x0F - -/* x x x x x PG2 PG1 PG0 - * x x x x x IN IN IN - * DDRG 0 0 0 0 0 0 0 0 - * x x x x x PU PU PU - * PORTG 0 0 0 0 0 1 1 1 - * - */ -#define VAL_DDRG 0x00 -#define VAL_PORTG 0x07 - -void hwinit(void) { - - /* - * I/O ports setup. - */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; - - /* - * External interrupts setup, all disabled initially. - */ - EICRA = 0x00; - EICRB = 0x00; - EIMSK = 0x00; - - /* - * Enables Idle mode for SLEEP instruction. - */ - SMCR = 1; - - /* - * Timer 0 setup. - */ - TCCR0A = (1 << WGM01) | (0 << WGM00) | // CTC mode. - (0 << COM0A1) | (0 << COM0A0) | // OC0A disabled (normal I/O). - (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. - OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; - TCNT0 = 0; // Reset counter. - TIFR0 = (1 << OCF0A); // Reset pending (if any). - TIMSK0 = (1 << OCIE0A); // Interrupt on compare. -} - -void _IdleThread(void *p) { - - while (TRUE) { -// asm volatile ("sleep"); - } -} - -void chSysHalt(void) { - - chSysLock(); - - while (TRUE) - ; -} diff --git a/demos/AVR-AT90CANx-GCC/chcore.h b/demos/AVR-AT90CANx-GCC/chcore.h deleted file mode 100644 index 9e1b95db8..000000000 --- a/demos/AVR-AT90CANx-GCC/chcore.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @addtogroup Core - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/* - * Interrupt saved context. - */ -struct extctx { - BYTE8 sr; - BYTE8 r31; - BYTE8 r30; - BYTE8 r27; - BYTE8 r26; - BYTE8 r25; - BYTE8 r24; - BYTE8 r23; - BYTE8 r22; - BYTE8 r21; - BYTE8 r20; - BYTE8 r19; - BYTE8 r18; - BYTE8 r1; - BYTE8 r0; - UWORD16 pc; -}; - -/* - * System saved context. - */ -struct intctx { - BYTE8 r29; - BYTE8 r28; - BYTE8 r17; - BYTE8 r16; - BYTE8 r15; - BYTE8 r14; - BYTE8 r13; - BYTE8 r12; - BYTE8 r11; - BYTE8 r10; - BYTE8 r9; - BYTE8 r8; - BYTE8 r7; - BYTE8 r6; - BYTE8 r5; - BYTE8 r4; - BYTE8 r3; - BYTE8 r2; - UWORD16 pc; -}; - -/* - * Port dependent part of the Thread structure, you may add fields in - * this structure. - */ -typedef struct { - struct intctx *sp; -} Context; - -/** - * Platform dependent part of the \p chThdCreate() API. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.sp--; \ - tp->p_ctx.sp->r2 = (int)pf; \ - tp->p_ctx.sp->r3 = (int)pf >> 8; \ - tp->p_ctx.sp->r4 = (int)arg; \ - tp->p_ctx.sp->r5 = (int)arg >> 8; \ - tp->p_ctx.sp->pc = (UWORD16)threadstart; \ -} - -#define INT_REQUIRED_STACK 0x10 -#define StackAlign(n) (n) -#define UserStackSize(n) StackAlign(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) -#define WorkingArea(s, n) BYTE8 s[UserStackSize(n)]; - -#define chSysLock() asm("cli") -#define chSysUnlock() asm("sei") -#define chSysPuts(msg) {} - -#define IDLE_THREAD_STACK_SIZE 8 -void _IdleThread(void *p) __attribute__((noreturn)); - -void chSysHalt(void) __attribute__((noreturn)) ; -void chSysSwitchI(Context *oldp, Context *newp); -void threadstart(void); - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/demos/AVR-AT90CANx-GCC/chcore2.S b/demos/AVR-AT90CANx-GCC/chcore2.S deleted file mode 100644 index 96c17f011..000000000 --- a/demos/AVR-AT90CANx-GCC/chcore2.S +++ /dev/null @@ -1,123 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -.global threadstart -threadstart: - sei - movw r24, r4 // argument - movw r30, r2 // thread function - icall - call chThdExit - -.global chSysSwitchI -chSysSwitchI: - push r2 - push r3 - push r4 - push r5 - push r6 - push r7 - push r8 - push r9 - push r10 - push r11 - push r12 - push r13 - push r14 - push r15 - push r16 - push r17 - push r28 - push r29 - movw r30, r24 // Z <- oldp - in r0, _SFR_IO_ADDR(SPL) - st Z, r0 - in r0, _SFR_IO_ADDR(SPH) - std Z+1, r0 - - movw r30, r22 // Z <- newp - ld r0, Z - out _SFR_IO_ADDR(SPL), r0 - ldd r0, Z+1 - out _SFR_IO_ADDR(SPH), r0 - pop r29 - pop r28 - pop r17 - pop r16 - pop r15 - pop r14 - pop r13 - pop r12 - pop r11 - pop r10 - pop r9 - pop r8 - pop r7 - pop r6 - pop r5 - pop r4 - pop r3 - pop r2 - ret - -.global __vector_17 -__vector_17: - push r0 - push r1 - push r18 - push r19 - push r20 - push r21 - push r22 - push r23 - push r24 - push r25 - push r26 - push r27 - push r30 - push r31 - in r0, _SFR_IO_ADDR(SREG) - push r0 - clr r1 - call chSysTimerHandlerI -intcommon: - call chSchRescRequiredI - tst r24 - breq noschd - call chSchDoRescheduleI -noschd: - pop r0 - out _SFR_IO_ADDR(SREG), r0 - pop r31 - pop r30 - pop r27 - pop r26 - pop r25 - pop r24 - pop r23 - pop r22 - pop r21 - pop r20 - pop r19 - pop r18 - pop r1 - pop r0 - reti diff --git a/demos/AVR-AT90CANx-GCC/chtypes.h b/demos/AVR-AT90CANx-GCC/chtypes.h deleted file mode 100644 index 60e16aaf4..000000000 --- a/demos/AVR-AT90CANx-GCC/chtypes.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -/* - * Generic types often dependant on the compiler. - */ -#define BOOL char -#define BYTE8 unsigned char -#define SBYTE8 signed char -#define WORD16 int -#define UWORD16 unsigned int -#define LONG32 long -#define ULONG32 unsigned long -#define PTR_EQ int - -typedef BYTE8 t_tmode; -typedef BYTE8 t_tstate; -typedef BYTE8 t_tid; -typedef BYTE8 t_prio; -typedef WORD16 t_msg; -typedef BYTE8 t_eventid; -typedef BYTE8 t_eventmask; -typedef UWORD16 t_time; -typedef SBYTE8 t_cnt; -typedef UWORD16 t_size; - -#define INLINE inline - -#endif /* _CHTYPES_H_ */ diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 14c45cf47..2379b670f 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -18,21 +18,38 @@ */ #include +#include +#include #include +#include "board.h" + void hwinit(void); static WorkingArea(waThread1, 32); -static t_msg Thread1(void *arg) { +static msg_t Thread1(void *arg) { while (TRUE) { - chThdSleep(800); + PORTE ^= PORTE_LED; + chThdSleep(500); } return 0; } +static void TimerHandler(eventid_t id) { + msg_t TestThread(void *p); + + if (!(PORTE & PORTE_BUTTON)) + TestThread(&SER2); +} + int main(int argc, char **argv) { + static EvTimer evt; + static evhandler_t handlers[1] = { + TimerHandler + }; + static EventListener el0; hwinit(); @@ -42,13 +59,20 @@ int main(int argc, char **argv) { */ chSysInit(); + /* + * Event Timer initialization. + */ + evtInit(&evt, 500); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + /* * Starts the LED blinker thread. */ chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); while(TRUE) - /* Do stuff*/ ; + chEvtWait(ALL_EVENTS, handlers); return 0; } diff --git a/demos/AVR-AT90CANx-GCC/readme.txt b/demos/AVR-AT90CANx-GCC/readme.txt new file mode 100644 index 000000000..3102bcf15 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for Atmel AVR AT90CAN128. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex AVR-CAN board. + +** The Demo ** + +The demo currently just flashes the board LED using a thread. It will be +expanded in next releases. +By pressing the board button the test suite is activated, output on serial +port 2. + +** Build Procedure ** + +The demo was built using the WinAVR toolchain. + +** Notes ** + +The demo requires include files from WinAVR that are not part of the ChibiOS/RT +distribution, please install WinAVR. + + http://winavr.sourceforge.net/ diff --git a/demos/AVR-ATmega128-GCC/readme.txt b/demos/AVR-ATmega128-GCC/readme.txt index b580dbc6e..1c6ab3c5d 100644 --- a/demos/AVR-ATmega128-GCC/readme.txt +++ b/demos/AVR-ATmega128-GCC/readme.txt @@ -1,5 +1,5 @@ ***************************************************************************** -** ChibiOS/RT port for Atmel AVRmega128. ** +** ChibiOS/RT port for Atmel AVR ATmega128. ** ***************************************************************************** ** TARGET ** @@ -10,6 +10,7 @@ The demo runs on an Olimex AVR-MT-128 board. The demo currently just toggles the relay using a thread. It will be expanded in next releases. +By pressing the button 1 the test suite is activated, output on serial port 2. ** Build Procedure ** -- cgit v1.2.3 From d3ff29c1893323a3749e0c7f45a5d1541430929b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 7 Mar 2008 15:24:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@219 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/Makefile | 2 +- demos/AVR-ATmega128-GCC/board.h | 24 +++++----- demos/AVR-ATmega128-GCC/lcd.c | 97 ++++++++++++++++++++++++++++++++++++++ demos/AVR-ATmega128-GCC/lcd.h | 52 ++++++++++++++++++++ demos/AVR-ATmega128-GCC/main.c | 15 +++++- demos/AVR-ATmega128-GCC/readme.txt | 4 +- 6 files changed, 178 insertions(+), 16 deletions(-) create mode 100644 demos/AVR-ATmega128-GCC/lcd.c create mode 100644 demos/AVR-ATmega128-GCC/lcd.h (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index e2b5dd8cc..34c228691 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -87,7 +87,7 @@ SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ ../../src/chserial.c \ ../../src/lib/evtimer.c \ ../../test/test.c \ - board.c main.c + board.c lcd.c main.c # List C++ source files here. (C dependencies are automatically generated.) diff --git a/demos/AVR-ATmega128-GCC/board.h b/demos/AVR-ATmega128-GCC/board.h index a29ee8664..97b9c684d 100644 --- a/demos/AVR-ATmega128-GCC/board.h +++ b/demos/AVR-ATmega128-GCC/board.h @@ -38,22 +38,22 @@ #define VAL_PORTB 0xFF /* D7 D6 D5 D4 PC3 E R/W RS - * IN IN IN IN IN OUT OUT OUT - * DDRC 0 0 0 0 0 1 1 1 + * OUT OUT OUT OUT IN OUT OUT OUT + * DDRC 1 1 1 1 0 1 1 1 * PU PU PU PU PU VAL VAL VAL - * PORTC 1 1 1 1 1 0 0 0 + * PORTC 0 0 0 0 1 0 0 0 */ -#define VAL_DDRC 0x03 -#define VAL_PORTC 0xF8 +#define VAL_DDRC 0xF7 +#define VAL_PORTC 0x08 /* PD7 PD6 PD5 PD4 TXD RXD PD1 PD0 * IN IN IN IN OUT IN IN IN * DDRD 0 0 0 0 1 0 0 0 - * PU PU PU PU VAL HiZ HiZ HiZ - * PORTD 1 1 1 1 1 0 0 0 + * PU PU PU PU VAL HiZ PU PU + * PORTD 1 1 1 1 1 0 1 1 */ #define VAL_DDRD 0x08 -#define VAL_PORTD 0xF8 +#define VAL_PORTD 0xFB /* PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0 * IN IN OUT OUT IN IN OUT IN @@ -67,12 +67,12 @@ /* TDI TDO TMS TCK PF3 PF2 PF1 PF0 * x x x x IN IN IN IN * DDRF 0 0 0 0 0 0 0 0 - * PU PU PU PU PU PU PU PU - * PORTF 1 1 1 1 1 1 1 1 + * x x x x PU PU PU PU + * PORTF 0 0 0 0 1 1 1 1 * */ #define VAL_DDRF 0x00 -#define VAL_PORTF 0xFF +#define VAL_PORTF 0x0F /* x x x x x PG2 PG1 PG0 * x x x x x IN IN IN @@ -99,6 +99,8 @@ #define PORTC_44780_D5 (1 << 5) #define PORTC_44780_D6 (1 << 6) #define PORTC_44780_D7 (1 << 7) +#define PORTC_44780_DATA (PORTC_44780_D4 | PORTC_44780_D5 | \ + PORTC_44780_D6 | PORTC_44780_D7) #define PORTE_BUZZ1 (1 << 4) #define PORTE_BUZZ2 (1 << 5) diff --git a/demos/AVR-ATmega128-GCC/lcd.c b/demos/AVR-ATmega128-GCC/lcd.c new file mode 100644 index 000000000..eed0c896e --- /dev/null +++ b/demos/AVR-ATmega128-GCC/lcd.c @@ -0,0 +1,97 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include + +#include "board.h" +#include "lcd.h" + +static void e_pulse(void) { + volatile uint8_t i; + + PORTC |= PORTC_44780_E; + for (i = 0; i < ELOOPVALUE; i++); + ; + PORTC &= ~PORTC_44780_E; +} + +static void wait_not_busy(void) { + + chThdSleep(2); +} + +/* + * 44780 soft reset procedure. + */ +void lcdInit(void) { + + PORTC = (PORTC & ~(PORTC_44780_DATA | PORTC_44780_RS | PORTC_44780_E | PORTC_44780_RW)) | + (LCD_CMD_INIT8 & PORTC_44780_DATA); + chThdSleep(50); + e_pulse(); + chThdSleep(10); + e_pulse(); + chThdSleep(2); + e_pulse(); + wait_not_busy(); + PORTC = (PORTC & ~(PORTC_44780_DATA | PORTC_44780_RS | PORTC_44780_E | PORTC_44780_RW)) | + (LCD_CMD_INIT4 & PORTC_44780_DATA); + e_pulse(); + lcdCmd(LCD_CMD_INIT4); + lcdCmd(LCD_SET_DM | LCD_DM_DISPLAY_ON); + lcdCmd(LCD_SET_INCREMENT_MODE); +} + +/* + * Sends a command byte to the 44780. + */ +void lcdCmd(uint8_t cmd) { + + wait_not_busy(); + PORTC = (PORTC | PORTC_44780_DATA) & (cmd | (0x0F & ~PORTC_44780_RS)); + e_pulse(); + PORTC = (PORTC | PORTC_44780_DATA) & ((cmd << 4) | (0x0F & ~PORTC_44780_RS)); + e_pulse(); +} + +/* + * Writes a char on the LCD at the current position. + */ +void lcdPutc(char c) { + uint8_t b; + + wait_not_busy(); + b = c | 0x0F; + PORTC = (PORTC | PORTC_44780_DATA | PORTC_44780_RS) & (c | 0x0F); + e_pulse(); + PORTC = (PORTC | PORTC_44780_DATA | PORTC_44780_RS) & ((c << 4) | 0x0F); + e_pulse(); +} + +/* + * Writes a string on the LCD at an absolute address. + */ +void lcdPuts(uint8_t pos, char *p) { + + lcdCmd(LCD_SET_DDRAM_ADDRESS | pos); + while (*p) + lcdPutc(*p++); +} diff --git a/demos/AVR-ATmega128-GCC/lcd.h b/demos/AVR-ATmega128-GCC/lcd.h new file mode 100644 index 000000000..12ffd127e --- /dev/null +++ b/demos/AVR-ATmega128-GCC/lcd.h @@ -0,0 +1,52 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _LCD_H_ +#define _LCD_H_ + +#define ELOOPVALUE 10 + +#define LCD_CLEAR 0x01 + +#define LCD_RETURN_HOME 0x02 + +#define LCD_SET_INCREMENT_MODE 0x06 + +#define LCD_SET_DM 0x08 +#define LCD_DM_DISPLAY_ON 4 +#define LCD_DM_DISPLAY_OFF 0 +#define LCD_DM_CURSOR_ON 2 +#define LCD_DM_CURSOR_OFF 0 +#define LCD_DM_BLINK_ON 1 +#define LCD_DM_BLINK_OFF 0 + +#define LCD_CMD_INIT4 0x28 +#define LCD_CMD_INIT8 0x38 + +#define LCD_SET_DDRAM_ADDRESS 0x80 + +#define LCD_LINE1 0 +#define LCD_LINE2 40 + +void lcdInit(void); +void lcdCmd(uint8_t cmd); +void lcdPutc(char c); +void lcdPuts(uint8_t pos, char *p); + +#endif /* _LCD_H_ */ diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 29a19701b..53fe21b2d 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -24,6 +24,7 @@ #include #include "board.h" +#include "lcd.h" void hwinit(void); @@ -31,7 +32,8 @@ static WorkingArea(waThread1, 32); static msg_t Thread1(void *arg) { while (TRUE) { - PORTA ^= PORTA_RELAY; + if (!(PINA & PORTA_BUTTON2)) + PORTA ^= PORTA_RELAY; chThdSleep(1000); } return 0; @@ -40,7 +42,7 @@ static msg_t Thread1(void *arg) { static void TimerHandler(eventid_t id) { msg_t TestThread(void *p); - if (!(PORTA & PORTA_BUTTON1)) + if (!(PINA & PORTA_BUTTON1)) TestThread(&SER2); } @@ -59,6 +61,15 @@ int main(int argc, char **argv) { */ chSysInit(); + /* + * This initialization requires the OS already active because it uses delay + * APIs inside. + */ + lcdInit(); + lcdCmd(LCD_CLEAR); + lcdPuts(LCD_LINE1, " ChibiOS/RT "); + lcdPuts(LCD_LINE2, " Hello World! "); + /* * Event Timer initialization. */ diff --git a/demos/AVR-ATmega128-GCC/readme.txt b/demos/AVR-ATmega128-GCC/readme.txt index 1c6ab3c5d..7158463fb 100644 --- a/demos/AVR-ATmega128-GCC/readme.txt +++ b/demos/AVR-ATmega128-GCC/readme.txt @@ -8,8 +8,8 @@ The demo runs on an Olimex AVR-MT-128 board. ** The Demo ** -The demo currently just toggles the relay using a thread. It will be expanded -in next releases. +The demo currently just writes a hello world on the LCD and toggles the relay +using a thread while button 2 is pressed. By pressing the button 1 the test suite is activated, output on serial port 2. ** Build Procedure ** -- cgit v1.2.3 From 88c256ae5265f5d6a7ffa25dc17f693e036256bf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 11 Mar 2008 14:32:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@222 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index c94b88fdb..5e1211efa 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -103,7 +103,7 @@ TOPT = -mthumb -D THUMB # increases the code size. OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing #OPT += -ffixed-r7 -OPT += -falign-functions=16 +#OPT += -falign-functions=16 # Define warning options here WARN = -Wall -Wstrict-prototypes diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 76a4459fd..64d348ad5 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -103,7 +103,7 @@ TOPT = -mthumb -D THUMB # increases the code size. OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing #OPT += -ffixed-r7 -OPT += -falign-functions=16 +#OPT += -falign-functions=16 # Define warning options here WARN = -Wall -Wstrict-prototypes -- cgit v1.2.3 From 777291ac8aaed233aa79bb4388ff3485e4c19de1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 12 Mar 2008 21:05:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@228 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/AVR-AT90CANx-GCC/Makefile | 2 +- demos/AVR-ATmega128-GCC/Makefile | 2 +- demos/Win32-MinGW/Makefile | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 5e1211efa..ea39d57e2 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -101,7 +101,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -O2 -ggdb -fomit-frame-pointer #OPT += -ffixed-r7 #OPT += -falign-functions=16 diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 64d348ad5..50883c63f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -101,7 +101,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -Os -ggdb -fomit-frame-pointer #OPT += -ffixed-r7 #OPT += -falign-functions=16 diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index d8ed9ed9b..7d7e8874c 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -99,7 +99,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -O2 -ggdb -fomit-frame-pointer #OPT += -ffixed-r7 OPT += -falign-functions=16 diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 621e71853..0df66f2d3 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -99,7 +99,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -Os -ggdb -fomit-frame-pointer #OPT += -ffixed-r7 OPT += -falign-functions=16 diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 5168f764a..32f08943e 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -102,7 +102,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -O2 -ggdb -fomit-frame-pointer #OPT += -ffixed-r7 OPT += -falign-functions=16 diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index 106c3c390..37c56acf9 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -161,7 +161,7 @@ CFLAGS += -funsigned-char CFLAGS += -funsigned-bitfields CFLAGS += -fpack-struct CFLAGS += -fshort-enums -CFLAGS += -fno-strict-aliasing +#CFLAGS += -fno-strict-aliasing CFLAGS += -Wall CFLAGS += -Wstrict-prototypes #CFLAGS += -mshort-calls diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index 34c228691..3be566c19 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -161,7 +161,7 @@ CFLAGS += -funsigned-char CFLAGS += -funsigned-bitfields CFLAGS += -fpack-struct CFLAGS += -fshort-enums -CFLAGS += -fno-strict-aliasing +#CFLAGS += -fno-strict-aliasing CFLAGS += -Wall CFLAGS += -Wstrict-prototypes #CFLAGS += -mshort-calls diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 8d4edec7e..ea206b0d0 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -76,7 +76,7 @@ ULIBDIR = ULIBS = # Define optimisation level here -OPT = -Os -fomit-frame-pointer -fno-strict-aliasing +OPT = -Os -fomit-frame-pointer # # End of user defines -- cgit v1.2.3 From 611ff4d2ed3e92f9f577f7dc320b1557e96d381f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 13 Mar 2008 14:41:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@231 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 165 +++++++++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/board.c | 28 ++++++ demos/ARMCM3-STM32F103-GCC/board.h | 25 ++++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 169 ++++++++++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/main.c | 57 ++++++++++++ 5 files changed, 444 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-GCC/Makefile create mode 100644 demos/ARMCM3-STM32F103-GCC/board.c create mode 100644 demos/ARMCM3-STM32F103-GCC/board.h create mode 100644 demos/ARMCM3-STM32F103-GCC/chconf.h create mode 100644 demos/ARMCM3-STM32F103-GCC/main.c (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile new file mode 100644 index 000000000..2de43bf20 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -0,0 +1,165 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = cortex-m3 + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +SRC = ../../ports/ARMCM3/chcore.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + board.c main.c + +# List ASM source files here +ASMSRC = +#../../ports/ARMCM3/crt0.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../ports/ARMCM3 + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -O2 -ggdb -fomit-frame-pointer +#OPT += -ffixed-r7 +#OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +COBJS = $(SRC:.c=.o) +ASMOBJS = $(ASMSRC:.s=.o) +OBJS = $(ASMOBJS) $(COBJS) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) -mthumb + +ASFLAGS = $(MCFLAGS) -mthumb -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(COBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(COBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c new file mode 100644 index 000000000..ec5ac2fb4 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { + +} diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h new file mode 100644 index 000000000..88459c3e7 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -0,0 +1,25 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define BOARD_OLIMEX_STM32_P103 + +#endif /* _BOARD_H_ */ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h new file mode 100644 index 000000000..c8817f85c --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +//#define CH_USE_MESSAGES_PRIORITY + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c new file mode 100644 index 000000000..60e53abd3 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WorkingArea(waThread1, 64); +static msg_t Thread1(void *arg) { + + while (TRUE) { + chThdSleep(1000); + } + return 0; +} + +/* + * Entry point, the interrupts are disabled on entry. + */ +int main(int argc, char **argv) { + + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ + chSysInit(); + + /* + * Creates the blinker threads. + */ + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop. + */ + while (TRUE) + chThdSleep(1000); + return 0; +} -- cgit v1.2.3 From 721061da2af13b2887962b8649507b3f0f47aabc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 14 Mar 2008 14:53:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@232 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 5 +-- demos/ARMCM3-STM32F103-GCC/ch.ld | 80 +++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 3 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/ch.ld (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 2de43bf20..dc01e39e3 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -71,8 +71,7 @@ SRC = ../../ports/ARMCM3/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = -#../../ports/ARMCM3/crt0.s +ASMSRC = ../../ports/ARMCM3/crt0.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARMCM3 @@ -109,7 +108,7 @@ OBJS = $(ASMOBJS) $(COBJS) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) -mthumb -ASFLAGS = $(MCFLAGS) -mthumb -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld new file mode 100644 index 000000000..2ddc2aab4 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 20k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : + { + _text = .; + *(.text); + *(.rodata); + *(.rodata*); + *(.glue_7t); + *(.glue_7); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; -- cgit v1.2.3 From 24359085b9ed5368480ef7a21af26b83879a351e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 17 Mar 2008 15:43:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@239 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/ch.ld | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index dc01e39e3..5b0e8f23e 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -71,7 +71,7 @@ SRC = ../../ports/ARMCM3/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARMCM3/crt0.s +ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../ports/ARMCM3 diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index 2ddc2aab4..96c5a3a1d 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -41,6 +41,7 @@ SECTIONS .text : { _text = .; + *(INTVEC); *(.text); *(.rodata); *(.rodata*); -- cgit v1.2.3 From d63f9c27be96d7b947b18b82d4398c4aa95d71ba Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 19 Mar 2008 15:17:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@242 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/readme.txt | 27 + .../ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h | 51 ++ .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h | 142 ++++ .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h | 857 +++++++++++++++++++++ .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h | 80 ++ 5 files changed, 1157 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-GCC/readme.txt create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt new file mode 100644 index 000000000..33c94445b --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -0,0 +1,27 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** +***************************************************************************** + +** TARGET ** + +The demo will on an Olimex STM32-P103 board. + +** The Demo ** + +Not complete yet. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license, see the header +present in all the source files under ./demos/ARMCM3-STM32F103/stm32lib for +details. +Also note that not all the files present in the ST library are distribuited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h new file mode 100644 index 000000000..822d01910 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h @@ -0,0 +1,51 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : cortexm3_macro.h +* Author : MCD Application Team +* Version : V1.0 +* Date : 10/08/2007 +* Description : Header file for cortexm3_macro.s. +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CORTEXM3_MACRO_H +#define __CORTEXM3_MACRO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void __WFI(void); +void __WFE(void); +void __SEV(void); +void __ISB(void); +void __DSB(void); +void __DMB(void); +void __SVC(void); +u32 __MRS_CONTROL(void); +void __MSR_CONTROL(u32 Control); +u32 __MRS_PSP(void); +void __MSR_PSP(u32 TopOfProcessStack); +u32 __MRS_MSP(void); +void __MSR_MSP(u32 TopOfMainStack); +void __SETPRIMASK(void); +void __RESETPRIMASK(void); +void __SETFAULTMASK(void); +void __RESETFAULTMASK(void); +void __BASEPRICONFIG(u32 NewPriority); +u32 __GetBASEPRI(void); +u16 __REV_HalfWord(u16 Data); +u32 __REV_Word(u32 Data); + +#endif /* __CORTEXM3_MACRO_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h new file mode 100644 index 000000000..59ae65d01 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h @@ -0,0 +1,142 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_conf.h +* Author : MCD Application Team +* Version : V1.0 +* Date : 10/08/2007 +* Description : Library configuration file. +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to compile the library in DEBUG mode, this will expanse + the "assert_param" macro in the firmware library code (see "Exported macro" + section below) */ +/* #define DEBUG 1*/ + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ADC ************************************/ +//#define _ADC +//#define _ADC1 +//#define _ADC2 + +/************************************* BKP ************************************/ +//#define _BKP + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* DMA ************************************/ +//#define _DMA +//#define _DMA_Channel1 +//#define _DMA_Channel2 +//#define _DMA_Channel3 +//#define _DMA_Channel4 +//#define _DMA_Channel5 +//#define _DMA_Channel6 +//#define _DMA_Channel7 + +/************************************* EXTI ***********************************/ +//#define _EXTI + +/************************************* FLASH and Option Bytes *****************/ +#define _FLASH +/* Uncomment the line below to enable FLASH program/erase/protections functions, + otherwise only FLASH configuration (latency, prefetch, half cycle) functions + are enabled */ +/* #define _FLASH_PROG */ + +/************************************* GPIO ***********************************/ +//#define _GPIO +//#define _GPIOA +//#define _GPIOB +//#define _GPIOC +//#define _GPIOD +//#define _GPIOE +//#define _AFIO + +/************************************* I2C ************************************/ +//#define _I2C +//#define _I2C1 +//#define _I2C2 + +/************************************* IWDG ***********************************/ +//#define _IWDG + +/************************************* NVIC ***********************************/ +#define _NVIC + +/************************************* PWR ************************************/ +//#define _PWR + +/************************************* RCC ************************************/ +#define _RCC + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* SPI ************************************/ +//#define _SPI +//#define _SPI1 +//#define _SPI2 + +/************************************* SysTick ********************************/ +//#define _SysTick + +/************************************* TIM1 ***********************************/ +//#define _TIM1 + +/************************************* TIM ************************************/ +//#define _TIM +//#define _TIM2 +//#define _TIM3 +//#define _TIM4 + +/************************************* USART **********************************/ +//#define _USART +//#define _USART1 +//#define _USART2 +//#define _USART3 + +/************************************* WWDG ***********************************/ +//#define _WWDG + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef DEBUG +/******************************************************************************* +* Macro Name : assert_param +* Description : The assert_param macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define assert_param(expr) ((void)0) +#endif /* DEBUG */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h new file mode 100644 index 000000000..410d78a6a --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h @@ -0,0 +1,857 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_map.h +* Author : MCD Application Team +* Version : V1.0 +* Date : 10/08/2007 +* Description : This file contains all the peripheral register's definitions +* and memory mapping. +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_MAP_H +#define __STM32F10x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_conf.h" +#include "stm32f10x_type.h" +#include "cortexm3_macro.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Peripheral registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu32 SR; + vu32 CR1; + vu32 CR2; + vu32 SMPR1; + vu32 SMPR2; + vu32 JOFR1; + vu32 JOFR2; + vu32 JOFR3; + vu32 JOFR4; + vu32 HTR; + vu32 LTR; + vu32 SQR1; + vu32 SQR2; + vu32 SQR3; + vu32 JSQR; + vu32 JDR1; + vu32 JDR2; + vu32 JDR3; + vu32 JDR4; + vu32 DR; +} ADC_TypeDef; + +/*------------------------ Backup Registers ----------------------------------*/ +typedef struct +{ + u32 RESERVED0; + vu16 DR1; + u16 RESERVED1; + vu16 DR2; + u16 RESERVED2; + vu16 DR3; + u16 RESERVED3; + vu16 DR4; + u16 RESERVED4; + vu16 DR5; + u16 RESERVED5; + vu16 DR6; + u16 RESERVED6; + vu16 DR7; + u16 RESERVED7; + vu16 DR8; + u16 RESERVED8; + vu16 DR9; + u16 RESERVED9; + vu16 DR10; + u16 RESERVED10; + vu16 RTCCR; + u16 RESERVED11; + vu16 CR; + u16 RESERVED12; + vu16 CSR; + u16 RESERVED13; +} BKP_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu32 TIR; + vu32 TDTR; + vu32 TDLR; + vu32 TDHR; +} CAN_TxMailBox_TypeDef; + +typedef struct +{ + vu32 RIR; + vu32 RDTR; + vu32 RDLR; + vu32 RDHR; +} CAN_FIFOMailBox_TypeDef; + +typedef struct +{ + vu32 FR0; + vu32 FR1; +} CAN_FilterRegister_TypeDef; + +typedef struct +{ + vu32 MCR; + vu32 MSR; + vu32 TSR; + vu32 RF0R; + vu32 RF1R; + vu32 IER; + vu32 ESR; + vu32 BTR; + u32 RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + u32 RESERVED1[12]; + vu32 FMR; + vu32 FM0R; + u32 RESERVED2[1]; + vu32 FS0R; + u32 RESERVED3[1]; + vu32 FFA0R; + u32 RESERVED4[1]; + vu32 FA0R; + u32 RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/*------------------------ DMA Controller ------------------------------------*/ +typedef struct +{ + vu32 CCR; + vu32 CNDTR; + vu32 CPAR; + vu32 CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + vu32 ISR; + vu32 IFCR; +} DMA_TypeDef; + +/*------------------------ External Interrupt/Event Controller ---------------*/ +typedef struct +{ + vu32 IMR; + vu32 EMR; + vu32 RTSR; + vu32 FTSR; + vu32 SWIER; + vu32 PR; +} EXTI_TypeDef; + +/*------------------------ FLASH and Option Bytes Registers ------------------*/ +typedef struct +{ + vu32 ACR; + vu32 KEYR; + vu32 OPTKEYR; + vu32 SR; + vu32 CR; + vu32 AR; + vu32 RESERVED; + vu32 OBR; + vu32 WRPR; +} FLASH_TypeDef; + +typedef struct +{ + vu16 RDP; + vu16 USER; + vu16 Data0; + vu16 Data1; + vu16 WRP0; + vu16 WRP1; + vu16 WRP2; + vu16 WRP3; +} OB_TypeDef; + +/*------------------------ General Purpose and Alternate Function IO ---------*/ +typedef struct +{ + vu32 CRL; + vu32 CRH; + vu32 IDR; + vu32 ODR; + vu32 BSRR; + vu32 BRR; + vu32 LCKR; +} GPIO_TypeDef; + +typedef struct +{ + vu32 EVCR; + vu32 MAPR; + vu32 EXTICR[4]; +} AFIO_TypeDef; + +/*------------------------ Inter-integrated Circuit Interface ----------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 OAR1; + u16 RESERVED2; + vu16 OAR2; + u16 RESERVED3; + vu16 DR; + u16 RESERVED4; + vu16 SR1; + u16 RESERVED5; + vu16 SR2; + u16 RESERVED6; + vu16 CCR; + u16 RESERVED7; + vu16 TRISE; + u16 RESERVED8; +} I2C_TypeDef; + +/*------------------------ Independent WATCHDOG ------------------------------*/ +typedef struct +{ + vu32 KR; + vu32 PR; + vu32 RLR; + vu32 SR; +} IWDG_TypeDef; + +/*------------------------ Nested Vectored Interrupt Controller --------------*/ +typedef struct +{ + vu32 ISER[2]; + u32 RESERVED0[30]; + vu32 ICER[2]; + u32 RSERVED1[30]; + vu32 ISPR[2]; + u32 RESERVED2[30]; + vu32 ICPR[2]; + u32 RESERVED3[30]; + vu32 IABR[2]; + u32 RESERVED4[62]; + vu32 IPR[11]; +} NVIC_TypeDef; + +typedef struct +{ + vuc32 CPUID; + vu32 ICSR; + vu32 VTOR; + vu32 AIRCR; + vu32 SCR; + vu32 CCR; + vu32 SHPR[3]; + vu32 SHCSR; + vu32 CFSR; + vu32 HFSR; + vu32 DFSR; + vu32 MMFAR; + vu32 BFAR; + vu32 AFSR; +} SCB_TypeDef; + +/*------------------------ Power Control -------------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CSR; +} PWR_TypeDef; + +/*------------------------ Reset and Clock Control ---------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFGR; + vu32 CIR; + vu32 APB2RSTR; + vu32 APB1RSTR; + vu32 AHBENR; + vu32 APB2ENR; + vu32 APB1ENR; + vu32 BDCR; + vu32 CSR; +} RCC_TypeDef; + +/*------------------------ Real-Time Clock -----------------------------------*/ +typedef struct +{ + vu16 CRH; + u16 RESERVED0; + vu16 CRL; + u16 RESERVED1; + vu16 PRLH; + u16 RESERVED2; + vu16 PRLL; + u16 RESERVED3; + vu16 DIVH; + u16 RESERVED4; + vu16 DIVL; + u16 RESERVED5; + vu16 CNTH; + u16 RESERVED6; + vu16 CNTL; + u16 RESERVED7; + vu16 ALRH; + u16 RESERVED8; + vu16 ALRL; + u16 RESERVED9; +} RTC_TypeDef; + +/*------------------------ Serial Peripheral Interface -----------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SR; + u16 RESERVED2; + vu16 DR; + u16 RESERVED3; + vu16 CRCPR; + u16 RESERVED4; + vu16 RXCRCR; + u16 RESERVED5; + vu16 TXCRCR; + u16 RESERVED6; +} SPI_TypeDef; + +/*------------------------ SystemTick ----------------------------------------*/ +typedef struct +{ + vu32 CTRL; + vu32 LOAD; + vu32 VAL; + vuc32 CALIB; +} SysTick_TypeDef; + +/*------------------------ Advanced Control Timer ----------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11; + vu16 RCR; + u16 RESERVED12; + vu16 CCR1; + u16 RESERVED13; + vu16 CCR2; + u16 RESERVED14; + vu16 CCR3; + u16 RESERVED15; + vu16 CCR4; + u16 RESERVED16; + vu16 BDTR; + u16 RESERVED17; + vu16 DCR; + u16 RESERVED18; + vu16 DMAR; + u16 RESERVED19; +} TIM1_TypeDef; + +/*------------------------ General Purpose Timer -----------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11[3]; + vu16 CCR1; + u16 RESERVED12; + vu16 CCR2; + u16 RESERVED13; + vu16 CCR3; + u16 RESERVED14; + vu16 CCR4; + u16 RESERVED15[3]; + vu16 DCR; + u16 RESERVED16; + vu16 DMAR; + u16 RESERVED17; +} TIM_TypeDef; + +/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ +typedef struct +{ + vu16 SR; + u16 RESERVED0; + vu16 DR; + u16 RESERVED1; + vu16 BRR; + u16 RESERVED2; + vu16 CR1; + u16 RESERVED3; + vu16 CR2; + u16 RESERVED4; + vu16 CR3; + u16 RESERVED5; + vu16 GTPR; + u16 RESERVED6; +} USART_TypeDef; + +/*------------------------ Window WATCHDOG -----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFR; + vu32 SR; +} WWDG_TypeDef; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Peripheral and SRAM base address in the alias region */ +#define PERIPH_BB_BASE ((u32)0x42000000) +#define SRAM_BB_BASE ((u32)0x22000000) + +/* Peripheral and SRAM base address in the bit-band region */ +#define SRAM_BASE ((u32)0x20000000) +#define PERIPH_BASE ((u32)0x40000000) + +/* Flash refisters base address */ +#define FLASH_BASE ((u32)0x40022000) +/* Flash Option Bytes base address */ +#define OB_BASE ((u32)0x1FFFF800) + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define DMA_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) + +/* System Control Space memory map */ +#define SCS_BASE ((u32)0xE000E000) + +#define SysTick_BASE (SCS_BASE + 0x0010) +#define NVIC_BASE (SCS_BASE + 0x0100) +#define SCB_BASE (SCS_BASE + 0x0D00) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/*------------------------ Non Debug Mode ------------------------------------*/ +#ifndef DEBUG +#ifdef _TIM2 + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#endif /*_TIM2 */ + +#ifdef _TIM3 + #define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#endif /*_TIM3 */ + +#ifdef _TIM4 + #define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#endif /*_TIM4 */ + +#ifdef _RTC + #define RTC ((RTC_TypeDef *) RTC_BASE) +#endif /*_RTC */ + +#ifdef _WWDG + #define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#endif /*_WWDG */ + +#ifdef _IWDG + #define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#endif /*_IWDG */ + +#ifdef _SPI2 + #define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#endif /*_SPI2 */ + +#ifdef _USART2 + #define USART2 ((USART_TypeDef *) USART2_BASE) +#endif /*_USART2 */ + +#ifdef _USART3 + #define USART3 ((USART_TypeDef *) USART3_BASE) +#endif /*_USART3 */ + +#ifdef _I2C1 + #define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#endif /*_I2C1 */ + +#ifdef _I2C2 + #define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#endif /*_I2C2 */ + +#ifdef _CAN + #define CAN ((CAN_TypeDef *) CAN_BASE) +#endif /*_CAN */ + +#ifdef _BKP + #define BKP ((BKP_TypeDef *) BKP_BASE) +#endif /*_BKP */ + +#ifdef _PWR + #define PWR ((PWR_TypeDef *) PWR_BASE) +#endif /*_PWR */ + +#ifdef _AFIO + #define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#endif /*_AFIO */ + +#ifdef _EXTI + #define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#endif /*_EXTI */ + +#ifdef _GPIOA + #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#endif /*_GPIOA */ + +#ifdef _GPIOB + #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#endif /*_GPIOB */ + +#ifdef _GPIOC + #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#endif /*_GPIOC */ + +#ifdef _GPIOD + #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#endif /*_GPIOD */ + +#ifdef _GPIOE + #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#endif /*_GPIOE */ + +#ifdef _ADC1 + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#endif /*_ADC1 */ + +#ifdef _ADC2 + #define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#endif /*_ADC2 */ + +#ifdef _TIM1 + #define TIM1 ((TIM1_TypeDef *) TIM1_BASE) +#endif /*_TIM1 */ + +#ifdef _SPI1 + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#endif /*_SPI1 */ + +#ifdef _USART1 + #define USART1 ((USART_TypeDef *) USART1_BASE) +#endif /*_USART1 */ + +#ifdef _DMA + #define DMA ((DMA_TypeDef *) DMA_BASE) +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE) +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE) +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE) +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE) +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE) +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE) +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE) +#endif /*_DMA_Channel7 */ + +#ifdef _FLASH + #define FLASH ((FLASH_TypeDef *) FLASH_BASE) + #define OB ((OB_TypeDef *) OB_BASE) +#endif /*_FLASH */ + +#ifdef _RCC + #define RCC ((RCC_TypeDef *) RCC_BASE) +#endif /*_RCC */ + +#ifdef _SysTick + #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#endif /*_SysTick */ + +#ifdef _NVIC + #define NVIC ((NVIC_TypeDef *) NVIC_BASE) + #define SCB ((SCB_TypeDef *) SCB_BASE) +#endif /*_NVIC */ + +/*------------------------ Debug Mode ----------------------------------------*/ +#else /* DEBUG */ +#ifdef _TIM2 + EXT TIM_TypeDef *TIM2; +#endif /*_TIM2 */ + +#ifdef _TIM3 + EXT TIM_TypeDef *TIM3; +#endif /*_TIM3 */ + +#ifdef _TIM4 + EXT TIM_TypeDef *TIM4; +#endif /*_TIM4 */ + +#ifdef _RTC + EXT RTC_TypeDef *RTC; +#endif /*_RTC */ + +#ifdef _WWDG + EXT WWDG_TypeDef *WWDG; +#endif /*_WWDG */ + +#ifdef _IWDG + EXT IWDG_TypeDef *IWDG; +#endif /*_IWDG */ + +#ifdef _SPI2 + EXT SPI_TypeDef *SPI2; +#endif /*_SPI2 */ + +#ifdef _USART2 + EXT USART_TypeDef *USART2; +#endif /*_USART2 */ + +#ifdef _USART3 + EXT USART_TypeDef *USART3; +#endif /*_USART3 */ + +#ifdef _I2C1 + EXT I2C_TypeDef *I2C1; +#endif /*_I2C1 */ + +#ifdef _I2C2 + EXT I2C_TypeDef *I2C2; +#endif /*_I2C2 */ + +#ifdef _CAN + EXT CAN_TypeDef *CAN; +#endif /*_CAN */ + +#ifdef _BKP + EXT BKP_TypeDef *BKP; +#endif /*_BKP */ + +#ifdef _PWR + EXT PWR_TypeDef *PWR; +#endif /*_PWR */ + +#ifdef _AFIO + EXT AFIO_TypeDef *AFIO; +#endif /*_AFIO */ + +#ifdef _EXTI + EXT EXTI_TypeDef *EXTI; +#endif /*_EXTI */ + +#ifdef _GPIOA + EXT GPIO_TypeDef *GPIOA; +#endif /*_GPIOA */ + +#ifdef _GPIOB + EXT GPIO_TypeDef *GPIOB; +#endif /*_GPIOB */ + +#ifdef _GPIOC + EXT GPIO_TypeDef *GPIOC; +#endif /*_GPIOC */ + +#ifdef _GPIOD + EXT GPIO_TypeDef *GPIOD; +#endif /*_GPIOD */ + +#ifdef _GPIOE + EXT GPIO_TypeDef *GPIOE; +#endif /*_GPIOE */ + +#ifdef _ADC1 + EXT ADC_TypeDef *ADC1; +#endif /*_ADC1 */ + +#ifdef _ADC2 + EXT ADC_TypeDef *ADC2; +#endif /*_ADC2 */ + +#ifdef _TIM1 + EXT TIM1_TypeDef *TIM1; +#endif /*_TIM1 */ + +#ifdef _SPI1 + EXT SPI_TypeDef *SPI1; +#endif /*_SPI1 */ + +#ifdef _USART1 + EXT USART_TypeDef *USART1; +#endif /*_USART1 */ + +#ifdef _DMA + EXT DMA_TypeDef *DMA; +#endif /*_DMA */ + +#ifdef _DMA_Channel1 + EXT DMA_Channel_TypeDef *DMA_Channel1; +#endif /*_DMA_Channel1 */ + +#ifdef _DMA_Channel2 + EXT DMA_Channel_TypeDef *DMA_Channel2; +#endif /*_DMA_Channel2 */ + +#ifdef _DMA_Channel3 + EXT DMA_Channel_TypeDef *DMA_Channel3; +#endif /*_DMA_Channel3 */ + +#ifdef _DMA_Channel4 + EXT DMA_Channel_TypeDef *DMA_Channel4; +#endif /*_DMA_Channel4 */ + +#ifdef _DMA_Channel5 + EXT DMA_Channel_TypeDef *DMA_Channel5; +#endif /*_DMA_Channel5 */ + +#ifdef _DMA_Channel6 + EXT DMA_Channel_TypeDef *DMA_Channel6; +#endif /*_DMA_Channel6 */ + +#ifdef _DMA_Channel7 + EXT DMA_Channel_TypeDef *DMA_Channel7; +#endif /*_DMA_Channel7 */ + +#ifdef _FLASH + EXT FLASH_TypeDef *FLASH; + EXT OB_TypeDef *OB; +#endif /*_FLASH */ + +#ifdef _RCC + EXT RCC_TypeDef *RCC; +#endif /*_RCC */ + +#ifdef _SysTick + EXT SysTick_TypeDef *SysTick; +#endif /*_SysTick */ + +#ifdef _NVIC + EXT NVIC_TypeDef *NVIC; + EXT SCB_TypeDef *SCB; +#endif /*_NVIC */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_MAP_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h new file mode 100644 index 000000000..92c8579e1 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_type.h +* Author : MCD Application Team +* Version : V1.0 +* Date : 10/08/2007 +* Description : This file contains all the common data types used for the +* STM32F10x firmware library. +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TYPE_H +#define __STM32F10x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)2147483648uL) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_TYPE_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3 From ef14f74f92fb52d0028eb36b7b48b7e7c4ef52c4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 27 Mar 2008 11:48:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@248 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 227 +++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-G++/Makefile.thumb | 199 +++++++++++++++++++++++++++++ demos/ARM7-LPC214x-G++/board.c | 135 ++++++++++++++++++++ demos/ARM7-LPC214x-G++/board.h | 64 ++++++++++ demos/ARM7-LPC214x-G++/ch.ld | 95 ++++++++++++++ demos/ARM7-LPC214x-G++/chconf.h | 169 ++++++++++++++++++++++++ demos/ARM7-LPC214x-G++/main.cpp | 141 ++++++++++++++++++++ demos/ARM7-LPC214x-G++/readme.txt | 25 ++++ demos/ARM7-LPC214x-GCC-minimal/board.c | 2 + 9 files changed, 1057 insertions(+) create mode 100644 demos/ARM7-LPC214x-G++/Makefile create mode 100644 demos/ARM7-LPC214x-G++/Makefile.thumb create mode 100644 demos/ARM7-LPC214x-G++/board.c create mode 100644 demos/ARM7-LPC214x-G++/board.h create mode 100644 demos/ARM7-LPC214x-G++/ch.ld create mode 100644 demos/ARM7-LPC214x-G++/chconf.h create mode 100644 demos/ARM7-LPC214x-G++/main.cpp create mode 100644 demos/ARM7-LPC214x-G++/readme.txt (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile new file mode 100644 index 000000000..087fa89d9 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -0,0 +1,227 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +CSRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + board.c + +# List ARM-mode C++ source files here +CPPSRC = ../../src/lib/ch.cpp main.cpp + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = + +# List ASM source files here +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-LPC214x + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -O2 -ggdb -fomit-frame-pointer +#OPT += -ffixed-r7 +OPT += -falign-functions=16 + +# C++ specific options here +# NOTE: -fno-rtti saves a LOT of code space, remove it only if you really need +# RTTI. +CPPOPT = -fno-rtti + +# Define warning options here +WARN = -Wall + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(CSRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +CPPOBJS = $(CPPSRC:.cpp=.o) +ASMOBJS = $(ASMSRC:.s=.o) +OBJS = $(ASMOBJS) $(CPPOBJS) $(AOBJS) $(TOBJS) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(WARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CFLAGS += -D THUMB_PRESENT + CPPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT + ifneq ($(CSRC),) + # Mixed ARM and THUMB case. + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CFLAGS += -D THUMB_NO_INTERWORKING + CPPFLAGS += -D THUMB_NO_INTERWORKING + LDFLAGS += -mthumb + ASFLAGS += -D THUMB_NO_INTERWORKING + endif +endif + +# Generate dependency information +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(CPPOBJS) : %.o : %.cpp + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(LD) $(ASMOBJS) $(AOBJS) $(TOBJS) $(CPPOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(CSRC:.c=.c.bak) + -rm -f $(CSRC:.c=.lst) + -rm -f $(CPPSRC:.cpp=.c.bak) + -rm -f $(CPPSRC:.cpp=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb new file mode 100644 index 000000000..0df66f2d3 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -0,0 +1,199 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +ASRC = + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + board.c main.c + +# List ASM source files here +ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib \ + ../../ports/ARM7 ../../ports/ARM7-LPC214x + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -Os -ggdb -fomit-frame-pointer +#OPT += -ffixed-r7 +OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -D THUMB_NO_INTERWORKING + LDFLAGS += -mthumb + ASFLAGS += -D THUMB_NO_INTERWORKING + endif +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c new file mode 100644 index 000000000..6f004ba29 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/board.c @@ -0,0 +1,135 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include +#include +#include +//#include "lpc214x_ssp.h" + +#include "board.h" +//#include "mmcsd.h" +//#include "buzzer.h" + +/* + * Non-vectored IRQs handling here. + */ +__attribute__((naked)) +static void IrqHandler(void) { + + chSysIRQEnterI(); + + /* nothing */ + VICVectAddr = 0; + + chSysIRQExitI(); +} + +/* + * Timer 0 IRQ handling here. + */ +__attribute__((naked)) +static void T0IrqHandler(void) { + + chSysIRQEnterI(); + + T0IR = 1; /* Clear interrupt on match MR0. */ + chSysTimerHandlerI(); + VICVectAddr = 0; + + chSysIRQExitI(); +} + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { + + /* + * All peripherals clock disabled by default in order to save power. + */ + PCONP = PCRTC | PCTIM0; + + /* + * MAM setup. + */ + MAMTIM = 0x3; /* 3 cycles for flash accesses. */ + MAMCR = 0x2; /* MAM fully enabled. */ + + /* + * PLL setup for Fosc=12MHz and CCLK=48MHz. + * P=2 M=3. + */ + PLL *pll = PLLBase; + pll->PLL0_CFG = 0x23; /* P and M values. */ + pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + while (!(pll->PLL0_STAT & 0x400)) + ; /* Wait for PLL lock. */ + + pll->PLL0_CON = 0x3; /* Connects the PLL. */ + pll->PLL0_FEED = 0xAA; + pll->PLL0_FEED = 0x55; + + /* + * VPB setup. + * PCLK = CCLK / 4. + */ + VPBDIV = VPD_D4; + + /* + * I/O pins configuration. + */ + PINSEL0 = VAL_PINSEL0; + PINSEL1 = VAL_PINSEL1; + PINSEL2 = VAL_PINSEL2; + IO0DIR = VAL_FIO0DIR; + IO0SET = 0xFFFFFFFF; + IO1DIR = VAL_FIO1DIR; + IO1SET = 0xFFFFFFFF; + + /* + * Interrupt vectors assignment. + */ + InitVIC(); + VICDefVectAddr = (IOREG32)IrqHandler; + + /* + * System Timer initialization, 1ms intervals. + */ + SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); + VICIntEnable = INTMASK(SOURCE_Timer0); + TC *timer = T0Base; + timer->TC_PR = VAL_TC0_PRESCALER; + timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); + timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ + timer->TC_TCR = 2; /* Reset counter and prescaler. */ + timer->TC_TCR = 1; /* Timer enabled. */ + + /* + * Other subsystems. + */ + InitSerial(1, 2); +// InitSSP(); +// InitMMC(); +// InitBuzzer(); +} diff --git a/demos/ARM7-LPC214x-G++/board.h b/demos/ARM7-LPC214x-G++/board.h new file mode 100644 index 000000000..c9d3f01b3 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/board.h @@ -0,0 +1,64 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define BOARD_OLIMEX_LCP_P2148 + +/* + * The following values are implementation dependent. You may change them in + * order to match your HW. + */ +#define FOSC 12000000 +#define CCLK 48000000 +#define PCLK 12000000 + +#define VAL_TC0_PRESCALER 0 + +/* + * Pins configuration for Olimex LPC-P2148. + * + * PINSEL0 + * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD + * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 + * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 + * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- + * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 + * + * PINSEL1 + * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 + * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 + * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 + * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN + * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 + * + * PINSEL2 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- + * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- + */ +#define VAL_PINSEL0 0x00055555 +#define VAL_PINSEL1 0x100840A8 +#define VAL_PINSEL2 0x00000004 +#define VAL_FIO0DIR 0xB0703C00 +#define VAL_FIO1DIR 0x00000000 + +#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld new file mode 100644 index 000000000..5fe907142 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -0,0 +1,95 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : + { + _text = .; + *(.text); + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h new file mode 100644 index 000000000..c8817f85c --- /dev/null +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +//#define CH_USE_MESSAGES_PRIORITY + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp new file mode 100644 index 000000000..b3c4f8e45 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -0,0 +1,141 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include +#include + +using namespace chibios_rt; + +/* + * LED blinking sequences. + */ +#define SLEEP 0 +#define STOP 1 +#define BITCLEAR 2 +#define BITSET 3 + +typedef struct { + uint8_t action; + uint32_t value; +} bitop_t; + +bitop_t LED1_sequence[] = +{ + {BITCLEAR, 0x00000400}, + {SLEEP, 200}, + {BITSET, 0x00000400}, + {SLEEP, 1800} +}; + +bitop_t LED2_sequence[] = +{ + {SLEEP, 1000}, + {BITCLEAR, 0x00000800}, + {SLEEP, 200}, + {BITSET, 0x00000800}, + {SLEEP, 800} +}; + +bitop_t LED3_sequence[] = +{ + {BITCLEAR, 0x80000000}, + {SLEEP, 200}, + {BITSET, 0x80000000}, + {SLEEP, 300} +}; + +/** + * LED blinker thread class. + */ +class BlinkerThread : chibios_rt::BaseThread { +private: + WorkingArea(wa, 64); + bitop_t *base, *curr, *top; + +protected: + virtual msg_t Main(void) { + + while (TRUE) { + switch(curr->action) { + case SLEEP: + Sleep(curr->value); + break; + case STOP: + return 0; + case BITCLEAR: + IO0CLR = curr->value; + break; + case BITSET: + IO0SET = curr->value; + break; + } + if (++curr >= top) + curr = base; + } + } + +public: + BlinkerThread(bitop_t *sequence, int n) : BaseThread(NORMALPRIO, 0, wa, sizeof wa) { + + base = curr = sequence; + top = sequence + n; + } +}; + +extern "C" { + msg_t TestThread(void *p); +} + +/* + * Executed as event handler at 500mS intervals. + */ +static void TimerHandler(eventid_t id) { + + if (!(IO0PIN & 0x00018000)) // Both buttons + TestThread(&COM1); +} + +/* + * Entry point, the interrupts are disabled on entry. + */ +int main(int argc, char **argv) { + static const evhandler_t evhndl[] = { + TimerHandler + }; + static EvTimer evt; + struct EventListener el0; + + System::Init(); + + evtInit(&evt, 500); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + + BlinkerThread blinker1(LED1_sequence, sizeof(LED1_sequence) / sizeof(bitop_t)); + BlinkerThread blinker2(LED2_sequence, sizeof(LED2_sequence) / sizeof(bitop_t)); + BlinkerThread blinker3(LED3_sequence, sizeof(LED3_sequence) / sizeof(bitop_t)); + + while(1) + Event::Wait(ALL_EVENTS, evhndl); + + return 0; +} diff --git a/demos/ARM7-LPC214x-G++/readme.txt b/demos/ARM7-LPC214x-G++/readme.txt new file mode 100644 index 000000000..8f99ee1d7 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI LPC214X using G++. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads implemented +as C++ classes. Pressing both buttons activates the test procedure on the +serial port 1. + +NOTE: the C++ GNU compiler can produce code sizes comparable to C if you + don't use RTTI and standard libraries, those are disabled by default + in the makefile. You can enable them if you have a lot of program space + available. It is possible to use a lot of C++ features without using + runtimes, just see the demo. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index ef86d8217..e140f2359 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -37,6 +37,7 @@ static void IrqHandler(void) { chSysIRQEnterI(); /* nothing */ + VICVectAddr = 0; chSysIRQExitI(); } @@ -51,6 +52,7 @@ static void T0IrqHandler(void) { T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); + VICVectAddr = 0; chSysIRQExitI(); } -- cgit v1.2.3 From 165bcc4a0708ff3252fe73156eace36b5980dbf9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 27 Mar 2008 12:33:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@249 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 2 +- demos/ARM7-LPC214x-G++/main.cpp | 52 ++++++++++++++++++++++++----------------- 2 files changed, 32 insertions(+), 22 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 087fa89d9..f2bdcd2ac 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -90,7 +90,7 @@ TSRC = ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib \ +UINCDIR = ../../src/include ../../src/lib ../../test \ ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index b3c4f8e45..1d8acfb5e 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -18,7 +18,9 @@ */ #include + #include +#include #include #include @@ -29,9 +31,10 @@ using namespace chibios_rt; * LED blinking sequences. */ #define SLEEP 0 -#define STOP 1 -#define BITCLEAR 2 -#define BITSET 3 +#define GOTO 1 +#define STOP 2 +#define BITCLEAR 3 +#define BITSET 4 typedef struct { uint8_t action; @@ -43,7 +46,8 @@ bitop_t LED1_sequence[] = {BITCLEAR, 0x00000400}, {SLEEP, 200}, {BITSET, 0x00000400}, - {SLEEP, 1800} + {SLEEP, 1800}, + {GOTO, 0} }; bitop_t LED2_sequence[] = @@ -52,7 +56,8 @@ bitop_t LED2_sequence[] = {BITCLEAR, 0x00000800}, {SLEEP, 200}, {BITSET, 0x00000800}, - {SLEEP, 800} + {SLEEP, 1800}, + {GOTO, 1} }; bitop_t LED3_sequence[] = @@ -60,13 +65,14 @@ bitop_t LED3_sequence[] = {BITCLEAR, 0x80000000}, {SLEEP, 200}, {BITSET, 0x80000000}, - {SLEEP, 300} + {SLEEP, 300}, + {GOTO, 0} }; /** - * LED blinker thread class. + * Blinker thread class. It can drive LEDs or other output pins. */ -class BlinkerThread : chibios_rt::BaseThread { +class BlinkerThread : BaseThread { private: WorkingArea(wa, 64); bitop_t *base, *curr, *top; @@ -79,6 +85,9 @@ protected: case SLEEP: Sleep(curr->value); break; + case GOTO: + curr = &base[curr->value]; + continue; case STOP: return 0; case BITCLEAR: @@ -88,23 +97,17 @@ protected: IO0SET = curr->value; break; } - if (++curr >= top) - curr = base; + curr++; } } public: - BlinkerThread(bitop_t *sequence, int n) : BaseThread(NORMALPRIO, 0, wa, sizeof wa) { + BlinkerThread(bitop_t *sequence) : BaseThread(NORMALPRIO, 0, wa, sizeof wa) { base = curr = sequence; - top = sequence + n; } }; -extern "C" { - msg_t TestThread(void *p); -} - /* * Executed as event handler at 500mS intervals. */ @@ -130,11 +133,18 @@ int main(int argc, char **argv) { evtStart(&evt); /* Starts the event timer. */ chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - BlinkerThread blinker1(LED1_sequence, sizeof(LED1_sequence) / sizeof(bitop_t)); - BlinkerThread blinker2(LED2_sequence, sizeof(LED2_sequence) / sizeof(bitop_t)); - BlinkerThread blinker3(LED3_sequence, sizeof(LED3_sequence) / sizeof(bitop_t)); - - while(1) + /* + * Starts serveral instances of the BlinkerThread class, each one operating + * on a different LED. + */ + BlinkerThread blinker1(LED1_sequence); + BlinkerThread blinker2(LED2_sequence); + BlinkerThread blinker3(LED3_sequence); + + /* + * Serves timer events. + */ + while (true) Event::Wait(ALL_EVENTS, evhndl); return 0; -- cgit v1.2.3 From b83cd4a1dc8b3240f821a23c588c8d7d690f70ae Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 27 Mar 2008 14:42:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@250 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 67 +++++++++++-------- demos/ARM7-LPC214x-G++/Makefile.thumb | 121 ++++++++++++++++++++++------------ demos/ARM7-LPC214x-G++/main.cpp | 39 ++++++----- 3 files changed, 140 insertions(+), 87 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index f2bdcd2ac..e05b79362 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -68,23 +68,24 @@ UDEFS = UADEFS = # List ARM-mode C source files here -CSRC = ../../ports/ARM7-LPC214x/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ - board.c +ACSRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + board.c # List ARM-mode C++ source files here -CPPSRC = ../../src/lib/ch.cpp main.cpp +ACPPSRC = ../../src/lib/ch.cpp main.cpp # List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = +TCSRC = + +# List THUMB-mode C++ source files here +TCPPSRC = # List ASM source files here ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s @@ -130,11 +131,15 @@ INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(CSRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -CPPOBJS = $(CPPSRC:.cpp=.o) +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRC = $(ASRC)$(TSRC) +ACOBJS = $(ACSRC:.c=.o) +ACPPOBJS = $(ACPPSRC:.cpp=.o) +TCOBJS = $(TCSRC:.c=.o) +TCPPOBJS = $(TCPPSRC:.cpp=.o) ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(CPPOBJS) $(AOBJS) $(TOBJS) +OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) @@ -149,7 +154,7 @@ ifneq ($(TSRC),) CFLAGS += -D THUMB_PRESENT CPPFLAGS += -D THUMB_PRESENT ASFLAGS += -D THUMB_PRESENT - ifneq ($(CSRC),) + ifneq ($(ASRC),) # Mixed ARM and THUMB case. CFLAGS += -mthumb-interwork CPPFLAGS += -mthumb-interwork @@ -173,15 +178,19 @@ CPPFLAGS += -MD -MP -MF .dep/$(@F).d all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp -$(CPPOBJS) : %.o : %.cpp +$(ACPPOBJS) : %.o : %.cpp @echo $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ -$(AOBJS) : %.o : %.c +$(TCPPOBJS) : %.o : %.cpp + @echo + $(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ACOBJS) : %.o : %.c @echo $(CC) -c $(CFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ -$(TOBJS) : %.o : %.c +$(TCOBJS) : %.o : %.c @echo $(CC) -c $(CFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ @@ -191,7 +200,7 @@ $(ASMOBJS) : %.o : %.s %elf: $(OBJS) @echo - $(LD) $(ASMOBJS) $(AOBJS) $(TOBJS) $(CPPOBJS) $(LDFLAGS) $(LIBS) -o $@ + $(LD) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) $(LDFLAGS) $(LIBS) -o $@ %hex: %elf $(HEX) $< $@ @@ -209,12 +218,14 @@ clean: -rm -f $(PROJECT).map -rm -f $(PROJECT).hex -rm -f $(PROJECT).bin - -rm -f $(CSRC:.c=.c.bak) - -rm -f $(CSRC:.c=.lst) - -rm -f $(CPPSRC:.cpp=.c.bak) - -rm -f $(CPPSRC:.cpp=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) + -rm -f $(ACSRC:.c=.c.bak) + -rm -f $(ACSRC:.c=.lst) + -rm -f $(TCSRC:.c=.c.bak) + -rm -f $(TCSRC:.c=.lst) + -rm -f $(ACPPSRC:.cpp=.c.bak) + -rm -f $(ACPPSRC:.cpp=.lst) + -rm -f $(TCPPSRC:.cpp=.c.bak) + -rm -f $(TCPPSRC:.cpp=.lst) -rm -f $(ASMSRC:.s=.s.bak) -rm -f $(ASMSRC:.s=.lst) -rm -fR .dep diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 0df66f2d3..16ab4d33f 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -18,6 +18,12 @@ TRGT = arm-elf- CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump @@ -62,24 +68,30 @@ UDEFS = UADEFS = # List ARM-mode C source files here -ASRC = +ACSRC = + +# List ARM-mode C++ source files here +ACPPSRC = # List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-LPC214x/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - board.c main.c +TCSRC = ../../ports/ARM7-LPC214x/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + board.c + +# List THUMB-mode C++ source files here +TCPPSRC = ../../src/lib/ch.cpp main.cpp # List ASM source files here ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib \ +UINCDIR = ../../src/include ../../src/lib ../../test \ ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here @@ -99,51 +111,66 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer +OPT = -O2 -ggdb -fomit-frame-pointer #OPT += -ffixed-r7 OPT += -falign-functions=16 +# C++ specific options here +# NOTE: -fno-rtti saves a LOT of code space, remove it only if you really need +# RTTI. +CPPOPT = -fno-rtti + # Define warning options here -WARN = -Wall -Wstrict-prototypes +WARN = -Wall # # End of user defines ############################################################################################## -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +ASRC = $(ACSRC)$(ACPPSRC) +TSRC = $(TCSRC)$(TCPPSRC) +SRC = $(ASRC)$(TSRC) +ACOBJS = $(ACSRC:.c=.o) +ACPPOBJS = $(ACPPSRC:.cpp=.o) +TCOBJS = $(TCSRC:.c=.o) +TCPPOBJS = $(TCPPSRC:.cpp=.o) +ASMOBJS = $(ASMSRC:.s=.o) +OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(WARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT + CFLAGS += -D THUMB_PRESENT + CPPFLAGS += -D THUMB_PRESENT ASFLAGS += -D THUMB_PRESENT ifneq ($(ASRC),) # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork + CFLAGS += -mthumb-interwork + CPPFLAGS += -mthumb-interwork LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -D THUMB_NO_INTERWORKING + CFLAGS += -D THUMB_NO_INTERWORKING + CPPFLAGS += -D THUMB_NO_INTERWORKING LDFLAGS += -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif endif # Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d +CFLAGS += -MD -MP -MF .dep/$(@F).d +CPPFLAGS += -MD -MP -MF .dep/$(@F).d # # Makefile rules @@ -151,13 +178,21 @@ CPFLAGS += -MD -MP -MF .dep/$(@F).d all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp -$(AOBJS) : %.o : %.c +$(ACPPOBJS) : %.o : %.cpp + @echo + $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TCPPOBJS) : %.o : %.cpp + @echo + $(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ACOBJS) : %.o : %.c @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + $(CC) -c $(CFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ -$(TOBJS) : %.o : %.c +$(TCOBJS) : %.o : %.c @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + $(CC) -c $(CFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ $(ASMOBJS) : %.o : %.s @echo @@ -165,7 +200,7 @@ $(ASMOBJS) : %.o : %.s %elf: $(OBJS) @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + $(LD) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) $(LDFLAGS) $(LIBS) -o $@ %hex: %elf $(HEX) $< $@ @@ -183,10 +218,14 @@ clean: -rm -f $(PROJECT).map -rm -f $(PROJECT).hex -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) + -rm -f $(ACSRC:.c=.c.bak) + -rm -f $(ACSRC:.c=.lst) + -rm -f $(TCSRC:.c=.c.bak) + -rm -f $(TCSRC:.c=.lst) + -rm -f $(ACPPSRC:.cpp=.c.bak) + -rm -f $(ACPPSRC:.cpp=.lst) + -rm -f $(TCPPSRC:.cpp=.c.bak) + -rm -f $(TCPPSRC:.cpp=.lst) -rm -f $(ASMSRC:.s=.s.bak) -rm -f $(ASMSRC:.s=.lst) -rm -fR .dep diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 1d8acfb5e..39b31e89a 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -28,7 +28,8 @@ using namespace chibios_rt; /* - * LED blinking sequences. + * LED blink sequences. + * NOTE: Sequences must always be terminated by a GOTO instruction. */ #define SLEEP 0 #define GOTO 1 @@ -39,9 +40,9 @@ using namespace chibios_rt; typedef struct { uint8_t action; uint32_t value; -} bitop_t; +} seqop_t; -bitop_t LED1_sequence[] = +static const seqop_t LED1_sequence[] = { {BITCLEAR, 0x00000400}, {SLEEP, 200}, @@ -50,7 +51,7 @@ bitop_t LED1_sequence[] = {GOTO, 0} }; -bitop_t LED2_sequence[] = +static const seqop_t LED2_sequence[] = { {SLEEP, 1000}, {BITCLEAR, 0x00000800}, @@ -60,7 +61,7 @@ bitop_t LED2_sequence[] = {GOTO, 1} }; -bitop_t LED3_sequence[] = +static const seqop_t LED3_sequence[] = { {BITCLEAR, 0x80000000}, {SLEEP, 200}, @@ -70,14 +71,16 @@ bitop_t LED3_sequence[] = }; /** - * Blinker thread class. It can drive LEDs or other output pins. + * Sequencer thread class. It can drive LEDs or other output pins. */ -class BlinkerThread : BaseThread { +class SequencerThread : BaseThread { private: - WorkingArea(wa, 64); - bitop_t *base, *curr, *top; + + WorkingArea(wa, 64); // Thread working area. + const seqop_t *base, *curr; // Thread local variables. protected: + virtual msg_t Main(void) { while (TRUE) { @@ -102,7 +105,7 @@ protected: } public: - BlinkerThread(bitop_t *sequence) : BaseThread(NORMALPRIO, 0, wa, sizeof wa) { + SequencerThread(const seqop_t *sequence) : BaseThread(NORMALPRIO, 0, wa, sizeof wa) { base = curr = sequence; } @@ -127,19 +130,19 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0; - System::Init(); + System::Init(); // ChibiOS/RT goes live here. - evtInit(&evt, 500); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + evtInit(&evt, 500); // Initializes an event timer object. + evtStart(&evt); // Starts the event timer. + chEvtRegister(&evt.et_es, &el0, 0); // Registers on the timer event source. /* - * Starts serveral instances of the BlinkerThread class, each one operating + * Starts serveral instances of the SequencerThread class, each one operating * on a different LED. */ - BlinkerThread blinker1(LED1_sequence); - BlinkerThread blinker2(LED2_sequence); - BlinkerThread blinker3(LED3_sequence); + SequencerThread blinker1(LED1_sequence); + SequencerThread blinker2(LED2_sequence); + SequencerThread blinker3(LED3_sequence); /* * Serves timer events. -- cgit v1.2.3 From 42a90cc8cebf186c64bbae50a16a90a9979b80f4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 28 Mar 2008 11:39:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@251 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/main.cpp | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 39b31e89a..b96a8271f 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -73,17 +73,14 @@ static const seqop_t LED3_sequence[] = /** * Sequencer thread class. It can drive LEDs or other output pins. */ -class SequencerThread : BaseThread { +class SequencerThread : EnhancedThread<64> { private: - - WorkingArea(wa, 64); // Thread working area. const seqop_t *base, *curr; // Thread local variables. protected: - virtual msg_t Main(void) { - while (TRUE) { + while (true) { switch(curr->action) { case SLEEP: Sleep(curr->value); @@ -105,7 +102,8 @@ protected: } public: - SequencerThread(const seqop_t *sequence) : BaseThread(NORMALPRIO, 0, wa, sizeof wa) { + SequencerThread(const seqop_t *sequence): + EnhancedThread<64>("sequencer", NORMALPRIO, 0) { base = curr = sequence; } -- cgit v1.2.3 From 64f96a5128c0358044efd962e0bcf7caee917348 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 28 Mar 2008 16:13:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@252 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/main.cpp | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index b96a8271f..37147fe91 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -30,6 +30,8 @@ using namespace chibios_rt; /* * LED blink sequences. * NOTE: Sequences must always be terminated by a GOTO instruction. + * NOTE: The sequencer language could be easily improved but this is outside + * the scope of this demo. */ #define SLEEP 0 #define GOTO 1 @@ -42,6 +44,7 @@ typedef struct { uint32_t value; } seqop_t; +// Flashing sequence for LED1. static const seqop_t LED1_sequence[] = { {BITCLEAR, 0x00000400}, @@ -51,6 +54,7 @@ static const seqop_t LED1_sequence[] = {GOTO, 0} }; +// Flashing sequence for LED2. static const seqop_t LED2_sequence[] = { {SLEEP, 1000}, @@ -61,6 +65,7 @@ static const seqop_t LED2_sequence[] = {GOTO, 1} }; +// Flashing sequence for LED3. static const seqop_t LED3_sequence[] = { {BITCLEAR, 0x80000000}, @@ -70,8 +75,10 @@ static const seqop_t LED3_sequence[] = {GOTO, 0} }; -/** +/* * Sequencer thread class. It can drive LEDs or other output pins. + * Any sequencer is just an instance of this class, all the details are + * totally encapsulated and hidden to the application level. */ class SequencerThread : EnhancedThread<64> { private: @@ -79,7 +86,6 @@ private: protected: virtual msg_t Main(void) { - while (true) { switch(curr->action) { case SLEEP: @@ -102,15 +108,14 @@ protected: } public: - SequencerThread(const seqop_t *sequence): - EnhancedThread<64>("sequencer", NORMALPRIO, 0) { + SequencerThread(const seqop_t *sequence) : EnhancedThread<64>("sequencer") { base = curr = sequence; } }; /* - * Executed as event handler at 500mS intervals. + * Executed as an event handler at 500mS intervals. */ static void TimerHandler(eventid_t id) { @@ -120,6 +125,7 @@ static void TimerHandler(eventid_t id) { /* * Entry point, the interrupts are disabled on entry. + * This is the real "application". */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -130,9 +136,9 @@ int main(int argc, char **argv) { System::Init(); // ChibiOS/RT goes live here. - evtInit(&evt, 500); // Initializes an event timer object. + evtInit(&evt, 500); // Initializes an event timer. evtStart(&evt); // Starts the event timer. - chEvtRegister(&evt.et_es, &el0, 0); // Registers on the timer event source. + chEvtRegister(&evt.et_es, &el0, 0); // Registers a listener on the source. /* * Starts serveral instances of the SequencerThread class, each one operating -- cgit v1.2.3 From 72dcfa88663999e2484463eaaa97ab861f2c7a19 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Apr 2008 15:34:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@256 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 20 +++++++++++ demos/ARMCM3-STM32F103-GCC/board.h | 39 ++++++++++++++++++++++ .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h | 20 +++++------ 3 files changed, 69 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index ec5ac2fb4..1d689bee8 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -19,10 +19,30 @@ #include +#include "board.h" + /* * Hardware initialization goes here. * NOTE: Interrupts are still disabled. */ void hwinit(void) { + /* + * I/O ports initialization as specified in board.h. + */ + GPIOA->CRL = VAL_GPIOACRL; + GPIOA->CRH = VAL_GPIOACRH; + GPIOA->ODR = VAL_GPIOAODR; + + GPIOB->CRL = VAL_GPIOBCRL; + GPIOB->CRH = VAL_GPIOBCRH; + GPIOB->ODR = VAL_GPIOBODR; + + GPIOC->CRL = VAL_GPIOCCRL; + GPIOC->CRH = VAL_GPIOCCRH; + GPIOC->ODR = VAL_GPIOCODR; + + GPIOD->CRL = VAL_GPIODCRL; + GPIOD->CRH = VAL_GPIODCRH; + GPIOD->ODR = VAL_GPIODODR; } diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 88459c3e7..cdb9d2588 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -20,6 +20,45 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#undef FALSE +#undef TRUE +#ifndef __STM32F10x_MAP_H +#include "stm32lib/stm32f10x_map.h" +#endif + #define BOARD_OLIMEX_STM32_P103 +#define LSECLK 32768 +#define HSECLK 8000000 +#define PLLDIV 1 +#define PLLMUL 9 +#define PLLCLK ((HSECLK / PLLDIV) * PLLMUL) + +#define GPIOA_BUTTON (1 << 0) + +#define GPIOC_MMCWP (1 << 6) +#define GPIOC_MMCCP (1 << 7) +#define GPIOC_CANCNTL (1 << 10) +#define GPIOC_DISC (1 << 11) +#define GPIOC_LED (1 << 12) + +/* + * All inputs with pullups unless otherwise specified. + */ +#define VAL_GPIOACRL 0x88888884 // PA0:FI +#define VAL_GPIOACRH 0x88888888 +#define VAL_GPIOAODR 0xFFFFFFFF + +#define VAL_GPIOBCRL 0x88883888 // PB3:PP +#define VAL_GPIOBCRH 0x88888888 +#define VAL_GPIOBODR 0xFFFFFFFF + +#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI +#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP +#define VAL_GPIOCODR 0xFFFFFFFF + +#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI +#define VAL_GPIODCRH 0x88888888 +#define VAL_GPIODODR 0xFFFFFFFF + #endif /* _BOARD_H_ */ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h index 59ae65d01..8e51a48fd 100644 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h @@ -34,7 +34,7 @@ //#define _ADC2 /************************************* BKP ************************************/ -//#define _BKP +//#define _BKP /************************************* CAN ************************************/ //#define _CAN @@ -60,11 +60,11 @@ /* #define _FLASH_PROG */ /************************************* GPIO ***********************************/ -//#define _GPIO -//#define _GPIOA -//#define _GPIOB -//#define _GPIOC -//#define _GPIOD +#define _GPIO +#define _GPIOA +#define _GPIOB +#define _GPIOC +#define _GPIOD //#define _GPIOE //#define _AFIO @@ -94,7 +94,7 @@ //#define _SPI2 /************************************* SysTick ********************************/ -//#define _SysTick +#define _SysTick /************************************* TIM1 ***********************************/ //#define _TIM1 @@ -123,13 +123,13 @@ /******************************************************************************* * Macro Name : assert_param * Description : The assert_param macro is used for function's parameters check. -* It is used only if the library is compiled in DEBUG mode. +* It is used only if the library is compiled in DEBUG mode. * Input : - expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source -* line number of the call that failed. +* line number of the call that failed. * If expr is true, it returns no value. * Return : None -*******************************************************************************/ +*******************************************************************************/ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(u8* file, u32 line); -- cgit v1.2.3 From b01aa7935cff4a5afe0505836b2b774a50f3c141 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 9 Apr 2008 15:26:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@257 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 46 ++++++++++++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/board.h | 40 +++++++++++++++++++++++++++++++-- 2 files changed, 84 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 1d689bee8..09636cb9d 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -21,15 +21,56 @@ #include "board.h" +/* + * Wait states setting is a function of the system clock. Those are the + * recommended values, there should not be need to change them. + */ +#if SYSCLK <= 24000000 +#define FLASHBITS 0x00000010 +#else +#if SYSCLK <= 48000000 +#define FLASHBITS 0x00000011 +#else +#define FLASHBITS 0x00000012 +#endif +#endif + /* * Hardware initialization goes here. * NOTE: Interrupts are still disabled. */ void hwinit(void) { + /* + * Clocks and PLL initialization. + */ + // HSI setup. + RCC->CR = 0x00000083; // Enforces a known state (HSI ON). + while (!(RCC->CR & (1 << 1))) + ; // Waits until HSI stable, it should already be. + // HSE setup. + RCC->CR |= (1 << 16); // HSE ON. + while (!(RCC->CR & (1 << 17))) + ; // Waits until HSE stable. + // PLL setup. + RCC->CFGR |= PLLPREBITS | PLLMULBITS | PLLSRCBITS; + RCC->CR |= (1 << 24); // PLL ON. + while (!(RCC->CR & (1 << 25))) + ; // Waits until PLL stable. + // Clock sources. + RCC->CFGR |= AHBBITS | PPRE1BITS | PPRE2BITS | ADCPREBITS | + USBPREBITS | MCOSRCBITS; + + /* + * Flash setup and final clock selection. + */ + FLASH->ACR = FLASHBITS; // Flash wait states depending on clock. + RCC->CFGR |= SYSSRCBITS; // Switches on the PLL clock. + /* * I/O ports initialization as specified in board.h. */ + RCC->APB2ENR = 0x0000003D; // Ports A-D enabled, AFIO enabled. GPIOA->CRL = VAL_GPIOACRL; GPIOA->CRH = VAL_GPIOACRH; GPIOA->ODR = VAL_GPIOAODR; @@ -45,4 +86,9 @@ void hwinit(void) { GPIOD->CRL = VAL_GPIODCRL; GPIOD->CRH = VAL_GPIODCRH; GPIOD->ODR = VAL_GPIODODR; + + /* + * NVIC/SCB setup. + */ + SCB->AIRCR = (0x5FA << 16) | (0x5 << 8); // PRIGROUP = 5 (2:6). } diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index cdb9d2588..b06745010 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -28,11 +28,47 @@ #define BOARD_OLIMEX_STM32_P103 +/* + * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. + */ +//#define SYSCLK_48 + +/* + * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. + */ #define LSECLK 32768 #define HSECLK 8000000 -#define PLLDIV 1 +#define HSICLK 8000000 +#define PLLPRE 1 +#ifdef SYSCLK_48 +#define PLLMUL 6 +#else #define PLLMUL 9 -#define PLLCLK ((HSECLK / PLLDIV) * PLLMUL) +#endif +#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) +#define SYSCLK PLLCLK +#define APB1CLK (SYSCLK / 2) +#define APB2CLK (SYSCLK / 2) +#define AHB1CLK (SYSCLK / 1) + +/* + * Various clock settings. + */ +#define SYSSRCBITS (0x2 << 0) // PLLCLK is SYSCLK (do not change) +#define AHBBITS (0x0 << 4) // Divided by 1 +#define PPRE1BITS (0x4 << 8) // Divided by 2 (must be <= 36MHz) +#define PPRE2BITS (0x4 << 11) // Divided by 2 +#define ADCPREBITS (0x3 << 14) // Divided by 8 +#define PLLSRCBITS (0x1 << 16) // PLL source is HSE/1 +#define PLLPREBITS ((PLLPRE - 1) << 17) +#define PLLMULBITS ((PLLMUL - 2) << 18) +#ifdef SYSCLK_48 +#define USBPREBITS (0x1 << 22) // Divided by 1 +#else +#define USBPREBITS (0x0 << 22) // Divided by 1.5 +#endif +#define MCOSRCBITS (0x0 << 24) // No MCO output. + #define GPIOA_BUTTON (1 << 0) -- cgit v1.2.3 From 2f99ed97a977f64fd7a11cb6cce569c879be4420 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Apr 2008 14:05:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@258 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/board.c | 35 ++++++++---- demos/ARMCM3-STM32F103-GCC/board.h | 65 ++++++++++++++++++---- .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h | 4 +- 4 files changed, 81 insertions(+), 25 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 5b0e8f23e..7fc33886a 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -62,7 +62,7 @@ UDEFS = UADEFS = # List ARM-mode C source files here -SRC = ../../ports/ARMCM3/chcore.c \ +SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 09636cb9d..631a13e0c 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" @@ -45,27 +46,29 @@ void hwinit(void) { * Clocks and PLL initialization. */ // HSI setup. - RCC->CR = 0x00000083; // Enforces a known state (HSI ON). - while (!(RCC->CR & (1 << 1))) + RCC->CR = HSITRIM_RESET_BITS | CR_HSION_MASK; + while (!(RCC->CR & CR_HSIRDY_MASK)) ; // Waits until HSI stable, it should already be. // HSE setup. - RCC->CR |= (1 << 16); // HSE ON. - while (!(RCC->CR & (1 << 17))) + RCC->CR |= CR_HSEON_MASK; + while (!(RCC->CR & CR_HSERDY_MASK)) ; // Waits until HSE stable. // PLL setup. - RCC->CFGR |= PLLPREBITS | PLLMULBITS | PLLSRCBITS; - RCC->CR |= (1 << 24); // PLL ON. - while (!(RCC->CR & (1 << 25))) + RCC->CFGR = PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; + RCC->CR |= CR_PLLON_MASK; + while (!(RCC->CR & CR_PLLRDY_MASK)) ; // Waits until PLL stable. // Clock sources. - RCC->CFGR |= AHBBITS | PPRE1BITS | PPRE2BITS | ADCPREBITS | - USBPREBITS | MCOSRCBITS; + RCC->CFGR |= HPRE_DIV1_BITS | PPRE1_DIV2_BITS | PPRE2_DIV2_BITS | + ADCPRE_DIV8_BITS | USBPREBITS | MCO_DISABLED_BITS; /* * Flash setup and final clock selection. */ FLASH->ACR = FLASHBITS; // Flash wait states depending on clock. - RCC->CFGR |= SYSSRCBITS; // Switches on the PLL clock. + RCC->CFGR |= SW_PLL_BITS; // Switches on the PLL clock. + while ((RCC->CFGR & CFGR_SWS_MASK) != SWS_PLL_BITS) + ; /* * I/O ports initialization as specified in board.h. @@ -88,7 +91,15 @@ void hwinit(void) { GPIOD->ODR = VAL_GPIODODR; /* - * NVIC/SCB setup. + * NVIC/SCB initialization. */ - SCB->AIRCR = (0x5FA << 16) | (0x5 << 8); // PRIGROUP = 5 (2:6). + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4). + + /* + * SysTick initialization. + */ + SCB_SHPR(2) = 0x10 << 24; // SysTick at priority 1:0 (highest - 1). + ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; + ST_CVR = 0; + ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; } diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index b06745010..fa47168ed 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -52,24 +52,69 @@ #define AHB1CLK (SYSCLK / 1) /* - * Various clock settings. + * Values derived from clock settings. */ -#define SYSSRCBITS (0x2 << 0) // PLLCLK is SYSCLK (do not change) -#define AHBBITS (0x0 << 4) // Divided by 1 -#define PPRE1BITS (0x4 << 8) // Divided by 2 (must be <= 36MHz) -#define PPRE2BITS (0x4 << 11) // Divided by 2 -#define ADCPREBITS (0x3 << 14) // Divided by 8 -#define PLLSRCBITS (0x1 << 16) // PLL source is HSE/1 #define PLLPREBITS ((PLLPRE - 1) << 17) #define PLLMULBITS ((PLLMUL - 2) << 18) #ifdef SYSCLK_48 -#define USBPREBITS (0x1 << 22) // Divided by 1 +#define USBPREBITS USBPRE_DIV1_BITS #else -#define USBPREBITS (0x0 << 22) // Divided by 1.5 +#define USBPREBITS USBPRE_DIV1P5_BITS #endif -#define MCOSRCBITS (0x0 << 24) // No MCO output. +/* + * Definitions for RCC_CR register. + */ +#define CR_HSION_MASK (0x1 << 0) +#define CR_HSIRDY_MASK (0x1 << 1) +#define CR_HSITRIM_MASK (0x1F << 3) +#define HSITRIM_RESET_BITS (1 << 3) +#define CR_HSICAL_MASK (0xFF << 8) +#define CR_HSEON_MASK (0x1 << 16) +#define CR_HSERDY_MASK (0x1 << 17) +#define CR_HSEBYP_MASK (0x1 << 18) +#define CR_CSSON_MASK (0x1 << 19) +#define CR_PLLON_MASK (0x1 << 24) +#define CR_PLLRDY_MASK (0x1 << 25) +/* + * Definitions for RCC_CFGR register. + */ +#define CFGR_SW_MASK (0x3 << 0) +#define SW_HSI_BITS (0 << 2) +#define SW_HSE_BITS (1 << 2) +#define SW_PLL_BITS (2 << 2) +#define CFGR_SWS_MASK (0x3 << 2) +#define SWS_HSI_BITS (0 << 2) +#define SWS_HSE_BITS (1 << 2) +#define SWS_PLL_BITS (2 << 2) +#define CFGR_HPRE_MASK (0xF << 4) +#define HPRE_DIV1_BITS (0 << 4) +#define CFGR_PPRE1_MASK (0x7 << 8) +#define PPRE1_DIV1_BITS (0 << 8) +#define PPRE1_DIV2_BITS (4 << 8) +#define CFGR_PPRE2_MASK (0x7 << 11) +#define PPRE2_DIV1_BITS (0 << 11) +#define PPRE2_DIV2_BITS (4 << 11) +#define CFGR_ADCPRE_MASK (0x3 << 14) +#define ADCPRE_DIV2_BITS (0 << 14) +#define ADCPRE_DIV4_BITS (1 << 14) +#define ADCPRE_DIV6_BITS (2 << 14) +#define ADCPRE_DIV8_BITS (3 << 14) +#define CFGR_PLLSRC_MASK (0x1 << 16) +#define PLLSRC_HSI_BITS (0 << 16) +#define PLLSRC_HSE_BITS (1 << 16) +#define CFGR_PLLXTPRE_MASK (0x1 << 17) +#define CFGR_PLLMUL_MASK (0xF << 18) +#define CFGR_USBPRE_MASK (0x1 << 22) +#define USBPRE_DIV1P5_BITS (0 << 22) +#define USBPRE_DIV1_BITS (1 << 22) +#define CFGR_MCO_MASK (0x7 << 24) +#define MCO_DISABLED_BITS (0 << 24) + +/* + * IO pins assignments. + */ #define GPIOA_BUTTON (1 << 0) #define GPIOC_MMCWP (1 << 6) diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h index 8e51a48fd..7df30d90d 100644 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h @@ -77,7 +77,7 @@ //#define _IWDG /************************************* NVIC ***********************************/ -#define _NVIC +//#define _NVIC /************************************* PWR ************************************/ //#define _PWR @@ -94,7 +94,7 @@ //#define _SPI2 /************************************* SysTick ********************************/ -#define _SysTick +//#define _SysTick /************************************* TIM1 ***********************************/ //#define _TIM1 -- cgit v1.2.3 From e1613c5169d7c792015d6a0bd2224626873af4e2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 11 Apr 2008 14:39:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@259 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 19 +++---------------- demos/ARMCM3-STM32F103-GCC/board.h | 18 ++++++++++-------- demos/ARMCM3-STM32F103-GCC/main.c | 6 ++++++ 3 files changed, 19 insertions(+), 24 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 631a13e0c..1323030f0 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -22,20 +22,6 @@ #include "board.h" -/* - * Wait states setting is a function of the system clock. Those are the - * recommended values, there should not be need to change them. - */ -#if SYSCLK <= 24000000 -#define FLASHBITS 0x00000010 -#else -#if SYSCLK <= 48000000 -#define FLASHBITS 0x00000011 -#else -#define FLASHBITS 0x00000012 -#endif -#endif - /* * Hardware initialization goes here. * NOTE: Interrupts are still disabled. @@ -89,7 +75,7 @@ void hwinit(void) { GPIOD->CRL = VAL_GPIODCRL; GPIOD->CRH = VAL_GPIODCRH; GPIOD->ODR = VAL_GPIODODR; - +#if 0 /* * NVIC/SCB initialization. */ @@ -98,8 +84,9 @@ void hwinit(void) { /* * SysTick initialization. */ - SCB_SHPR(2) = 0x10 << 24; // SysTick at priority 1:0 (highest - 1). + SCB_SHPR(2) = 0x80 << 24; // SysTick at priority 8:0. ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; ST_CVR = 0; ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; +#endif } diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index fa47168ed..a1a0080ef 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -41,9 +41,9 @@ #define HSICLK 8000000 #define PLLPRE 1 #ifdef SYSCLK_48 -#define PLLMUL 6 + #define PLLMUL 6 #else -#define PLLMUL 9 + #define PLLMUL 9 #endif #define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) #define SYSCLK PLLCLK @@ -52,14 +52,16 @@ #define AHB1CLK (SYSCLK / 1) /* - * Values derived from clock settings. + * Values derived from the clock settings. */ #define PLLPREBITS ((PLLPRE - 1) << 17) #define PLLMULBITS ((PLLMUL - 2) << 18) #ifdef SYSCLK_48 -#define USBPREBITS USBPRE_DIV1_BITS + #define USBPREBITS USBPRE_DIV1_BITS + #define FLASHBITS 0x00000011 #else -#define USBPREBITS USBPRE_DIV1P5_BITS + #define USBPREBITS USBPRE_DIV1P5_BITS + #define FLASHBITS 0x00000012 #endif /* @@ -81,9 +83,9 @@ * Definitions for RCC_CFGR register. */ #define CFGR_SW_MASK (0x3 << 0) -#define SW_HSI_BITS (0 << 2) -#define SW_HSE_BITS (1 << 2) -#define SW_PLL_BITS (2 << 2) +#define SW_HSI_BITS (0 << 0) +#define SW_HSE_BITS (1 << 0) +#define SW_PLL_BITS (2 << 0) #define CFGR_SWS_MASK (0x3 << 2) #define SWS_HSI_BITS (0 << 2) #define SWS_HSE_BITS (1 << 2) diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 60e53abd3..99a1c085e 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -19,6 +19,8 @@ #include +#include "board.h" + /* * Red LEDs blinker thread, times are in milliseconds. */ @@ -36,6 +38,10 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + GPIOC->BRR = GPIOC_LED; + while(1) + ; + /* * The main() function becomes a thread here then the interrupts are * enabled and ChibiOS/RT goes live. -- cgit v1.2.3 From f0c8dde933f7fee21163d9831821dc524b56e6ef Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 12 Apr 2008 13:56:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@260 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 3 +-- demos/ARMCM3-STM32F103-GCC/ch.ld | 2 +- demos/ARMCM3-STM32F103-GCC/main.c | 9 ++++----- 3 files changed, 6 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 1323030f0..283341c4f 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -75,7 +75,7 @@ void hwinit(void) { GPIOD->CRL = VAL_GPIODCRL; GPIOD->CRH = VAL_GPIODCRH; GPIOD->ODR = VAL_GPIODODR; -#if 0 + /* * NVIC/SCB initialization. */ @@ -88,5 +88,4 @@ void hwinit(void) { ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; ST_CVR = 0; ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; -#endif } diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index 96c5a3a1d..d5f948476 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -20,7 +20,7 @@ /* * ST32F103 memory setup. */ -__main_stack_size__ = 0x0100; +__main_stack_size__ = 0x0200; __process_stack_size__ = 0x0100; __stacks_total_size__ = __main_stack_size__ + __process_stack_size__; diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 99a1c085e..a5b766de5 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -28,7 +28,10 @@ static WorkingArea(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - chThdSleep(1000); + GPIOC->BRR = GPIOC_LED; + chThdSleep(500); + GPIOC->BSRR = GPIOC_LED; + chThdSleep(500); } return 0; } @@ -38,10 +41,6 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { - GPIOC->BRR = GPIOC_LED; - while(1) - ; - /* * The main() function becomes a thread here then the interrupts are * enabled and ChibiOS/RT goes live. -- cgit v1.2.3 From 18030639fb09e63627c975186896426a2d9c97de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 13 Apr 2008 09:46:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@261 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 1 + demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 7fc33886a..24a2f0982 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -63,6 +63,7 @@ UADEFS = # List ARM-mode C source files here SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ + ../../ports/ARMCM3-STM32F103/stm32_serial.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h index 7df30d90d..681abcffe 100644 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h @@ -106,10 +106,10 @@ //#define _TIM4 /************************************* USART **********************************/ -//#define _USART -//#define _USART1 -//#define _USART2 -//#define _USART3 +#define _USART +#define _USART1 +#define _USART2 +#define _USART3 /************************************* WWDG ***********************************/ //#define _WWDG -- cgit v1.2.3 From 97ec157b500badfd14f4387ebb8e8a6bf3ac929e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 13 Apr 2008 17:03:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@263 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 3 +- demos/ARMCM3-STM32F103-GCC/board.c | 6 + demos/ARMCM3-STM32F103-GCC/main.c | 9 +- .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h | 251 +++++++++++++++++++++ 4 files changed, 266 insertions(+), 3 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 24a2f0982..4cb6c7a4a 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -75,7 +75,8 @@ SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../ports/ARMCM3 +UINCDIR = ../../src/include ../../src/lib ../../test \ + ../../ports/ARMCM3 ../../ports/ARMCM3-STM32F103 # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 283341c4f..38a8e177c 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -21,6 +21,7 @@ #include #include "board.h" +#include "stm32_serial.h" /* * Hardware initialization goes here. @@ -88,4 +89,9 @@ void hwinit(void) { ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; ST_CVR = 0; ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; + + /* + * Other subsystems initialization. + */ + InitSerial(0xA0, 0xA0, 0xA0); } diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index a5b766de5..234878b7b 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -18,8 +18,10 @@ */ #include +#include #include "board.h" +#include "stm32_serial.h" /* * Red LEDs blinker thread, times are in milliseconds. @@ -56,7 +58,10 @@ int main(int argc, char **argv) { * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop. */ - while (TRUE) - chThdSleep(1000); + while (TRUE) { + if (GPIOA->IDR & GPIOA_BUTTON) + TestThread(&COM2); + chThdSleep(500); + } return 0; } diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h new file mode 100644 index 000000000..4d14ef493 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h @@ -0,0 +1,251 @@ +/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.h +* Author : MCD Application Team +* Version : V1.0 +* Date : 10/08/2007 +* Description : This file contains all the functions prototypes for the +* NVIC firmware library. +******************************************************************************** +* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_NVIC_H +#define __STM32F10x_NVIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* NVIC Init Structure definition */ +typedef struct +{ + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ Channels --------------------------------------------------------------*/ +#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ +#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ +#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ +#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ +#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ +#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ +#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ +#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ +#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ +#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ +#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ +#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */ +#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */ +#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */ +#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */ +#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */ +#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */ +#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */ +#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */ +#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ +#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ +#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ +#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ +#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ +#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ +#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ +#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ +#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ +#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ +#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ +#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ +#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ +#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ +#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ +#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ +#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ +#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ +#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ +#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ +#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ +#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ +#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ +#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ + +#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \ + (CHANNEL == PVD_IRQChannel) || \ + (CHANNEL == TAMPER_IRQChannel) || \ + (CHANNEL == RTC_IRQChannel) || \ + (CHANNEL == FLASH_IRQChannel) || \ + (CHANNEL == RCC_IRQChannel) || \ + (CHANNEL == EXTI0_IRQChannel) || \ + (CHANNEL == EXTI1_IRQChannel) || \ + (CHANNEL == EXTI2_IRQChannel) || \ + (CHANNEL == EXTI3_IRQChannel) || \ + (CHANNEL == EXTI4_IRQChannel) || \ + (CHANNEL == DMAChannel1_IRQChannel) || \ + (CHANNEL == DMAChannel2_IRQChannel) || \ + (CHANNEL == DMAChannel3_IRQChannel) || \ + (CHANNEL == DMAChannel4_IRQChannel) || \ + (CHANNEL == DMAChannel5_IRQChannel) || \ + (CHANNEL == DMAChannel6_IRQChannel) || \ + (CHANNEL == DMAChannel7_IRQChannel) || \ + (CHANNEL == ADC_IRQChannel) || \ + (CHANNEL == USB_HP_CAN_TX_IRQChannel) || \ + (CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \ + (CHANNEL == CAN_RX1_IRQChannel) || \ + (CHANNEL == CAN_SCE_IRQChannel) || \ + (CHANNEL == EXTI9_5_IRQChannel) || \ + (CHANNEL == TIM1_BRK_IRQChannel) || \ + (CHANNEL == TIM1_UP_IRQChannel) || \ + (CHANNEL == TIM1_TRG_COM_IRQChannel) || \ + (CHANNEL == TIM1_CC_IRQChannel) || \ + (CHANNEL == TIM2_IRQChannel) || \ + (CHANNEL == TIM3_IRQChannel) || \ + (CHANNEL == TIM4_IRQChannel) || \ + (CHANNEL == I2C1_EV_IRQChannel) || \ + (CHANNEL == I2C1_ER_IRQChannel) || \ + (CHANNEL == I2C2_EV_IRQChannel) || \ + (CHANNEL == I2C2_ER_IRQChannel) || \ + (CHANNEL == SPI1_IRQChannel) || \ + (CHANNEL == SPI2_IRQChannel) || \ + (CHANNEL == USART1_IRQChannel) || \ + (CHANNEL == USART2_IRQChannel) || \ + (CHANNEL == USART3_IRQChannel) || \ + (CHANNEL == EXTI15_10_IRQChannel) || \ + (CHANNEL == RTCAlarm_IRQChannel) || \ + (CHANNEL == USBWakeUp_IRQChannel)) + +/* System Handlers -----------------------------------------------------------*/ +#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ +#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ +#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ +#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ +#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ +#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ +#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ +#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ +#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ + +#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault)) + +#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_SVCall) || \ + (HANDLER == SystemHandler_DebugMonitor) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_SVCall)) + +#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_SVCall) || \ + (HANDLER == SystemHandler_DebugMonitor) || \ + (HANDLER == SystemHandler_PSV) || \ + (HANDLER == SystemHandler_SysTick)) + +#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \ + (HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault) || \ + (HANDLER == SystemHandler_UsageFault) || \ + (HANDLER == SystemHandler_DebugMonitor)) + +#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ + (HANDLER == SystemHandler_BusFault)) + + +/* Vector Table Base ---------------------------------------------------------*/ +#define NVIC_VectTab_RAM ((u32)0x20000000) +#define NVIC_VectTab_FLASH ((u32)0x08000000) + +#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \ + (VECTTAB == NVIC_VectTab_FLASH)) + +/* System Low Power ----------------------------------------------------------*/ +#define NVIC_LP_SEVONPEND ((u8)0x10) +#define NVIC_LP_SLEEPDEEP ((u8)0x04) +#define NVIC_LP_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \ + (LP == NVIC_LP_SLEEPDEEP) || \ + (LP == NVIC_LP_SLEEPONEXIT)) + +/* Preemption Priority Group -------------------------------------------------*/ +#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \ + (GROUP == NVIC_PriorityGroup_1) || \ + (GROUP == NVIC_PriorityGroup_2) || \ + (GROUP == NVIC_PriorityGroup_3) || \ + (GROUP == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10) +#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF) +#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NVIC_DeInit(void); +void NVIC_SCBDeInit(void); +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SETPRIMASK(void); +void NVIC_RESETPRIMASK(void); +void NVIC_SETFAULTMASK(void); +void NVIC_RESETFAULTMASK(void); +void NVIC_BASEPRICONFIG(u32 NewPriority); +u32 NVIC_GetBASEPRI(void); +u16 NVIC_GetCurrentPendingIRQChannel(void); +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); +u16 NVIC_GetCurrentActiveHandler(void); +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); +u32 NVIC_GetCPUID(void); +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); +void NVIC_GenerateSystemReset(void); +void NVIC_GenerateCoreReset(void); +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority); +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); +u32 NVIC_GetFaultAddress(u32 SystemHandler); + +#endif /* __STM32F10x_NVIC_H */ + +/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3 From f1ae9df82658d2e29402c931b098336909f772a3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 15 Apr 2008 15:42:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@266 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 38a8e177c..f10269aa6 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -81,11 +81,12 @@ void hwinit(void) { * NVIC/SCB initialization. */ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4). + SCB_SHPR(2) = 0xF0 << 16; // PendSV at lowest priority. /* * SysTick initialization. */ - SCB_SHPR(2) = 0x80 << 24; // SysTick at priority 8:0. + SCB_SHPR(2) |= 0x40 << 24; // SysTick at priority 4:0. ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; ST_CVR = 0; ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; @@ -93,5 +94,5 @@ void hwinit(void) { /* * Other subsystems initialization. */ - InitSerial(0xA0, 0xA0, 0xA0); + InitSerial(0x80, 0x80, 0x80); } -- cgit v1.2.3 From e6ee866d8a37842faa3e9a99e3c3b4935ba28bf0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 17 Apr 2008 14:44:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@268 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F103-GCC/main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index c8817f85c..f2b87e5bc 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -158,7 +158,7 @@ * @note the debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. */ -//#define CH_USE_DEBUG +#define CH_USE_DEBUG /** Debug option: Includes the threads context switch tracing feature. */ diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 234878b7b..270786695 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -26,7 +26,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WorkingArea(waThread1, 64); +static WorkingArea(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { -- cgit v1.2.3 From f71ba1635af2197a9543a37ea2b19a608a28320f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 17 Apr 2008 14:50:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@269 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index f2b87e5bc..c8817f85c 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -158,7 +158,7 @@ * @note the debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. */ -#define CH_USE_DEBUG +//#define CH_USE_DEBUG /** Debug option: Includes the threads context switch tracing feature. */ -- cgit v1.2.3 From 792c528dbc75f0ffeb19766594607bee73fa36ad Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Apr 2008 12:33:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@270 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/readme.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt index 33c94445b..d3954897a 100644 --- a/demos/ARMCM3-STM32F103-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -8,7 +8,9 @@ The demo will on an Olimex STM32-P103 board. ** The Demo ** -Not complete yet. +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +COM2 (USART2). ** Build Procedure ** -- cgit v1.2.3 From f563ad9387e132cece6634811a89aa450c60a176 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Apr 2008 13:27:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@271 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 4cb6c7a4a..465e405b2 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -89,9 +89,9 @@ ULIBS = # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 -#OPT += -falign-functions=16 +OPT += -falign-functions=16 # Define warning options here WARN = -Wall -Wstrict-prototypes -- cgit v1.2.3 From 5f310adb748bd2a9e62c85f2d3b9a982049144a9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Apr 2008 08:22:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@273 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 1 + demos/ARMCM3-STM32F103-GCC/readme.txt | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 465e405b2..d51c8113d 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -17,6 +17,7 @@ # TRGT = arm-none-eabi- +#TRGT = arm-eabi- CC = $(TRGT)gcc CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt index d3954897a..ca17e697f 100644 --- a/demos/ARMCM3-STM32F103-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -14,8 +14,9 @@ COM2 (USART2). ** Build Procedure ** -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. +The demo was tested by using the free Codesourcery GCC-based toolchain (a +modified 4.2.1 GCC) and an experimental WinARM build including GCC 4.3.0. +Just modify the TRGT line in the makefile in order to use different GCC ports. ** Notes ** -- cgit v1.2.3 From 25d517877dd7725e67c2d094031a023c41ec6f05 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Apr 2008 08:36:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@275 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 9 ++++++--- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 9 ++++++--- demos/ARM7-LPC214x-G++/Makefile | 12 ++++++++---- demos/ARM7-LPC214x-G++/Makefile.thumb | 12 ++++++++---- demos/ARM7-LPC214x-GCC-minimal/Makefile | 9 ++++++--- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 9 ++++++--- demos/ARM7-LPC214x-GCC/Makefile | 9 ++++++--- demos/ARM7-LPC214x-GCC/Makefile.thumb | 9 ++++++--- 8 files changed, 52 insertions(+), 26 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index ea39d57e2..6c6d8f783 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -101,7 +101,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 #OPT += -falign-functions=16 @@ -138,10 +138,13 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 50883c63f..212886957 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -101,7 +101,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer +OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 #OPT += -falign-functions=16 @@ -138,10 +138,13 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index e05b79362..6c04023a8 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -111,7 +111,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 @@ -161,11 +161,15 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -D THUMB_NO_INTERWORKING - CPPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 16ab4d33f..9171d2b72 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -111,7 +111,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 @@ -161,11 +161,15 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -D THUMB_NO_INTERWORKING - CPPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + CPPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + CPPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 7d7e8874c..fc941b4ce 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -99,7 +99,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 @@ -136,10 +136,13 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 0df66f2d3..95cb19000 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -99,7 +99,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer +OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 @@ -136,10 +136,13 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 32f08943e..88d64b911 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -102,7 +102,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 @@ -139,10 +139,13 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index a8840a293..3c8ba1947 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -102,7 +102,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer -fno-strict-aliasing +OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 @@ -139,10 +139,13 @@ ifneq ($(TSRC),) LDFLAGS += -mthumb-interwork else # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -D THUMB_NO_INTERWORKING - LDFLAGS += -mthumb + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb ASFLAGS += -D THUMB_NO_INTERWORKING endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork endif # Generate dependency information -- cgit v1.2.3 From d1626cc8b53ab6a787693d0e040171e0201b24b3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 6 May 2008 15:04:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@281 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h index c5dc4728f..57629be2f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -55,8 +55,8 @@ #define PIOB_SW2 (1 << 25) #define PIOB_PHY_IRQ (1 << 26) #define PIOB_PB27_AD0 (1 << 27) -#define PIOB_PB27_AD1 (1 << 28) -#define PIOB_PB27_AD2 (1 << 29) -#define PIOB_PB27_AD3 (1 << 30) +#define PIOB_PB28_AD1 (1 << 28) +#define PIOB_PB29_AD2 (1 << 29) +#define PIOB_PB30_AD3 (1 << 30) #endif /* _BOARD_H_ */ -- cgit v1.2.3 From f5551fd8d6e8b7db2537d8ec14b936d2ad897441 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 7 May 2008 13:08:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@283 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 151 ++++++++++++++++ demos/MSP430-MSP430x1611-GCC/board.c | 29 ++++ demos/MSP430-MSP430x1611-GCC/board.h | 29 ++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 170 ++++++++++++++++++ demos/MSP430-MSP430x1611-GCC/main.c | 67 ++++++++ demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x | 201 ++++++++++++++++++++++ demos/MSP430-MSP430x1611-GCC/readme.txt | 22 +++ 7 files changed, 669 insertions(+) create mode 100644 demos/MSP430-MSP430x1611-GCC/Makefile create mode 100644 demos/MSP430-MSP430x1611-GCC/board.c create mode 100644 demos/MSP430-MSP430x1611-GCC/board.h create mode 100644 demos/MSP430-MSP430x1611-GCC/chconf.h create mode 100644 demos/MSP430-MSP430x1611-GCC/main.c create mode 100644 demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x create mode 100644 demos/MSP430-MSP430x1611-GCC/readme.txt (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile new file mode 100644 index 000000000..637a26456 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -0,0 +1,151 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = msp430- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = msp430x1611 + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= mspgcc/msp430x1611.x + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List ARM-mode C source files here +SRC = ../../ports/MSP430/chcore.c \ + ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c \ + ../../src/lib/evtimer.c ../../test/test.c \ + board.c main.c + +# List ASM source files here +ASMSRC = + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../test ../../ports/MSP430 + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +OPT = -O2 -ggdb -fomit-frame-pointer +#OPT += -ffixed-r7 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +COBJS = $(SRC:.c=.o) +ASMOBJS = $(ASMSRC:.s=.o) +OBJS = $(ASMOBJS) $(COBJS) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mmcu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# +# Makefile rules +# +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(COBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(COBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + +# *** EOF *** diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c new file mode 100644 index 000000000..68131b345 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -0,0 +1,29 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "board.h" + +/* + * Hardware initialization goes here. + * NOTE: Interrupts are still disabled. + */ +void hwinit(void) { +} diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h new file mode 100644 index 000000000..38ebf3f60 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -0,0 +1,29 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifndef __msp430x16x +#include +#endif + +void hwinit(void); + +#endif /* _BOARD_H_ */ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h new file mode 100644 index 000000000..4ca12304e --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -0,0 +1,170 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/* + * NOTE: this is just documentation for doxigen, the real configuration file + * is the one into the project directories. + */ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +#define CH_USE_MESSAGES_PRIORITY + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-\. + */ +//#define CH_CURRP_REGISTER_CACHE "reg" + +/** Debug option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c new file mode 100644 index 000000000..c1d9c86bb --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include "board.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WorkingArea(waThread1, 64); +static msg_t Thread1(void *arg) { + + while (TRUE) { + chThdSleep(500); + chThdSleep(500); + } + return 0; +} + +/* + * Entry point, the interrupts are disabled on entry. + */ +int main(int argc, char **argv) { + + /* + * Hardware initialization, see board.c. + */ + hwinit(); + + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ + chSysInit(); + + /* + * Creates the blinker threads. + */ + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop. + */ + while (TRUE) { + chThdSleep(500); + } + return 0; +} diff --git a/demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x b/demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x new file mode 100644 index 000000000..7d7c676c3 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/mspgcc/msp430x1611.x @@ -0,0 +1,201 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-msp430","elf32-msp430","elf32-msp430") +OUTPUT_ARCH(msp:16) +MEMORY +{ + text (rx) : ORIGIN = 0x4000, LENGTH = 0xbfe0 + data (rwx) : ORIGIN = 0x1100, LENGTH = 0x2800 + vectors (rw) : ORIGIN = 0xffe0 LENGTH = 32 + bootloader(rx) : ORIGIN = 0x0c00, LENGTH = 1K + infomem(rx) : ORIGIN = 0x1000, LENGTH = 256 + infomemnobits(rx) : ORIGIN = 0x1000, LENGTH = 256 +} +SECTIONS +{ + /* Read-only sections, merged into text segment. */ + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + /* Internal text space. */ + .text : + { + . = ALIGN(2); + *(.init) + *(.init0) /* Start here after reset. */ + *(.init1) + *(.init2) /* Copy data loop */ + *(.init3) + *(.init4) /* Clear bss */ + *(.init5) + *(.init6) /* C++ constructors. */ + *(.init7) + *(.init8) + *(.init9) /* Call main(). */ + __ctors_start = . ; + *(.ctors) + __ctors_end = . ; + __dtors_start = . ; + *(.dtors) + __dtors_end = . ; + . = ALIGN(2); + *(.text) + . = ALIGN(2); + *(.text.*) + . = ALIGN(2); + *(.fini9) /* */ + *(.fini8) + *(.fini7) + *(.fini6) /* C++ destructors. */ + *(.fini5) + *(.fini4) + *(.fini3) + *(.fini2) + *(.fini1) + *(.fini0) /* Infinite loop after program termination. */ + *(.fini) + _etext = .; + } > text + .data : AT (ADDR (.text) + SIZEOF (.text)) + { + PROVIDE (__data_start = .) ; + . = ALIGN(2); + *(.data) + . = ALIGN(2); + *(.gnu.linkonce.d*) + . = ALIGN(2); + _edata = . ; + } > data + /* Bootloader. */ + .bootloader : + { + PROVIDE (__boot_start = .) ; + *(.bootloader) + . = ALIGN(2); + *(.bootloader.*) + } > bootloader + /* Information memory. */ + .infomem : + { + *(.infomem) + . = ALIGN(2); + *(.infomem.*) + } > infomem + /* Information memory (not loaded into MPU). */ + .infomemnobits : + { + *(.infomemnobits) + . = ALIGN(2); + *(.infomemnobits.*) + } > infomemnobits + .bss SIZEOF(.data) + ADDR(.data) : + { + PROVIDE (__bss_start = .) ; + *(.bss) + *(COMMON) + PROVIDE (__bss_end = .) ; + _end = . ; + } > data + .noinit SIZEOF(.bss) + ADDR(.bss) : + { + PROVIDE (__noinit_start = .) ; + *(.noinit) + *(COMMON) + PROVIDE (__noinit_end = .) ; + _end = . ; + } > data + .vectors : + { + PROVIDE (__vectors_start = .) ; + *(.vectors*) + _vectors_end = . ; + } > vectors + /* Stabs for profiling information*/ + .profiler 0 : { *(.profiler) } + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + PROVIDE (__stack = 0x3900) ; + PROVIDE (__data_start_rom = _etext) ; + PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ; + PROVIDE (__noinit_start_rom = _etext + SIZEOF (.data)) ; + PROVIDE (__noinit_end_rom = _etext + SIZEOF (.data) + SIZEOF (.noinit)) ; + PROVIDE (__subdevice_has_heap = 0) ; +} diff --git a/demos/MSP430-MSP430x1611-GCC/readme.txt b/demos/MSP430-MSP430x1611-GCC/readme.txt new file mode 100644 index 000000000..5533287ff --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/readme.txt @@ -0,0 +1,22 @@ +***************************************************************************** +** ChibiOS/RT port for Texas Instruments MSP430. ** +***************************************************************************** + +** TARGET ** + +This is an abstract demo. it is not tested on real hardware yet. + +** The Demo ** + +Creates a thread that just sleeps in a continuous loop. + +** Build Procedure ** + +The demo was built using the MSPGCC toolchain. + +** Notes ** + +The demo requires include files from MSPGCC that are not part of the ChibiOS/RT +distribution, please install MSPGCC. + + http://mspgcc.sourceforge.net/ -- cgit v1.2.3 From 3f9aac327ba999d67f9501ebf590d171e496b448 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 7 May 2008 15:47:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@284 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 20 ++++++++++++++++++++ demos/MSP430-MSP430x1611-GCC/board.h | 3 +++ 2 files changed, 23 insertions(+) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 68131b345..09f93075a 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" @@ -26,4 +27,23 @@ * NOTE: Interrupts are still disabled. */ void hwinit(void) { + + /* + * I/O ports initialization. + */ + + /* + * Timer 0 setup. + */ + TACCR0 = ACLK / CH_FREQUENCY; /* Counter limit. */ + TACTL = TACLR; /* Clean start. */ + TACTL = TASSEL_1 | MC_1; /* Src=ACLK, cmp=TACCR0. */ + TACCTL0 = CCIE; /* Interrupt on compare. */ +} + +interrupt(TIMERA0_VECTOR) tmr0irq(void) { + + chSysIRQEnterI(); + chSysTimerHandlerI(); + chSysIRQExitI(); } diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index 38ebf3f60..005b019a9 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -24,6 +24,9 @@ #include #endif +#define MCLK 8000000 +#define ACLK 8000000 + void hwinit(void); #endif /* _BOARD_H_ */ -- cgit v1.2.3 From 83bbc0a6c61cabde630dfb08d69e4d6a29657dd2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 8 May 2008 10:12:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@285 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 32 +++++++++++++++++- demos/MSP430-MSP430x1611-GCC/board.h | 60 +++++++++++++++++++++++++++++++-- demos/MSP430-MSP430x1611-GCC/main.c | 4 +++ demos/MSP430-MSP430x1611-GCC/readme.txt | 4 +-- 4 files changed, 94 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 09f93075a..b591ec3d6 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -28,14 +28,44 @@ */ void hwinit(void) { + /* + * Clock sources setup. + */ + DCOCTL = VAL_DCOCTL; + BCSCTL1 = VAL_BCSCTL1; + BCSCTL2 = VAL_BCSCTL2; + /* * I/O ports initialization. */ + P1OUT = VAL_P1OUT; + P1DIR = VAL_P1DIR; + P1SEL = VAL_P1SEL; + + P2OUT = VAL_P2OUT; + P2DIR = VAL_P2DIR; + P2SEL = VAL_P2SEL; + + P3OUT = VAL_P3OUT; + P3DIR = VAL_P3DIR; + P3SEL = VAL_P3SEL; + + P4OUT = VAL_P4OUT; + P4DIR = VAL_P4DIR; + P4SEL = VAL_P4SEL; + + P5OUT = VAL_P5OUT; + P5DIR = VAL_P5DIR; + P5SEL = VAL_P5SEL; + + P6OUT = VAL_P6OUT; + P6DIR = VAL_P6DIR; + P6SEL = VAL_P6SEL; /* * Timer 0 setup. */ - TACCR0 = ACLK / CH_FREQUENCY; /* Counter limit. */ + TACCR0 = ACLK / CH_FREQUENCY - 1; /* Counter limit. */ TACTL = TACLR; /* Clean start. */ TACTL = TASSEL_1 | MC_1; /* Src=ACLK, cmp=TACCR0. */ TACCTL0 = CCIE; /* Interrupt on compare. */ diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index 005b019a9..fe4523b6a 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -20,12 +20,66 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#ifndef __msp430x16x #include + +#define MSP_USE_XT2CLK + +#define LFXT1CLK 32768 +#define XT2CLK 8000000 +#define DCOCLK 1000000 + +#define ACLK LFXT1CLK +#ifdef MSP_USE_XT2CLK +#define MCLK XT2CLK +#define SMCLK (XT2CLK / 8) +#else +#define MCLK DCOCLK +#define SMCLK LFXT1CLK #endif -#define MCLK 8000000 -#define ACLK 8000000 +#define VAL_DCOCTL (DCO0 | DCO1) +#ifdef MSP_USE_XT2CLK +#define VAL_BCSCTL1 (RSEL2) +#define VAL_BCSCTL2 (SELM_2 | DIVM_0 | DIVS_3 | SELS) +#else +#define VAL_BCSCTL1 (XT2OFF | RSEL2) +#define VAL_BCSCTL2 (SELM_0 | DIVM_0 | DIVS_0) +#endif + +/* + * Pin definitionsfor the Olimex MSP430-P1611 board. + */ +#define P3_O_TXD0 (1 << 4) +#define P3_I_RXD0 (1 << 5) +#define P6_O_LED (1 << 0) +#define P6_I_BUTTON (1 << 1) + +/* + * Initial I/O ports settings. + */ +#define VAL_P1OUT 0x00 +#define VAL_P1DIR 0xFF +#define VAL_P1SEL 0x00 + +#define VAL_P2OUT 0x00 +#define VAL_P2DIR 0xFF +#define VAL_P2SEL 0x00 + +#define VAL_P3OUT P3_O_TXD0 +#define VAL_P3DIR ~P3_I_RXD0 +#define VAL_P3SEL 0x00 + +#define VAL_P4OUT 0x00 +#define VAL_P4DIR 0xFF +#define VAL_P4SEL 0x00 + +#define VAL_P5OUT 0x00 +#define VAL_P5DIR 0xFF +#define VAL_P5SEL 0x00 + +#define VAL_P6OUT P6_O_LED +#define VAL_P6DIR ~P6_I_BUTTON +#define VAL_P6SEL 0x00 void hwinit(void); diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index c1d9c86bb..6790720ef 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -29,7 +29,9 @@ static WorkingArea(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { + P6OUT |= P6_O_LED; chThdSleep(500); + P6OUT &= ~P6_O_LED; chThdSleep(500); } return 0; @@ -61,6 +63,8 @@ int main(int argc, char **argv) { * sleeping in a loop. */ while (TRUE) { +// if (!(P6IN & P6_I_BUTTON)) +// TestThread(&COM1); chThdSleep(500); } return 0; diff --git a/demos/MSP430-MSP430x1611-GCC/readme.txt b/demos/MSP430-MSP430x1611-GCC/readme.txt index 5533287ff..0fd0c5a7b 100644 --- a/demos/MSP430-MSP430x1611-GCC/readme.txt +++ b/demos/MSP430-MSP430x1611-GCC/readme.txt @@ -4,11 +4,11 @@ ** TARGET ** -This is an abstract demo. it is not tested on real hardware yet. +The demo runs on an Olimex MSP430-P1611 board but it is still untested. ** The Demo ** -Creates a thread that just sleeps in a continuous loop. +The demo flashes the board LED using a thread. ** Build Procedure ** -- cgit v1.2.3 From f2e73138ba524d67734de4fdaa07fea16fb31e67 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 8 May 2008 15:32:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@286 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 6 +++--- demos/MSP430-MSP430x1611-GCC/board.h | 5 ++++- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index b591ec3d6..c6cfedce2 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -63,11 +63,11 @@ void hwinit(void) { P6SEL = VAL_P6SEL; /* - * Timer 0 setup. + * Timer 0 setup, uses SMCLK as source. */ - TACCR0 = ACLK / CH_FREQUENCY - 1; /* Counter limit. */ + TACCR0 = SMCLK / CH_FREQUENCY - 1; /* Counter limit. */ TACTL = TACLR; /* Clean start. */ - TACTL = TASSEL_1 | MC_1; /* Src=ACLK, cmp=TACCR0. */ + TACTL = TASSEL_2 | MC_1; /* Src=SMCLK, cmp=TACCR0. */ TACCTL0 = CCIE; /* Interrupt on compare. */ } diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index fe4523b6a..8b335f64f 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -22,6 +22,9 @@ #include +/* + * Clock settings. + */ #define MSP_USE_XT2CLK #define LFXT1CLK 32768 @@ -34,7 +37,7 @@ #define SMCLK (XT2CLK / 8) #else #define MCLK DCOCLK -#define SMCLK LFXT1CLK +#define SMCLK DCOCLK #endif #define VAL_DCOCTL (DCO0 | DCO1) -- cgit v1.2.3 From 1e99857780de7d93c5e6c246202584c1fe270696 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 May 2008 09:17:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@291 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 3 ++- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 3 ++- demos/ARM7-AT91SAM7X-GCC/ch.ld | 2 +- demos/ARM7-AT91SAM7X-GCC/main.c | 6 +++--- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/main.c | 2 +- demos/ARMCM3-STM32F103-GCC/main.c | 2 +- 8 files changed, 12 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 6c6d8f783..8ac2a69af 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -64,6 +64,7 @@ UADEFS = # List ARM-mode C source files here ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -81,7 +82,7 @@ TSRC = ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib \ +UINCDIR = ../../src/include ../../src/lib ../../test \ ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X # List the user directory to look for the libraries here diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 212886957..e3fb4a6ce 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -69,6 +69,7 @@ ASRC = # enabled for all modules and that lowers performance. TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -81,7 +82,7 @@ TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib \ +UINCDIR = ../../src/include ../../src/lib ../../test \ ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X # List the user directory to look for the libraries here diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 541c73b5b..847340cb4 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -30,7 +30,7 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { - flash : org = 0x100000, len = 256k + flash : org = 0x000000, len = 256k ram : org = 0x200020, len = 64k - 0x20 } diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index a255c9939..27fc20a3d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" #include "sam7x_serial.h" @@ -27,9 +28,9 @@ static msg_t Thread1(void *arg) { while (TRUE) { AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. - chThdSleep(500); + chThdSleep(100); AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // LCD off. - chThdSleep(500); + chThdSleep(900); } return 0; } @@ -38,7 +39,6 @@ static msg_t Thread1(void *arg) { * Entry point, the interrupts are disabled on entry. */ int main(int argc, char **argv) { - msg_t TestThread(void *p); /* * The main() function becomes a thread here then the interrupts are diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 88d64b911..5d0450021 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -82,7 +82,7 @@ TSRC = ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib \ +UINCDIR = ../../src/include ../../src/lib ../../test \ ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 3c8ba1947..83e19ebff 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -82,7 +82,7 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s # List all user directories here -UINCDIR = ../../src/include ../../src/lib \ +UINCDIR = ../../src/include ../../src/lib ../../test \ ../../ports/ARM7 ../../ports/ARM7-LPC214x # List the user directory to look for the libraries here diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index ad2ab2700..10cae19da 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -18,6 +18,7 @@ */ #include +#include #include "lpc214x.h" #include "lpc214x_serial.h" @@ -63,7 +64,6 @@ static msg_t Thread2(void *arg) { * Executed as event handler at 500mS intervals. */ static void TimerHandler(eventid_t id) { - msg_t TestThread(void *p); if (!(IO0PIN & 0x00018000)) { // Both buttons TestThread(&COM1); diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 270786695..6a2037393 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -56,7 +56,7 @@ int main(int argc, char **argv) { /* * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop. + * sleeping in a loop and check the button state. */ while (TRUE) { if (GPIOA->IDR & GPIOA_BUTTON) -- cgit v1.2.3 From cadf83110acc18314197ace9e3d5083a99e3fdb8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 May 2008 15:09:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@292 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/ch.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 847340cb4..541c73b5b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -30,7 +30,7 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { - flash : org = 0x000000, len = 256k + flash : org = 0x100000, len = 256k ram : org = 0x200020, len = 64k - 0x20 } -- cgit v1.2.3 From 602cff4618efa156b746e20b668c6eab8615c438 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 May 2008 16:10:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@295 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/main.c | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 8ac2a69af..c799658c8 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -102,7 +102,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +OPT = -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 #OPT += -falign-functions=16 diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 27fc20a3d..2ac2f7e08 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -21,7 +21,8 @@ #include #include "board.h" -#include "sam7x_serial.h" +#include +#include static WorkingArea(waThread1, 64); static msg_t Thread1(void *arg) { @@ -40,6 +41,8 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + InitEMAC(AT91C_AIC_PRIOR_HIGHEST - 3); + /* * The main() function becomes a thread here then the interrupts are * enabled and ChibiOS/RT goes live. -- cgit v1.2.3 From 629f56d09feaa384e02f614d5ec33c6902e0cdd4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 May 2008 10:52:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@296 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 236e1100e..ff7e9dc19 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -115,7 +115,7 @@ void hwinit(void) { */ AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // Set to low. AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL; // Configure as output. - AT91C_BASE_PIOA->PIO_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. AT91C_BASE_PIOA->PIO_SODR = PIOA_LCD_RESET; // Set to high. AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET; // Configure as output. -- cgit v1.2.3 From b5a6f8abec0c55b226ee703efedc0679b8eb9f0b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 May 2008 12:18:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@298 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 3 +-- demos/ARM7-AT91SAM7X-GCC/board.c | 3 ++- demos/ARM7-AT91SAM7X-GCC/main.c | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index c799658c8..0ff70ca56 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -64,7 +64,6 @@ UADEFS = # List ARM-mode C source files here ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ @@ -102,7 +101,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -ggdb -fomit-frame-pointer -mabi=apcs-gnu +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 #OPT += -falign-functions=16 diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index ff7e9dc19..4bc78f086 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -20,9 +20,10 @@ #include #include "board.h" -#include "sam7x_serial.h" #include "at91lib/aic.h" +#include + extern void FiqHandler(void); __attribute__((naked)) diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 2ac2f7e08..e5c2e7d4f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -22,7 +22,6 @@ #include "board.h" #include -#include static WorkingArea(waThread1, 64); static msg_t Thread1(void *arg) { @@ -41,8 +40,6 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { - InitEMAC(AT91C_AIC_PRIOR_HIGHEST - 3); - /* * The main() function becomes a thread here then the interrupts are * enabled and ChibiOS/RT goes live. -- cgit v1.2.3 From f2022a264125bdf3b18e5fe0fe0c2e523cf41ded Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 May 2008 14:24:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@302 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 224 ++ demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 224 ++ .../ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h | 2918 ++++++++++++++++++++ demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c | 84 + demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h | 78 + demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 159 ++ demos/ARM7-AT91SAM7X-WEB-GCC/board.h | 62 + demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld | 84 + demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 169 ++ demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 66 + demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt | 26 + demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h | 42 + demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h | 157 ++ demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 65 + demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h | 31 + 15 files changed, 4389 insertions(+) create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/Makefile create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/board.c create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/board.h create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/main.c create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile new file mode 100644 index 000000000..0e66ef5ee --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -0,0 +1,224 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List of all the ChibiOS/RT kernel files, there is no need to remove the files +# from this list, you can disable parts of the kernel by editing chconf.h. +KSRC = ../../src/chinit.c ../../src/chdebug.c \ + ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c \ + ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c + +# List of the required uIP source files. +USRC = ../../ext/uip-1.0/uip/uip_arp.c \ + ../../ext/uip-1.0/uip/psock.c \ + ../../ext/uip-1.0/uip/timer.c \ + ../../ext/uip-1.0/uip/uip.c \ + ../../ext/uip-1.0/apps/webserver/httpd.c \ + ../../ext/uip-1.0/apps/webserver/http-strings.c \ + ../../ext/uip-1.0/apps/webserver/httpd-fs.c \ + ../../ext/uip-1.0/apps/webserver/httpd-cgi.c + +# List ARM-mode C source files here +ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ + ${KSRC} ${USRC} \ + ../../src/lib/evtimer.c ../../test/test.c \ + at91lib/aic.c \ + web/webthread.c \ + board.c main.c + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = + +# List ASM source files here +ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../test \ + ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X \ + ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -ggdb -fomit-frame-pointer -mabi=apcs-gnu +#OPT += -ffixed-r7 +#OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb + ASFLAGS += -D THUMB_NO_INTERWORKING + endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb new file mode 100644 index 000000000..9171d3084 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -0,0 +1,224 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +MCU = arm7tdmi + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List of all the ChibiOS/RT kernel files, there is no need to remove the files +# from this list, you can disable parts of the kernel by editing chconf.h. +KSRC = ../../src/chinit.c ../../src/chdebug.c \ + ../../src/chlists.c ../../src/chdelta.c \ + ../../src/chschd.c ../../src/chthreads.c \ + ../../src/chsem.c ../../src/chmtx.c \ + ../../src/chevents.c ../../src/chmsg.c \ + ../../src/chsleep.c ../../src/chqueues.c \ + ../../src/chserial.c + +# List of the required uIP source files. +USRC = ../../ext/uip-1.0/uip/uip_arp.c \ + ../../ext/uip-1.0/uip/psock.c \ + ../../ext/uip-1.0/uip/timer.c \ + ../../ext/uip-1.0/uip/uip.c \ + ../../ext/uip-1.0/apps/webserver/httpd.c \ + ../../ext/uip-1.0/apps/webserver/http-strings.c \ + ../../ext/uip-1.0/apps/webserver/httpd-fs.c \ + ../../ext/uip-1.0/apps/webserver/httpd-cgi.c + +# List ARM-mode C source files here +ASRC = + +# List THUMB-mode C sources here +# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is +# enabled for all modules and that lowers performance. +TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ + ${KSRC} ${USRC} \ + ../../src/lib/evtimer.c ../../test/test.c \ + at91lib/aic.c \ + web/webthread.c \ + board.c main.c + +# List ASM source files here +ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s + +# List all user directories here +UINCDIR = ../../src/include ../../src/lib ../../test \ + ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X \ + ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -D THUMB + +# Common options here +# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in +# chconf.h. +# NOTE: -falign-functions=16 may improve the performance, not always, but +# increases the code size. +OPT = -ggdb -fomit-frame-pointer -mabi=apcs-gnu +#OPT += -ffixed-r7 +#OPT += -falign-functions=16 + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +AOBJS = $(ASRC:.c=.o) +TOBJS = $(TSRC:.c=.o) +OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) +ASMOBJS = $(ASMSRC:.s=.o) +LIBS = $(DLIBS) $(ULIBS) +MCFLAGS = -mcpu=$(MCU) + +ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) +LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ODFLAGS = -x --syms + +# Thumb interwork enabled only if needed because it kills performance. +ifneq ($(TSRC),) + CPFLAGS += -D THUMB_PRESENT + ASFLAGS += -D THUMB_PRESENT + ifneq ($(ASRC),) + # Mixed ARM and THUMB case. + CPFLAGS += -mthumb-interwork + LDFLAGS += -mthumb-interwork + else + # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. + CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING + LDFLAGS += -mno-thumb-interwork -mthumb + ASFLAGS += -D THUMB_NO_INTERWORKING + endif +else + CPFLAGS += -mno-thumb-interwork + LDFLAGS += -mno-thumb-interwork +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# Makefile rules +# + +all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp + +$(AOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ + +$(TOBJS) : %.o : %.c + @echo + $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ + +$(ASMOBJS) : %.o : %.s + @echo + $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ + +%elf: $(OBJS) + @echo + $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ + +%hex: %elf + $(HEX) $< $@ + +%bin: %elf + $(BIN) $< $@ + +%dmp: %elf + $(OD) $(ODFLAGS) $< > $@ + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).elf + -rm -f $(PROJECT).dmp + -rm -f $(PROJECT).map + -rm -f $(PROJECT).hex + -rm -f $(PROJECT).bin + -rm -f $(ASRC:.c=.c.bak) + -rm -f $(ASRC:.c=.lst) + -rm -f $(TSRC:.c=.c.bak) + -rm -f $(TSRC:.c=.lst) + -rm -f $(ASMSRC:.s=.s.bak) + -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h new file mode 100644 index 000000000..20b0e747d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h @@ -0,0 +1,2918 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// - Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the disclaimer below in the documentation and/or +// other materials provided with the distribution. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 06/19/2007 (15:41:06) +// +// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// +// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// +// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved2[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; +#else +#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register +#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register +#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register +#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register +#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register +#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register +#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register +#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register + +#endif +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; +#else +#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register +#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register +#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register +#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register +#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register +#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register +#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register +#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register +#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register +#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register +#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register +#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register + +#endif +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; +#else +#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register +#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register +#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register +#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register +#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer +#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer +#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register +#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register +#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register +#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register +#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register +#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register +#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register +#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register +#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register +#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register +#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register +#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register +#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register +#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register +#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register +#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register +#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register +#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register +#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register +#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register +#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register +#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register +#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register +#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register +#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register +#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register +#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register +#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register +#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] +#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] +#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register +#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register +#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register +#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register +#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register + +#endif +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes + +#endif diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c new file mode 100644 index 000000000..66eebf94e --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "aic.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the interrupt associated with the given source, using the +/// specified mode and interrupt handler. +/// \param source Interrupt source to configure. +/// \param mode Triggering mode of the interrupt. +/// \param handler Interrupt handler function. +//------------------------------------------------------------------------------ +void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )) +{ + // Disable the interrupt first + AT91C_BASE_AIC->AIC_IDCR = 1 << source; + + // Configure mode and handler + AT91C_BASE_AIC->AIC_SMR[source] = mode; + AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; + + // Clear interrupt + AT91C_BASE_AIC->AIC_ICCR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Enables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_EnableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IECR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Disables interrupts coming from the given (unique) source. +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_DisableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IDCR = 1 << source; +} + diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h new file mode 100644 index 000000000..e8e52c78a --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + * ---------------------------------------------------------------------------- + * Copyright (c) 2006, Atmel Corporation + + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaiimer below. + * + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the disclaimer below in the documentation and/or + * other materials provided with the distribution. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Methods and definitions for configuring interrupts using the Advanced +/// Interrupt Controller (AIC). +/// +/// !Usage +/// -# Configure an interrupt source using AIC_ConfigureIT +/// -# Enable or disable interrupt generation of a particular source with +/// AIC_EnableIT and AIC_DisableIT. +//------------------------------------------------------------------------------ + +#ifndef AIC_H +#define AIC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL + /// Redefinition of missing constant. + #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )); + +extern void AIC_EnableIT(unsigned int source); + +extern void AIC_DisableIT(unsigned int source); + +#endif //#ifndef AIC_H + diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c new file mode 100644 index 000000000..2bc9c6395 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "board.h" +#include "at91lib/aic.h" + +#include +#include + +extern void FiqHandler(void); + +__attribute__((naked)) +static void SpuriousHandler(void) { + + chSysIRQEnterI(); + + AT91C_BASE_AIC->AIC_EOICR = 0; + + chSysIRQExitI(); +} + +/* + * SYS IRQ handling here. + */ +__attribute__((naked)) +static void SYSIrqHandler(void) { + + chSysIRQEnterI(); + + if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { + (void) AT91C_BASE_PITC->PITC_PIVR; + chSysTimerHandlerI(); + } + AT91C_BASE_AIC->AIC_EOICR = 0; \ + + chSysIRQExitI(); +} + +/* + * Board initialization code. + */ +void hwinit(void) { + int i; + + /* + * Flash Memory: 1 wait state, about 50 cycles in a microsecond. + */ + AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; + + /* + * Watchdog disabled. + */ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + /* + * Enables the main oscillator and waits 56 slow cycles as startup time. + */ + AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) + ; + + /* + * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 + * PLLfreq = 96109714 Hz (rounded) + */ + AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (10 << 8)) | + (AT91C_CKGR_MUL & (72 << 16)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) + ; + + /* + * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) + */ + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) + ; + + /* + * I/O setup, enable clocks, initially all pins are inputs with pullups. + */ + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); + AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; + AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; + + /* + * Default AIC setup, the device drivers will modify it as needed. + */ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; + for (i = 1; i < 31; i++) { + AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; + } + AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; + + /* + * LCD pins setup. + */ + AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // Set to low. + AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL; // Configure as output. + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. + + AT91C_BASE_PIOA->PIO_SODR = PIOA_LCD_RESET; // Set to high. + AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET; // Configure as output. + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET; // Disable internal pullup resistor. + + /* + * Joystick and buttons, disable pullups, already inputs. + */ + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1 | PIOA_B2 | PIOA_B3 | PIOA_B4 | PIOA_B5; + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1 | PIOB_SW2; + + /* + * MMC/SD slot, disable pullups, already inputs. + */ + AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP | PIOB_MMC_CP; + + /* + * PIT Initialization. + */ + AIC_ConfigureIT(AT91C_ID_SYS, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), + SYSIrqHandler); + AIC_EnableIT(AT91C_ID_SYS); + AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + + /* + * Serial driver initialization, RTS/CTS pins enabled for USART0 only. + */ + InitSerial(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + + /* + * EMAC driver initialization. + */ + InitEMAC(AT91C_AIC_PRIOR_HIGHEST - 3); +} diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.h b/demos/ARM7-AT91SAM7X-WEB-GCC/board.h new file mode 100644 index 000000000..57629be2f --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.h @@ -0,0 +1,62 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifndef AT91SAM7X256_H +#include "at91lib/AT91SAM7X256.h" +#endif + +#define BOARD_OLIMEX_SAM7_EX256 + +#define CLK 18432000 +#define MCK 48054857 + +/* + * I/O definitions. + */ +#define PIOA_LCD_RESET (1 << 2) +#define PIOA_B1 (1 << 7) +#define PIOA_B2 (1 << 8) +#define PIOA_B3 (1 << 9) +#define PIOA_B4 (1 << 14) +#define PIOA_B5 (1 << 15) +#define PIOA_USB_PUP (1 << 25) +#define PIOA_USB_PR (1 << 26) +#define PIOA_PA27 (1 << 27) +#define PIOA_PA28 (1 << 28) +#define PIOA_PA29 (1 << 29) +#define PIOA_PA30 (1 << 30) + +#define PIOB_PHY_PD (1 << 18) +#define PIOB_AUDIO_OUT (1 << 19) +#define PIOB_LCD_BL (1 << 20) +#define PIOB_PB21 (1 << 21) +#define PIOB_MMC_WP (1 << 22) +#define PIOB_MMC_CP (1 << 23) +#define PIOB_SW1 (1 << 24) +#define PIOB_SW2 (1 << 25) +#define PIOB_PHY_IRQ (1 << 26) +#define PIOB_PB27_AD0 (1 << 27) +#define PIOB_PB28_AD1 (1 << 28) +#define PIOB_PB29_AD2 (1 << 29) +#define PIOB_PB30_AD3 (1 << 30) + +#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld new file mode 100644 index 000000000..541c73b5b --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld @@ -0,0 +1,84 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0100; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : + { + _text = .; + *(.text); + *(.rodata); + *(.rodata*); + *(.glue_7t); + *(.glue_7); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h new file mode 100644 index 000000000..c8817f85c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -0,0 +1,169 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Configuration file for LPC214x-GCC demo project. + */ + +/** + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/** Configuration option: if specified then time efficient rather than space + * efficient code is used when two possible implementations exist, note + * that this is not related to the compiler optimization options.*/ +#define CH_OPTIMIZE_SPEED + +/** Configuration option: if specified then the Virtual Timers subsystem is + * included in the kernel.*/ +#define CH_USE_VIRTUAL_TIMERS + +/** Configuration option: if specified then the System Timer subsystem is + * included in the kernel.*/ +#define CH_USE_SYSTEMTIME + +/** Configuration option: if specified then the \p chThdSleep() function is + * included in the kernel. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SLEEP + +/** Configuration option: if specified then the \p chThdResume() + * function is included in the kernel.*/ +#define CH_USE_RESUME + +/** Configuration option: if specified then the \p chThdSuspend() + * function is included in the kernel.*/ +#define CH_USE_SUSPEND + +/** Configuration option: if specified then the \p chThdTerminate() + * and \p chThdShouldTerminate() functions are included in the kernel.*/ +#define CH_USE_TERMINATE + +/** Configuration option: if specified then the \p chThdWait() function + * is included in the kernel.*/ +#define CH_USE_WAITEXIT + +/** Configuration option: if specified then the Semaphores APIs are included + * in the kernel.*/ +#define CH_USE_SEMAPHORES + +/** Configuration option: if specified then the Semaphores atomic Signal+Wait + * APIs are included in the kernel.*/ +#define CH_USE_SEMSW + +/** Configuration option: if specified then the Semaphores with timeout APIs + * are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_SEMAPHORES_TIMEOUT + +/** Configuration option: if specified then the Mutexes APIs are included in + * the kernel.*/ +#define CH_USE_MUTEXES + +/** Configuration option: if specified then the Events APIs are included in + * the kernel.*/ +#define CH_USE_EVENTS + +/** Configuration option: if specified then the \p chEvtWaitTimeout() + * function is included in the kernel. + * @note requires \p CH_USE_EVENTS. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_EVENTS_TIMEOUT + +/** Configuration option: if specified then the Synchronous Messages APIs are + * included in the kernel.*/ +#define CH_USE_MESSAGES + +/** Configuration option: if specified then the \p chMsgSendWithEvent() + * function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ +#define CH_USE_MESSAGES_EVENT + +/** Configuration option: If enabled then the threads have an option to serve + * messages by priority instead of FIFO order. + * @note requires \p CH_USE_MESSAGES.*/ +//#define CH_USE_MESSAGES_PRIORITY + +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. + * @note requires \p CH_USE_EVENTS.*/ +#define CH_USE_EXIT_EVENT + +/** Configuration option: if specified then the I/O queues APIs are included + * in the kernel.*/ +#define CH_USE_QUEUES + +/** Configuration option: if specified then the halfduplex queue APIs are + * included in the kernel.*/ +#define CH_USE_QUEUES_HALFDUPLEX + +/** Configuration option: if specified then the I/O queues with timeout + * APIs are included in the kernel. + * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ +#define CH_USE_QUEUES_TIMEOUT + +/** Configuration option: if specified then the full duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_FULLDUPLEX + +/** Configuration option: if specified then the half duplex serial driver APIs + * are included in the kernel.*/ +#define CH_USE_SERIAL_HALFDUPLEX + +/** Configuration option: Frequency of the system timer that drives the system + * ticks. This also defines the system time unit.*/ +#define CH_FREQUENCY 1000 + +/** Configuration option: This constant is the number of ticks allowed for the + * threads before preemption occurs.*/ +#define CH_TIME_QUANTUM 20 + +/** Configuration option: Defines a CPU register to be used as storage for the + * global \p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only useable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option \p + * -ffixed-. + */ +//#define CH_CURRP_REGISTER_CACHE "r7" + +/** Configuration option: Includes basic debug support to the kernel. + * @note the debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + */ +//#define CH_USE_DEBUG + +/** Debug option: Includes the threads context switch tracing feature. + */ +//#define CH_USE_TRACE + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c new file mode 100644 index 000000000..e53bd5b7c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -0,0 +1,66 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include "board.h" +#include +#include + +#include "web/webthread.h" + +static WorkingArea(waWebThread, 256); +static WorkingArea(waThread1, 64); + +static msg_t Thread1(void *arg) { + + while (TRUE) { + AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. + chThdSleep(100); + AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // LCD off. + chThdSleep(900); + } + return 0; +} + +/* + * Entry point, the interrupts are disabled on entry. + */ +int main(int argc, char **argv) { + + /* + * The main() function becomes a thread here then the interrupts are + * enabled and ChibiOS/RT goes live. + */ + chSysInit(); + + chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreate(NORMALPRIO - 1, 0, waWebThread, sizeof(waWebThread), WebThread, NULL); + + while (TRUE) { + chThdSleep(500); + if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) + chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); + if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW2)) + TestThread(&COM1); + } + + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt b/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt new file mode 100644 index 000000000..fc561fa4d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-EX256 board. + +** The Demo ** + +Work in progress, not finished yet. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/AT91SAM7X256/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h new file mode 100644 index 000000000..e205f9c8d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include + +typedef systime_t clock_time_t; +#define CLOCK_CONF_SECOND CH_FREQUENCY + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h new file mode 100644 index 000000000..289d4a150 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h @@ -0,0 +1,157 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1518 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c new file mode 100644 index 000000000..a4fb3de03 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -0,0 +1,65 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include + +#include +#include +#include +#include +#include + +static EvTimer evt; +struct EventListener el0, el1, el2; + +void clock_init(void) {} + +clock_time_t clock_time( void ) +{ + return chSysGetTime(); +} + +/* + * Executed as event handler at 1000mS intervals. + */ +static void TimerHandler(eventid_t id) { + + (void)EMACGetLinkStatus(); +} + +msg_t WebThread(void *p) { + static const evhandler_t evhndl[] = { + TimerHandler, + NULL, + NULL + }; + + evtInit(&evt, 1000); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + chEvtRegister(&EMACFrameTransmitted, &el1, 1); + chEvtRegister(&EMACFrameReceived, &el2, 2); + + while (TRUE) { + chEvtWait(ALL_EVENTS, evhndl); + } + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h new file mode 100644 index 000000000..bd71b4dc4 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _WEBTHREAD_H_ +#define _WEBTHREAD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + msg_t WebThread(void *p); + #ifdef __cplusplus +} +#endif + +#endif /* _WEBTHREAD_H_ */ -- cgit v1.2.3 From b34347c0257b14e5da0704ba2c710f39a9f9f002 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 May 2008 13:57:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@303 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 118 +++++++++++++++++++++++++-- 3 files changed, 113 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 0e66ef5ee..0f9806151 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -121,7 +121,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -ggdb -fomit-frame-pointer -mabi=apcs-gnu +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 #OPT += -falign-functions=16 diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb index 9171d3084..1ff7b8211 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -121,7 +121,7 @@ TOPT = -mthumb -D THUMB # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. -OPT = -ggdb -fomit-frame-pointer -mabi=apcs-gnu +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 #OPT += -falign-functions=16 diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index a4fb3de03..c99813fe8 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -17,6 +17,8 @@ along with this program. If not, see . */ +#include + #include #include #include @@ -27,8 +29,59 @@ #include #include +#define IPADDR0 10 +#define IPADDR1 151 +#define IPADDR2 218 +#define IPADDR3 245 + +#define SEND_RETRY_MAX 10 +#define SEND_RETRY_INTERVAL 2 + +static const struct uip_eth_addr macaddr = { + {0xC2, 0xAF, 0x51, 0x03, 0xCF, 0x46} +}; + static EvTimer evt; -struct EventListener el0, el1, el2; +struct EventListener el0, el1; + +#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + +/* + * uIP send function wrapping the EMAC functions. + */ +static void network_device_send(void) { + int i; + BufDescriptorEntry *bdep; + + for (i = 0; i < SEND_RETRY_MAX; i++) { + if ((bdep = EMACGetTransmitbuffer()) != NULL) { + uint8_t *bp = (uint8_t *)bdep->w1; + + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) + memcpy(bp, &uip_buf[0], uip_len); + else { + memcpy(bp, &uip_buf[0], UIP_LLH_LEN + UIP_TCPIP_HLEN); + memcpy(bp + UIP_LLH_LEN + UIP_TCPIP_HLEN, + uip_appdata, + uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); + } + EMACTransmit(bdep, uip_len); + return; + } + chThdSleep(SEND_RETRY_INTERVAL); + } + /* Dropped... */ +} + +/* + * uIP receive function wrapping the EMAC function. + */ +static size_t network_device_read(void) { + size_t size = UIP_CONF_BUFFER_SIZE; + if (EMACReceive(uip_buf, &size)) + return size; + return 0; +} void clock_init(void) {} @@ -38,7 +91,7 @@ clock_time_t clock_time( void ) } /* - * Executed as event handler at 1000mS intervals. + * Ethernet link status monitor. */ static void TimerHandler(eventid_t id) { @@ -48,18 +101,69 @@ static void TimerHandler(eventid_t id) { msg_t WebThread(void *p) { static const evhandler_t evhndl[] = { TimerHandler, - NULL, NULL }; + uip_ipaddr_t ipaddr; + struct timer periodic_timer, arp_timer; + + EMACSetAddress(&macaddr.addr[0]); + /* + * Event sources setup. + */ evtInit(&evt, 1000); /* Initializes an event timer object. */ evtStart(&evt); /* Starts the event timer. */ chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - chEvtRegister(&EMACFrameTransmitted, &el1, 1); - chEvtRegister(&EMACFrameReceived, &el2, 2); - + chEvtRegister(&EMACFrameReceived, &el1, 1); + + /* + * uIP initialization. + */ + timer_set(&periodic_timer, 500); + timer_set(&arp_timer, 10000); + uip_init(); + uip_setethaddr(macaddr); + uip_ipaddr(ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3); + uip_sethostaddr(ipaddr); + httpd_init(); + while (TRUE) { - chEvtWait(ALL_EVENTS, evhndl); + uip_len = network_device_read(); + if (uip_len > 0) { + if (BUF->type == htons(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } + else if (BUF->type == htons(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if (uip_len > 0) + network_device_send(); + } + } + else { + if (timer_expired(&periodic_timer)) { + int i; + timer_reset(&periodic_timer); + for (i = 0; i < UIP_CONNS; i++) { + uip_periodic(i); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } + if (timer_expired(&arp_timer)) { + timer_reset(&arp_timer); + uip_arp_timer(); + } + } + else { + chEvtWait(ALL_EVENTS, evhndl); + } + } } return 0; } -- cgit v1.2.3 From 9032cb5a184ecf8923e0e5046bafaa19da511898 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 May 2008 20:32:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@304 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index c99813fe8..127304295 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -119,8 +119,8 @@ msg_t WebThread(void *p) { /* * uIP initialization. */ - timer_set(&periodic_timer, 500); - timer_set(&arp_timer, 10000); + timer_set(&periodic_timer, CLOCK_SECOND / 2); + timer_set(&arp_timer, CLOCK_SECOND * 10); uip_init(); uip_setethaddr(macaddr); uip_ipaddr(ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3); -- cgit v1.2.3 From 49254d5eb3163415e19b6ef85b1be1205a9dd465 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 May 2008 09:02:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@305 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 1 - 1 file changed, 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index e3fb4a6ce..9dc1a0d7f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -69,7 +69,6 @@ ASRC = # enabled for all modules and that lowers performance. TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ -- cgit v1.2.3 From d1cad4edb86a9a4bd70bb9eb232c21f9540bbb0d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 26 May 2008 08:25:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@306 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 4 ++-- demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index e53bd5b7c..296ec7f67 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -26,8 +26,8 @@ #include "web/webthread.h" -static WorkingArea(waWebThread, 256); -static WorkingArea(waThread1, 64); +static WorkingArea(waWebThread, 512); +static WorkingArea(waThread1, 128); static msg_t Thread1(void *arg) { diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h index 289d4a150..273b7cb71 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h @@ -85,6 +85,13 @@ typedef uint16_t u16_t; */ typedef unsigned short uip_stats_t; +/** + * Modifier for packed structures. + * + * \hideinitializer + */ +#define UIP_CONF_PACKED __attribute__((packed)) + /** * Maximum number of TCP connections. * -- cgit v1.2.3 From 04a68710857b5583d3704c65cf74ff7bf9b59d6e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 26 May 2008 10:07:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@307 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 127304295..2a45309f5 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -54,7 +54,7 @@ static void network_device_send(void) { BufDescriptorEntry *bdep; for (i = 0; i < SEND_RETRY_MAX; i++) { - if ((bdep = EMACGetTransmitbuffer()) != NULL) { + if ((bdep = EMACGetTransmitBuffer()) != NULL) { uint8_t *bp = (uint8_t *)bdep->w1; if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) -- cgit v1.2.3 From d8e1d5a103aa5cd43e4d7e2437448327aa06ff08 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 27 May 2008 09:30:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@310 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt | 8 +++++++- demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h | 9 +++++++++ demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h | 9 ++------- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 8 ++++++-- 5 files changed, 25 insertions(+), 11 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index 296ec7f67..bf23f3278 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -27,7 +27,7 @@ #include "web/webthread.h" static WorkingArea(waWebThread, 512); -static WorkingArea(waThread1, 128); +static WorkingArea(waThread1, 64); static msg_t Thread1(void *arg) { diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt b/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt index fc561fa4d..4dedc0658 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt @@ -8,7 +8,10 @@ The demo runs on an Olimex SAM7-EX256 board. ** The Demo ** -Work in progress, not finished yet. +The demo currently just flashes the LCD background using a thread and serves +HTTP requests at address 192.168.1.20 on port 80. +The button SW1 prints an "Hello World!" string on COM1, the button SW2 +activates che ChibiOS/RT test suite, output on COM1. ** Build Procedure ** @@ -24,3 +27,6 @@ Also note that not all the files present in the Atmel library are distribuited with ChibiOS/RT, you can find the whole library on the Atmel web site: http://www.atmel.com + +The uIP stack also has its own license, please read the info into the included +uIP distribution files. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h new file mode 100644 index 000000000..744cf56ef --- /dev/null +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h @@ -0,0 +1,9 @@ +#ifndef __CC_ARCH_H__ +#define __CC_ARCH_H__ + +#define PACK_STRUCT_FIELD(x) x __attribute__((packed)) +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END + +#endif /* __CC_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h index 273b7cb71..b6a17c970 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h @@ -57,6 +57,8 @@ #include +#include /* patched */ + /** * 8 bit datatype * @@ -85,13 +87,6 @@ typedef uint16_t u16_t; */ typedef unsigned short uip_stats_t; -/** - * Modifier for packed structures. - * - * \hideinitializer - */ -#define UIP_CONF_PACKED __attribute__((packed)) - /** * Maximum number of TCP connections. * diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 2a45309f5..425a6366d 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -29,6 +29,10 @@ #include #include +//#define IPADDR0 192 +//#define IPADDR1 168 +//#define IPADDR2 1 +//#define IPADDR3 20 #define IPADDR0 10 #define IPADDR1 151 #define IPADDR2 218 @@ -130,7 +134,7 @@ msg_t WebThread(void *p) { while (TRUE) { uip_len = network_device_read(); if (uip_len > 0) { - if (BUF->type == htons(UIP_ETHTYPE_IP)) { + if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { uip_arp_ipin(); uip_input(); if (uip_len > 0) { @@ -138,7 +142,7 @@ msg_t WebThread(void *p) { network_device_send(); } } - else if (BUF->type == htons(UIP_ETHTYPE_ARP)) { + else if (BUF->type == HTONS(UIP_ETHTYPE_ARP)) { uip_arp_arpin(); if (uip_len > 0) network_device_send(); -- cgit v1.2.3 From 16e097d23edef273e73f64d9f7ea51ecc0636e77 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 27 May 2008 13:26:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@311 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 1 - demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 121 ++++++++++++++------------- 2 files changed, 65 insertions(+), 57 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 0f9806151..a1ebaba71 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -74,7 +74,6 @@ KSRC = ../../src/chinit.c ../../src/chdebug.c \ # List of the required uIP source files. USRC = ../../ext/uip-1.0/uip/uip_arp.c \ ../../ext/uip-1.0/uip/psock.c \ - ../../ext/uip-1.0/uip/timer.c \ ../../ext/uip-1.0/uip/uip.c \ ../../ext/uip-1.0/apps/webserver/httpd.c \ ../../ext/uip-1.0/apps/webserver/http-strings.c \ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 425a6366d..825ff1eff 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -26,7 +26,6 @@ #include #include #include -#include #include //#define IPADDR0 192 @@ -45,9 +44,6 @@ static const struct uip_eth_addr macaddr = { {0xC2, 0xAF, 0x51, 0x03, 0xCF, 0x46} }; -static EvTimer evt; -struct EventListener el0, el1; - #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) /* @@ -95,79 +91,92 @@ clock_time_t clock_time( void ) } /* - * Ethernet link status monitor. + * TCP/IP periodic timer. + */ +static void PeriodicTimerHandler(eventid_t id) { + int i; + + for (i = 0; i < UIP_CONNS; i++) { + uip_periodic(i); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } +} + +/* + * ARP periodic timer. */ -static void TimerHandler(eventid_t id) { +static void ARPTimerHandler(eventid_t id) { + uip_arp_timer(); (void)EMACGetLinkStatus(); } +/* + * Ethernet frame received. + */ +static void FrameReceivedHandler(eventid_t id) { + + while ((uip_len = network_device_read()) > 0) { + if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } + else if (BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if (uip_len > 0) + network_device_send(); + } + } +} + +#define FRAME_RECEIVED_ID 0 +#define PERIODIC_TIMER_ID 1 +#define ARP_TIMER_ID 2 + +static const evhandler_t evhndl[] = { + FrameReceivedHandler, + PeriodicTimerHandler, + ARPTimerHandler +}; + msg_t WebThread(void *p) { - static const evhandler_t evhndl[] = { - TimerHandler, - NULL - }; + EvTimer evt1, evt2; + EventListener el0, el1, el2; uip_ipaddr_t ipaddr; - struct timer periodic_timer, arp_timer; EMACSetAddress(&macaddr.addr[0]); + (void)EMACGetLinkStatus(); /* * Event sources setup. */ - evtInit(&evt, 1000); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - chEvtRegister(&EMACFrameReceived, &el1, 1); + chEvtRegister(&EMACFrameReceived, &el0, FRAME_RECEIVED_ID); - /* + evtInit(&evt1, CH_FREQUENCY / 2); + evtStart(&evt1); + chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); + + evtInit(&evt2, CH_FREQUENCY * 10); + evtStart(&evt2); + chEvtRegister(&evt2.et_es, &el2, ARP_TIMER_ID); + + /* * uIP initialization. */ - timer_set(&periodic_timer, CLOCK_SECOND / 2); - timer_set(&arp_timer, CLOCK_SECOND * 10); uip_init(); uip_setethaddr(macaddr); uip_ipaddr(ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3); uip_sethostaddr(ipaddr); httpd_init(); - while (TRUE) { - uip_len = network_device_read(); - if (uip_len > 0) { - if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if (uip_len > 0) { - uip_arp_out(); - network_device_send(); - } - } - else if (BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if (uip_len > 0) - network_device_send(); - } - } - else { - if (timer_expired(&periodic_timer)) { - int i; - timer_reset(&periodic_timer); - for (i = 0; i < UIP_CONNS; i++) { - uip_periodic(i); - if (uip_len > 0) { - uip_arp_out(); - network_device_send(); - } - } - if (timer_expired(&arp_timer)) { - timer_reset(&arp_timer); - uip_arp_timer(); - } - } - else { - chEvtWait(ALL_EVENTS, evhndl); - } - } - } + while (TRUE) + chEvtWait(ALL_EVENTS, evhndl); return 0; } -- cgit v1.2.3 From 9873f0d9548d49d471b3fcb272b081f2c3b6cd64 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 27 May 2008 13:52:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@312 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 825ff1eff..05fea0c69 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -151,14 +151,12 @@ msg_t WebThread(void *p) { EventListener el0, el1, el2; uip_ipaddr_t ipaddr; - EMACSetAddress(&macaddr.addr[0]); - (void)EMACGetLinkStatus(); - /* * Event sources setup. */ chEvtRegister(&EMACFrameReceived, &el0, FRAME_RECEIVED_ID); - + chEvtSend(&EMACFrameReceived); /* In case some frames are already buffered */ + evtInit(&evt1, CH_FREQUENCY / 2); evtStart(&evt1); chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); @@ -167,7 +165,13 @@ msg_t WebThread(void *p) { evtStart(&evt2); chEvtRegister(&evt2.et_es, &el2, ARP_TIMER_ID); - /* + /* + * EMAC settings. + */ + EMACSetAddress(&macaddr.addr[0]); + (void)EMACGetLinkStatus(); + + /* * uIP initialization. */ uip_init(); -- cgit v1.2.3 From 70a9f7f82c8c71ae2a6b499d0f3448cbb190a29c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 31 May 2008 07:49:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@314 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt | 4 +++- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 12 ++++-------- 2 files changed, 7 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt b/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt index 4dedc0658..129f245c2 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt @@ -9,7 +9,8 @@ The demo runs on an Olimex SAM7-EX256 board. ** The Demo ** The demo currently just flashes the LCD background using a thread and serves -HTTP requests at address 192.168.1.20 on port 80. +HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP +address into webthread.c in order to adapt it to your network settings). The button SW1 prints an "Hello World!" string on COM1, the button SW2 activates che ChibiOS/RT test suite, output on COM1. @@ -17,6 +18,7 @@ activates che ChibiOS/RT test suite, output on COM1. The demo was built using the YAGARTO toolchain but any toolchain based on GCC and GNU userspace programs will work. +The demo requires the patcher uIP 1.0 stack, see: ./ext/readme.txt ** Notes ** diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 05fea0c69..727cd3dc1 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -28,14 +28,10 @@ #include #include -//#define IPADDR0 192 -//#define IPADDR1 168 -//#define IPADDR2 1 -//#define IPADDR3 20 -#define IPADDR0 10 -#define IPADDR1 151 -#define IPADDR2 218 -#define IPADDR3 245 +#define IPADDR0 192 +#define IPADDR1 168 +#define IPADDR2 1 +#define IPADDR3 20 #define SEND_RETRY_MAX 10 #define SEND_RETRY_INTERVAL 2 -- cgit v1.2.3 From 3d8180d95a02c876aa9de65a3364fd5de6657bc7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 19 Jun 2008 13:14:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@319 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chtypes.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'demos') diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 2fd609b1f..0b74459bc 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -40,5 +40,8 @@ typedef uint32_t systime_t; typedef int32_t cnt_t; #define INLINE inline +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END #endif /* _CHTYPES_H_ */ -- cgit v1.2.3 From 5c37fb51c8e91ea1b5d2ac34d358c82d65ec8ac5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 20 Jun 2008 11:37:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@320 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/mmcsd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index c06123f88..98d377406 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -253,7 +253,7 @@ bool_t mmcGetSize(MMCCSD *data) { bool_t mmcRead(uint8_t *buf, uint32_t blknum) { sspAcquireBus(); - sendhdr(CMDREAD, blknum << 8); + sendhdr(CMDREAD, blknum << 9); if (recvr1() != 0x00) { sspReleaseBus(); return TRUE; @@ -277,7 +277,7 @@ bool_t mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { static const uint8_t stopcmd[] = {0x40 | CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; sspAcquireBus(); - sendhdr(CMDREADMULTIPLE, blknum << 8); + sendhdr(CMDREADMULTIPLE, blknum << 9); if (recvr1() != 0x00) { sspReleaseBus(); return TRUE; @@ -314,7 +314,7 @@ bool_t mmcWrite(uint8_t *buf, uint32_t blknum) { uint8_t b[4]; sspAcquireBus(); - sendhdr(CMDWRITE, blknum << 8); + sendhdr(CMDWRITE, blknum << 9); if (recvr1() != 0x00) { sspReleaseBus(); return TRUE; @@ -346,7 +346,7 @@ bool_t mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { uint8_t b[4]; sspAcquireBus(); - sendhdr(CMDWRITEMULTIPLE, blknum << 8); + sendhdr(CMDWRITEMULTIPLE, blknum << 9); if (recvr1() != 0x00) { sspReleaseBus(); return TRUE; -- cgit v1.2.3 From 300ecfe103d1d305e78a15196d2fa1aecfddc729 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 26 Jun 2008 10:54:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@323 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 5d0450021..e0061f78b 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -70,7 +70,9 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ../../src/lib/evtimer.c \ + ../../test/test.c ../../test/testrdy.c ../../test/testsem.c \ + ../../test/testmtx.c ../../test/testmsg.c \ board.c buzzer.c mmcsd.c main.c # List THUMB-mode C sources here -- cgit v1.2.3 From 8292744ffd977bbe16d4fe4273a4acdc196e463d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 26 Jun 2008 13:36:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@324 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index e0061f78b..5ee1985a6 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -72,7 +72,7 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../src/chserial.c \ ../../src/lib/evtimer.c \ ../../test/test.c ../../test/testrdy.c ../../test/testsem.c \ - ../../test/testmtx.c ../../test/testmsg.c \ + ../../test/testmtx.c ../../test/testmsg.c ../../test/testbmk.c \ board.c buzzer.c mmcsd.c main.c # List THUMB-mode C sources here -- cgit v1.2.3 From cc44376c6e07d5c47561db9f6179e51e0654391d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 26 Jun 2008 14:06:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@325 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 12 +++++++----- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 12 +++++++----- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 18 +++++++----------- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 18 +++++++----------- demos/ARM7-LPC214x-G++/Makefile | 12 +++++++----- demos/ARM7-LPC214x-G++/Makefile.thumb | 12 +++++++----- demos/ARM7-LPC214x-GCC-minimal/Makefile | 9 +++++---- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 9 +++++---- demos/ARM7-LPC214x-GCC/Makefile | 12 ++++++------ demos/ARM7-LPC214x-GCC/Makefile.thumb | 12 +++++++----- demos/ARMCM3-STM32F103-GCC/Makefile | 12 +++++++----- demos/AVR-AT90CANx-GCC/Makefile | 12 +++++++----- demos/AVR-ATmega128-GCC/Makefile | 12 +++++++----- demos/MSP430-MSP430x1611-GCC/Makefile | 12 +++++++----- demos/Win32-MinGW/Makefile | 13 +++++++------ 15 files changed, 100 insertions(+), 87 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 0ff70ca56..7d3a7b71e 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -61,14 +61,16 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ at91lib/aic.c \ board.c main.c diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 9dc1a0d7f..0b2779708 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -61,6 +61,10 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ASRC = @@ -69,11 +73,9 @@ ASRC = # enabled for all modules and that lowers performance. TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ at91lib/aic.c \ board.c main.c diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index a1ebaba71..77651350c 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -61,15 +61,9 @@ UDEFS = # Define ASM defines here UADEFS = -# List of all the ChibiOS/RT kernel files, there is no need to remove the files -# from this list, you can disable parts of the kernel by editing chconf.h. -KSRC = ../../src/chinit.c ../../src/chdebug.c \ - ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c \ - ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk # List of the required uIP source files. USRC = ../../ext/uip-1.0/uip/uip_arp.c \ @@ -84,8 +78,10 @@ USRC = ../../ext/uip-1.0/uip/uip_arp.c \ ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ - ${KSRC} ${USRC} \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ${USRC} \ + ../../src/lib/evtimer.c \ at91lib/aic.c \ web/webthread.c \ board.c main.c diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb index 1ff7b8211..431111305 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -61,15 +61,9 @@ UDEFS = # Define ASM defines here UADEFS = -# List of all the ChibiOS/RT kernel files, there is no need to remove the files -# from this list, you can disable parts of the kernel by editing chconf.h. -KSRC = ../../src/chinit.c ../../src/chdebug.c \ - ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c \ - ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c \ - ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk # List of the required uIP source files. USRC = ../../ext/uip-1.0/uip/uip_arp.c \ @@ -90,8 +84,10 @@ ASRC = TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ - ${KSRC} ${USRC} \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ${USRC} \ + ../../src/lib/evtimer.c \ at91lib/aic.c \ web/webthread.c \ board.c main.c diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 6c04023a8..f54c1ba2d 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -67,15 +67,17 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ACSRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ board.c # List ARM-mode C++ source files here diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 9171d2b72..4e2fd2f7c 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -67,6 +67,10 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ACSRC = @@ -77,11 +81,9 @@ ACPPSRC = TCSRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ board.c # List THUMB-mode C++ source files here diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index fc941b4ce..93e7df446 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -61,13 +61,14 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ASRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ + ${KERNSRC} \ board.c main.c # List THUMB-mode C sources here diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 95cb19000..11b393c47 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -61,6 +61,10 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ASRC = @@ -69,10 +73,7 @@ ASRC = # enabled for all modules and that lowers performance. TSRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ + ${KERNSRC} \ board.c main.c # List ASM source files here diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 5ee1985a6..a2dd69afe 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -61,18 +61,18 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ASRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ + ${KERNSRC} \ + ${TESTSRC} \ ../../src/lib/evtimer.c \ - ../../test/test.c ../../test/testrdy.c ../../test/testsem.c \ - ../../test/testmtx.c ../../test/testmsg.c ../../test/testbmk.c \ board.c buzzer.c mmcsd.c main.c # List THUMB-mode C sources here diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 83e19ebff..0e426e5b7 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -61,6 +61,10 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here ASRC = @@ -71,11 +75,9 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ board.c buzzer.c mmcsd.c main.c # List ASM source files here diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index d51c8113d..dbf9fd9eb 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -62,14 +62,16 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ ../../ports/ARMCM3-STM32F103/stm32_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ board.c main.c # List ASM source files here diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index 37c56acf9..a72f1f913 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -79,14 +79,16 @@ TARGET = ch OBJDIR = . +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + + # List C source files here. (C dependencies are automatically generated.) SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ + ${KERNSRC} \ + ${TESTSRC} \ ../../src/lib/evtimer.c \ - ../../test/test.c \ board.c main.c diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index 3be566c19..89b5118ff 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -79,14 +79,16 @@ TARGET = ch OBJDIR = . +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + + # List C source files here. (C dependencies are automatically generated.) SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ + ${KERNSRC} \ + ${TESTSRC} \ ../../src/lib/evtimer.c \ - ../../test/test.c \ board.c lcd.c main.c diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 637a26456..4d2b01bd3 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -61,13 +61,15 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List ARM-mode C source files here SRC = ../../ports/MSP430/chcore.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ - ../../src/lib/evtimer.c ../../test/test.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ board.c main.c # List ASM source files here diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index ea206b0d0..fe06db6e1 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -55,13 +55,14 @@ UDEFS = # Define ASM defines here UADEFS = +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + # List C source files here -SRC = chcore.c demo.c \ - ../../test/test.c ../../ports/win32/simcom.c \ - ../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \ - ../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \ - ../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \ - ../../src/chserial.c \ +SRC = chcore.c demo.c ../../ports/win32/simcom.c \ + ${KERNSRC} \ + ${TESTSRC} # List ASM source files here ASRC = chcore2.s -- cgit v1.2.3 From e5bd63772994b9b9aa448c43870acf3580efaab7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 4 Jul 2008 09:50:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@332 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 10cae19da..d83a386d5 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -131,8 +131,8 @@ int main(int argc, char **argv) { * are not started in order to make accurate benchmarks. */ if ((IO0PIN & 0x00018000) == 0x00018000) { - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); - chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateFast(NORMALPRIO, waThread2, sizeof(waThread2), Thread2); } /* -- cgit v1.2.3 From f53cac6961b33a09913a5ae87dfe410686f153bb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 4 Jul 2008 12:12:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@333 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 4 ++-- demos/ARM7-LPC214x-GCC-minimal/main.c | 4 ++-- demos/ARMCM3-STM32F103-GCC/main.c | 2 +- demos/AVR-AT90CANx-GCC/main.c | 2 +- demos/AVR-ATmega128-GCC/main.c | 2 +- demos/MSP430-MSP430x1611-GCC/main.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index e5c2e7d4f..db1959c0c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -46,7 +46,7 @@ int main(int argc, char **argv) { */ chSysInit(); - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); while (TRUE) { chThdSleep(500); diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index bf23f3278..7861a0408 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -51,8 +51,8 @@ int main(int argc, char **argv) { */ chSysInit(); - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); - chThdCreate(NORMALPRIO - 1, 0, waWebThread, sizeof(waWebThread), WebThread, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateFast(NORMALPRIO - 1, waWebThread, sizeof(waWebThread), WebThread); while (TRUE) { chThdSleep(500); diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 87d59dce0..bbbc3ce6c 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -69,8 +69,8 @@ int main(int argc, char **argv) { /* * Creates the blinker threads. */ - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); - chThdCreate(NORMALPRIO, 0, waThread2, sizeof(waThread2), Thread2, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateFast(NORMALPRIO, waThread2, sizeof(waThread2), Thread2); /* * Normal main() thread activity, in this demo it does nothing except diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 6a2037393..c8d35815c 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -52,7 +52,7 @@ int main(int argc, char **argv) { /* * Creates the blinker threads. */ - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); /* * Normal main() thread activity, in this demo it does nothing except diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 2379b670f..9dde101ef 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -69,7 +69,7 @@ int main(int argc, char **argv) { /* * Starts the LED blinker thread. */ - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); while(TRUE) chEvtWait(ALL_EVENTS, handlers); diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 53fe21b2d..f238642ef 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -80,7 +80,7 @@ int main(int argc, char **argv) { /* * Starts the LED blinker thread. */ - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); while(TRUE) chEvtWait(ALL_EVENTS, handlers); diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 6790720ef..07b420b55 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -56,7 +56,7 @@ int main(int argc, char **argv) { /* * Creates the blinker threads. */ - chThdCreate(NORMALPRIO, 0, waThread1, sizeof(waThread1), Thread1, NULL); + chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); /* * Normal main() thread activity, in this demo it does nothing except -- cgit v1.2.3 From 65961139301315ba0507a07c607e961b1c40a5ae Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Jul 2008 10:22:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@348 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index a1a0080ef..3f7953d5b 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -31,7 +31,7 @@ /* * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. */ -//#define SYSCLK_48 +#define SYSCLK_48 /* * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. -- cgit v1.2.3 From 077d372e2ffc959be1f13d23ee14d00a53589b4a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Jul 2008 10:38:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@349 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 12 ++++++------ demos/ARM7-LPC214x-GCC/buzzer.c | 2 +- demos/ARM7-LPC214x-GCC/mmcsd.c | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 727cd3dc1..547437047 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -52,7 +52,7 @@ static void network_device_send(void) { for (i = 0; i < SEND_RETRY_MAX; i++) { if ((bdep = EMACGetTransmitBuffer()) != NULL) { uint8_t *bp = (uint8_t *)bdep->w1; - + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) memcpy(bp, &uip_buf[0], uip_len); else { @@ -98,7 +98,7 @@ static void PeriodicTimerHandler(eventid_t id) { uip_arp_out(); network_device_send(); } - } + } } /* @@ -114,7 +114,7 @@ static void ARPTimerHandler(eventid_t id) { * Ethernet frame received. */ static void FrameReceivedHandler(eventid_t id) { - + while ((uip_len = network_device_read()) > 0) { if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { uip_arp_ipin(); @@ -146,13 +146,13 @@ msg_t WebThread(void *p) { EvTimer evt1, evt2; EventListener el0, el1, el2; uip_ipaddr_t ipaddr; - + /* * Event sources setup. */ chEvtRegister(&EMACFrameReceived, &el0, FRAME_RECEIVED_ID); - chEvtSend(&EMACFrameReceived); /* In case some frames are already buffered */ - + chEvtBroadcast(&EMACFrameReceived); /* In case some frames are already buffered */ + evtInit(&evt1, CH_FREQUENCY / 2); evtStart(&evt1); chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index 249b1542b..25be0e2d9 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -61,7 +61,7 @@ static void stop(void *p) { TC *tc = T1Base; StopCounter(tc); - chEvtSendI(&BuzzerSilentEventSource); + chEvtBroadcastI(&BuzzerSilentEventSource); } void PlaySound(int freq, systime_t duration) { diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 98d377406..bd1997fce 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -44,7 +44,7 @@ void tmrfunc(void *par) { if (cnt) { if (!(IO1PIN & (1 << 25))) { if (!--cnt) - chEvtSendI(&MMCInsertEventSource); + chEvtBroadcastI(&MMCInsertEventSource); } else cnt = POLLING_INTERVAL; @@ -52,7 +52,7 @@ void tmrfunc(void *par) { else { if (IO1PIN & (1 << 25)) { cnt = POLLING_INTERVAL; - chEvtSendI(&MMCRemoveEventSource); + chEvtBroadcastI(&MMCRemoveEventSource); } } chVTSetI(&vt, 10, tmrfunc, NULL); -- cgit v1.2.3 From 266206d33a7626341f3a206d730cb842dd39d2bc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Jul 2008 12:09:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@351 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 3f7953d5b..a1a0080ef 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -31,7 +31,7 @@ /* * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. */ -#define SYSCLK_48 +//#define SYSCLK_48 /* * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. -- cgit v1.2.3 From eb9b4efd31018e4949e3cc09830a5ecfc1304664 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 25 Jul 2008 14:32:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@353 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 7 ++++++- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 7 ++++++- demos/ARM7-LPC214x-G++/chconf.h | 7 ++++++- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 7 ++++++- demos/ARM7-LPC214x-GCC/chconf.h | 7 ++++++- demos/ARMCM3-STM32F103-GCC/chconf.h | 7 ++++++- demos/AVR-AT90CANx-GCC/chconf.h | 7 ++++++- demos/AVR-ATmega128-GCC/chconf.h | 7 ++++++- demos/MSP430-MSP430x1611-GCC/chconf.h | 7 ++++++- demos/Win32-MinGW/chconf.h | 7 ++++++- 10 files changed, 60 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index c8817f85c..8db71b445 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index c8817f85c..8db71b445 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index c8817f85c..8db71b445 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index d12a1827e..9f903df06 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index c8817f85c..8db71b445 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index c8817f85c..8db71b445 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 17c2c3d38..fca0159a2 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 17c2c3d38..fca0159a2 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -38,6 +38,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -138,7 +142,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 4ca12304e..7e29d314e 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -39,6 +39,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -139,7 +143,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 15cf3d323..b17295c65 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -43,6 +43,10 @@ * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS +/** Configuration option: if specified then the kernel performs the round + * robin scheduling algorithm on threads of equal priority. */ +#define CH_USE_ROUNDROBIN + /** Configuration option: if specified then the System Timer subsystem is * included in the kernel.*/ #define CH_USE_SYSTEMTIME @@ -143,7 +147,8 @@ #define CH_FREQUENCY 1000 /** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs.*/ + * threads before preemption occurs. This option is only meaningful if the + * option \p CH_USE_ROUNDROBIN is also active.*/ #define CH_TIME_QUANTUM 20 /** Configuration option: Defines a CPU register to be used as storage for the -- cgit v1.2.3 From 69f9642bf44e6e3de680b07a22a290b9219ab47d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Jul 2008 09:25:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@359 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chconf.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 8db71b445..a1d28bc9c 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -75,6 +75,8 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. -- cgit v1.2.3 From 6ae1a6c88223d875f0dbd81066d4d8f40713b0a0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Jul 2008 09:46:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@360 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 4 ++++ demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 4 ++++ demos/ARM7-LPC214x-G++/chconf.h | 4 ++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 4 ++++ demos/ARM7-LPC214x-GCC/chconf.h | 2 ++ demos/ARMCM3-STM32F103-GCC/chconf.h | 4 ++++ demos/AVR-AT90CANx-GCC/chconf.h | 4 ++++ demos/AVR-ATmega128-GCC/chconf.h | 4 ++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 4 ++++ demos/Win32-MinGW/chconf.h | 4 ++++ 10 files changed, 38 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 8db71b445..5555184c4 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -75,6 +75,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 8db71b445..5555184c4 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -75,6 +75,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 8db71b445..5555184c4 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -75,6 +75,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 9f903df06..83a8865af 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -75,6 +75,10 @@ * APIs are included in the kernel.*/ //#define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +//#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index a1d28bc9c..5555184c4 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -75,6 +75,8 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ #define CH_USE_CONDVARS /** Configuration option: if specified then the Semaphores with timeout APIs diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 8db71b445..5555184c4 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -75,6 +75,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index fca0159a2..a6b0f4a95 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -75,6 +75,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index fca0159a2..a6b0f4a95 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -75,6 +75,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 7e29d314e..b4bc56505 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -76,6 +76,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index b17295c65..e18ab2d0b 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -80,6 +80,10 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel.*/ +#define CH_USE_CONDVARS + /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. -- cgit v1.2.3 From b27329f45b8e51d9ee2149e2ea102d13ce15f886 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Jul 2008 17:39:01 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@366 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 4 ---- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 4 ---- demos/ARM7-LPC214x-G++/chconf.h | 4 ---- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 4 ---- demos/ARM7-LPC214x-GCC/chconf.h | 4 ---- demos/ARMCM3-STM32F103-GCC/chconf.h | 4 ---- demos/AVR-AT90CANx-GCC/chconf.h | 4 ---- demos/AVR-ATmega128-GCC/chconf.h | 4 ---- demos/MSP430-MSP430x1611-GCC/chconf.h | 4 ---- demos/Win32-MinGW/chconf.h | 4 ---- 10 files changed, 40 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 5555184c4..8db71b445 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 5555184c4..8db71b445 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 5555184c4..8db71b445 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 83a8865af..9f903df06 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ //#define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -//#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 5555184c4..8db71b445 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 5555184c4..8db71b445 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index a6b0f4a95..fca0159a2 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index a6b0f4a95..fca0159a2 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -75,10 +75,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index b4bc56505..7e29d314e 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -76,10 +76,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index e18ab2d0b..b17295c65 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -80,10 +80,6 @@ * APIs are included in the kernel.*/ #define CH_USE_SEMSW -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel.*/ -#define CH_USE_CONDVARS - /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. * @note requires \p CH_USE_SEMAPHORES. -- cgit v1.2.3 From b689f00e31591e2f3b5b3607b15be428dfeb7e88 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 25 Aug 2008 13:00:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@401 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.h | 1 + 1 file changed, 1 insertion(+) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index bc0ed3e42..c3c3f3a0b 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -59,6 +59,7 @@ typedef struct { #define chSysLock() #define chSysUnlock() +#define chSysEnable() #define chSysPuts(msg) {} #define chSysIRQEnterI() #define chSysIRQExitI() -- cgit v1.2.3 From 01afd268a5f8bb48007b44e6c2aa7c0d3eafe757 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 25 Aug 2008 13:40:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@403 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 15 +++++++++++++-- demos/ARM7-LPC214x-GCC/Makefile.thumb | 15 +++++++++++++-- demos/ARM7-LPC214x-GCC/ch.ld | 13 +++++++++++-- 3 files changed, 37 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index a2dd69afe..c10ff9d94 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -108,6 +111,10 @@ OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + # Define warning options here WARN = -Wall -Wstrict-prototypes @@ -126,10 +133,14 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 0e426e5b7..b388e64d7 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -108,6 +111,10 @@ OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + # Define warning options here WARN = -Wall -Wstrict-prototypes @@ -126,10 +133,14 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index a71fac21b..bb59cec1c 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -48,11 +48,16 @@ SECTIONS .text : { _text = .; - *(.text); + KEEP(*(.startup)) + *(.text) + *(.text.*); *(.rodata); - *(.rodata*); + *(.rodata.*); *(.glue_7t); *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); . = ALIGN(4); _etext = .; } > flash @@ -64,6 +69,8 @@ SECTIONS _data = .; *(.data) . = ALIGN(4); + *(.data.*) + . = ALIGN(4); *(.ramtext) . = ALIGN(4); _edata = .; @@ -74,6 +81,8 @@ SECTIONS _bss_start = .; *(.bss) . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); *(COMMON) . = ALIGN(4); _bss_end = .; -- cgit v1.2.3 From 65baafa9e6e82293a202c96e832c7779b7216550 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 25 Aug 2008 14:17:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@404 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 15 +++++++++++++-- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 15 +++++++++++++-- demos/ARM7-AT91SAM7X-GCC/ch.ld | 14 ++++++++++++-- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 14 +++++++++++++- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 14 +++++++++++++- demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld | 14 ++++++++++++-- demos/ARM7-LPC214x-G++/Makefile | 15 +++++++++++++-- demos/ARM7-LPC214x-G++/Makefile.thumb | 15 +++++++++++++-- demos/ARM7-LPC214x-G++/ch.ld | 5 +++-- demos/ARM7-LPC214x-GCC-minimal/Makefile | 15 +++++++++++++-- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 15 +++++++++++++-- demos/ARM7-LPC214x-GCC-minimal/ch.ld | 13 +++++++++++-- demos/ARM7-LPC214x-GCC/Makefile | 8 ++++---- demos/ARM7-LPC214x-GCC/Makefile.thumb | 8 ++++---- demos/ARMCM3-STM32F103-GCC/Makefile | 15 +++++++++++++-- demos/ARMCM3-STM32F103-GCC/ch.ld | 14 +++++++++++--- 16 files changed, 174 insertions(+), 35 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 7d3a7b71e..5629c9842 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -114,6 +117,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -125,10 +132,14 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 0b2779708..4ca9bded5 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -114,6 +117,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -125,10 +132,14 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 541c73b5b..7459bdac1 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -45,11 +45,16 @@ SECTIONS .text : { _text = .; - *(.text); + KEEP(*(.startup)) + *(.text) + *(.text.*); *(.rodata); - *(.rodata*); + *(.rodata.*); *(.glue_7t); *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); . = ALIGN(4); _etext = .; } > flash @@ -58,9 +63,12 @@ SECTIONS .data : { + _data = .; _data = .; *(.data) . = ALIGN(4); + *(.data.*) + . = ALIGN(4); *(.ramtext) . = ALIGN(4); _edata = .; @@ -71,6 +79,8 @@ SECTIONS _bss_start = .; *(.bss) . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); *(COMMON) . = ALIGN(4); _bss_end = .; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 77651350c..243d525f8 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -127,6 +130,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -138,10 +145,15 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb index 431111305..0b5c72349 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -128,6 +131,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -139,10 +146,15 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld index 541c73b5b..7459bdac1 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld @@ -45,11 +45,16 @@ SECTIONS .text : { _text = .; - *(.text); + KEEP(*(.startup)) + *(.text) + *(.text.*); *(.rodata); - *(.rodata*); + *(.rodata.*); *(.glue_7t); *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); . = ALIGN(4); _etext = .; } > flash @@ -58,9 +63,12 @@ SECTIONS .data : { + _data = .; _data = .; *(.data) . = ALIGN(4); + *(.data.*) + . = ALIGN(4); *(.ramtext) . = ALIGN(4); _edata = .; @@ -71,6 +79,8 @@ SECTIONS _bss_start = .; *(.bss) . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); *(COMMON) . = ALIGN(4); _bss_end = .; diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index f54c1ba2d..95d6bfdb8 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -32,6 +32,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -129,6 +132,10 @@ WARN = -Wall # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -145,11 +152,15 @@ OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(WARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 4e2fd2f7c..29f2a61a4 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -32,6 +32,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -129,6 +132,10 @@ WARN = -Wall # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -145,11 +152,15 @@ OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(WARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index 5fe907142..bb59cec1c 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; +__sys_stack_size__ = 0x0100; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY @@ -48,7 +48,8 @@ SECTIONS .text : { _text = .; - *(.text); + KEEP(*(.startup)) + *(.text) *(.text.*); *(.rodata); *(.rodata.*); diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 93e7df446..d035f6f23 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -111,6 +114,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -122,10 +129,14 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 11b393c47..ace728b15 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -26,6 +26,9 @@ BIN = $(CP) -O binary MCU = arm7tdmi +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -111,6 +114,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -122,10 +129,14 @@ ASMOBJS = $(ASMSRC:.s=.o) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Thumb interwork enabled only if needed because it kills performance. ifneq ($(TSRC),) diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld index a71fac21b..bb59cec1c 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -48,11 +48,16 @@ SECTIONS .text : { _text = .; - *(.text); + KEEP(*(.startup)) + *(.text) + *(.text.*); *(.rodata); - *(.rodata*); + *(.rodata.*); *(.glue_7t); *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); . = ALIGN(4); _etext = .; } > flash @@ -64,6 +69,8 @@ SECTIONS _data = .; *(.data) . = ALIGN(4); + *(.data.*) + . = ALIGN(4); *(.ramtext) . = ALIGN(4); _edata = .; @@ -74,6 +81,8 @@ SECTIONS _bss_start = .; *(.bss) . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); *(COMMON) . = ALIGN(4); _bss_end = .; diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index c10ff9d94..8e1790bb2 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -111,10 +111,6 @@ OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - # Define warning options here WARN = -Wall -Wstrict-prototypes @@ -122,6 +118,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index b388e64d7..4b62f9091 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -111,10 +111,6 @@ OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - # Define warning options here WARN = -Wall -Wstrict-prototypes @@ -122,6 +118,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index dbf9fd9eb..a0c76a43b 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -27,6 +27,9 @@ BIN = $(CP) -O binary MCU = cortex-m3 +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -103,6 +106,10 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(LINK_GC),yes) + OPT += -ffunction-sections -fdata-sections +endif + INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -113,10 +120,14 @@ OBJS = $(ASMOBJS) $(COBJS) LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU) -mthumb +ODFLAGS = -x --syms ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms +ifeq ($(LINK_GC),yes) + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) +else + LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index d5f948476..b6b390f80 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -41,12 +41,16 @@ SECTIONS .text : { _text = .; - *(INTVEC); - *(.text); + KEEP(*(INTVEC)); + *(.text) + *(.text.*); *(.rodata); - *(.rodata*); + *(.rodata.*); *(.glue_7t); *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); . = ALIGN(4); _etext = .; } > flash @@ -58,6 +62,8 @@ SECTIONS _data = .; *(.data) . = ALIGN(4); + *(.data.*) + . = ALIGN(4); *(.ramtext) . = ALIGN(4); _edata = .; @@ -68,6 +74,8 @@ SECTIONS _bss_start = .; *(.bss) . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); *(COMMON) . = ALIGN(4); _bss_end = .; -- cgit v1.2.3 From ac6b3caba1b75ca603e63946f8ca7f54c7ab598f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 26 Aug 2008 10:38:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@407 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 8 ++++++++ demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 8 ++++++++ demos/ARM7-LPC214x-G++/chconf.h | 8 ++++++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 8 ++++++++ demos/ARM7-LPC214x-GCC/chconf.h | 8 ++++++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 8 ++++++++ demos/AVR-AT90CANx-GCC/chconf.h | 8 ++++++++ demos/AVR-ATmega128-GCC/chconf.h | 8 ++++++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 8 ++++++++ demos/Win32-MinGW/chconf.h | 8 ++++++++ demos/Win32-MinGW/chtypes.h | 1 + 11 files changed, 81 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 8db71b445..b66e8f595 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 8db71b445..b66e8f595 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 8db71b445..b66e8f595 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 9f903df06..cfa407fc5 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ //#define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +//#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +//#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 8db71b445..b66e8f595 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 8db71b445..b66e8f595 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index fca0159a2..182ba1a9b 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index fca0159a2..182ba1a9b 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -137,6 +137,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 7e29d314e..336c0d6b0 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -138,6 +138,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index b17295c65..674d747c1 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -142,6 +142,14 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS + +/** Configuration option: if specified then the memory pools allocator + provides an implementation of the sbrk() function.*/ +#define CH_MEMPOOLS_PROVIDE_SBRK + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 0b74459bc..6f8662bd9 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -22,6 +22,7 @@ #define __need_NULL #define __need_size_t +#define __need_ptrdiff_t #include #if !defined(_STDINT_H) && !defined(__STDINT_H_) -- cgit v1.2.3 From d9d134c7ad07db84b3555d56e9ea388593e60fb2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 26 Aug 2008 12:22:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@408 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chconf.h | 4 ++-- demos/AVR-ATmega128-GCC/chconf.h | 4 ++-- demos/MSP430-MSP430x1611-GCC/chconf.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 182ba1a9b..bd9c528d2 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -139,11 +139,11 @@ /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +//#define CH_USE_MEMPOOLS /** Configuration option: if specified then the memory pools allocator provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK +//#define CH_MEMPOOLS_PROVIDE_SBRK /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 182ba1a9b..bd9c528d2 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -139,11 +139,11 @@ /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +//#define CH_USE_MEMPOOLS /** Configuration option: if specified then the memory pools allocator provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK +//#define CH_MEMPOOLS_PROVIDE_SBRK /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 336c0d6b0..521aae128 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -140,11 +140,11 @@ /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +//#define CH_USE_MEMPOOLS /** Configuration option: if specified then the memory pools allocator provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK +//#define CH_MEMPOOLS_PROVIDE_SBRK /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ -- cgit v1.2.3 From e192ac85aa7b3fa76defc5bb7f8e7a8f32edd787 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 26 Aug 2008 17:39:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@410 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index a0c76a43b..349a0bd1f 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -16,8 +16,8 @@ # Start of default section # -TRGT = arm-none-eabi- -#TRGT = arm-eabi- +#TRGT = arm-none-eabi- +TRGT = arm-eabi- CC = $(TRGT)gcc CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp -- cgit v1.2.3 From c1b95a7182aa0884133b3e12477d7cb7fb97ee63 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 26 Aug 2008 18:34:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@411 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 349a0bd1f..a0c76a43b 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -16,8 +16,8 @@ # Start of default section # -#TRGT = arm-none-eabi- -TRGT = arm-eabi- +TRGT = arm-none-eabi- +#TRGT = arm-eabi- CC = $(TRGT)gcc CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp -- cgit v1.2.3 From 7768c51b7b1ef0becc4090705a9bd2f14aa28d00 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 28 Aug 2008 13:34:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@412 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 20 ++++++++++++++++---- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 20 ++++++++++++++++---- demos/ARM7-LPC214x-G++/chconf.h | 20 ++++++++++++++++---- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 20 ++++++++++++++++---- demos/ARM7-LPC214x-GCC/chconf.h | 20 ++++++++++++++++---- demos/ARMCM3-STM32F103-GCC/chconf.h | 20 ++++++++++++++++---- demos/AVR-AT90CANx-GCC/chconf.h | 22 +++++++++++++++++----- demos/AVR-ATmega128-GCC/chconf.h | 22 +++++++++++++++++----- demos/MSP430-MSP430x1611-GCC/chconf.h | 22 +++++++++++++++++----- demos/Win32-MinGW/chconf.h | 20 ++++++++++++++++---- 10 files changed, 163 insertions(+), 43 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index b66e8f595..8d31e854a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -137,14 +137,26 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory heap allocator APIs + * are included in the kernel.*/ +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 + +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +//#define CH_USE_MALLOC_HEAP + /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ #define CH_USE_MEMPOOLS -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK - /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index b66e8f595..8d31e854a 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -137,14 +137,26 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory heap allocator APIs + * are included in the kernel.*/ +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 + +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +//#define CH_USE_MALLOC_HEAP + /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ #define CH_USE_MEMPOOLS -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK - /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index b66e8f595..c9b0b4c50 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -137,14 +137,26 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory heap allocator APIs + * are included in the kernel.*/ +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 + +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +#define CH_USE_MALLOC_HEAP + /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ #define CH_USE_MEMPOOLS -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK - /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index cfa407fc5..e81935083 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -137,14 +137,26 @@ * are included in the kernel.*/ //#define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory heap allocator APIs + * are included in the kernel.*/ +//#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 + +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +//#define CH_USE_MALLOC_HEAP + /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ //#define CH_USE_MEMPOOLS -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -//#define CH_MEMPOOLS_PROVIDE_SBRK - /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index b66e8f595..8d31e854a 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -137,14 +137,26 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory heap allocator APIs + * are included in the kernel.*/ +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 + +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +//#define CH_USE_MALLOC_HEAP + /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ #define CH_USE_MEMPOOLS -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK - /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index b66e8f595..8d31e854a 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -137,14 +137,26 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory heap allocator APIs + * are included in the kernel.*/ +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 + +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +//#define CH_USE_MALLOC_HEAP + /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ #define CH_USE_MEMPOOLS -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK - /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index bd9c528d2..594d28272 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -137,13 +137,25 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX -/** Configuration option: if specified then the memory pools allocator APIs +/** Configuration option: if specified then the memory heap allocator APIs * are included in the kernel.*/ -//#define CH_USE_MEMPOOLS +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -//#define CH_MEMPOOLS_PROVIDE_SBRK +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +#define CH_USE_MALLOC_HEAP + +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index bd9c528d2..594d28272 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -137,13 +137,25 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX -/** Configuration option: if specified then the memory pools allocator APIs +/** Configuration option: if specified then the memory heap allocator APIs * are included in the kernel.*/ -//#define CH_USE_MEMPOOLS +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -//#define CH_MEMPOOLS_PROVIDE_SBRK +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +#define CH_USE_MALLOC_HEAP + +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 521aae128..2205cdd33 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -138,13 +138,25 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX -/** Configuration option: if specified then the memory pools allocator APIs +/** Configuration option: if specified then the memory heap allocator APIs * are included in the kernel.*/ -//#define CH_USE_MEMPOOLS +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 0 -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -//#define CH_MEMPOOLS_PROVIDE_SBRK +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +#define CH_USE_MALLOC_HEAP + +/** Configuration option: if specified then the memory pools allocator APIs + * are included in the kernel.*/ +#define CH_USE_MEMPOOLS /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 674d747c1..0912c3f6d 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -142,14 +142,26 @@ * are included in the kernel.*/ #define CH_USE_SERIAL_HALFDUPLEX +/** Configuration option: if specified then the memory heap allocator APIs + * are included in the kernel.*/ +#define CH_USE_HEAP + +/** Configuration option: Number of RAM bytes to use as system heap. If set to + * zero then the whole available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the \p __heap_base__ and \p __heap_end__ symbols. + * @note requires \p CH_USE_HEAP. + */ +#define CH_HEAP_SIZE 16384 + +/** Configuration option: enforces the use of the C-runtime \p malloc() and + * \p free() functions as backend for the system heap allocator.*/ +//#define CH_USE_MALLOC_HEAP + /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ #define CH_USE_MEMPOOLS -/** Configuration option: if specified then the memory pools allocator - provides an implementation of the sbrk() function.*/ -#define CH_MEMPOOLS_PROVIDE_SBRK - /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 -- cgit v1.2.3 From 090b4c11096363cf25ba9c4ea2a788cae1d7e8a4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 30 Aug 2008 08:48:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@419 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/chconf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 594d28272..7ff7df502 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -147,11 +147,11 @@ * provide the \p __heap_base__ and \p __heap_end__ symbols. * @note requires \p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#define CH_HEAP_SIZE 128 /** Configuration option: enforces the use of the C-runtime \p malloc() and * \p free() functions as backend for the system heap allocator.*/ -#define CH_USE_MALLOC_HEAP +//#define CH_USE_MALLOC_HEAP /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ -- cgit v1.2.3 From 071e9457b0645f07a90485bd7a7c68fa5e34801b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 3 Sep 2008 12:18:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@421 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 17 ----------------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 17 ----------------- demos/ARM7-LPC214x-G++/chconf.h | 17 ----------------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 17 ----------------- demos/ARM7-LPC214x-GCC/chconf.h | 17 ----------------- demos/ARMCM3-STM32F103-GCC/chconf.h | 17 ----------------- demos/AVR-AT90CANx-GCC/chconf.h | 17 ----------------- demos/AVR-ATmega128-GCC/chconf.h | 17 ----------------- demos/MSP430-MSP430x1611-GCC/chconf.h | 17 ----------------- demos/Win32-MinGW/chconf.h | 17 ----------------- 10 files changed, 170 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 8d31e854a..f06a707b6 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 8d31e854a..f06a707b6 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index c9b0b4c50..847a62d4a 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index e81935083..1302dac3e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -//#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ //#define CH_USE_WAITEXIT diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 8d31e854a..f06a707b6 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 8d31e854a..f06a707b6 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 594d28272..132bc4f15 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 7ff7df502..58f0fca7e 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -46,23 +46,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 2205cdd33..8087f679f 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -47,23 +47,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 0912c3f6d..f16918f72 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -51,23 +51,6 @@ * included in the kernel.*/ #define CH_USE_SYSTEMTIME -/** Configuration option: if specified then the \p chThdSleep() function is - * included in the kernel. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ -#define CH_USE_SLEEP - -/** Configuration option: if specified then the \p chThdResume() - * function is included in the kernel.*/ -#define CH_USE_RESUME - -/** Configuration option: if specified then the \p chThdSuspend() - * function is included in the kernel.*/ -#define CH_USE_SUSPEND - -/** Configuration option: if specified then the \p chThdTerminate() - * and \p chThdShouldTerminate() functions are included in the kernel.*/ -#define CH_USE_TERMINATE - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT -- cgit v1.2.3 From 517440bad9d6d2f27689e4e3de72794d869d2c26 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 5 Sep 2008 13:04:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@425 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 24 ++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 24 ++++++++++++++++++++++++ demos/ARM7-LPC214x-G++/chconf.h | 24 ++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 24 ++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/chconf.h | 24 ++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 24 ++++++++++++++++++++++++ demos/AVR-AT90CANx-GCC/chconf.h | 24 ++++++++++++++++++++++++ demos/AVR-ATmega128-GCC/chconf.h | 24 ++++++++++++++++++++++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 24 ++++++++++++++++++++++++ demos/Win32-MinGW/chconf.h | 29 ++++++++++++++++++++++++----- 10 files changed, 240 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index f06a707b6..57cc9d013 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index f06a707b6..57cc9d013 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 847a62d4a..292074816 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 1302dac3e..206272504 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ //#define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index f06a707b6..57cc9d013 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index f06a707b6..57cc9d013 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 132bc4f15..eca46b974 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 58f0fca7e..c44cd39d5 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -34,6 +34,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -172,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 8087f679f..0d1773a6a 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -35,6 +35,13 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -173,6 +180,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index f16918f72..71a2cf36e 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -29,16 +29,18 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/* - * NOTE: this is just documentation for doxigen, the real configuration file - * is the one into the project directories. - */ - /** Configuration option: if specified then time efficient rather than space * efficient code is used when two possible implementations exist, note * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: it specified this option enables the \p Thread + * extension fields and initiazation code. + * @see THREAD_EXT_FIELDS + * @see THREAD_EXT_INIT + */ +//#define CH_USE_THREAD_EXT + /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -177,6 +179,23 @@ */ //#define CH_USE_TRACE +/** User fields added to the end of the \p Thread structure if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add fields here.*/ \ +}; + +/** User initialization code added to the \p chThdCreate() API if the + * \p CH_USE_THREAD_EXT option is enabled. + * @see CH_USE_THREAD_EXT + */ +#define THREAD_EXT_INIT(tp) { \ + /* Add initialization code here.*/ \ +} + #endif /* _CHCONF_H_ */ /** @} */ -- cgit v1.2.3 From 15ee17c8740a378cffcae681421b9e28fcde3d4c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Sep 2008 08:56:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@426 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 3 ++- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 3 ++- demos/ARM7-LPC214x-G++/chconf.h | 3 ++- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 1 + demos/ARM7-LPC214x-GCC/chconf.h | 3 ++- demos/ARMCM3-STM32F103-GCC/chconf.h | 5 +++-- demos/AVR-AT90CANx-GCC/chconf.h | 3 ++- demos/AVR-ATmega128-GCC/chconf.h | 3 ++- demos/MSP430-MSP430x1611-GCC/chconf.h | 3 ++- demos/Win32-MinGW/chconf.h | 1 + 10 files changed, 19 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 57cc9d013..181dde8f4 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -102,9 +102,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 57cc9d013..181dde8f4 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -102,9 +102,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 292074816..8ac22dec5 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -102,9 +102,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 206272504..fbd6f7d0e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -102,6 +102,7 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ //#define CH_USE_EXIT_EVENT diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 57cc9d013..181dde8f4 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -102,9 +102,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 57cc9d013..c5f1cbb90 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -98,13 +98,14 @@ /** Configuration option: If enabled then the threads have an option to serve * messages by priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index eca46b974..1d9f2acff 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -102,9 +102,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index c44cd39d5..736c4064e 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -102,9 +102,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 0d1773a6a..feb1a78ab 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -103,9 +103,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EXIT_EVENT +//#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 71a2cf36e..b52281cfa 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -102,6 +102,7 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EXIT_EVENT -- cgit v1.2.3 From 0ae0293b4fde3c450967fe083bdf7a87b38e27d3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Sep 2008 08:59:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@427 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index c5f1cbb90..181dde8f4 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -98,7 +98,7 @@ /** Configuration option: If enabled then the threads have an option to serve * messages by priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_PRIORITY +//#define CH_USE_MESSAGES_PRIORITY /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. -- cgit v1.2.3 From a474010e54534785366d1924554f5452725499b0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 11 Sep 2008 15:03:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@430 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 3 +-- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 3 +-- demos/ARM7-LPC214x-G++/chconf.h | 3 +-- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 1 - demos/ARM7-LPC214x-GCC/chconf.h | 3 +-- demos/ARMCM3-STM32F103-GCC/chconf.h | 3 +-- demos/AVR-AT90CANx-GCC/chconf.h | 3 +-- demos/AVR-ATmega128-GCC/chconf.h | 3 +-- demos/MSP430-MSP430x1611-GCC/chconf.h | 3 +-- 9 files changed, 8 insertions(+), 17 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 181dde8f4..57cc9d013 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -102,10 +102,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 181dde8f4..57cc9d013 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -102,10 +102,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 8ac22dec5..292074816 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -102,10 +102,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index fbd6f7d0e..206272504 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -102,7 +102,6 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ //#define CH_USE_EXIT_EVENT diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 181dde8f4..57cc9d013 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -102,10 +102,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 181dde8f4..57cc9d013 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -102,10 +102,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 1d9f2acff..eca46b974 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -102,10 +102,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 736c4064e..c44cd39d5 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -102,10 +102,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index feb1a78ab..0d1773a6a 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -103,10 +103,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EXIT_EVENT +#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ -- cgit v1.2.3 From 9a1c91e6ee9baaee3529e16fc732cbd9c7e99844 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Sep 2008 15:29:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@437 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 6 ++++++ demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 6 ++++++ demos/ARM7-LPC214x-G++/chconf.h | 6 ++++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 6 ++++++ demos/ARM7-LPC214x-GCC/chconf.h | 6 ++++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 6 ++++++ demos/AVR-AT90CANx-GCC/chconf.h | 6 ++++++ demos/AVR-ATmega128-GCC/chconf.h | 6 ++++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 6 ++++++ demos/Win32-MinGW/chconf.h | 6 ++++++ 10 files changed, 60 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 57cc9d013..13c3766e4 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 57cc9d013..13c3766e4 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 292074816..3bf626af0 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 206272504..da927fe6a 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ //#define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +//#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 57cc9d013..13c3766e4 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 57cc9d013..13c3766e4 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index eca46b974..a3c3697af 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index c44cd39d5..f3975e8a4 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -147,6 +147,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 0d1773a6a..40a333f1c 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -148,6 +148,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index b52281cfa..c5bbf0410 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -148,6 +148,12 @@ * are included in the kernel.*/ #define CH_USE_MEMPOOLS +/** Configuration option: if specified then the dynamic objects creation APIs + * are included in the kernel. + * @note requires \p CH_USE_WAITEXIT. + */ +#define CH_USE_DYNAMIC + /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ #define CH_FREQUENCY 1000 -- cgit v1.2.3 From c9205e2fd961c60cffd1000936340806a8e45558 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 24 Sep 2008 12:28:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@442 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 4 ++-- demos/ARM7-LPC214x-GCC-minimal/main.c | 4 ++-- demos/ARM7-LPC214x-GCC/main.c | 4 ++-- demos/ARMCM3-STM32F103-GCC/main.c | 4 ++-- demos/AVR-AT90CANx-GCC/main.c | 2 +- demos/AVR-ATmega128-GCC/main.c | 2 +- demos/MSP430-MSP430x1611-GCC/main.c | 4 ++-- 8 files changed, 13 insertions(+), 13 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index db1959c0c..abd84bd87 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -46,7 +46,7 @@ int main(int argc, char **argv) { */ chSysInit(); - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); while (TRUE) { chThdSleep(500); diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index 7861a0408..5887beedf 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -51,8 +51,8 @@ int main(int argc, char **argv) { */ chSysInit(); - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); - chThdCreateFast(NORMALPRIO - 1, waWebThread, sizeof(waWebThread), WebThread); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waWebThread, sizeof(waWebThread), NORMALPRIO - 1, WebThread, NULL); while (TRUE) { chThdSleep(500); diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index bbbc3ce6c..a7c896222 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -69,8 +69,8 @@ int main(int argc, char **argv) { /* * Creates the blinker threads. */ - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); - chThdCreateFast(NORMALPRIO, waThread2, sizeof(waThread2), Thread2); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); /* * Normal main() thread activity, in this demo it does nothing except diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index d83a386d5..588bd21af 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -131,8 +131,8 @@ int main(int argc, char **argv) { * are not started in order to make accurate benchmarks. */ if ((IO0PIN & 0x00018000) == 0x00018000) { - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); - chThdCreateFast(NORMALPRIO, waThread2, sizeof(waThread2), Thread2); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); } /* diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index c8d35815c..59e7b792a 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -50,9 +50,9 @@ int main(int argc, char **argv) { chSysInit(); /* - * Creates the blinker threads. + * Creates the blinker thread. */ - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); /* * Normal main() thread activity, in this demo it does nothing except diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 9dde101ef..987deb072 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -69,7 +69,7 @@ int main(int argc, char **argv) { /* * Starts the LED blinker thread. */ - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); while(TRUE) chEvtWait(ALL_EVENTS, handlers); diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index f238642ef..873a28a79 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -80,7 +80,7 @@ int main(int argc, char **argv) { /* * Starts the LED blinker thread. */ - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); while(TRUE) chEvtWait(ALL_EVENTS, handlers); diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 07b420b55..72736fc54 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -54,9 +54,9 @@ int main(int argc, char **argv) { chSysInit(); /* - * Creates the blinker threads. + * Creates the blinker thread. */ - chThdCreateFast(NORMALPRIO, waThread1, sizeof(waThread1), Thread1); + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); /* * Normal main() thread activity, in this demo it does nothing except -- cgit v1.2.3 From 8feba91865981a1cb8b1ba12c4bce09997141f2f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Sep 2008 10:46:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@444 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 36 +++++++++++++++------------------ demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 34 ++++++++++++++----------------- demos/ARM7-LPC214x-G++/chconf.h | 34 ++++++++++++++----------------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 34 ++++++++++++++----------------- demos/ARM7-LPC214x-GCC/chconf.h | 34 ++++++++++++++----------------- demos/ARMCM3-STM32F103-GCC/chconf.h | 34 ++++++++++++++----------------- demos/AVR-AT90CANx-GCC/chconf.h | 34 ++++++++++++++----------------- demos/AVR-ATmega128-GCC/chconf.h | 34 ++++++++++++++----------------- demos/MSP430-MSP430x1611-GCC/chconf.h | 34 ++++++++++++++----------------- demos/Win32-MinGW/chconf.h | 35 ++++++++++++++------------------ 10 files changed, 151 insertions(+), 192 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 13c3766e4..f6f40d5e3 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -79,10 +72,12 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. +/** Configuration option: if specified then the + * \p chThdGetExitEventSource() function is included in the kernel. * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 13c3766e4..a5b956523 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,8 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 3bf626af0..b307e8a52 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,8 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index da927fe6a..ade1aa207 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ //#define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,8 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ //#define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 13c3766e4..a5b956523 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,8 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 13c3766e4..a5b956523 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,8 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index a3c3697af..ea26be7ad 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,8 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index f3975e8a4..34b26c7be 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,8 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -185,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 40a333f1c..da9878f86 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -35,13 +35,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -103,8 +96,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -186,21 +181,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index c5bbf0410..46272d552 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -34,13 +34,6 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: it specified this option enables the \p Thread - * extension fields and initiazation code. - * @see THREAD_EXT_FIELDS - * @see THREAD_EXT_INIT - */ -//#define CH_USE_THREAD_EXT - /** Configuration option: if specified then the Virtual Timers subsystem is * included in the kernel.*/ #define CH_USE_VIRTUAL_TIMERS @@ -102,9 +95,10 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @deprecated - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0. + */ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included @@ -186,21 +180,22 @@ */ //#define CH_USE_TRACE -/** User fields added to the end of the \p Thread structure if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User fields added to the end of the \p Thread structure. */ #define THREAD_EXT_FIELDS \ struct { \ - /* Add fields here.*/ \ + /* Add thread custom fields here.*/ \ }; -/** User initialization code added to the \p chThdCreate() API if the - * \p CH_USE_THREAD_EXT option is enabled. - * @see CH_USE_THREAD_EXT - */ +/** User initialization code added to the \p chThdCreate() API. + * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ - /* Add initialization code here.*/ \ + /* Add thread initialization code here.*/ \ +} + +/** User finalization code added to the \p chThdExit() API. + * @note It is inserted into lock zone. */ +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ } #endif /* _CHCONF_H_ */ -- cgit v1.2.3 From 102341ad5d0e39af783675233b888977ab4585db Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 07:44:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@447 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 3 ++- demos/ARMCM3-STM32F103-GCC/readme.txt | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index a0c76a43b..6c3417ca6 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -16,8 +16,9 @@ # Start of default section # -TRGT = arm-none-eabi- +#TRGT = arm-none-eabi- #TRGT = arm-eabi- +TRGT = arm-elf- CC = $(TRGT)gcc CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt index ca17e697f..a3ca86747 100644 --- a/demos/ARMCM3-STM32F103-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -15,7 +15,8 @@ COM2 (USART2). ** Build Procedure ** The demo was tested by using the free Codesourcery GCC-based toolchain (a -modified 4.2.1 GCC) and an experimental WinARM build including GCC 4.3.0. +modified 4.2.3 GCC), YAGARTO 4.3.2 and an experimental WinARM build including +GCC 4.3.0. Just modify the TRGT line in the makefile in order to use different GCC ports. ** Notes ** -- cgit v1.2.3 From 9415b92dde53fe5898be66a29ccf35bb25d2ebe5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 09:31:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@450 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 20 +++++++++++++++++--- demos/ARMCM3-STM32F103-GCC/main.c | 9 ++------- 2 files changed, 19 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index f10269aa6..7bfa42133 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -24,10 +24,11 @@ #include "stm32_serial.h" /* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. */ -void hwinit(void) { +void hwinit0(void) { /* * Clocks and PLL initialization. @@ -76,6 +77,14 @@ void hwinit(void) { GPIOD->CRL = VAL_GPIODCRL; GPIOD->CRH = VAL_GPIODCRH; GPIOD->ODR = VAL_GPIODODR; +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { /* * NVIC/SCB initialization. @@ -95,4 +104,9 @@ void hwinit(void) { * Other subsystems initialization. */ InitSerial(0x80, 0x80, 0x80); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); } diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 59e7b792a..0df4bc03d 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -39,16 +39,11 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, the interrupts are disabled on entry. + * Entry point, note, the main() function is already a thread in the system + * on entry. */ int main(int argc, char **argv) { - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. - */ - chSysInit(); - /* * Creates the blinker thread. */ -- cgit v1.2.3 From 215de527a7627a67af2d2b0f6b4882497a299efc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 09:42:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@452 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/ch.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index b6b390f80..f18ba7e5d 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -41,7 +41,7 @@ SECTIONS .text : { _text = .; - KEEP(*(INTVEC)); + KEEP(*(vectors)); *(.text) *(.text.*); *(.rodata); -- cgit v1.2.3 From 63c5df56a93280ff24010066b2dabd006995ac62 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 09:53:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@453 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 3 ++- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 3 ++- demos/ARM7-AT91SAM7X-GCC/ch.ld | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 5629c9842..dbdca2c31 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -83,7 +83,8 @@ ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 4ca9bded5..3013eeb95 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -83,7 +83,8 @@ TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 7459bdac1..89a2c2f2b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -45,7 +45,7 @@ SECTIONS .text : { _text = .; - KEEP(*(.startup)) + KEEP(*(vectors)); *(.text) *(.text.*); *(.rodata); -- cgit v1.2.3 From 88d9fc3ce959134051241fd261f9f56026248648 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 09:55:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@454 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 3 ++- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 3 ++- demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 243d525f8..b7b859220 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -95,7 +95,8 @@ ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb index 0b5c72349..2ef54fb5d 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -96,7 +96,8 @@ TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-AT91SAM7X/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld index 7459bdac1..89a2c2f2b 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld @@ -45,7 +45,7 @@ SECTIONS .text : { _text = .; - KEEP(*(.startup)) + KEEP(*(vectors)); *(.text) *(.text.*); *(.rodata); -- cgit v1.2.3 From b7affa79a14cc90a38b3e48c9393cd87710512b9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 09:59:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@455 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 22 ++++++++++++++++++---- demos/ARM7-AT91SAM7X-GCC/main.c | 12 +++++++----- 2 files changed, 25 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 4bc78f086..8a4b7c4ea 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -54,11 +54,11 @@ static void SYSIrqHandler(void) { } /* - * Board initialization code. + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. */ -void hwinit(void) { - int i; - +void hwinit0(void) { /* * Flash Memory: 1 wait state, about 50 cycles in a microsecond. */ @@ -99,6 +99,15 @@ void hwinit(void) { AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { + int i; /* * Default AIC setup, the device drivers will modify it as needed. @@ -150,4 +159,9 @@ void hwinit(void) { AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); } diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index abd84bd87..c280e5489 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -36,18 +36,20 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, the interrupts are disabled on entry. + * Entry point, note, the main() function is already a thread in the system + * on entry. */ int main(int argc, char **argv) { + /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. + * Creates the blinker thread. */ - chSysInit(); - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + /* + * Normal main() thread activity. + */ while (TRUE) { chThdSleep(500); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) -- cgit v1.2.3 From 983920ddc9e3f074defd7ab68e72248401d8ca3c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 10:03:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@456 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/main.c | 1 - demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 17 +++++++++++++---- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 11 ++++++----- 3 files changed, 19 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index c280e5489..1fc284cd3 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -41,7 +41,6 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { - /* * Creates the blinker thread. */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 2bc9c6395..8c483f1f0 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -55,11 +55,11 @@ static void SYSIrqHandler(void) { } /* - * Board initialization code. + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. */ -void hwinit(void) { - int i; - +void hwinit0(void) { /* * Flash Memory: 1 wait state, about 50 cycles in a microsecond. */ @@ -100,6 +100,15 @@ void hwinit(void) { AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { + int i; /* * Default AIC setup, the device drivers will modify it as needed. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index 5887beedf..00dc9193e 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -41,19 +41,20 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, the interrupts are disabled on entry. + * Entry point, note, the main() function is already a thread in the system + * on entry. */ int main(int argc, char **argv) { /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. + * Creates the blinker and web server threads. */ - chSysInit(); - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); chThdCreateStatic(waWebThread, sizeof(waWebThread), NORMALPRIO - 1, WebThread, NULL); + /* + * Normal main() thread activity. + */ while (TRUE) { chThdSleep(500); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) -- cgit v1.2.3 From a3bb2266cf4fc0c3b6deb6595bb992d30b698191 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 10:52:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@458 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 8c483f1f0..0d2fd0996 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -165,4 +165,9 @@ void hwinit1(void) { * EMAC driver initialization. */ InitEMAC(AT91C_AIC_PRIOR_HIGHEST - 3); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); } -- cgit v1.2.3 From f44bd871c77406f8e28047d9484cbabafa626040 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Oct 2008 12:00:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@459 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 3 ++- demos/ARM7-LPC214x-G++/Makefile.thumb | 3 ++- demos/ARM7-LPC214x-G++/board.c | 20 +++++++++++++++++--- demos/ARM7-LPC214x-G++/ch.ld | 2 +- demos/ARM7-LPC214x-G++/main.cpp | 6 ++---- demos/ARM7-LPC214x-GCC-minimal/Makefile | 3 ++- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 3 ++- demos/ARM7-LPC214x-GCC-minimal/board.c | 20 +++++++++++++++++--- demos/ARM7-LPC214x-GCC-minimal/ch.ld | 2 +- demos/ARM7-LPC214x-GCC-minimal/main.c | 9 ++------- demos/ARM7-LPC214x-GCC/Makefile | 3 ++- demos/ARM7-LPC214x-GCC/Makefile.thumb | 3 ++- demos/ARM7-LPC214x-GCC/board.c | 20 +++++++++++++++++--- demos/ARM7-LPC214x-GCC/ch.ld | 2 +- demos/ARM7-LPC214x-GCC/main.c | 9 ++------- 15 files changed, 72 insertions(+), 36 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 95d6bfdb8..9bd08a8ee 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -93,7 +93,8 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-LPC214x/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 29f2a61a4..177e7cda0 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -93,7 +93,8 @@ TCSRC = ../../ports/ARM7-LPC214x/chcore.c \ TCPPSRC = ../../src/lib/ch.cpp main.cpp # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-LPC214x/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index 6f004ba29..8b17399e0 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -58,10 +58,11 @@ static void T0IrqHandler(void) { } /* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. */ -void hwinit(void) { +void hwinit0(void) { /* * All peripherals clock disabled by default in order to save power. @@ -106,6 +107,14 @@ void hwinit(void) { IO0SET = 0xFFFFFFFF; IO1DIR = VAL_FIO1DIR; IO1SET = 0xFFFFFFFF; +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { /* * Interrupt vectors assignment. @@ -132,4 +141,9 @@ void hwinit(void) { // InitSSP(); // InitMMC(); // InitBuzzer(); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); } diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index bb59cec1c..81ab80dc6 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -48,7 +48,7 @@ SECTIONS .text : { _text = .; - KEEP(*(.startup)) + KEEP(*(vectors)) *(.text) *(.text.*); *(.rodata); diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 37147fe91..576581b79 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -124,8 +124,8 @@ static void TimerHandler(eventid_t id) { } /* - * Entry point, the interrupts are disabled on entry. - * This is the real "application". + * Entry point, note, the main() function is already a thread in the system + * on entry. */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -134,8 +134,6 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0; - System::Init(); // ChibiOS/RT goes live here. - evtInit(&evt, 500); // Initializes an event timer. evtStart(&evt); // Starts the event timer. chEvtRegister(&evt.et_es, &el0, 0); // Registers a listener on the source. diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index d035f6f23..6450cad6b 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -80,7 +80,8 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-LPC214x/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib \ diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index ace728b15..f4fe4c25b 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -80,7 +80,8 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-LPC214x/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib \ diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index e140f2359..3b3bd848e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -58,10 +58,11 @@ static void T0IrqHandler(void) { } /* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. */ -void hwinit(void) { +void hwinit0(void) { /* * All peripherals clock disabled by default in order to save power. @@ -106,6 +107,14 @@ void hwinit(void) { IO0SET = 0xFFFFFFFF; IO1DIR = VAL_FIO1DIR; IO1SET = 0xFFFFFFFF; +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { /* * Interrupt vectors assignment. @@ -132,4 +141,9 @@ void hwinit(void) { // InitSSP(); // InitMMC(); // InitBuzzer(); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); } diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld index bb59cec1c..81ab80dc6 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -48,7 +48,7 @@ SECTIONS .text : { _text = .; - KEEP(*(.startup)) + KEEP(*(vectors)) *(.text) *(.text.*); *(.rodata); diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index a7c896222..11fdd7b56 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -56,16 +56,11 @@ static msg_t Thread2(void *arg) { } /* - * Entry point, the interrupts are disabled on entry. + * Entry point, note, the main() function is already a thread in the system + * on entry. */ int main(int argc, char **argv) { - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. - */ - chSysInit(); - /* * Creates the blinker threads. */ diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 8e1790bb2..2bdf1959f 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -84,7 +84,8 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-LPC214x/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 4b62f9091..a676a4af1 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -84,7 +84,8 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ board.c buzzer.c mmcsd.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ + ../../ports/ARM7-LPC214x/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 94bc21336..9f453100c 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -58,10 +58,11 @@ static void T0IrqHandler(void) { } /* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. */ -void hwinit(void) { +void hwinit0(void) { /* * All peripherals clock disabled by default in order to save power. @@ -106,6 +107,14 @@ void hwinit(void) { IO0SET = 0xFFFFFFFF; IO1DIR = VAL_FIO1DIR; IO1SET = 0xFFFFFFFF; +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { /* * Interrupt vectors assignment. @@ -132,4 +141,9 @@ void hwinit(void) { InitSSP(); InitMMC(); InitBuzzer(); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); } diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index bb59cec1c..81ab80dc6 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -48,7 +48,7 @@ SECTIONS .text : { _text = .; - KEEP(*(.startup)) + KEEP(*(vectors)) *(.text) *(.text.*); *(.rodata); diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 588bd21af..3ff516077 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -109,7 +109,8 @@ static void RemoveHandler(eventid_t id) { } /* - * Entry point, the interrupts are disabled on entry. + * Entry point, note, the main() function is already a thread in the system + * on entry. */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -120,12 +121,6 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0, el1, el2; - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. - */ - chSysInit(); - /* * If a button is pressed during the reset then the blinking leds threads * are not started in order to make accurate benchmarks. -- cgit v1.2.3 From b4143002333b4d1ffdd4caa0f717d3e8485ebd62 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 11 Oct 2008 10:29:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@460 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 8 ++++++++ demos/MSP430-MSP430x1611-GCC/board.h | 18 +++++++++++++----- 2 files changed, 21 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index c6cfedce2..caef10720 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -33,6 +33,14 @@ void hwinit(void) { */ DCOCTL = VAL_DCOCTL; BCSCTL1 = VAL_BCSCTL1; +#if defined(MSP_USE_XT2CLK) + do { + int i; + IFG1 &= ~OFIFG; + for (i = 255; i > 0; i--) + asm("nop"); + } while (IFG1 & OFIFG); +#endif BCSCTL2 = VAL_BCSCTL2; /* diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index 8b335f64f..d72da9c2c 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -25,26 +25,34 @@ /* * Clock settings. */ -#define MSP_USE_XT2CLK +//#define MSP_USE_XT2CLK +#define MSP_USE_DCOCLK + +#if defined(MSP_USE_XT2CLK) && defined(MSP_USE_DCOCLK) +#error "Define MSP_USE_XT2CLK or MSP_USE_DCOCLK, not both" +#endif #define LFXT1CLK 32768 #define XT2CLK 8000000 #define DCOCLK 1000000 #define ACLK LFXT1CLK -#ifdef MSP_USE_XT2CLK +#if defined(MSP_USE_XT2CLK) #define MCLK XT2CLK #define SMCLK (XT2CLK / 8) -#else +#elif defined(MSP_USE_DCOCLK) #define MCLK DCOCLK #define SMCLK DCOCLK +#else +#error "Default clock source not selected" #endif #define VAL_DCOCTL (DCO0 | DCO1) -#ifdef MSP_USE_XT2CLK +#if defined(MSP_USE_XT2CLK) #define VAL_BCSCTL1 (RSEL2) #define VAL_BCSCTL2 (SELM_2 | DIVM_0 | DIVS_3 | SELS) -#else +#endif +#if defined(MSP_USE_DCOCLK) #define VAL_BCSCTL1 (XT2OFF | RSEL2) #define VAL_BCSCTL2 (SELM_0 | DIVM_0 | DIVS_0) #endif -- cgit v1.2.3 From ae8b38ea55f4d798d5313666194a7280053f460f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 12 Oct 2008 10:04:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@461 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 1 + demos/MSP430-MSP430x1611-GCC/board.c | 6 ++++++ demos/MSP430-MSP430x1611-GCC/board.h | 2 +- demos/MSP430-MSP430x1611-GCC/main.c | 5 +++-- 4 files changed, 11 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 4d2b01bd3..097300911 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -67,6 +67,7 @@ include ../../test/test.mk # List ARM-mode C source files here SRC = ../../ports/MSP430/chcore.c \ + ../../ports/MSP430/msp430_serial.c \ ${KERNSRC} \ ${TESTSRC} \ ../../src/lib/evtimer.c \ diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index caef10720..e6ae187da 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -21,6 +21,7 @@ #include #include "board.h" +#include "msp430_serial.h" /* * Hardware initialization goes here. @@ -77,6 +78,11 @@ void hwinit(void) { TACTL = TACLR; /* Clean start. */ TACTL = TASSEL_2 | MC_1; /* Src=SMCLK, cmp=TACCR0. */ TACCTL0 = CCIE; /* Interrupt on compare. */ + + /* + * Other subsystems. + */ + InitSerial(); } interrupt(TIMERA0_VECTOR) tmr0irq(void) { diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index d72da9c2c..f7173f712 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -34,7 +34,7 @@ #define LFXT1CLK 32768 #define XT2CLK 8000000 -#define DCOCLK 1000000 +#define DCOCLK 750000 #define ACLK LFXT1CLK #if defined(MSP_USE_XT2CLK) diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 72736fc54..19ffacf7f 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -21,6 +21,7 @@ #include #include "board.h" +#include "msp430_serial.h" /* * Red LEDs blinker thread, times are in milliseconds. @@ -63,8 +64,8 @@ int main(int argc, char **argv) { * sleeping in a loop. */ while (TRUE) { -// if (!(P6IN & P6_I_BUTTON)) -// TestThread(&COM1); + if (!(P6IN & P6_I_BUTTON)) + TestThread(&COM1); chThdSleep(500); } return 0; -- cgit v1.2.3 From e6757ceef9a5d80d1102b6b4215929c719a4b96a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 14 Oct 2008 21:03:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@467 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 4 ++-- demos/MSP430-MSP430x1611-GCC/chconf.h | 4 ++-- demos/MSP430-MSP430x1611-GCC/main.c | 6 +++--- demos/MSP430-MSP430x1611-GCC/readme.txt | 6 ++++-- 4 files changed, 11 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index e6ae187da..8fcecec17 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -74,9 +74,9 @@ void hwinit(void) { /* * Timer 0 setup, uses SMCLK as source. */ - TACCR0 = SMCLK / CH_FREQUENCY - 1; /* Counter limit. */ + TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit. */ TACTL = TACLR; /* Clean start. */ - TACTL = TASSEL_2 | MC_1; /* Src=SMCLK, cmp=TACCR0. */ + TACTL = TASSEL_2 | ID_2 | MC_1; /* Src=SMCLK, ID=4, cmp=TACCR0. */ TACCTL0 = CCIE; /* Interrupt on compare. */ /* diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index da9878f86..c78c97701 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -151,12 +151,12 @@ /** Configuration option: Frequency of the system timer that drives the system * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +#define CH_FREQUENCY 100 /** Configuration option: This constant is the number of ticks allowed for the * threads before preemption occurs. This option is only meaningful if the * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +#define CH_TIME_QUANTUM 10 /** Configuration option: Defines a CPU register to be used as storage for the * global \p currp variable. Caching this variable in a register can greatly diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 19ffacf7f..9904dfdb0 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -31,9 +31,9 @@ static msg_t Thread1(void *arg) { while (TRUE) { P6OUT |= P6_O_LED; - chThdSleep(500); + chThdSleep(50); P6OUT &= ~P6_O_LED; - chThdSleep(500); + chThdSleep(50); } return 0; } @@ -66,7 +66,7 @@ int main(int argc, char **argv) { while (TRUE) { if (!(P6IN & P6_I_BUTTON)) TestThread(&COM1); - chThdSleep(500); + chThdSleep(50); } return 0; } diff --git a/demos/MSP430-MSP430x1611-GCC/readme.txt b/demos/MSP430-MSP430x1611-GCC/readme.txt index 0fd0c5a7b..3c1682098 100644 --- a/demos/MSP430-MSP430x1611-GCC/readme.txt +++ b/demos/MSP430-MSP430x1611-GCC/readme.txt @@ -4,11 +4,13 @@ ** TARGET ** -The demo runs on an Olimex MSP430-P1611 board but it is still untested. +The demo runs on an Olimex MSP430-P1611 board. ** The Demo ** -The demo flashes the board LED using a thread. +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +COM1 (USART0). ** Build Procedure ** -- cgit v1.2.3 From 875c8f368683e77371f75c0b9f1aa18237f118f2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 15 Oct 2008 18:26:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@468 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 9904dfdb0..72025d6a4 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -31,9 +31,9 @@ static msg_t Thread1(void *arg) { while (TRUE) { P6OUT |= P6_O_LED; - chThdSleep(50); + chThdSleep(MS2ST(500)); P6OUT &= ~P6_O_LED; - chThdSleep(50); + chThdSleep(MS2ST(500)); } return 0; } @@ -66,7 +66,7 @@ int main(int argc, char **argv) { while (TRUE) { if (!(P6IN & P6_I_BUTTON)) TestThread(&COM1); - chThdSleep(50); + chThdSleep(MS2ST(500)); } return 0; } -- cgit v1.2.3 From 8317685beb67ed9341bc83d03153580b816f452e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 25 Oct 2008 07:11:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@480 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 097300911..b42da1da3 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -113,6 +113,9 @@ CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ODFLAGS = -x --syms +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + # # Makefile rules # @@ -150,5 +153,11 @@ clean: -rm -f $(SRC:.c=.lst) -rm -f $(ASMSRC:.s=.s.bak) -rm -f $(ASMSRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) # *** EOF *** -- cgit v1.2.3 From 902470d1c542735b989a727355744a974af43de4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 25 Oct 2008 09:34:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@481 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 18 ++---------------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 21 +++------------------ demos/ARM7-LPC214x-G++/chconf.h | 21 +++------------------ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 21 +++------------------ demos/ARM7-LPC214x-GCC/chconf.h | 21 +++------------------ demos/ARMCM3-STM32F103-GCC/chconf.h | 21 +++------------------ demos/AVR-AT90CANx-GCC/chconf.h | 21 +++------------------ demos/AVR-ATmega128-GCC/chconf.h | 21 +++------------------ demos/MSP430-MSP430x1611-GCC/chconf.h | 17 +++-------------- demos/Win32-MinGW/chconf.h | 21 +++------------------ 10 files changed, 29 insertions(+), 174 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index f6f40d5e3..7bf6e138e 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -86,8 +73,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index a5b956523..45202074e 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index b307e8a52..ea0e068c6 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index ade1aa207..543edbea2 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ //#define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ //#define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ //#define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ //#define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index a5b956523..45202074e 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index a5b956523..45202074e 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index ea26be7ad..8408f6f22 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 34b26c7be..6ec07fca9 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for LPC214x-GCC demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index c78c97701..fb6203d46 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -35,18 +35,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -61,8 +53,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -75,8 +66,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -85,8 +75,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 46272d552..f33f54930 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -17,10 +17,6 @@ along with this program. If not, see . */ -/* - * Configuration file for MingGW32 demo project. - */ - /** * @addtogroup Config * @{ @@ -34,18 +30,10 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED -/** Configuration option: if specified then the Virtual Timers subsystem is - * included in the kernel.*/ -#define CH_USE_VIRTUAL_TIMERS - /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -/** Configuration option: if specified then the System Timer subsystem is - * included in the kernel.*/ -#define CH_USE_SYSTEMTIME - /** Configuration option: if specified then the \p chThdWait() function * is included in the kernel.*/ #define CH_USE_WAITEXIT @@ -60,8 +48,7 @@ /** Configuration option: if specified then the Semaphores with timeout APIs * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_SEMAPHORES.*/ #define CH_USE_SEMAPHORES_TIMEOUT /** Configuration option: if specified then the Mutexes APIs are included in @@ -74,8 +61,7 @@ /** Configuration option: if specified then the \p chEvtWaitTimeout() * function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_EVENTS.*/ #define CH_USE_EVENTS_TIMEOUT /** Configuration option: if specified then the Synchronous Messages APIs are @@ -84,8 +70,7 @@ /** Configuration option: if specified then the \p chMsgSendWithEvent() * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_VIRTUAL_TIMERS.*/ + * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT /** Configuration option: If enabled then the threads have an option to serve -- cgit v1.2.3 From 69d06df416f4aa337de7183b6ed54ffe527ca0c0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 1 Nov 2008 16:46:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@488 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/Makefile | 2 +- demos/AVR-ATmega128-GCC/chconf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index 89b5118ff..f291af1fb 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -109,7 +109,7 @@ ASRC = # Optimization level, can be [0, 1, 2, 3, s]. # 0 = turn off optimization. s = optimize for size. # (Note: 3 is not always the best optimization level. See avr-libc FAQ.) -OPT = s +OPT = 2 # Debugging format. diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 6ec07fca9..a3e829134 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -117,7 +117,7 @@ * provide the \p __heap_base__ and \p __heap_end__ symbols. * @note requires \p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 128 +#define CH_HEAP_SIZE 512 /** Configuration option: enforces the use of the C-runtime \p malloc() and * \p free() functions as backend for the system heap allocator.*/ -- cgit v1.2.3 From e3978f80b5c3307ad4a803e518d9bc8ec462c49a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 2 Nov 2008 17:23:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@493 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 1 - 1 file changed, 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 6c3417ca6..481f8ac5c 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -136,7 +136,6 @@ CPFLAGS += -MD -MP -MF .dep/$(@F).d # # Makefile rules # - all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp $(COBJS) : %.o : %.c -- cgit v1.2.3 From 9336c1fc9fdae776126295737131d0a22b2f05b8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Nov 2008 10:58:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@501 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 13 +++---------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 5 ----- demos/ARM7-LPC214x-G++/chconf.h | 5 ----- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 5 ----- demos/ARM7-LPC214x-GCC/chconf.h | 5 ----- demos/ARMCM3-STM32F103-GCC/chconf.h | 5 ----- demos/AVR-AT90CANx-GCC/chconf.h | 5 ----- demos/AVR-ATmega128-GCC/chconf.h | 5 ----- demos/MSP430-MSP430x1611-GCC/chconf.h | 5 ----- demos/Win32-MinGW/chconf.h | 5 ----- 10 files changed, 3 insertions(+), 55 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 7bf6e138e..45c63947b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -59,14 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES @@ -83,8 +75,9 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS.*/ + * @note requires \p CH_USE_EVENTS. + * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be + * removed in version 1.0.0.*/ #define CH_USE_EXIT_EVENT /** Configuration option: if specified then the I/O queues APIs are included diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 45202074e..493c66fb0 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index ea0e068c6..77b8b109d 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 543edbea2..fbc6d496e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ //#define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -//#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ //#define CH_USE_MESSAGES diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 45202074e..493c66fb0 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 45202074e..493c66fb0 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 8408f6f22..383f714f3 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index a3e829134..87b92479e 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index fb6203d46..c2204e3da 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -64,11 +64,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index f33f54930..7c0420af6 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -59,11 +59,6 @@ * the kernel.*/ #define CH_USE_EVENTS -/** Configuration option: if specified then the \p chEvtWaitTimeout() - * function is included in the kernel. - * @note requires \p CH_USE_EVENTS.*/ -#define CH_USE_EVENTS_TIMEOUT - /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES -- cgit v1.2.3 From cbc30670d8004caeb7b0a8a9567377ac99032805 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Nov 2008 12:44:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@502 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 11 +++++++++-- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 6 ++++++ demos/ARM7-LPC214x-G++/chconf.h | 6 ++++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 6 ++++++ demos/ARM7-LPC214x-GCC/chconf.h | 6 ++++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 6 ++++++ demos/AVR-AT90CANx-GCC/chconf.h | 6 ++++++ demos/AVR-ATmega128-GCC/chconf.h | 6 ++++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 6 ++++++ demos/Win32-MinGW/chconf.h | 6 ++++++ 10 files changed, 63 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 45c63947b..122d34c97 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES @@ -75,6 +81,7 @@ /** Configuration option: if specified then the * \p chThdGetExitEventSource() function is included in the kernel. + * @note requires \p CH_USE_MESSAGES. * @note requires \p CH_USE_EVENTS. * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be * removed in version 1.0.0.*/ @@ -150,8 +157,8 @@ //#define CH_CURRP_REGISTER_CACHE "r7" /** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * @note The debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. */ //#define CH_USE_DEBUG diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 493c66fb0..513c352a6 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 77b8b109d..e4595ba4a 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index fbc6d496e..df9f1fa97 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ //#define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +//#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ //#define CH_USE_MESSAGES diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 493c66fb0..513c352a6 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 493c66fb0..513c352a6 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 383f714f3..7e972155f 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 87b92479e..bda3d497b 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index c2204e3da..dc9574ef7 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -64,6 +64,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 7c0420af6..7a444aa2d 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -59,6 +59,12 @@ * the kernel.*/ #define CH_USE_EVENTS +/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() + * functions are included in the kernel. + * @note requires \p CH_USE_EVENTS. + */ +#define CH_USE_EVENTS_TIMEOUT + /** Configuration option: if specified then the Synchronous Messages APIs are * included in the kernel.*/ #define CH_USE_MESSAGES -- cgit v1.2.3 From 87d83b1b7e37925f3e32e79e6e6baedb5b13f192 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 9 Nov 2008 09:31:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@504 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/main.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 3ff516077..9b231408f 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -60,13 +60,17 @@ static msg_t Thread2(void *arg) { return 0; } +static WorkingArea(waTestThread, 128); + /* * Executed as event handler at 500mS intervals. */ static void TimerHandler(eventid_t id) { if (!(IO0PIN & 0x00018000)) { // Both buttons - TestThread(&COM1); + Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), + NORMALPRIO, TestThread, &COM1); + chThdWait(tp); PlaySound(500, 100); } else { -- cgit v1.2.3 From 6776d069274223f061f9f4e15e5732a7b454bd51 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 9 Nov 2008 11:12:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@505 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chconf.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 513c352a6..ddf733411 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS -- cgit v1.2.3 From aafa0564b8cdd61c68165217a4b7576bd35b2b4b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 9 Nov 2008 13:28:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@508 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 10 ++++++++++ demos/ARM7-LPC214x-G++/chconf.h | 10 ++++++++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 10 ++++++++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 10 ++++++++++ demos/AVR-AT90CANx-GCC/chconf.h | 10 ++++++++++ demos/AVR-ATmega128-GCC/chconf.h | 10 ++++++++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 10 ++++++++++ demos/Win32-MinGW/chconf.h | 10 ++++++++++ 9 files changed, 90 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 122d34c97..33532e535 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 513c352a6..ddf733411 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index e4595ba4a..a6cf96004 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index df9f1fa97..af4a62d09 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ //#define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +//#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +//#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ //#define CH_USE_EVENTS diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 513c352a6..ddf733411 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 7e972155f..89b01bfae 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index bda3d497b..d2a689b62 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index dc9574ef7..5a43ac1b2 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -60,6 +60,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 7a444aa2d..07ff4d0d5 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -55,6 +55,16 @@ * the kernel.*/ #define CH_USE_MUTEXES +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS + +/** Configuration option: if specified then the Conditional Variables APIs are + * included in the kernel. + * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ +#define CH_USE_CONDVARS_TIMEOUT + /** Configuration option: if specified then the Events APIs are included in * the kernel.*/ #define CH_USE_EVENTS -- cgit v1.2.3 From bc3964df2684cd45fde0802597f4cdf1face4a12 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Nov 2008 09:51:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@509 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 11 ++++++----- demos/MSP430-MSP430x1611-GCC/chconf.h | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 547437047..c9b3b395e 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -151,13 +151,13 @@ msg_t WebThread(void *p) { * Event sources setup. */ chEvtRegister(&EMACFrameReceived, &el0, FRAME_RECEIVED_ID); - chEvtBroadcast(&EMACFrameReceived); /* In case some frames are already buffered */ + chEvtPend(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ - evtInit(&evt1, CH_FREQUENCY / 2); + evtInit(&evt1, MS2ST(500)); evtStart(&evt1); chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); - evtInit(&evt2, CH_FREQUENCY * 10); + evtInit(&evt2, S2ST(10)); evtStart(&evt2); chEvtRegister(&evt2.et_es, &el2, ARP_TIMER_ID); @@ -176,7 +176,8 @@ msg_t WebThread(void *p) { uip_sethostaddr(ipaddr); httpd_init(); - while (TRUE) - chEvtWait(ALL_EVENTS, evhndl); + while (TRUE) { + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + } return 0; } diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 5a43ac1b2..785abb912 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -133,7 +133,7 @@ * provide the \p __heap_base__ and \p __heap_end__ symbols. * @note requires \p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#define CH_HEAP_SIZE 512 /** Configuration option: enforces the use of the C-runtime \p malloc() and * \p free() functions as backend for the system heap allocator.*/ -- cgit v1.2.3 From ae97c97b114c0e56d9881d54fbc97a052976b25a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Nov 2008 10:19:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@510 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/main.c | 32 ++++++++++++++++---------------- demos/ARMCM3-STM32F103-GCC/main.c | 6 +++--- 2 files changed, 19 insertions(+), 19 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 9b231408f..90dece112 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -34,13 +34,13 @@ static msg_t Thread1(void *arg) { while (TRUE) { IO0CLR = 0x00000800; - chThdSleep(200); + chThdSleepMilliseconds(200); IO0SET = 0x00000C00; - chThdSleep(800); + chThdSleepMilliseconds(800); IO0CLR = 0x00000400; - chThdSleep(200); + chThdSleepMilliseconds(200); IO0SET = 0x00000C00; - chThdSleep(800); + chThdSleepMilliseconds(800); } return 0; } @@ -53,9 +53,9 @@ static msg_t Thread2(void *arg) { while (TRUE) { IO0CLR = 0x80000000; - chThdSleep(200); + chThdSleepMilliseconds(200); IO0SET = 0x80000000; - chThdSleep(300); + chThdSleepMilliseconds(300); } return 0; } @@ -71,14 +71,14 @@ static void TimerHandler(eventid_t id) { Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), NORMALPRIO, TestThread, &COM1); chThdWait(tp); - PlaySound(500, 100); + PlaySound(500, MS2ST(100)); } else { if (!(IO0PIN & 0x00008000)) // Button 1 - PlaySound(1000, 100); + PlaySound(1000, MS2ST(100)); if (!(IO0PIN & 0x00010000)) { // Button 2 chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); - PlaySound(2000, 100); + PlaySound(2000, MS2ST(100)); } } } @@ -91,8 +91,8 @@ static void InsertHandler(eventid_t id) { static uint8_t rwbuf[512]; MMCCSD data; - PlaySoundWait(1000, 100); - PlaySoundWait(2000, 100); + PlaySoundWait(1000, MS2ST(100)); + PlaySoundWait(2000, MS2ST(100)); if (mmcInit()) return; /* Card ready, do stuff.*/ @@ -100,7 +100,7 @@ static void InsertHandler(eventid_t id) { return; if (mmcRead(rwbuf, 0)) return; - PlaySound(440, 200); + PlaySound(440, MS2ST(200)); } /* @@ -108,8 +108,8 @@ static void InsertHandler(eventid_t id) { */ static void RemoveHandler(eventid_t id) { - PlaySoundWait(2000, 100); - PlaySoundWait(1000, 100); + PlaySoundWait(2000, MS2ST(100)); + PlaySoundWait(1000, MS2ST(100)); } /* @@ -138,13 +138,13 @@ int main(int argc, char **argv) { * Normal main() activity, in this demo it serves events generated by * various sources. */ - evtInit(&evt, 500); /* Initializes an event timer object. */ + evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ evtStart(&evt); /* Starts the event timer. */ chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ mmcStartPolling(); /* Starts the MMC connector polling. */ chEvtRegister(&MMCInsertEventSource, &el1, 1); chEvtRegister(&MMCRemoveEventSource, &el2, 2); while (TRUE) /* Just serve events. */ - chEvtWait(ALL_EVENTS, evhndl); + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); return 0; } diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 0df4bc03d..055fa3a45 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -31,9 +31,9 @@ static msg_t Thread1(void *arg) { while (TRUE) { GPIOC->BRR = GPIOC_LED; - chThdSleep(500); + chThdSleepMilliseconds(500); GPIOC->BSRR = GPIOC_LED; - chThdSleep(500); + chThdSleepMilliseconds(500); } return 0; } @@ -56,7 +56,7 @@ int main(int argc, char **argv) { while (TRUE) { if (GPIOA->IDR & GPIOA_BUTTON) TestThread(&COM2); - chThdSleep(500); + chThdSleepMilliseconds(500); } return 0; } -- cgit v1.2.3 From 554e9da84ac99455e812d366418dc508eb51f09d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Nov 2008 10:34:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@511 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/main.c | 6 +++--- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 6 +++--- demos/ARM7-LPC214x-GCC-minimal/main.c | 14 +++++++------- demos/AVR-AT90CANx-GCC/main.c | 6 +++--- demos/AVR-ATmega128-GCC/main.c | 6 +++--- demos/MSP430-MSP430x1611-GCC/main.c | 6 +++--- 6 files changed, 22 insertions(+), 22 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 1fc284cd3..1d60db848 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -28,9 +28,9 @@ static msg_t Thread1(void *arg) { while (TRUE) { AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. - chThdSleep(100); + chThdSleepMilliseconds(100); AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // LCD off. - chThdSleep(900); + chThdSleepMilliseconds(900); } return 0; } @@ -50,7 +50,7 @@ int main(int argc, char **argv) { * Normal main() thread activity. */ while (TRUE) { - chThdSleep(500); + chThdSleepMilliseconds(500); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW2)) diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index 00dc9193e..a3da190d7 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -33,9 +33,9 @@ static msg_t Thread1(void *arg) { while (TRUE) { AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. - chThdSleep(100); + chThdSleepMilliseconds(100); AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // LCD off. - chThdSleep(900); + chThdSleepMilliseconds(900); } return 0; } @@ -56,7 +56,7 @@ int main(int argc, char **argv) { * Normal main() thread activity. */ while (TRUE) { - chThdSleep(500); + chThdSleepMilliseconds(500); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW2)) diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 11fdd7b56..134d74f5d 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -29,13 +29,13 @@ static msg_t Thread1(void *arg) { while (TRUE) { IO0CLR = 0x00000800; - chThdSleep(200); + chThdSleepMilliseconds(200); IO0SET = 0x00000C00; - chThdSleep(800); + chThdSleepMilliseconds(800); IO0CLR = 0x00000400; - chThdSleep(200); + chThdSleepMilliseconds(200); IO0SET = 0x00000C00; - chThdSleep(800); + chThdSleepMilliseconds(800); } return 0; } @@ -48,9 +48,9 @@ static msg_t Thread2(void *arg) { while (TRUE) { IO0CLR = 0x80000000; - chThdSleep(200); + chThdSleepMilliseconds(200); IO0SET = 0x80000000; - chThdSleep(300); + chThdSleepMilliseconds(300); } return 0; } @@ -72,6 +72,6 @@ int main(int argc, char **argv) { * sleeping in a loop. */ while (TRUE) - chThdSleep(1000); + chThdSleepMilliseconds(1000); return 0; } diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 987deb072..b7e646c6b 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -32,7 +32,7 @@ static msg_t Thread1(void *arg) { while (TRUE) { PORTE ^= PORTE_LED; - chThdSleep(500); + chThdSleepMilliseconds(500); } return 0; } @@ -62,7 +62,7 @@ int main(int argc, char **argv) { /* * Event Timer initialization. */ - evtInit(&evt, 500); /* Initializes an event timer object. */ + evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ evtStart(&evt); /* Starts the event timer. */ chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ @@ -72,7 +72,7 @@ int main(int argc, char **argv) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); while(TRUE) - chEvtWait(ALL_EVENTS, handlers); + chEvtDispatch(handlers, chEvtWaitOne(ALL_EVENTS)); return 0; } diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 873a28a79..40b2f8b89 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -34,7 +34,7 @@ static msg_t Thread1(void *arg) { while (TRUE) { if (!(PINA & PORTA_BUTTON2)) PORTA ^= PORTA_RELAY; - chThdSleep(1000); + chThdSleepMilliseconds(1000); } return 0; } @@ -73,7 +73,7 @@ int main(int argc, char **argv) { /* * Event Timer initialization. */ - evtInit(&evt, 500); /* Initializes an event timer object. */ + evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ evtStart(&evt); /* Starts the event timer. */ chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ @@ -83,7 +83,7 @@ int main(int argc, char **argv) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); while(TRUE) - chEvtWait(ALL_EVENTS, handlers); + chEvtDispatch(handlers, chEvtWaitOne(ALL_EVENTS)); return 0; } diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 72025d6a4..911ba84d9 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -31,9 +31,9 @@ static msg_t Thread1(void *arg) { while (TRUE) { P6OUT |= P6_O_LED; - chThdSleep(MS2ST(500)); + chThdSleepMilliseconds(500); P6OUT &= ~P6_O_LED; - chThdSleep(MS2ST(500)); + chThdSleepMilliseconds(500); } return 0; } @@ -66,7 +66,7 @@ int main(int argc, char **argv) { while (TRUE) { if (!(P6IN & P6_I_BUTTON)) TestThread(&COM1); - chThdSleep(MS2ST(500)); + chThdSleepMilliseconds(500); } return 0; } -- cgit v1.2.3 From c247b6b26c704931435490ce51fe42da7bf67be5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Nov 2008 11:08:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@512 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 785abb912..c6ca7420a 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -137,7 +137,7 @@ /** Configuration option: enforces the use of the C-runtime \p malloc() and * \p free() functions as backend for the system heap allocator.*/ -#define CH_USE_MALLOC_HEAP +//#define CH_USE_MALLOC_HEAP /** Configuration option: if specified then the memory pools allocator APIs * are included in the kernel.*/ -- cgit v1.2.3 From b3e92dc72078603137a7182759419e2b801755b9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 29 Nov 2008 10:54:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@521 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/main.c | 2 +- demos/ARM7-LPC214x-GCC/main.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 1d60db848..c51c911c9 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -23,7 +23,7 @@ #include "board.h" #include -static WorkingArea(waThread1, 64); +static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 90dece112..96b117f8a 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -29,7 +29,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WorkingArea(waThread1, 64); +static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { @@ -48,7 +48,7 @@ static msg_t Thread1(void *arg) { /* * Yellow LED blinker thread, times are in milliseconds. */ -static WorkingArea(waThread2, 64); +static WORKING_AREA(waThread2, 64); static msg_t Thread2(void *arg) { while (TRUE) { @@ -60,7 +60,7 @@ static msg_t Thread2(void *arg) { return 0; } -static WorkingArea(waTestThread, 128); +static WORKING_AREA(waTestThread, 128); /* * Executed as event handler at 500mS intervals. -- cgit v1.2.3 From 994fc74888092de07dd5aa166e7e45f8ae5da035 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 29 Nov 2008 11:15:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@522 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 4 ++-- demos/ARM7-LPC214x-GCC-minimal/main.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index a3da190d7..07af9b0bd 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -26,8 +26,8 @@ #include "web/webthread.h" -static WorkingArea(waWebThread, 512); -static WorkingArea(waThread1, 64); +static WORKING_AREA(waWebThread, 512); +static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 134d74f5d..b80264ed7 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -24,7 +24,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WorkingArea(waThread1, 64); +static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { @@ -43,7 +43,7 @@ static msg_t Thread1(void *arg) { /* * Yellow LED blinker thread, times are in milliseconds. */ -static WorkingArea(waThread2, 64); +static WORKING_AREA(waThread2, 64); static msg_t Thread2(void *arg) { while (TRUE) { -- cgit v1.2.3 From ce0b1af78d0c382696fdf00bf32bb2cecbfd7f50 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 29 Nov 2008 12:15:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@523 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 055fa3a45..ec59c4ffd 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -26,7 +26,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WorkingArea(waThread1, 128); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { -- cgit v1.2.3 From 62d821990abb79f9c7bb27f32d249bc934fa0990 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 29 Nov 2008 12:55:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@524 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/main.c | 2 +- demos/AVR-ATmega128-GCC/main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index b7e646c6b..aa9b99dc0 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -27,7 +27,7 @@ void hwinit(void); -static WorkingArea(waThread1, 32); +static WORKING_AREA(waThread1, 32); static msg_t Thread1(void *arg) { while (TRUE) { diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 40b2f8b89..405770d00 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -28,7 +28,7 @@ void hwinit(void); -static WorkingArea(waThread1, 32); +static WORKING_AREA(waThread1, 32); static msg_t Thread1(void *arg) { while (TRUE) { -- cgit v1.2.3 From 21c82221ac2b03ff34f3e9aa0e6f2412d0cd9fe2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 29 Nov 2008 13:57:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@526 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 911ba84d9..4bc7d9895 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -26,7 +26,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WorkingArea(waThread1, 64); +static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { -- cgit v1.2.3 From 8a18733367054dd6a3a68633d25633f672ae87c0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Dec 2008 11:20:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@530 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/ch.ld | 90 ++++++++++++++++++------------------ demos/ARM7-LPC214x-GCC-minimal/ch.ld | 90 ++++++++++++++++++------------------ demos/ARM7-LPC214x-GCC/ch.ld | 90 ++++++++++++++++++------------------ 3 files changed, 135 insertions(+), 135 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index 81ab80dc6..b0425dbca 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -30,16 +30,16 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 } -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; SECTIONS { @@ -47,46 +47,46 @@ SECTIONS .text : { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash - _textdata = _etext; + _textdata = _etext; - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld index 81ab80dc6..b0425dbca 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -30,16 +30,16 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 } -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; SECTIONS { @@ -47,46 +47,46 @@ SECTIONS .text : { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash - _textdata = _etext; + _textdata = _etext; - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index 81ab80dc6..b0425dbca 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -30,16 +30,16 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 } -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; SECTIONS { @@ -47,46 +47,46 @@ SECTIONS .text : { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash - _textdata = _etext; + _textdata = _etext; - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram } PROVIDE(end = .); -- cgit v1.2.3 From ed3ffb35089836df6b5b51b76c428078a80dbb3b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Dec 2008 11:42:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@531 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/ch.ld | 2 +- demos/ARM7-LPC214x-GCC-minimal/ch.ld | 2 +- demos/ARM7-LPC214x-GCC/ch.ld | 2 +- demos/ARMCM3-STM32F103-GCC/ch.ld | 96 ++++++++++++++++++------------------ 4 files changed, 51 insertions(+), 51 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index b0425dbca..2bbea7477 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -45,7 +45,7 @@ SECTIONS { . = 0; - .text : + .text : ALIGN(16) SUBALIGN(16) { _text = .; KEEP(*(vectors)) diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld index b0425dbca..2bbea7477 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -45,7 +45,7 @@ SECTIONS { . = 0; - .text : + .text : ALIGN(16) SUBALIGN(16) { _text = .; KEEP(*(vectors)) diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index b0425dbca..2bbea7477 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -45,7 +45,7 @@ SECTIONS { . = 0; - .text : + .text : ALIGN(16) SUBALIGN(16) { _text = .; KEEP(*(vectors)) diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index f18ba7e5d..af13b206d 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -26,64 +26,64 @@ __stacks_total_size__ = __main_stack_size__ + __process_stack_size__; MEMORY { - flash : org = 0x08000000, len = 128k - ram : org = 0x20000000, len = 20k + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 20k } -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; SECTIONS { - . = 0; + . = 0; - .text : - { - _text = .; - KEEP(*(vectors)); - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)); + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash - _textdata = _etext; + _textdata = _etext; - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram } PROVIDE(end = .); -_end = .; +_end = .; -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; -- cgit v1.2.3 From dae3de6609b9251dbaaa280c1ce886a350c3c0c5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 7 Dec 2008 10:21:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@536 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 576581b79..a269189ab 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -139,7 +139,7 @@ int main(int argc, char **argv) { chEvtRegister(&evt.et_es, &el0, 0); // Registers a listener on the source. /* - * Starts serveral instances of the SequencerThread class, each one operating + * Starts several instances of the SequencerThread class, each one operating * on a different LED. */ SequencerThread blinker1(LED1_sequence); @@ -150,7 +150,7 @@ int main(int argc, char **argv) { * Serves timer events. */ while (true) - Event::Wait(ALL_EVENTS, evhndl); + Event::Dispatch(evhndl, Event::WaitOne(ALL_EVENTS)); return 0; } -- cgit v1.2.3 From 2b8c31c32f67d2e31ff19507ca3425f9bcecba76 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Dec 2008 08:44:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@538 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.c | 2 +- demos/Win32-MinGW/chcore.h | 35 +++++++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 047fe66da..48842f186 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -91,7 +91,7 @@ void ChkIntSources(void) { } } -msg_t _IdleThread(void *p) { +msg_t _idle(void *p) { while (TRUE) { diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index c3c3f3a0b..2c916f536 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -24,6 +24,16 @@ #ifndef _CHCORE_H_ #define _CHCORE_H_ +/* + * Unique macro for the implemented architecture. + */ +#define CH_ARCHITECTURE_WIN32SIM + +/* + * Base type for stack alignment. + */ +typedef uint32_t stkalign_t; + typedef void *regx86; /* @@ -65,17 +75,26 @@ typedef struct { #define chSysIRQExitI() #define INT_REQUIRED_STACK 0 -#define StackAlign(n) ((((n) - 1) | 3) + 1) -#define UserStackSize(n) StackAlign(sizeof(Thread) + \ - sizeof(void *) * 2 + \ - sizeof(struct intctx) + \ - (n) + \ - INT_REQUIRED_STACK) -#define WorkingArea(s, n) uint32_t s[UserStackSize(n) >> 2]; +#define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1) +#define StackAlign(n) STACK_ALIGN(n) + +#define THD_WA_SIZE(n) StackAlign(sizeof(Thread) + \ + sizeof(void *) * 2 + \ + sizeof(struct intctx) + \ + (n) + \ + INT_REQUIRED_STACK) +#define UserStackSize(n) THD_WA_SIZE(n) + +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; +#define WorkingArea(s, n) WORKING_AREA(s, n) + +/* + * Stack size for the system idle thread. + */ #define IDLE_THREAD_STACK_SIZE 16384 -msg_t _IdleThread(void *p); +msg_t _idle(void *p); __attribute__((fastcall)) void chSysHalt(void); __attribute__((fastcall)) void chSysSwitchI(Thread *otp, Thread *ntp); __attribute__((fastcall)) void threadstart(void); -- cgit v1.2.3 From 436aa85ab1c30168d6cdd64de2a4eb1ca9fee534 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Dec 2008 09:55:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@539 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 4 +- demos/Win32-MinGW/demo.c | 301 --------------------------------------------- demos/Win32-MinGW/main.c | 301 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 303 insertions(+), 303 deletions(-) delete mode 100644 demos/Win32-MinGW/demo.c create mode 100644 demos/Win32-MinGW/main.c (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index fe06db6e1..46cb9cad0 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -60,7 +60,7 @@ include ../../src/kernel.mk include ../../test/test.mk # List C source files here -SRC = chcore.c demo.c ../../ports/win32/simcom.c \ +SRC = chcore.c main.c ../../ports/win32/simcom.c \ ${KERNSRC} \ ${TESTSRC} @@ -77,7 +77,7 @@ ULIBDIR = ULIBS = # Define optimisation level here -OPT = -Os -fomit-frame-pointer +OPT = -ggdb -Os -fomit-frame-pointer # # End of user defines diff --git a/demos/Win32-MinGW/demo.c b/demos/Win32-MinGW/demo.c deleted file mode 100644 index f3d276599..000000000 --- a/demos/Win32-MinGW/demo.c +++ /dev/null @@ -1,301 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include - -#include - -static uint32_t wdguard; -static WorkingArea(wdarea, 2048); - -static uint32_t cdguard; -static WorkingArea(cdarea, 2048); -static Thread *cdtp; - -static msg_t WatchdogThread(void *arg); -static msg_t ConsoleThread(void *arg); - -msg_t TestThread(void *p); - -void InitCore(void); -extern FullDuplexDriver COM1, COM2; - -#define cprint(msg) chMsgSend(cdtp, (msg_t)msg) - -/* - * Watchdog thread, it checks magic values located under the various stack - * areas. The system is halted if something is wrong. - */ -static msg_t WatchdogThread(void *arg) { - wdguard = 0xA51F2E3D; - cdguard = 0xA51F2E3D; - while (TRUE) { - - if ((wdguard != 0xA51F2E3D) || - (cdguard != 0xA51F2E3D)) { - printf("Halted by watchdog"); - chSysHalt(); - } - chThdSleep(50); - } - return 0; -} - -/* - * Console print server done using synchronous messages. This makes the access - * to the C printf() thread safe and the print operation atomic among threads. - * In this example the message is the zero termitated string itself. - */ -static msg_t ConsoleThread(void *arg) { - - while (!chThdShouldTerminate()) { - printf((char *)chMsgWait()); - chMsgRelease(RDY_OK); - } - return 0; -} - -static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { - - while (*msg) - chFDDPut(sd, *msg++); -} - -static bool_t GetLineFDD(FullDuplexDriver *sd, char *line, int size) { - char *p = line; - - while (TRUE) { - short c = chIQGet(&sd->sd_iqueue); - if (c < 0) - return TRUE; - if (c == 4) { - PrintLineFDD(sd, "^D\r\n"); - return TRUE; - } - if (c == 8) { - if (p != line) { - chFDDPut(sd, (uint8_t)c); - chFDDPut(sd, 0x20); - chFDDPut(sd, (uint8_t)c); - p--; - } - continue; - } - if (c == '\r') { - PrintLineFDD(sd, "\r\n"); - *p = 0; - return FALSE; - } - if (c < 0x20) - continue; - if (p < line + size - 1) { - chFDDPut(sd, (uint8_t)c); - *p++ = (uint8_t)c; - } - } -} - -/* - * Example thread, not much to see here. It simulates the CTRL-C but there - * are no real signals involved. - */ -static msg_t HelloWorldThread(void *arg) { - int i; - short c; - FullDuplexDriver *sd = (FullDuplexDriver *)arg; - - for (i = 0; i < 100; i++) { - - PrintLineFDD(sd, "Hello World\r\n"); - c = chFDDGetTimeout(sd, 333); - switch (c) { - case -1: - continue; - case -2: - return 1; - case 3: - PrintLineFDD(sd, "^C\r\n"); - return 0; - default: - chThdSleep(333); - } - } - return 0; -} - -static bool_t checkend(FullDuplexDriver *sd) { - - char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ - if (lp) { - PrintLineFDD(sd, lp); - PrintLineFDD(sd, " ?\r\n"); - return TRUE; - } - return FALSE; -} - -/* - * Simple command shell thread, the argument is the serial line for the - * standard input and output. It recognizes few simple commands. - */ -static msg_t ShellThread(void *arg) { - FullDuplexDriver *sd = (FullDuplexDriver *)arg; - char *lp, line[64]; - Thread *tp; - WorkingArea(tarea, 2048); - - chIQReset(&sd->sd_iqueue); - chOQReset(&sd->sd_oqueue); - PrintLineFDD(sd, "ChibiOS/RT Command Shell\r\n\n"); - while (TRUE) { - PrintLineFDD(sd, "ch> "); - if (GetLineFDD(sd, line, sizeof(line))) { - PrintLineFDD(sd, "\nlogout"); - break; - } - lp = strtok(line, " \009"); // Note: not thread safe but it is just a demo. - if (lp) { - if ((stricmp(lp, "help") == 0) || - (stricmp(lp, "h") == 0) || - (stricmp(lp, "?") == 0)) { - if (checkend(sd)) - continue; - PrintLineFDD(sd, "Commands:\r\n"); - PrintLineFDD(sd, " help,h,? - This help\r\n"); - PrintLineFDD(sd, " exit - Logout from ChibiOS/RT\r\n"); - PrintLineFDD(sd, " time - Prints the system timer value\r\n"); - PrintLineFDD(sd, " hello - Runs the Hello World demo thread\r\n"); - PrintLineFDD(sd, " test - Runs the System Test thread\r\n"); - } - else if (stricmp(lp, "exit") == 0) { - if (checkend(sd)) - continue; - PrintLineFDD(sd, "\nlogout"); - break; - } - else if (stricmp(lp, "time") == 0) { - if (checkend(sd)) - continue; - sprintf(line, "Time: %d\r\n", chSysGetTime()); - PrintLineFDD(sd, line); - } - else if (stricmp(lp, "hello") == 0) { - if (checkend(sd)) - continue; - tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), - HelloWorldThread, sd); - if (chThdWait(tp)) - break; // Lost connection while executing the hello thread. - } - else if (stricmp(lp, "test") == 0) { - if (checkend(sd)) - continue; - tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), - TestThread, arg); - if (chThdWait(tp)) - break; // Lost connection while executing the hello thread. - } - else { - PrintLineFDD(sd, lp); - PrintLineFDD(sd, " ?\r\n"); - } - } - } - return 0; -} - -static WorkingArea(s1area, 4096); -static Thread *s1; -EventListener s1tel; - -static void COM1Handler(eventid_t id) { - dflags_t flags; - - if (s1 && chThdTerminated(s1)) { - s1 = NULL; - cprint("Init: disconnection on COM1\n"); - } - flags = chFDDGetAndClearFlags(&COM1); - if ((flags & SD_CONNECTED) && (s1 == NULL)) { - cprint("Init: connection on COM1\n"); - s1 = chThdCreate(NORMALPRIO, P_SUSPENDED, s1area, sizeof(s1area), - ShellThread, &COM1); - chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); - chThdResume(s1); - } - if ((flags & SD_DISCONNECTED) && (s1 != NULL)) - chIQReset(&COM1.sd_iqueue); -} - -static WorkingArea(s2area, 4096); -static Thread *s2; -EventListener s2tel; - -static void COM2Handler(eventid_t id) { - dflags_t flags; - - if (s2 && chThdTerminated(s2)) { - s2 = NULL; - cprint("Init: disconnection on COM2\n"); - } - flags = chFDDGetAndClearFlags(&COM2); - if ((flags & SD_CONNECTED) && (s2 == NULL)) { - cprint("Init: connection on COM2\n"); - s2 = chThdCreate(NORMALPRIO, P_SUSPENDED, s2area, sizeof(s1area), - ShellThread, &COM2); - chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); - chThdResume(s2); - } - if ((flags & SD_DISCONNECTED) && (s2 != NULL)) - chIQReset(&COM2.sd_iqueue); -} - -static evhandler_t fhandlers[2] = { - COM1Handler, - COM2Handler -}; - -/*------------------------------------------------------------------------* - * Simulator main, start here your threads, examples inside. * - *------------------------------------------------------------------------*/ -int main(void) { - EventListener c1fel, c2fel; - - InitCore(); - - // Startup ChibiOS/RT. - chSysInit(); - - chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); - cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); - - cprint("Console service started on COM1, COM2\n"); - cprint(" - Listening for connections on COM1\n"); - chFDDGetAndClearFlags(&COM1); - chEvtRegister(&COM1.sd_sevent, &c1fel, 0); - cprint(" - Listening for connections on COM2\n"); - chFDDGetAndClearFlags(&COM2); - chEvtRegister(&COM2.sd_sevent, &c2fel, 1); - while (!chThdShouldTerminate()) - chEvtWait(ALL_EVENTS, fhandlers); - chEvtUnregister(&COM2.sd_sevent, &c2fel); // Never invoked but this is an example... - chEvtUnregister(&COM1.sd_sevent, &c1fel); // Never invoked but this is an example... - return 0; -} diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c new file mode 100644 index 000000000..f3d276599 --- /dev/null +++ b/demos/Win32-MinGW/main.c @@ -0,0 +1,301 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include + +static uint32_t wdguard; +static WorkingArea(wdarea, 2048); + +static uint32_t cdguard; +static WorkingArea(cdarea, 2048); +static Thread *cdtp; + +static msg_t WatchdogThread(void *arg); +static msg_t ConsoleThread(void *arg); + +msg_t TestThread(void *p); + +void InitCore(void); +extern FullDuplexDriver COM1, COM2; + +#define cprint(msg) chMsgSend(cdtp, (msg_t)msg) + +/* + * Watchdog thread, it checks magic values located under the various stack + * areas. The system is halted if something is wrong. + */ +static msg_t WatchdogThread(void *arg) { + wdguard = 0xA51F2E3D; + cdguard = 0xA51F2E3D; + while (TRUE) { + + if ((wdguard != 0xA51F2E3D) || + (cdguard != 0xA51F2E3D)) { + printf("Halted by watchdog"); + chSysHalt(); + } + chThdSleep(50); + } + return 0; +} + +/* + * Console print server done using synchronous messages. This makes the access + * to the C printf() thread safe and the print operation atomic among threads. + * In this example the message is the zero termitated string itself. + */ +static msg_t ConsoleThread(void *arg) { + + while (!chThdShouldTerminate()) { + printf((char *)chMsgWait()); + chMsgRelease(RDY_OK); + } + return 0; +} + +static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { + + while (*msg) + chFDDPut(sd, *msg++); +} + +static bool_t GetLineFDD(FullDuplexDriver *sd, char *line, int size) { + char *p = line; + + while (TRUE) { + short c = chIQGet(&sd->sd_iqueue); + if (c < 0) + return TRUE; + if (c == 4) { + PrintLineFDD(sd, "^D\r\n"); + return TRUE; + } + if (c == 8) { + if (p != line) { + chFDDPut(sd, (uint8_t)c); + chFDDPut(sd, 0x20); + chFDDPut(sd, (uint8_t)c); + p--; + } + continue; + } + if (c == '\r') { + PrintLineFDD(sd, "\r\n"); + *p = 0; + return FALSE; + } + if (c < 0x20) + continue; + if (p < line + size - 1) { + chFDDPut(sd, (uint8_t)c); + *p++ = (uint8_t)c; + } + } +} + +/* + * Example thread, not much to see here. It simulates the CTRL-C but there + * are no real signals involved. + */ +static msg_t HelloWorldThread(void *arg) { + int i; + short c; + FullDuplexDriver *sd = (FullDuplexDriver *)arg; + + for (i = 0; i < 100; i++) { + + PrintLineFDD(sd, "Hello World\r\n"); + c = chFDDGetTimeout(sd, 333); + switch (c) { + case -1: + continue; + case -2: + return 1; + case 3: + PrintLineFDD(sd, "^C\r\n"); + return 0; + default: + chThdSleep(333); + } + } + return 0; +} + +static bool_t checkend(FullDuplexDriver *sd) { + + char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ + if (lp) { + PrintLineFDD(sd, lp); + PrintLineFDD(sd, " ?\r\n"); + return TRUE; + } + return FALSE; +} + +/* + * Simple command shell thread, the argument is the serial line for the + * standard input and output. It recognizes few simple commands. + */ +static msg_t ShellThread(void *arg) { + FullDuplexDriver *sd = (FullDuplexDriver *)arg; + char *lp, line[64]; + Thread *tp; + WorkingArea(tarea, 2048); + + chIQReset(&sd->sd_iqueue); + chOQReset(&sd->sd_oqueue); + PrintLineFDD(sd, "ChibiOS/RT Command Shell\r\n\n"); + while (TRUE) { + PrintLineFDD(sd, "ch> "); + if (GetLineFDD(sd, line, sizeof(line))) { + PrintLineFDD(sd, "\nlogout"); + break; + } + lp = strtok(line, " \009"); // Note: not thread safe but it is just a demo. + if (lp) { + if ((stricmp(lp, "help") == 0) || + (stricmp(lp, "h") == 0) || + (stricmp(lp, "?") == 0)) { + if (checkend(sd)) + continue; + PrintLineFDD(sd, "Commands:\r\n"); + PrintLineFDD(sd, " help,h,? - This help\r\n"); + PrintLineFDD(sd, " exit - Logout from ChibiOS/RT\r\n"); + PrintLineFDD(sd, " time - Prints the system timer value\r\n"); + PrintLineFDD(sd, " hello - Runs the Hello World demo thread\r\n"); + PrintLineFDD(sd, " test - Runs the System Test thread\r\n"); + } + else if (stricmp(lp, "exit") == 0) { + if (checkend(sd)) + continue; + PrintLineFDD(sd, "\nlogout"); + break; + } + else if (stricmp(lp, "time") == 0) { + if (checkend(sd)) + continue; + sprintf(line, "Time: %d\r\n", chSysGetTime()); + PrintLineFDD(sd, line); + } + else if (stricmp(lp, "hello") == 0) { + if (checkend(sd)) + continue; + tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), + HelloWorldThread, sd); + if (chThdWait(tp)) + break; // Lost connection while executing the hello thread. + } + else if (stricmp(lp, "test") == 0) { + if (checkend(sd)) + continue; + tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), + TestThread, arg); + if (chThdWait(tp)) + break; // Lost connection while executing the hello thread. + } + else { + PrintLineFDD(sd, lp); + PrintLineFDD(sd, " ?\r\n"); + } + } + } + return 0; +} + +static WorkingArea(s1area, 4096); +static Thread *s1; +EventListener s1tel; + +static void COM1Handler(eventid_t id) { + dflags_t flags; + + if (s1 && chThdTerminated(s1)) { + s1 = NULL; + cprint("Init: disconnection on COM1\n"); + } + flags = chFDDGetAndClearFlags(&COM1); + if ((flags & SD_CONNECTED) && (s1 == NULL)) { + cprint("Init: connection on COM1\n"); + s1 = chThdCreate(NORMALPRIO, P_SUSPENDED, s1area, sizeof(s1area), + ShellThread, &COM1); + chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); + chThdResume(s1); + } + if ((flags & SD_DISCONNECTED) && (s1 != NULL)) + chIQReset(&COM1.sd_iqueue); +} + +static WorkingArea(s2area, 4096); +static Thread *s2; +EventListener s2tel; + +static void COM2Handler(eventid_t id) { + dflags_t flags; + + if (s2 && chThdTerminated(s2)) { + s2 = NULL; + cprint("Init: disconnection on COM2\n"); + } + flags = chFDDGetAndClearFlags(&COM2); + if ((flags & SD_CONNECTED) && (s2 == NULL)) { + cprint("Init: connection on COM2\n"); + s2 = chThdCreate(NORMALPRIO, P_SUSPENDED, s2area, sizeof(s1area), + ShellThread, &COM2); + chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); + chThdResume(s2); + } + if ((flags & SD_DISCONNECTED) && (s2 != NULL)) + chIQReset(&COM2.sd_iqueue); +} + +static evhandler_t fhandlers[2] = { + COM1Handler, + COM2Handler +}; + +/*------------------------------------------------------------------------* + * Simulator main, start here your threads, examples inside. * + *------------------------------------------------------------------------*/ +int main(void) { + EventListener c1fel, c2fel; + + InitCore(); + + // Startup ChibiOS/RT. + chSysInit(); + + chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); + cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); + + cprint("Console service started on COM1, COM2\n"); + cprint(" - Listening for connections on COM1\n"); + chFDDGetAndClearFlags(&COM1); + chEvtRegister(&COM1.sd_sevent, &c1fel, 0); + cprint(" - Listening for connections on COM2\n"); + chFDDGetAndClearFlags(&COM2); + chEvtRegister(&COM2.sd_sevent, &c2fel, 1); + while (!chThdShouldTerminate()) + chEvtWait(ALL_EVENTS, fhandlers); + chEvtUnregister(&COM2.sd_sevent, &c2fel); // Never invoked but this is an example... + chEvtUnregister(&COM1.sd_sevent, &c1fel); // Never invoked but this is an example... + return 0; +} -- cgit v1.2.3 From 7f7cdc881e70aa0356eaa647647ab5d4cd2b5d27 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Dec 2008 10:34:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@540 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.c | 1 + demos/Win32-MinGW/main.c | 34 ++++++++++++++++++---------------- 2 files changed, 19 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 48842f186..9e9aba3fd 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -65,6 +65,7 @@ void InitCore(void) { InitSimCom1(); InitSimCom2(); + fflush(stdout); } /* diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index f3d276599..5de6ee938 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -23,10 +23,10 @@ #include static uint32_t wdguard; -static WorkingArea(wdarea, 2048); +static WORKING_AREA(wdarea, 2048); static uint32_t cdguard; -static WorkingArea(cdarea, 2048); +static WORKING_AREA(cdarea, 2048); static Thread *cdtp; static msg_t WatchdogThread(void *arg); @@ -51,6 +51,7 @@ static msg_t WatchdogThread(void *arg) { if ((wdguard != 0xA51F2E3D) || (cdguard != 0xA51F2E3D)) { printf("Halted by watchdog"); + fflush(stdout); chSysHalt(); } chThdSleep(50); @@ -67,6 +68,7 @@ static msg_t ConsoleThread(void *arg) { while (!chThdShouldTerminate()) { printf((char *)chMsgWait()); + fflush(stdout); chMsgRelease(RDY_OK); } return 0; @@ -159,7 +161,7 @@ static msg_t ShellThread(void *arg) { FullDuplexDriver *sd = (FullDuplexDriver *)arg; char *lp, line[64]; Thread *tp; - WorkingArea(tarea, 2048); + WORKING_AREA(tarea, 2048); chIQReset(&sd->sd_iqueue); chOQReset(&sd->sd_oqueue); @@ -199,16 +201,16 @@ static msg_t ShellThread(void *arg) { else if (stricmp(lp, "hello") == 0) { if (checkend(sd)) continue; - tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), - HelloWorldThread, sd); + tp = chThdCreateStatic(tarea, sizeof(tarea), + NORMALPRIO, HelloWorldThread, sd); if (chThdWait(tp)) break; // Lost connection while executing the hello thread. } else if (stricmp(lp, "test") == 0) { if (checkend(sd)) continue; - tp = chThdCreate(NORMALPRIO, 0, tarea, sizeof(tarea), - TestThread, arg); + tp = chThdCreateStatic(tarea, sizeof(tarea), + NORMALPRIO, TestThread, arg); if (chThdWait(tp)) break; // Lost connection while executing the hello thread. } @@ -221,7 +223,7 @@ static msg_t ShellThread(void *arg) { return 0; } -static WorkingArea(s1area, 4096); +static WORKING_AREA(s1area, 4096); static Thread *s1; EventListener s1tel; @@ -235,8 +237,8 @@ static void COM1Handler(eventid_t id) { flags = chFDDGetAndClearFlags(&COM1); if ((flags & SD_CONNECTED) && (s1 == NULL)) { cprint("Init: connection on COM1\n"); - s1 = chThdCreate(NORMALPRIO, P_SUSPENDED, s1area, sizeof(s1area), - ShellThread, &COM1); + s1 = chThdInit(s1area, sizeof(s1area), + NORMALPRIO, ShellThread, &COM1); chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); chThdResume(s1); } @@ -244,7 +246,7 @@ static void COM1Handler(eventid_t id) { chIQReset(&COM1.sd_iqueue); } -static WorkingArea(s2area, 4096); +static WORKING_AREA(s2area, 4096); static Thread *s2; EventListener s2tel; @@ -258,8 +260,8 @@ static void COM2Handler(eventid_t id) { flags = chFDDGetAndClearFlags(&COM2); if ((flags & SD_CONNECTED) && (s2 == NULL)) { cprint("Init: connection on COM2\n"); - s2 = chThdCreate(NORMALPRIO, P_SUSPENDED, s2area, sizeof(s1area), - ShellThread, &COM2); + s2 = chThdInit(s2area, sizeof(s1area), + NORMALPRIO, ShellThread, &COM2); chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); chThdResume(s2); } @@ -283,8 +285,8 @@ int main(void) { // Startup ChibiOS/RT. chSysInit(); - chThdCreate(NORMALPRIO + 2, 0, wdarea, sizeof(wdarea), WatchdogThread, NULL); - cdtp = chThdCreate(NORMALPRIO + 1, 0, cdarea, sizeof(cdarea), ConsoleThread, NULL); + chThdCreateStatic(wdarea, sizeof(wdarea), NORMALPRIO + 2, WatchdogThread, NULL); + cdtp = chThdCreateStatic(cdarea, sizeof(cdarea), NORMALPRIO + 1, ConsoleThread, NULL); cprint("Console service started on COM1, COM2\n"); cprint(" - Listening for connections on COM1\n"); @@ -294,7 +296,7 @@ int main(void) { chFDDGetAndClearFlags(&COM2); chEvtRegister(&COM2.sd_sevent, &c2fel, 1); while (!chThdShouldTerminate()) - chEvtWait(ALL_EVENTS, fhandlers); + chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); chEvtUnregister(&COM2.sd_sevent, &c2fel); // Never invoked but this is an example... chEvtUnregister(&COM1.sd_sevent, &c1fel); // Never invoked but this is an example... return 0; -- cgit v1.2.3 From dd39b808aceeb2cc726c9b90fe9ca3116bf0ebd7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Dec 2008 10:31:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@544 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/readme.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'demos') diff --git a/demos/Win32-MinGW/readme.txt b/demos/Win32-MinGW/readme.txt index 283ee42b2..047425ffe 100644 --- a/demos/Win32-MinGW/readme.txt +++ b/demos/Win32-MinGW/readme.txt @@ -20,3 +20,14 @@ See demo.c for details. ** Build Procedure ** The demo was built using the MinGW toolchain. + +** Connect to the demo ** + +In order to connect to the demo a telnet client is required. A good choice +is PuTTY: + +http://www.putty.org/ + +Host Name: 127.0.0.1 +Port: 29001 and/or 29002 +Connection Type: Raw -- cgit v1.2.3 From 3e9765e2069a9faedff2721a1abf46607cf1189d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 28 Dec 2008 10:07:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@545 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 12 ++---------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 12 ++---------- demos/ARM7-LPC214x-G++/chconf.h | 12 ++---------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 12 ++---------- demos/ARM7-LPC214x-GCC/chconf.h | 12 ++---------- demos/ARMCM3-STM32F103-GCC/chconf.h | 12 ++---------- demos/AVR-AT90CANx-GCC/chconf.h | 12 ++---------- demos/AVR-ATmega128-GCC/chconf.h | 12 ++---------- demos/MSP430-MSP430x1611-GCC/chconf.h | 14 +++----------- demos/Win32-MinGW/chconf.h | 12 ++---------- 10 files changed, 21 insertions(+), 101 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 33532e535..f8302116d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_MESSAGES. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0.*/ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index ddf733411..ed950dd3f 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index a6cf96004..2d0a1513f 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index af4a62d09..94ff64676 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -//#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ //#define CH_USE_QUEUES diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index ddf733411..ed950dd3f 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index ddf733411..ed950dd3f 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 89b01bfae..4900dd240 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index d2a689b62..ea028aed6 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index c6ca7420a..bf7a9afad 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -89,18 +89,10 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT +//#define CH_USE_MESSAGES_PRIORITY /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 07ff4d0d5..3187998cc 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -84,19 +84,11 @@ * @note requires \p CH_USE_MESSAGES.*/ #define CH_USE_MESSAGES_EVENT -/** Configuration option: If enabled then the threads have an option to serve - * messages by priority instead of FIFO order. +/** Configuration option: If enabled then the threads serve messages by + * priority instead of FIFO order. * @note requires \p CH_USE_MESSAGES.*/ //#define CH_USE_MESSAGES_PRIORITY -/** Configuration option: if specified then the - * \p chThdGetExitEventSource() function is included in the kernel. - * @note requires \p CH_USE_EVENTS. - * @deprecated \p THREAD_EXT_EXIT should be used, this functionality will be - * removed in version 1.0.0. - */ -#define CH_USE_EXIT_EVENT - /** Configuration option: if specified then the I/O queues APIs are included * in the kernel.*/ #define CH_USE_QUEUES -- cgit v1.2.3 From ca4419762eaab74d52e07e02defbaac42570fea3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 28 Dec 2008 11:17:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@546 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 2c916f536..9c7f9e8c1 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -77,17 +77,14 @@ typedef struct { #define INT_REQUIRED_STACK 0 #define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1) -#define StackAlign(n) STACK_ALIGN(n) #define THD_WA_SIZE(n) StackAlign(sizeof(Thread) + \ sizeof(void *) * 2 + \ sizeof(struct intctx) + \ (n) + \ INT_REQUIRED_STACK) -#define UserStackSize(n) THD_WA_SIZE(n) #define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; -#define WorkingArea(s, n) WORKING_AREA(s, n) /* * Stack size for the system idle thread. -- cgit v1.2.3 From 5300fced15f40774f8fcf75904373541ea351efa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 29 Dec 2008 08:58:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@553 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chconf.h | 6 ++++++ demos/Win32-MinGW/chcore.h | 10 +++++----- 2 files changed, 11 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 3187998cc..5b487dbe7 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -172,20 +172,26 @@ #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ + /* The thread termination \p EventSource.*/ \ + EventSource p_exitesource; \ }; /** User initialization code added to the \p chThdCreate() API. * @note It is invoked from within \p chThdInit(). */ #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ + chEvtInit(&tp->p_exitesource); \ } /** User finalization code added to the \p chThdExit() API. * @note It is inserted into lock zone. */ #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ + chEvtBroadcastI(&currp->p_exitesource); \ } +#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 9c7f9e8c1..d1f209a68 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -78,11 +78,11 @@ typedef struct { #define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1) -#define THD_WA_SIZE(n) StackAlign(sizeof(Thread) + \ - sizeof(void *) * 2 + \ - sizeof(struct intctx) + \ - (n) + \ - INT_REQUIRED_STACK) +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(void *) * 2 + \ + sizeof(struct intctx) + \ + (n) + \ + INT_REQUIRED_STACK) #define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; -- cgit v1.2.3 From d64c4c5b2efbd41410cae2f4226e79e96ee82360 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 30 Dec 2008 18:17:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@568 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/ch.ld | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index af13b206d..a68d88396 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -20,9 +20,9 @@ /* * ST32F103 memory setup. */ -__main_stack_size__ = 0x0200; -__process_stack_size__ = 0x0100; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0100; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; MEMORY { @@ -30,9 +30,9 @@ MEMORY ram : org = 0x20000000, len = 20k } -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; SECTIONS { -- cgit v1.2.3 From 9f6887fdd7c0abe03144f29d9585ee71c645c8dc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 6 Jan 2009 09:32:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@588 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index ed950dd3f..e329d0bdd 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge with ChibiOS/RT external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -- cgit v1.2.3 From 8ca74ca641b40428107879b934a0ad4337776f37 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 6 Jan 2009 11:46:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@592 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index e329d0bdd..cc2870abd 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -34,7 +34,7 @@ * @p chSysUnlock() operations is allowed.
* For performance and code size reasons the recommended setting is leave * this option disabled.
- * You can use this option if you need to merge with ChibiOS/RT external + * You can use this option if you need to merge ChibiOS/RT with external * libraries that require nested lock/unlock operations. */ //#define CH_USE_NESTED_LOCKS -- cgit v1.2.3 From 52ab7591c76c47228b41c23c45f943b7b0d43483 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 9 Jan 2009 11:05:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@595 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 8fcecec17..f5e5e4012 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -85,9 +85,13 @@ void hwinit(void) { InitSerial(); } -interrupt(TIMERA0_VECTOR) tmr0irq(void) { +SYS_IRQ_HANDLER(TIMERA0_VECTOR) tmr0irq(void) { - chSysIRQEnterI(); + SYS_IRQ_PROLOGUE(); + + chSysLockI(); chSysTimerHandlerI(); - chSysIRQExitI(); + chSysUnlockI(); + + SYS_IRQ_EPILOGUE(); } -- cgit v1.2.3 From e1b6b9e988d70442e71b520f5a8f43e355688a71 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 9 Jan 2009 14:26:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@596 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/board.c | 11 +++++------ demos/AVR-ATmega128-GCC/board.c | 11 +++++------ 2 files changed, 10 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c index e78360e9a..bd052b9c9 100644 --- a/demos/AVR-AT90CANx-GCC/board.c +++ b/demos/AVR-AT90CANx-GCC/board.c @@ -19,19 +19,18 @@ #include -#include -#include - #include "board.h" #include "avr_serial.h" -ISR(TIMER0_COMP_vect) { +SYS_IRQ_HANDLER(TIMER0_COMP_vect) { - chSysIRQEnterI(); + SYS_IRQ_PROLOGUE(); + chSysLockI(); chSysTimerHandlerI(); + chSysUnlockI(); - chSysIRQExitI(); + SYS_IRQ_EPILOGUE(); } /* diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index 03907d391..96c810b17 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -19,19 +19,18 @@ #include -#include -#include - #include "board.h" #include "avr_serial.h" -ISR(TIMER0_COMP_vect) { +SYS_IRQ_HANDLER(TIMER0_COMP_vect) { - chSysIRQEnterI(); + SYS_IRQ_PROLOGUE(); + chSysLockI(); chSysTimerHandlerI(); + chSysUnlockI(); - chSysIRQExitI(); + SYS_IRQ_EPILOGUE(); } /* -- cgit v1.2.3 From b73680a97d5c312cb6175614be7d562a52a3812c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 9 Jan 2009 16:18:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@597 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.c | 125 ++++++++++++++++++---------------------- demos/Win32-MinGW/chcore.h | 141 ++++++++++++++++++++++++++++++++++++--------- 2 files changed, 168 insertions(+), 98 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 9e9aba3fd..1d1a134b7 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -17,91 +17,76 @@ along with this program. If not, see . */ -/* - * Core file for MingGW32 demo project. +/** + * @addtogroup WIN32SIM_CORE + * @{ */ -#include -#include - -#undef CDECL - #include -static LARGE_INTEGER nextcnt; -static LARGE_INTEGER slice; - -void InitSimCom1(void); -void InitSimCom2(void); -BOOL Com1ConnInterruptSimCom(void); -BOOL Com2ConnInterruptSimCom(void); -BOOL Com1InInterruptSimCom(void); -BOOL Com2InInterruptSimCom(void); -BOOL Com1OutInterruptSimCom(void); -BOOL Com2OutInterruptSimCom(void); - /* - * Simulated HW initialization. + * This file is a template of the system driver functions provided by a port. + * Some of the following functions may be implemented as macros in chcore.h if + * the implementer decides that there is an advantage in doing so, as example + * because performance concerns. */ -void InitCore(void) { - WSADATA wsaData; - - // Initialization. - if (WSAStartup(2, &wsaData) != 0) { - printf("Unable to locate a winsock DLL\n"); - exit(1); - } - printf("Win32 ChibiOS/RT simulator\n\n"); - printf("Thread structure %d bytes\n", sizeof(Thread)); - if (!QueryPerformanceFrequency(&slice)) { - printf("QueryPerformanceFrequency() error"); - exit(1); - } - printf("Core Frequency %u Hz\n", (int)slice.LowPart); - slice.QuadPart /= CH_FREQUENCY; - QueryPerformanceCounter(&nextcnt); - nextcnt.QuadPart += slice.QuadPart; - - InitSimCom1(); - InitSimCom2(); - fflush(stdout); +/** + * Prints a message on the system console. + * @param msg pointer to the message + * @note The function is declared as a weak symbol, it is possible to redefine + * it in your application code. + */ +__attribute__((weak)) +void sys_puts(char *msg) { } -/* - * Interrupt simulation. +/** + * Performs a context switch between two threads. + * @param otp the thread to be switched out + * @param ntp the thread to be switched in + * @note The function is declared as a weak symbol, it is possible to redefine + * it in your application code. */ -void ChkIntSources(void) { - LARGE_INTEGER n; +__attribute__((naked, weak)) +void sys_switch(Thread *otp, Thread *ntp) { + register struct intctx *esp asm("esp"); + + asm volatile ("push %ebp \n\t" \ + "push %esi \n\t" \ + "push %edi \n\t" \ + "push %ebx"); + otp->p_ctx.esp = esp; + esp = ntp->p_ctx.esp; + asm volatile ("pop %ebx \n\t" \ + "pop %edi \n\t" \ + "pop %esi \n\t" \ + "pop %ebp \n\t" \ + "ret" : : "r" (esp)); +} - if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || - Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || - Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { - if (chSchRescRequiredI()) - chSchDoRescheduleI(); - return; - } +/** + * Halts the system. In this implementation it just exits the simulation. + * @note The function is declared as a weak symbol, it is possible to redefine + * it in your application code. + */ +__attribute__((weak)) +void sys_halt(void) { - // Interrupt Timer simulation (10ms interval). - QueryPerformanceCounter(&n); - if (n.QuadPart > nextcnt.QuadPart) { - nextcnt.QuadPart += slice.QuadPart; - chSysTimerHandlerI(); - if (chSchRescRequiredI()) - chSchDoRescheduleI(); - } + exit(2); } -msg_t _idle(void *p) { - - while (TRUE) { +/** + * Threads return point, it just invokes @p chThdExit(). + * @note The function is declared as a weak symbol, it is possible to redefine + * it in your application code. + */ +__attribute__((naked, weak)) +void threadexit(void) { - ChkIntSources(); - Sleep(0); - } + asm volatile ("push %eax \n\t" \ + "call _chThdExit"); } -__attribute__((fastcall)) void chSysHalt(void) { - - exit(2); } +/** @} */ diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index d1f209a68..6c9bf1f7e 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -17,27 +17,40 @@ along with this program. If not, see . */ -/* - * Core file for MingGW32 demo project. +/** + * @addtogroup WIN32SIM_CORE + * @{ */ #ifndef _CHCORE_H_ #define _CHCORE_H_ -/* - * Unique macro for the implemented architecture. +/** + * Macro defining the a simulated architecture into Win32. */ #define CH_ARCHITECTURE_WIN32SIM -/* - * Base type for stack alignment. +/** + * 32 bit stack alignment. */ typedef uint32_t stkalign_t; +/** + * Generic x86 register. + */ typedef void *regx86; -/* - * Stack saved context. +/** + * Interrupt saved context. + * This structure represents the stack frame saved during a preemption-capable + * interrupt handler. + */ +struct extctx { +}; + +/** + * System saved context. + * @note In this demo the floating point registers are not saved. */ struct intctx { regx86 ebx; @@ -47,17 +60,26 @@ struct intctx { regx86 eip; }; +/** + * Platform dependent part of the @p Thread structure. + * This structure usually contains just the saved stack pointer defined as a + * pointer to a @p intctx structure. + */ typedef struct { struct intctx *esp; } Context; #define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ +/** + * Platform dependent part of the @p chThdInit() API. + * This code usually setup the context switching frame represented by a + * @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ uint8_t *esp = (uint8_t *)workspace + wsize; \ APUSH(esp, arg); \ - APUSH(esp, threadstart); \ + APUSH(esp, threadexit); \ esp -= sizeof(struct intctx); \ ((struct intctx *)esp)->eip = pf; \ ((struct intctx *)esp)->ebx = 0; \ @@ -67,33 +89,96 @@ typedef struct { tp->p_ctx.esp = (struct intctx *)esp; \ } -#define chSysLock() -#define chSysUnlock() -#define chSysEnable() -#define chSysPuts(msg) {} -#define chSysIRQEnterI() -#define chSysIRQExitI() - -#define INT_REQUIRED_STACK 0 +/** + * Stack size for the system idle thread. + */ +#ifndef IDLE_THREAD_STACK_SIZE +#define IDLE_THREAD_STACK_SIZE 256 +#endif + +/** + * Per-thread stack overhead for interrupts servicing, it is used in the + * calculation of the correct working area size. + * It requires stack space because the simulated "interrupt handlers" invoke + * Win32 APIs inside so it better have a lot of space. + */ +#ifndef INT_REQUIRED_STACK +#define INT_REQUIRED_STACK 16384 +#endif +/** + * Enforces a correct alignment for a stack area size value. + */ #define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1) + /** + * Computes the thread working area global size. + */ #define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ sizeof(void *) * 2 + \ sizeof(struct intctx) + \ - (n) + \ - INT_REQUIRED_STACK) + sizeof(struct extctx) + \ + (n) + (INT_REQUIRED_STACK)) +/** + * Macro used to allocate a thread working area aligned as both position and + * size. + */ #define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; -/* - * Stack size for the system idle thread. +/** + * IRQ prologue code, inserted at the start of all IRQ handlers enabled to + * invoke system APIs. + */ +#define SYS_IRQ_PROLOGUE() + +/** + * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to + * invoke system APIs. + */ +#define SYS_IRQ_EPILOGUE() + +/** + * Does nothing in this simulator. + */ +#define sys_disable() + +/** + * Does nothing in this simulator. + */ +#define sys_enable() + +/** + * Does nothing in this simulator. + */ +#define sys_disable_from_isr() + +/** + * Does nothing in this simulator. + */ +#define sys_enable_from_isr() + +/** + * Does nothing in this simulator. */ -#define IDLE_THREAD_STACK_SIZE 16384 +#define sys_wait_for_interrupt() -msg_t _idle(void *p); -__attribute__((fastcall)) void chSysHalt(void); -__attribute__((fastcall)) void chSysSwitchI(Thread *otp, Thread *ntp); -__attribute__((fastcall)) void threadstart(void); +/** + * IRQ handler function modifier. + */ +#define SYS_IRQ_HANDLER + +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((fastcall)) void sys_puts(char *msg); + __attribute__((fastcall)) void sys_switch(Thread *otp, Thread *ntp); + __attribute__((fastcall)) void sys_halt(void); + void threadexit(void); +#ifdef __cplusplus +} +#endif #endif /* _CHCORE_H_ */ + +/** @} */ -- cgit v1.2.3 From 49fe48fd7a816f46eb50a52342d14173ffbd0c1e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 10 Jan 2009 09:35:58 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@601 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 2 +- demos/Win32-MinGW/chcore.c | 91 +++++++++++++++++++++++++++++++++++---------- demos/Win32-MinGW/chcore.h | 2 +- demos/Win32-MinGW/chcore2.s | 43 --------------------- 4 files changed, 73 insertions(+), 65 deletions(-) delete mode 100644 demos/Win32-MinGW/chcore2.s (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 46cb9cad0..bda1426cb 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -65,7 +65,7 @@ SRC = chcore.c main.c ../../ports/win32/simcom.c \ ${TESTSRC} # List ASM source files here -ASRC = chcore2.s +ASRC = # List all user directories here UINCDIR = ../../src/include diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 1d1a134b7..1dc05569c 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -17,6 +17,11 @@ along with this program. If not, see . */ +#include +#include + +#undef CDECL + /** * @addtogroup WIN32SIM_CORE * @{ @@ -24,20 +29,75 @@ #include +static LARGE_INTEGER nextcnt; +static LARGE_INTEGER slice; + +void InitSimCom1(void); +void InitSimCom2(void); +BOOL Com1ConnInterruptSimCom(void); +BOOL Com2ConnInterruptSimCom(void); +BOOL Com1InInterruptSimCom(void); +BOOL Com2InInterruptSimCom(void); +BOOL Com1OutInterruptSimCom(void); +BOOL Com2OutInterruptSimCom(void); + /* - * This file is a template of the system driver functions provided by a port. - * Some of the following functions may be implemented as macros in chcore.h if - * the implementer decides that there is an advantage in doing so, as example - * because performance concerns. + * Simulated HW initialization. */ +void InitCore(void) { + WSADATA wsaData; + + // Initialization. + if (WSAStartup(2, &wsaData) != 0) { + printf("Unable to locate a winsock DLL\n"); + exit(1); + } + + printf("Win32 ChibiOS/RT simulator\n\n"); + printf("Thread structure %d bytes\n", sizeof(Thread)); + if (!QueryPerformanceFrequency(&slice)) { + printf("QueryPerformanceFrequency() error"); + exit(1); + } + printf("Core Frequency %u Hz\n", (int)slice.LowPart); + slice.QuadPart /= CH_FREQUENCY; + QueryPerformanceCounter(&nextcnt); + nextcnt.QuadPart += slice.QuadPart; + + InitSimCom1(); + InitSimCom2(); + fflush(stdout); +} + +/* + * Interrupt simulation. + */ +void ChkIntSources(void) { + LARGE_INTEGER n; + + if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || + Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || + Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { + if (chSchRescRequiredI()) + chSchDoRescheduleI(); + return; + } + + // Interrupt Timer simulation (10ms interval). + QueryPerformanceCounter(&n); + if (n.QuadPart > nextcnt.QuadPart) { + nextcnt.QuadPart += slice.QuadPart; + chSysTimerHandlerI(); + if (chSchRescRequiredI()) + chSchDoRescheduleI(); + } +} /** * Prints a message on the system console. * @param msg pointer to the message - * @note The function is declared as a weak symbol, it is possible to redefine - * it in your application code. */ -__attribute__((weak)) +__attribute__((fastcall)) void sys_puts(char *msg) { } @@ -45,12 +105,10 @@ void sys_puts(char *msg) { * Performs a context switch between two threads. * @param otp the thread to be switched out * @param ntp the thread to be switched in - * @note The function is declared as a weak symbol, it is possible to redefine - * it in your application code. */ -__attribute__((naked, weak)) +__attribute__((fastcall)) void sys_switch(Thread *otp, Thread *ntp) { - register struct intctx *esp asm("esp"); + register struct intctx volatile *esp asm("esp"); asm volatile ("push %ebp \n\t" \ "push %esi \n\t" \ @@ -61,16 +119,13 @@ void sys_switch(Thread *otp, Thread *ntp) { asm volatile ("pop %ebx \n\t" \ "pop %edi \n\t" \ "pop %esi \n\t" \ - "pop %ebp \n\t" \ - "ret" : : "r" (esp)); + "pop %ebp"); } /** * Halts the system. In this implementation it just exits the simulation. - * @note The function is declared as a weak symbol, it is possible to redefine - * it in your application code. */ -__attribute__((weak)) +__attribute__((fastcall)) void sys_halt(void) { exit(2); @@ -78,15 +133,11 @@ void sys_halt(void) { /** * Threads return point, it just invokes @p chThdExit(). - * @note The function is declared as a weak symbol, it is possible to redefine - * it in your application code. */ -__attribute__((naked, weak)) void threadexit(void) { asm volatile ("push %eax \n\t" \ "call _chThdExit"); } -} /** @} */ diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 6c9bf1f7e..2a9fe7de8 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -66,7 +66,7 @@ struct intctx { * pointer to a @p intctx structure. */ typedef struct { - struct intctx *esp; + struct intctx volatile *esp; } Context; #define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) diff --git a/demos/Win32-MinGW/chcore2.s b/demos/Win32-MinGW/chcore2.s deleted file mode 100644 index 9334fbfdc..000000000 --- a/demos/Win32-MinGW/chcore2.s +++ /dev/null @@ -1,43 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -.text - -.p2align 4,,15 -.globl @chSysSwitchI@8 -@chSysSwitchI@8: - # Switch out - push %ebp - push %esi - push %edi - push %ebx - movl %esp,16(%ecx) - # Switch in - movl 16(%edx),%esp - pop %ebx - pop %edi - pop %esi - pop %ebp - ret - -.p2align 4,,15 -.globl @threadstart@0 -@threadstart@0: - push %eax - call _chThdExit -- cgit v1.2.3 From 791d101af5ce38335694b882149449c83f650fda Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 10 Jan 2009 09:42:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@602 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chconf.h | 2 +- demos/Win32-MinGW/chcore.h | 7 +++++-- demos/Win32-MinGW/main.c | 1 - 3 files changed, 6 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 5b487dbe7..c00b4873f 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -120,7 +120,7 @@ * provide the \p __heap_base__ and \p __heap_end__ symbols. * @note requires \p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 16384 +#define CH_HEAP_SIZE 0x20000 /** Configuration option: enforces the use of the C-runtime \p malloc() and * \p free() functions as backend for the system heap allocator.*/ diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 2a9fe7de8..5f9f35716 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -159,9 +159,10 @@ typedef struct { #define sys_enable_from_isr() /** - * Does nothing in this simulator. + * In the simulator this does a polling pass on the simulated interrupt + * sources. */ -#define sys_wait_for_interrupt() +#define sys_wait_for_interrupt() ChkIntSources() /** * IRQ handler function modifier. @@ -174,6 +175,8 @@ extern "C" { __attribute__((fastcall)) void sys_puts(char *msg); __attribute__((fastcall)) void sys_switch(Thread *otp, Thread *ntp); __attribute__((fastcall)) void sys_halt(void); + void InitCore(void); + void ChkIntSources(void); void threadexit(void); #ifdef __cplusplus } diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 5de6ee938..eaf2504dd 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -34,7 +34,6 @@ static msg_t ConsoleThread(void *arg); msg_t TestThread(void *p); -void InitCore(void); extern FullDuplexDriver COM1, COM2; #define cprint(msg) chMsgSend(cdtp, (msg_t)msg) -- cgit v1.2.3 From ea60d55415892ca1a98c735d95c310637b835bf3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 10 Jan 2009 14:56:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@606 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 2bdf1959f..5a2d70c8f 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -84,7 +84,7 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here -- cgit v1.2.3 From e2b6b440e12562804f161d8db677554bbd666bd1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 10 Jan 2009 16:21:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@612 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 2 +- demos/ARM7-AT91SAM7X-GCC/board.c | 16 ++++++++-------- demos/ARM7-AT91SAM7X-GCC/chconf.h | 9 +++++++++ demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 16 ++++++++-------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 9 +++++++++ demos/ARM7-LPC214x-G++/Makefile | 2 +- demos/ARM7-LPC214x-G++/Makefile.thumb | 2 +- demos/ARM7-LPC214x-G++/board.c | 14 ++++++-------- demos/ARM7-LPC214x-G++/chconf.h | 9 +++++++++ demos/ARM7-LPC214x-GCC-minimal/Makefile | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC-minimal/board.c | 14 ++++++-------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 9 +++++++++ demos/ARM7-LPC214x-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/board.c | 14 ++++++-------- demos/ARM7-LPC214x-GCC/chconf.h | 9 +++++++++ demos/AVR-AT90CANx-GCC/board.c | 6 +++--- demos/AVR-ATmega128-GCC/board.c | 6 +++--- demos/AVR-ATmega128-GCC/chconf.h | 9 +++++++++ demos/MSP430-MSP430x1611-GCC/board.c | 6 +++--- demos/MSP430-MSP430x1611-GCC/chconf.h | 9 +++++++++ demos/Win32-MinGW/chconf.h | 9 +++++++++ 25 files changed, 124 insertions(+), 58 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index dbdca2c31..7d22aa586 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -83,7 +83,7 @@ ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 3013eeb95..922113f45 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -83,7 +83,7 @@ TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 8a4b7c4ea..2329b0080 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -26,31 +26,31 @@ extern void FiqHandler(void); -__attribute__((naked)) -static void SpuriousHandler(void) { +CH_IRQ_HANDLER static void SpuriousHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); AT91C_BASE_AIC->AIC_EOICR = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* * SYS IRQ handling here. */ -__attribute__((naked)) -static void SYSIrqHandler(void) { +CH_IRQ_HANDLER static void SYSIrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; + chSysLockI(); chSysTimerHandlerI(); + chSysUnlockI(); } AT91C_BASE_AIC->AIC_EOICR = 0; \ - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index f8302116d..c1b6d8c5a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index b7b859220..44bb4469a 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -95,7 +95,7 @@ ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb index 2ef54fb5d..f2f9a851c 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -96,7 +96,7 @@ TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 0d2fd0996..87bc438ea 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -27,31 +27,31 @@ extern void FiqHandler(void); -__attribute__((naked)) -static void SpuriousHandler(void) { +CH_IRQ_HANDLER static void SpuriousHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); AT91C_BASE_AIC->AIC_EOICR = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* * SYS IRQ handling here. */ -__attribute__((naked)) -static void SYSIrqHandler(void) { +CH_IRQ_HANDLER static void SYSIrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; + chSysLockI(); chSysTimerHandlerI(); + chSysUnlockI(); } AT91C_BASE_AIC->AIC_EOICR = 0; \ - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index ed950dd3f..cc2870abd 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 9bd08a8ee..bb2c22929 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -93,7 +93,7 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 177e7cda0..8d3ec2c0c 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -93,7 +93,7 @@ TCSRC = ../../ports/ARM7-LPC214x/chcore.c \ TCPPSRC = ../../src/lib/ch.cpp main.cpp # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index 8b17399e0..fef4deb36 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -31,30 +31,28 @@ /* * Non-vectored IRQs handling here. */ -__attribute__((naked)) -static void IrqHandler(void) { +CH_IRQ_HANDLER static void IrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); /* nothing */ VICVectAddr = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* * Timer 0 IRQ handling here. */ -__attribute__((naked)) -static void T0IrqHandler(void) { +CH_IRQ_HANDLER static void T0IrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); VICVectAddr = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 2d0a1513f..73323e4cf 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 6450cad6b..a3ab18333 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -80,7 +80,7 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index f4fe4c25b..2f4463583 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -80,7 +80,7 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index 3b3bd848e..e10297562 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -31,30 +31,28 @@ /* * Non-vectored IRQs handling here. */ -__attribute__((naked)) -static void IrqHandler(void) { +CH_IRQ_HANDLER static void IrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); /* nothing */ VICVectAddr = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* * Timer 0 IRQ handling here. */ -__attribute__((naked)) -static void T0IrqHandler(void) { +CH_IRQ_HANDLER static void T0IrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); VICVectAddr = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 94ff64676..876afc52a 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ //#define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index a676a4af1..211107deb 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -84,7 +84,7 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ board.c buzzer.c mmcsd.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 9f453100c..767fb9123 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -31,30 +31,28 @@ /* * Non-vectored IRQs handling here. */ -__attribute__((naked)) -static void IrqHandler(void) { +CH_IRQ_HANDLER static void IrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); /* nothing */ VICVectAddr = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* * Timer 0 IRQ handling here. */ -__attribute__((naked)) -static void T0IrqHandler(void) { +CH_IRQ_HANDLER static void T0IrqHandler(void) { - chSysIRQEnterI(); + CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ chSysTimerHandlerI(); VICVectAddr = 0; - chSysIRQExitI(); + CH_IRQ_EPILOGUE(); } /* diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index ed950dd3f..cc2870abd 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c index bd052b9c9..cf97132cf 100644 --- a/demos/AVR-AT90CANx-GCC/board.c +++ b/demos/AVR-AT90CANx-GCC/board.c @@ -22,15 +22,15 @@ #include "board.h" #include "avr_serial.h" -SYS_IRQ_HANDLER(TIMER0_COMP_vect) { +CH_IRQ_HANDLER(TIMER0_COMP_vect) { - SYS_IRQ_PROLOGUE(); + CH_IRQ_PROLOGUE(); chSysLockI(); chSysTimerHandlerI(); chSysUnlockI(); - SYS_IRQ_EPILOGUE(); + CH_IRQ_EPILOGUE(); } /* diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index 96c810b17..0e40c20f4 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -22,15 +22,15 @@ #include "board.h" #include "avr_serial.h" -SYS_IRQ_HANDLER(TIMER0_COMP_vect) { +CH_IRQ_HANDLER(TIMER0_COMP_vect) { - SYS_IRQ_PROLOGUE(); + CH_IRQ_PROLOGUE(); chSysLockI(); chSysTimerHandlerI(); chSysUnlockI(); - SYS_IRQ_EPILOGUE(); + CH_IRQ_EPILOGUE(); } /* diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index ea028aed6..4e9abec89 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index f5e5e4012..51a50afb0 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -85,13 +85,13 @@ void hwinit(void) { InitSerial(); } -SYS_IRQ_HANDLER(TIMERA0_VECTOR) tmr0irq(void) { +CH_IRQ_HANDLER(TIMERA0_VECTOR) tmr0irq(void) { - SYS_IRQ_PROLOGUE(); + CH_IRQ_PROLOGUE(); chSysLockI(); chSysTimerHandlerI(); chSysUnlockI(); - SYS_IRQ_EPILOGUE(); + CH_IRQ_EPILOGUE(); } diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index bf7a9afad..10be65000 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -35,6 +35,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index c00b4873f..07d741e99 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -30,6 +30,15 @@ * that this is not related to the compiler optimization options.*/ #define CH_OPTIMIZE_SPEED +/** Configuration option: If enabled then the used of nested @p chSysLock() / + * @p chSysUnlock() operations is allowed.
+ * For performance and code size reasons the recommended setting is leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + */ +//#define CH_USE_NESTED_LOCKS + /** Configuration option: if specified then the kernel performs the round * robin scheduling algorithm on threads of equal priority. */ #define CH_USE_ROUNDROBIN -- cgit v1.2.3 From 8b17d5526d2745c409aac95a3e1da3102959626c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 10 Jan 2009 16:25:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@613 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 5f9f35716..70efa7edb 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -138,6 +138,11 @@ typedef struct { */ #define SYS_IRQ_EPILOGUE() +/** + * IRQ handler function modifier. + */ +#define SYS_IRQ_HANDLER + /** * Does nothing in this simulator. */ @@ -159,15 +164,15 @@ typedef struct { #define sys_enable_from_isr() /** - * In the simulator this does a polling pass on the simulated interrupt - * sources. + * Does nothing in this simulator. */ -#define sys_wait_for_interrupt() ChkIntSources() +#define sys_disable_all() /** - * IRQ handler function modifier. + * In the simulator this does a polling pass on the simulated interrupt + * sources. */ -#define SYS_IRQ_HANDLER +#define sys_wait_for_interrupt() ChkIntSources() #ifdef __cplusplus extern "C" { -- cgit v1.2.3 From a9b4e8fc7225e8e2f26554b388f9d069d8f05b5e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Jan 2009 15:41:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@621 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.h | 21 ++++++++++++++++++--- demos/Win32-MinGW/main.c | 2 -- 2 files changed, 18 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 70efa7edb..40555df63 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -143,6 +143,16 @@ typedef struct { */ #define SYS_IRQ_HANDLER +/** + * Simulator initialization. + */ +#define sys_init() InitCore() + +/** + * Does nothing in this simulator. + */ +#define sys_disable_all() + /** * Does nothing in this simulator. */ @@ -156,17 +166,22 @@ typedef struct { /** * Does nothing in this simulator. */ -#define sys_disable_from_isr() +#define sys_lock() /** * Does nothing in this simulator. */ -#define sys_enable_from_isr() +#define sys_unlock() /** * Does nothing in this simulator. */ -#define sys_disable_all() +#define sys_lock_from_isr() + +/** + * Does nothing in this simulator. + */ +#define sys_unlock_from_isr() /** * In the simulator this does a polling pass on the simulated interrupt diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index eaf2504dd..a72d7b4da 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -279,8 +279,6 @@ static evhandler_t fhandlers[2] = { int main(void) { EventListener c1fel, c2fel; - InitCore(); - // Startup ChibiOS/RT. chSysInit(); -- cgit v1.2.3 From 31c706bccb2eb65cbb97bf6952130d8e5d94dada Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Jan 2009 18:22:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@626 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-G++/Makefile | 2 +- demos/ARM7-LPC214x-G++/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/Makefile.thumb | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 7d22aa586..effdd4aba 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -83,7 +83,7 @@ ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index 922113f45..d0e92d4b8 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -83,7 +83,7 @@ TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 44bb4469a..3470b25cf 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -95,7 +95,7 @@ ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb index f2f9a851c..76d73e592 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -96,7 +96,7 @@ TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-AT91SAM7X/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index bb2c22929..931d5e3bf 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -93,7 +93,7 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 8d3ec2c0c..65c432409 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -93,7 +93,7 @@ TCSRC = ../../ports/ARM7-LPC214x/chcore.c \ TCPPSRC = ../../src/lib/ch.cpp main.cpp # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index a3ab18333..fc0edbfea 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -80,7 +80,7 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 2f4463583..6fa067182 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -80,7 +80,7 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ board.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 5a2d70c8f..1eb4d602f 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -84,7 +84,7 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \ TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 211107deb..769c6a174 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -84,7 +84,7 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \ board.c buzzer.c mmcsd.c main.c # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsysasm.s \ +ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ ../../ports/ARM7-LPC214x/vectors.s # List all user directories here -- cgit v1.2.3 From dec8eecc8eaa46edad5b380c1d26c28c576c276b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Jan 2009 09:12:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@630 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 1eb4d602f..478e9a287 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -69,7 +69,7 @@ include ../../src/kernel.mk include ../../test/test.mk # List ARM-mode C source files here -ASRC = ../../ports/ARM7-LPC214x/chcore.c \ +ASRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ -- cgit v1.2.3 From db629a04618090b3f45c12d9563adf5215a31969 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Jan 2009 09:16:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@631 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC/Makefile.thumb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index effdd4aba..65219c2da 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -69,7 +69,7 @@ include ../../src/kernel.mk include ../../test/test.mk # List ARM-mode C source files here -ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ +ASRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ${KERNSRC} \ ${TESTSRC} \ diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb index d0e92d4b8..6d06e82a7 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb @@ -74,7 +74,7 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ +TSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ${KERNSRC} \ ${TESTSRC} \ diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb index 769c6a174..aa3046c20 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC/Makefile.thumb @@ -74,7 +74,7 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-LPC214x/chcore.c \ +TSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ -- cgit v1.2.3 From ed534c135cf6013575fa691db0f48a0b7388a164 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Jan 2009 09:20:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@632 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 2 +- demos/ARM7-LPC214x-G++/Makefile | 2 +- demos/ARM7-LPC214x-G++/Makefile.thumb | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 3470b25cf..74146d985 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -78,7 +78,7 @@ USRC = ../../ext/uip-1.0/uip/uip_arp.c \ ../../ext/uip-1.0/apps/webserver/httpd-cgi.c # List ARM-mode C source files here -ASRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ +ASRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ${KERNSRC} \ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb index 76d73e592..e476abc6b 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb @@ -84,7 +84,7 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-AT91SAM7X/chcore.c \ +TSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ${KERNSRC} \ diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 931d5e3bf..56506f8f5 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -75,7 +75,7 @@ include ../../src/kernel.mk include ../../test/test.mk # List ARM-mode C source files here -ACSRC = ../../ports/ARM7-LPC214x/chcore.c \ +ACSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ${KERNSRC} \ diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb index 65c432409..6a5bdbaf2 100644 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ b/demos/ARM7-LPC214x-G++/Makefile.thumb @@ -81,7 +81,7 @@ ACSRC = ACPPSRC = # List THUMB-mode C sources here -TCSRC = ../../ports/ARM7-LPC214x/chcore.c \ +TCSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ${KERNSRC} \ diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index fc0edbfea..c584b1d69 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -69,7 +69,7 @@ include ../../src/kernel.mk include ../../test/test.mk # List ARM-mode C source files here -ASRC = ../../ports/ARM7-LPC214x/chcore.c \ +ASRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ${KERNSRC} \ board.c main.c diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb index 6fa067182..876298a3d 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb @@ -74,7 +74,7 @@ ASRC = # List THUMB-mode C sources here # NOTE: If any module is compiled in thumb mode then -mthumb-interwork is # enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7-LPC214x/chcore.c \ +TSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ ${KERNSRC} \ board.c main.c -- cgit v1.2.3 From 48d08ca9476ca38ba936ec7ff5ae3b79d8b02bd2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Jan 2009 13:44:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@634 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 7bfa42133..6a13c126b 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -90,12 +90,13 @@ void hwinit1(void) { * NVIC/SCB initialization. */ SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4). - SCB_SHPR(2) = 0xF0 << 16; // PendSV at lowest priority. + NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL); + NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK); + NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV); /* * SysTick initialization. */ - SCB_SHPR(2) |= 0x40 << 24; // SysTick at priority 4:0. ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; ST_CVR = 0; ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; @@ -103,7 +104,7 @@ void hwinit1(void) { /* * Other subsystems initialization. */ - InitSerial(0x80, 0x80, 0x80); + InitSerial(0xC0, 0xC0, 0xC0); /* * ChibiOS/RT initialization. -- cgit v1.2.3 From bd996b1663e9a10aad21ec395eab944a98f3a905 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Jan 2009 19:50:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@646 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 6 +++--- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 6 +++--- demos/ARM7-LPC214x-G++/board.c | 12 +++++++----- demos/ARM7-LPC214x-GCC-minimal/board.c | 12 +++++++----- demos/ARM7-LPC214x-GCC/board.c | 12 +++++++----- 5 files changed, 27 insertions(+), 21 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 2329b0080..754b0b366 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -26,7 +26,7 @@ extern void FiqHandler(void); -CH_IRQ_HANDLER static void SpuriousHandler(void) { +static CH_IRQ_HANDLER(SpuriousHandler) { CH_IRQ_PROLOGUE(); @@ -38,7 +38,7 @@ CH_IRQ_HANDLER static void SpuriousHandler(void) { /* * SYS IRQ handling here. */ -CH_IRQ_HANDLER static void SYSIrqHandler(void) { +static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_PROLOGUE(); @@ -48,7 +48,7 @@ CH_IRQ_HANDLER static void SYSIrqHandler(void) { chSysTimerHandlerI(); chSysUnlockI(); } - AT91C_BASE_AIC->AIC_EOICR = 0; \ + AT91C_BASE_AIC->AIC_EOICR = 0; CH_IRQ_EPILOGUE(); } diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 87bc438ea..38c91d9fa 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -27,7 +27,7 @@ extern void FiqHandler(void); -CH_IRQ_HANDLER static void SpuriousHandler(void) { +static CH_IRQ_HANDLER(SpuriousHandler) { CH_IRQ_PROLOGUE(); @@ -39,7 +39,7 @@ CH_IRQ_HANDLER static void SpuriousHandler(void) { /* * SYS IRQ handling here. */ -CH_IRQ_HANDLER static void SYSIrqHandler(void) { +static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_PROLOGUE(); @@ -49,7 +49,7 @@ CH_IRQ_HANDLER static void SYSIrqHandler(void) { chSysTimerHandlerI(); chSysUnlockI(); } - AT91C_BASE_AIC->AIC_EOICR = 0; \ + AT91C_BASE_AIC->AIC_EOICR = 0; CH_IRQ_EPILOGUE(); } diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index fef4deb36..f6792851a 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -31,27 +31,29 @@ /* * Non-vectored IRQs handling here. */ -CH_IRQ_HANDLER static void IrqHandler(void) { +static CH_IRQ_HANDLER(IrqHandler) { CH_IRQ_PROLOGUE(); /* nothing */ - VICVectAddr = 0; + VICVectAddr = 0; CH_IRQ_EPILOGUE(); } /* * Timer 0 IRQ handling here. */ -CH_IRQ_HANDLER static void T0IrqHandler(void) { +static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); - T0IR = 1; /* Clear interrupt on match MR0. */ + + chSysLockI(); chSysTimerHandlerI(); - VICVectAddr = 0; + chSysUnlockI(); + VICVectAddr = 0; CH_IRQ_EPILOGUE(); } diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index e10297562..4ccb5e78c 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -31,27 +31,29 @@ /* * Non-vectored IRQs handling here. */ -CH_IRQ_HANDLER static void IrqHandler(void) { +static CH_IRQ_HANDLER(IrqHandler) { CH_IRQ_PROLOGUE(); /* nothing */ - VICVectAddr = 0; + VICVectAddr = 0; CH_IRQ_EPILOGUE(); } /* * Timer 0 IRQ handling here. */ -CH_IRQ_HANDLER static void T0IrqHandler(void) { +static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); - T0IR = 1; /* Clear interrupt on match MR0. */ + + chSysLockI(); chSysTimerHandlerI(); - VICVectAddr = 0; + chSysUnlockI(); + VICVectAddr = 0; CH_IRQ_EPILOGUE(); } diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 767fb9123..3de7f82ba 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -31,27 +31,29 @@ /* * Non-vectored IRQs handling here. */ -CH_IRQ_HANDLER static void IrqHandler(void) { +static CH_IRQ_HANDLER(IrqHandler) { CH_IRQ_PROLOGUE(); /* nothing */ - VICVectAddr = 0; + VICVectAddr = 0; CH_IRQ_EPILOGUE(); } /* * Timer 0 IRQ handling here. */ -CH_IRQ_HANDLER static void T0IrqHandler(void) { +static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); - T0IR = 1; /* Clear interrupt on match MR0. */ + + chSysLockI(); chSysTimerHandlerI(); - VICVectAddr = 0; + chSysUnlockI(); + VICVectAddr = 0; CH_IRQ_EPILOGUE(); } -- cgit v1.2.3 From b1d77bf4bc7fb6e89b5280d99f401caa50c8a0d8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Jan 2009 20:56:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@648 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 51a50afb0..c10e73172 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -85,7 +85,7 @@ void hwinit(void) { InitSerial(); } -CH_IRQ_HANDLER(TIMERA0_VECTOR) tmr0irq(void) { +CH_IRQ_HANDLER(TIMERA0_VECTOR) { CH_IRQ_PROLOGUE(); -- cgit v1.2.3 From 4d2e568b56607bb166c4d2dd004b1c9970c2879f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Jan 2009 20:11:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@650 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 2 +- demos/Win32-MinGW/chcore.c | 6 +++--- demos/Win32-MinGW/chcore.h | 36 ++++++++++++++++++------------------ 3 files changed, 22 insertions(+), 22 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index bda1426cb..841557827 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -77,7 +77,7 @@ ULIBDIR = ULIBS = # Define optimisation level here -OPT = -ggdb -Os -fomit-frame-pointer +OPT = -ggdb -O2 -fomit-frame-pointer # # End of user defines diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 1dc05569c..446508e3c 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -98,7 +98,7 @@ void ChkIntSources(void) { * @param msg pointer to the message */ __attribute__((fastcall)) -void sys_puts(char *msg) { +void port_puts(char *msg) { } /** @@ -107,7 +107,7 @@ void sys_puts(char *msg) { * @param ntp the thread to be switched in */ __attribute__((fastcall)) -void sys_switch(Thread *otp, Thread *ntp) { +void port_switch(Thread *otp, Thread *ntp) { register struct intctx volatile *esp asm("esp"); asm volatile ("push %ebp \n\t" \ @@ -126,7 +126,7 @@ void sys_switch(Thread *otp, Thread *ntp) { * Halts the system. In this implementation it just exits the simulation. */ __attribute__((fastcall)) -void sys_halt(void) { +void port_halt(void) { exit(2); } diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 40555df63..029de3566 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -65,9 +65,9 @@ struct intctx { * This structure usually contains just the saved stack pointer defined as a * pointer to a @p intctx structure. */ -typedef struct { +struct context { struct intctx volatile *esp; -} Context; +}; #define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) @@ -130,71 +130,71 @@ typedef struct { * IRQ prologue code, inserted at the start of all IRQ handlers enabled to * invoke system APIs. */ -#define SYS_IRQ_PROLOGUE() +#define PORT_IRQ_PROLOGUE() /** * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to * invoke system APIs. */ -#define SYS_IRQ_EPILOGUE() +#define PORT_IRQ_EPILOGUE() /** - * IRQ handler function modifier. + * IRQ handler function declaration. */ -#define SYS_IRQ_HANDLER +#define PORT_IRQ_HANDLER(id) void id(void) /** * Simulator initialization. */ -#define sys_init() InitCore() +#define port_init() InitCore() /** * Does nothing in this simulator. */ -#define sys_disable_all() +#define port_lock() /** * Does nothing in this simulator. */ -#define sys_disable() +#define port_unlock() /** * Does nothing in this simulator. */ -#define sys_enable() +#define port_lock_from_isr() /** * Does nothing in this simulator. */ -#define sys_lock() +#define port_unlock_from_isr() /** * Does nothing in this simulator. */ -#define sys_unlock() +#define port_disable() /** * Does nothing in this simulator. */ -#define sys_lock_from_isr() +#define port_suspend() /** * Does nothing in this simulator. */ -#define sys_unlock_from_isr() +#define port_enable() /** * In the simulator this does a polling pass on the simulated interrupt * sources. */ -#define sys_wait_for_interrupt() ChkIntSources() +#define port_wait_for_interrupt() ChkIntSources() #ifdef __cplusplus extern "C" { #endif - __attribute__((fastcall)) void sys_puts(char *msg); - __attribute__((fastcall)) void sys_switch(Thread *otp, Thread *ntp); - __attribute__((fastcall)) void sys_halt(void); + __attribute__((fastcall)) void port_puts(char *msg); + __attribute__((fastcall)) void port_switch(Thread *otp, Thread *ntp); + __attribute__((fastcall)) void port_halt(void); void InitCore(void); void ChkIntSources(void); void threadexit(void); -- cgit v1.2.3 From 1170025270003c5cbbc84bf07de5c83253318b28 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Jan 2009 20:43:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@651 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index a72d7b4da..ae06ff841 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -127,9 +127,9 @@ static msg_t HelloWorldThread(void *arg) { PrintLineFDD(sd, "Hello World\r\n"); c = chFDDGetTimeout(sd, 333); switch (c) { - case -1: + case Q_TIMEOUT: continue; - case -2: + case Q_RESET: return 1; case 3: PrintLineFDD(sd, "^C\r\n"); -- cgit v1.2.3 From 2debe881379d58a4fa92a984471a02e7f5de07c4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Jan 2009 21:23:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@652 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index ae06ff841..1d80b9d76 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -122,7 +122,7 @@ static msg_t HelloWorldThread(void *arg) { short c; FullDuplexDriver *sd = (FullDuplexDriver *)arg; - for (i = 0; i < 100; i++) { + for (i = 0; i < 10; i++) { PrintLineFDD(sd, "Hello World\r\n"); c = chFDDGetTimeout(sd, 333); -- cgit v1.2.3 From 8fa109243e5d626a941db8e7d6dc30bb64f9bc9f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Jan 2009 17:59:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@675 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 4 ++-- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 4 ++-- demos/ARM7-LPC214x-G++/board.c | 4 ++-- demos/ARM7-LPC214x-GCC-minimal/board.c | 4 ++-- demos/ARM7-LPC214x-GCC/board.c | 4 ++-- demos/AVR-AT90CANx-GCC/board.c | 4 ++-- demos/AVR-ATmega128-GCC/board.c | 4 ++-- demos/MSP430-MSP430x1611-GCC/board.c | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 754b0b366..d0793ef4d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -44,9 +44,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); } AT91C_BASE_AIC->AIC_EOICR = 0; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 38c91d9fa..bf5990b0d 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -45,9 +45,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); } AT91C_BASE_AIC->AIC_EOICR = 0; diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index f6792851a..2bced8d70 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -49,9 +49,9 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); VICVectAddr = 0; CH_IRQ_EPILOGUE(); diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index 4ccb5e78c..b234cb7a1 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -49,9 +49,9 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); VICVectAddr = 0; CH_IRQ_EPILOGUE(); diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 3de7f82ba..8e0bcfb34 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -49,9 +49,9 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); VICVectAddr = 0; CH_IRQ_EPILOGUE(); diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c index cf97132cf..96b6c7e53 100644 --- a/demos/AVR-AT90CANx-GCC/board.c +++ b/demos/AVR-AT90CANx-GCC/board.c @@ -26,9 +26,9 @@ CH_IRQ_HANDLER(TIMER0_COMP_vect) { CH_IRQ_PROLOGUE(); - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); } diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index 0e40c20f4..0a6201eed 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -26,9 +26,9 @@ CH_IRQ_HANDLER(TIMER0_COMP_vect) { CH_IRQ_PROLOGUE(); - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); } diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index c10e73172..866ff8adf 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -89,9 +89,9 @@ CH_IRQ_HANDLER(TIMERA0_VECTOR) { CH_IRQ_PROLOGUE(); - chSysLockI(); + chSysLockFromIsr(); chSysTimerHandlerI(); - chSysUnlockI(); + chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); } -- cgit v1.2.3 From fd3e840247b14247ef8c361ec68e0d99a8f7ec9a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 31 Jan 2009 17:58:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@703 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index a1a0080ef..98a82bc94 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -70,7 +70,7 @@ #define CR_HSION_MASK (0x1 << 0) #define CR_HSIRDY_MASK (0x1 << 1) #define CR_HSITRIM_MASK (0x1F << 3) -#define HSITRIM_RESET_BITS (1 << 3) +#define HSITRIM_RESET_BITS (0x10 << 3) #define CR_HSICAL_MASK (0xFF << 8) #define CR_HSEON_MASK (0x1 << 16) #define CR_HSERDY_MASK (0x1 << 17) -- cgit v1.2.3 From 3b31842a05737a1ff36d53b0141b05e60f1bdc0a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 1 Feb 2009 20:07:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@710 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chtypes.h | 1 - 1 file changed, 1 deletion(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h index 6f8662bd9..354da269e 100644 --- a/demos/Win32-MinGW/chtypes.h +++ b/demos/Win32-MinGW/chtypes.h @@ -32,7 +32,6 @@ typedef int8_t bool_t; typedef uint8_t tmode_t; typedef uint8_t tstate_t; -typedef uint16_t tid_t; typedef uint32_t tprio_t; typedef int32_t msg_t; typedef int32_t eventid_t; -- cgit v1.2.3 From ec4178dd0ff7587b79a8c525aa88d467642ce629 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 2 Feb 2009 12:48:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@712 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 5 +++++ demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 5 +++++ demos/ARM7-LPC214x-G++/chconf.h | 5 +++++ demos/ARM7-LPC214x-GCC-minimal/chconf.h | 5 +++++ demos/ARM7-LPC214x-GCC/chconf.h | 5 +++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 5 +++++ demos/AVR-AT90CANx-GCC/chconf.h | 5 +++++ demos/AVR-ATmega128-GCC/chconf.h | 5 +++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 5 +++++ demos/Win32-MinGW/chconf.h | 5 +++++ 10 files changed, 50 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index c1b6d8c5a..4c42fbfad 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index cc2870abd..ff4a00298 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 73323e4cf..c22e9b542 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 876afc52a..61484aec7 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ //#define CH_USE_SEMSW diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index cc2870abd..ff4a00298 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index cc2870abd..ff4a00298 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 4900dd240..2cf2f8507 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -42,6 +42,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 4e9abec89..2de244954 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 10be65000..0fb97ecb7 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -56,6 +56,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 07d741e99..a10e43b7d 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -51,6 +51,11 @@ * in the kernel.*/ #define CH_USE_SEMAPHORES +/** Configuration option: If enabled then the threads are enqueued on semaphores + * by priority rather than FIFO order. + * @note requires @p CH_USE_SEMAPHORES.*/ +//#define CH_USE_SEMAPHORES_PRIORITY + /** Configuration option: if specified then the Semaphores atomic Signal+Wait * APIs are included in the kernel.*/ #define CH_USE_SEMSW -- cgit v1.2.3 From d0eaffef7c0a4df7451c47153a25def02bc948f9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 5 Feb 2009 19:51:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@720 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 866ff8adf..de9ac6387 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -82,7 +82,7 @@ void hwinit(void) { /* * Other subsystems. */ - InitSerial(); + msp430_serial_init(); } CH_IRQ_HANDLER(TIMERA0_VECTOR) { -- cgit v1.2.3 From 1ddd49eec7be60413d5054937ee1a1c001842769 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 6 Feb 2009 17:40:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@725 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/board.c | 6 +++--- demos/ARM7-LPC214x-GCC-minimal/board.c | 6 +++--- demos/ARM7-LPC214x-GCC/board.c | 6 +++--- demos/ARM7-LPC214x-GCC/mmcsd.c | 4 ++-- demos/ARMCM3-STM32F103-GCC/board.c | 2 +- 5 files changed, 12 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index 2bced8d70..93227e0ed 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -119,7 +119,7 @@ void hwinit1(void) { /* * Interrupt vectors assignment. */ - InitVIC(); + lpc214x_vic_init(); VICDefVectAddr = (IOREG32)IrqHandler; /* @@ -137,8 +137,8 @@ void hwinit1(void) { /* * Other subsystems. */ - InitSerial(1, 2); -// InitSSP(); + lpc2148x_serial_init(1, 2); +// lpc214x_ssp_init(); // InitMMC(); // InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index b234cb7a1..76e4c7eb8 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -119,7 +119,7 @@ void hwinit1(void) { /* * Interrupt vectors assignment. */ - InitVIC(); + lpc214x_vic_init(); VICDefVectAddr = (IOREG32)IrqHandler; /* @@ -137,8 +137,8 @@ void hwinit1(void) { /* * Other subsystems. */ -// InitSerial(1, 2); -// InitSSP(); +// lpc2148x_serial_init(1, 2); +// lpc214x_ssp_init(); // InitMMC(); // InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 8e0bcfb34..9d6d77fc7 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -119,7 +119,7 @@ void hwinit1(void) { /* * Interrupt vectors assignment. */ - InitVIC(); + lpc214x_vic_init(); VICDefVectAddr = (IOREG32)IrqHandler; /* @@ -137,8 +137,8 @@ void hwinit1(void) { /* * Other subsystems. */ - InitSerial(1, 2); - InitSSP(); + lpc2148x_serial_init(1, 2); + lpc214x_ssp_init(); InitMMC(); InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index bd1997fce..10e6c6c5b 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -167,7 +167,7 @@ bool_t mmcInit(void) { /* * Starting initialization with slow clock mode. */ - SetSSP(254, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); + lpc214x_ssp_setup(254, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); /* * SPI mode selection. @@ -200,7 +200,7 @@ bool_t mmcInit(void) { /* * Full speed. */ - SetSSP(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); + lpc214x_ssp_setup(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); return FALSE; } diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 6a13c126b..c545728ec 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -104,7 +104,7 @@ void hwinit1(void) { /* * Other subsystems initialization. */ - InitSerial(0xC0, 0xC0, 0xC0); + stm32_serial_init(0xC0, 0xC0, 0xC0); /* * ChibiOS/RT initialization. -- cgit v1.2.3 From 52fb58eca6f6aa8ce415ce1a368d03533e6cfaf1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 6 Feb 2009 17:43:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@726 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 98a82bc94..2fd5757e4 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -20,11 +20,17 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +/* + * Tricks required to make the TRUE/FALSE declaration inside the library + * compatible. + */ #undef FALSE #undef TRUE #ifndef __STM32F10x_MAP_H #include "stm32lib/stm32f10x_map.h" #endif +#define FALSE FALSE +#define TRUE TRUE #define BOARD_OLIMEX_STM32_P103 -- cgit v1.2.3 From 724de0c330e40a599896bf5bca119ab121c24382 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 6 Feb 2009 20:11:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@727 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 2fd5757e4..8d240d02e 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -29,8 +29,6 @@ #ifndef __STM32F10x_MAP_H #include "stm32lib/stm32f10x_map.h" #endif -#define FALSE FALSE -#define TRUE TRUE #define BOARD_OLIMEX_STM32_P103 -- cgit v1.2.3 From 0ed5d7e2e02604710863224857e4a74e6004cd3e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 6 Feb 2009 21:03:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@729 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index d0793ef4d..18f548c92 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -155,7 +155,7 @@ void hwinit1(void) { /* * Serial driver initialization, RTS/CTS pins enabled for USART0 only. */ - InitSerial(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + sam7x_serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index bf5990b0d..b5e1ca70a 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -156,7 +156,7 @@ void hwinit1(void) { /* * Serial driver initialization, RTS/CTS pins enabled for USART0 only. */ - InitSerial(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + sam7x_serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; @@ -164,7 +164,7 @@ void hwinit1(void) { /* * EMAC driver initialization. */ - InitEMAC(AT91C_AIC_PRIOR_HIGHEST - 3); + sam7x_emac_init(AT91C_AIC_PRIOR_HIGHEST - 3); /* * ChibiOS/RT initialization. -- cgit v1.2.3 From 35b0454ddb7ac3b9a7b4142c7c04be4570a29798 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 6 Feb 2009 21:28:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@731 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 8d240d02e..81e918ae3 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -29,6 +29,8 @@ #ifndef __STM32F10x_MAP_H #include "stm32lib/stm32f10x_map.h" #endif +#define FALSE 0 +#define TRUE (!FALSE) #define BOARD_OLIMEX_STM32_P103 -- cgit v1.2.3 From d5f443f74d551831ef4f93c043f70b53d9b1008b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 6 Feb 2009 22:07:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@732 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 4 ++-- demos/ARM7-LPC214x-G++/board.c | 6 +++--- demos/ARM7-LPC214x-GCC-minimal/board.c | 6 +++--- demos/ARM7-LPC214x-GCC/board.c | 6 +++--- demos/ARM7-LPC214x-GCC/mmcsd.c | 4 ++-- demos/ARMCM3-STM32F103-GCC/board.c | 2 +- demos/MSP430-MSP430x1611-GCC/board.c | 2 +- 8 files changed, 16 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 18f548c92..ba64e335e 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -155,7 +155,7 @@ void hwinit1(void) { /* * Serial driver initialization, RTS/CTS pins enabled for USART0 only. */ - sam7x_serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index b5e1ca70a..5f49016e0 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -156,7 +156,7 @@ void hwinit1(void) { /* * Serial driver initialization, RTS/CTS pins enabled for USART0 only. */ - sam7x_serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; @@ -164,7 +164,7 @@ void hwinit1(void) { /* * EMAC driver initialization. */ - sam7x_emac_init(AT91C_AIC_PRIOR_HIGHEST - 3); + emac_init(AT91C_AIC_PRIOR_HIGHEST - 3); /* * ChibiOS/RT initialization. diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index 93227e0ed..0e54eeb71 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -119,7 +119,7 @@ void hwinit1(void) { /* * Interrupt vectors assignment. */ - lpc214x_vic_init(); + vic_init(); VICDefVectAddr = (IOREG32)IrqHandler; /* @@ -137,8 +137,8 @@ void hwinit1(void) { /* * Other subsystems. */ - lpc2148x_serial_init(1, 2); -// lpc214x_ssp_init(); + serial_init(1, 2); +// ssp_init(); // InitMMC(); // InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index 76e4c7eb8..e34bb3c55 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -119,7 +119,7 @@ void hwinit1(void) { /* * Interrupt vectors assignment. */ - lpc214x_vic_init(); + vic_init(); VICDefVectAddr = (IOREG32)IrqHandler; /* @@ -137,8 +137,8 @@ void hwinit1(void) { /* * Other subsystems. */ -// lpc2148x_serial_init(1, 2); -// lpc214x_ssp_init(); +// serial_init(1, 2); +// ssp_init(); // InitMMC(); // InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 9d6d77fc7..69aed08f3 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -119,7 +119,7 @@ void hwinit1(void) { /* * Interrupt vectors assignment. */ - lpc214x_vic_init(); + vic_init(); VICDefVectAddr = (IOREG32)IrqHandler; /* @@ -137,8 +137,8 @@ void hwinit1(void) { /* * Other subsystems. */ - lpc2148x_serial_init(1, 2); - lpc214x_ssp_init(); + serial_init(1, 2); + ssp_init(); InitMMC(); InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 10e6c6c5b..292b450d5 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -167,7 +167,7 @@ bool_t mmcInit(void) { /* * Starting initialization with slow clock mode. */ - lpc214x_ssp_setup(254, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); + ssp_setup(254, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); /* * SPI mode selection. @@ -200,7 +200,7 @@ bool_t mmcInit(void) { /* * Full speed. */ - lpc214x_ssp_setup(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); + ssp_setup(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); return FALSE; } diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index c545728ec..d3e776d1a 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -104,7 +104,7 @@ void hwinit1(void) { /* * Other subsystems initialization. */ - stm32_serial_init(0xC0, 0xC0, 0xC0); + serial_init(0xC0, 0xC0, 0xC0); /* * ChibiOS/RT initialization. diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index de9ac6387..794070803 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -82,7 +82,7 @@ void hwinit(void) { /* * Other subsystems. */ - msp430_serial_init(); + serial_init(); } CH_IRQ_HANDLER(TIMERA0_VECTOR) { -- cgit v1.2.3 From aaf826b161d38f5d2139d64b6d18898dbc902b19 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 7 Feb 2009 10:16:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@733 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/board.c | 2 +- demos/AVR-ATmega128-GCC/board.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c index 96b6c7e53..3119b82be 100644 --- a/demos/AVR-AT90CANx-GCC/board.c +++ b/demos/AVR-AT90CANx-GCC/board.c @@ -82,5 +82,5 @@ void hwinit(void) { /* * Other initializations. */ - InitSerial(); + serial_init(); } diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index 0a6201eed..490dd0362 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -82,5 +82,5 @@ void hwinit(void) { /* * Other initializations. */ - InitSerial(); + serial_init(); } -- cgit v1.2.3 From b08638d7c8e46b3a207705a2e55fdfe4b78cfb3e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 7 Feb 2009 12:42:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@735 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 459 ++++++++++++++++++++++++------------ 1 file changed, 313 insertions(+), 146 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index ff4a00298..f05f8b0b5 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,180 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 0 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r7" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ -- cgit v1.2.3 From 6cfef53ca56e835c9fcd28206971bf15e17fb31b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 7 Feb 2009 14:59:26 +0000 Subject: Configuration system improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@739 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 461 ++++++++++++++++++++++---------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 459 +++++++++++++++++++++---------- demos/ARM7-LPC214x-G++/chconf.h | 459 +++++++++++++++++++++---------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 459 +++++++++++++++++++++---------- demos/ARM7-LPC214x-GCC/chconf.h | 459 +++++++++++++++++++++---------- demos/AVR-AT90CANx-GCC/chconf.h | 450 +++++++++++++++++++++---------- demos/AVR-ATmega128-GCC/chconf.h | 459 +++++++++++++++++++++---------- demos/MSP430-MSP430x1611-GCC/chconf.h | 460 ++++++++++++++++++++----------- demos/Win32-MinGW/chconf.h | 459 +++++++++++++++++++++---------- 9 files changed, 2816 insertions(+), 1309 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 4c42fbfad..f05f8b0b5 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,180 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 0 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r7" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some + * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index ff4a00298..f05f8b0b5 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,180 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 0 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r7" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index c22e9b542..f05f8b0b5 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,180 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 0 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r7" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 61484aec7..03352998a 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,180 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -//#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -//#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -//#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -//#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -//#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -//#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -//#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -//#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -//#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -//#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -//#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -//#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -//#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -//#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -//#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN FALSE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT FALSE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES FALSE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW FALSE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT FALSE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES FALSE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS FALSE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT FALSE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS FALSE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT FALSE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES FALSE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT FALSE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES FALSE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX FALSE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT FALSE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX FALSE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX FALSE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP FALSE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 0 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -//#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS FALSE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -//#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC FALSE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r7" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index ff4a00298..f05f8b0b5 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,180 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 0 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r7" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 2cf2f8507..5e787d675 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,171 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 512 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r8" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 2de244954..5e787d675 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,180 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 512 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 512 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "r8" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 0fb97ecb7..f24019fcd 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,185 +27,345 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/* - * NOTE: this is just documentation for doxigen, the real configuration file - * is the one into the project directories. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 512 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 512 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 100 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 100 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 10 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 10 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-\. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "reg" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Debug option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #endif /* _CHCONF_H_ */ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index a10e43b7d..ac7131871 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -18,6 +18,8 @@ */ /** + * @file src/templates/chconf.h + * @brief Configuration file template. * @addtogroup Config * @{ */ @@ -25,184 +27,349 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -/** Configuration option: if specified then time efficient rather than space - * efficient code is used when two possible implementations exist, note - * that this is not related to the compiler optimization options.*/ -#define CH_OPTIMIZE_SPEED - -/** Configuration option: If enabled then the used of nested @p chSysLock() / - * @p chSysUnlock() operations is allowed.
- * For performance and code size reasons the recommended setting is leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - */ -//#define CH_USE_NESTED_LOCKS - -/** Configuration option: if specified then the kernel performs the round - * robin scheduling algorithm on threads of equal priority. */ -#define CH_USE_ROUNDROBIN - -/** Configuration option: if specified then the \p chThdWait() function - * is included in the kernel.*/ -#define CH_USE_WAITEXIT - -/** Configuration option: if specified then the Semaphores APIs are included - * in the kernel.*/ -#define CH_USE_SEMAPHORES - -/** Configuration option: If enabled then the threads are enqueued on semaphores - * by priority rather than FIFO order. - * @note requires @p CH_USE_SEMAPHORES.*/ -//#define CH_USE_SEMAPHORES_PRIORITY - -/** Configuration option: if specified then the Semaphores atomic Signal+Wait - * APIs are included in the kernel.*/ -#define CH_USE_SEMSW - -/** Configuration option: if specified then the Semaphores with timeout APIs - * are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES.*/ -#define CH_USE_SEMAPHORES_TIMEOUT - -/** Configuration option: if specified then the Mutexes APIs are included in - * the kernel.*/ -#define CH_USE_MUTEXES - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS - -/** Configuration option: if specified then the Conditional Variables APIs are - * included in the kernel. - * @note requires \p CH_USE_CONDVARS and \p CH_USE_MUTEXES.*/ -#define CH_USE_CONDVARS_TIMEOUT - -/** Configuration option: if specified then the Events APIs are included in - * the kernel.*/ -#define CH_USE_EVENTS - -/** Configuration option: if specified then the \p chEvtWaitXXXTimeout() - * functions are included in the kernel. - * @note requires \p CH_USE_EVENTS. - */ -#define CH_USE_EVENTS_TIMEOUT - -/** Configuration option: if specified then the Synchronous Messages APIs are - * included in the kernel.*/ -#define CH_USE_MESSAGES - -/** Configuration option: if specified then the \p chMsgSendWithEvent() - * function is included in the kernel. - * @note requires \p CH_USE_MESSAGES.*/ -#define CH_USE_MESSAGES_EVENT - -/** Configuration option: If enabled then the threads serve messages by - * priority instead of FIFO order. - * @note requires \p CH_USE_MESSAGES.*/ -//#define CH_USE_MESSAGES_PRIORITY - -/** Configuration option: if specified then the I/O queues APIs are included - * in the kernel.*/ -#define CH_USE_QUEUES - -/** Configuration option: if specified then the halfduplex queue APIs are - * included in the kernel.*/ -#define CH_USE_QUEUES_HALFDUPLEX - -/** Configuration option: if specified then the I/O queues with timeout - * APIs are included in the kernel. - * @note requires \p CH_USE_SEMAPHORES_TIMEOUT.*/ -#define CH_USE_QUEUES_TIMEOUT - -/** Configuration option: if specified then the full duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_FULLDUPLEX - -/** Configuration option: if specified then the half duplex serial driver APIs - * are included in the kernel.*/ -#define CH_USE_SERIAL_HALFDUPLEX - -/** Configuration option: if specified then the memory heap allocator APIs - * are included in the kernel.*/ -#define CH_USE_HEAP - -/** Configuration option: Number of RAM bytes to use as system heap. If set to - * zero then the whole available RAM is used as system heap. +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#ifndef CH_OPTIMIZE_SPEED +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#ifndef CH_USE_NESTED_LOCKS +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_ROUNDROBIN +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_WAITEXIT +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_SEMAPHORES +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_PRIORITY +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMSW +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Semaphores with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_SEMAPHORES_TIMEOUT +#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MUTEXES +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#ifndef CH_USE_CONDVARS +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#ifndef CH_USE_CONDVARS_TIMEOUT +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_EVENTS +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#ifndef CH_USE_EVENTS_TIMEOUT +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MESSAGES +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If specified then the @p chMsgSendWithEvent() function is included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. + */ +#ifndef CH_USE_MESSAGES_EVENT +#define CH_USE_MESSAGES_EVENT TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#ifndef CH_USE_MESSAGES_PRIORITY +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the half duplex queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#ifndef CH_USE_QUEUES_HALFDUPLEX +#define CH_USE_QUEUES_HALFDUPLEX TRUE +#endif + +/** + * If specified then the I/O queues with timeout APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. + */ +#ifndef CH_USE_QUEUES_TIMEOUT +#define CH_USE_QUEUES_TIMEOUT TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#ifndef CH_USE_SERIAL_FULLDUPLEX +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the half duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. + */ +#ifndef CH_USE_SERIAL_HALFDUPLEX +#define CH_USE_SERIAL_HALFDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#ifndef CH_USE_HEAP +#define CH_USE_HEAP TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. * @note In order to use the whole RAM as system heap the linker script must - * provide the \p __heap_base__ and \p __heap_end__ symbols. - * @note requires \p CH_USE_HEAP. + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. */ -#define CH_HEAP_SIZE 0x20000 +#ifndef CH_HEAP_SIZE +#define CH_HEAP_SIZE 0x20000 +#endif -/** Configuration option: enforces the use of the C-runtime \p malloc() and - * \p free() functions as backend for the system heap allocator.*/ -//#define CH_USE_MALLOC_HEAP +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#ifndef CH_USE_MALLOC_HEAP +#define CH_USE_MALLOC_HEAP FALSE +#endif -/** Configuration option: if specified then the memory pools allocator APIs - * are included in the kernel.*/ -#define CH_USE_MEMPOOLS +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#ifndef CH_USE_MEMPOOLS +#define CH_USE_MEMPOOLS TRUE +#endif -/** Configuration option: if specified then the dynamic objects creation APIs - * are included in the kernel. - * @note requires \p CH_USE_WAITEXIT. +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. */ -#define CH_USE_DYNAMIC +#ifndef CH_USE_DYNAMIC +#define CH_USE_DYNAMIC TRUE +#endif -/** Configuration option: Frequency of the system timer that drives the system - * ticks. This also defines the system time unit.*/ -#define CH_FREQUENCY 1000 +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#ifndef CH_FREQUENCY +#define CH_FREQUENCY 1000 +#endif -/** Configuration option: This constant is the number of ticks allowed for the - * threads before preemption occurs. This option is only meaningful if the - * option \p CH_USE_ROUNDROBIN is also active.*/ -#define CH_TIME_QUANTUM 20 +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#ifndef CH_TIME_QUANTUM +#define CH_TIME_QUANTUM 20 +#endif -/** Configuration option: Defines a CPU register to be used as storage for the - * global \p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only useable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option \p - * -ffixed-\. +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. */ -//#define CH_CURRP_REGISTER_CACHE "reg" +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif -/** Configuration option: Includes basic debug support to the kernel. - * @note the debug support is port-dependent, it may be not present on some +/** + * Debug option, if enableed includes basic debug support to the kernel. + * @note The debug support is port-dependent, it may be not present on some * targets. In that case stub functions will be included. + * @note The default is @p FALSE. */ -//#define CH_USE_DEBUG +#ifndef CH_USE_DEBUG +#define CH_USE_DEBUG FALSE +#endif -/** Debug option: Includes the threads context switch tracing feature. +/** + * Debug option, includes the threads context switch tracing feature. + * @note The default is @p FALSE. */ -//#define CH_USE_TRACE +#ifndef CH_USE_TRACE +#define CH_USE_TRACE FALSE +#endif -/** User fields added to the end of the \p Thread structure. */ +/** + * User fields added to the end of the @p Thread structure. + */ +#ifndef THREAD_EXT_FIELDS #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ /* The thread termination \p EventSource.*/ \ EventSource p_exitesource; \ }; +#endif -/** User initialization code added to the \p chThdCreate() API. - * @note It is invoked from within \p chThdInit(). */ +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#ifndef THREAD_EXT_INIT #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ chEvtInit(&tp->p_exitesource); \ } +#endif -/** User finalization code added to the \p chThdExit() API. - * @note It is inserted into lock zone. */ +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#ifndef THREAD_EXT_EXIT #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ chEvtBroadcastI(&currp->p_exitesource); \ } +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#ifndef IDLE_LOOP_HOOK +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif #define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) -- cgit v1.2.3 From 1aa7798d0e8052ccc4579b7e3be43bac3cab8101 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 8 Feb 2009 11:07:35 +0000 Subject: STM32 library integration improvements. Updated to the latest version 2.03. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@744 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 3 +- demos/ARMCM3-STM32F103-GCC/board.h | 2 +- .../ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h | 51 - .../stm32lib/inc/cortexm3_macro.h | 53 + .../stm32lib/inc/stm32f10x_conf.h | 174 + .../stm32lib/inc/stm32f10x_map.h | 7603 ++++++++++++++++++++ .../stm32lib/inc/stm32f10x_nvic.h | 287 + .../stm32lib/inc/stm32f10x_type.h | 80 + .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h | 142 - .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h | 857 --- .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h | 251 - .../ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h | 80 - 12 files changed, 8200 insertions(+), 1383 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 481f8ac5c..a669ad3d5 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -83,7 +83,8 @@ ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s # List all user directories here UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARMCM3 ../../ports/ARMCM3-STM32F103 + ../../ports/ARMCM3 ../../ports/ARMCM3-STM32F103 \ + ./stm32lib/inc # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 81e918ae3..680668cc2 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -27,7 +27,7 @@ #undef FALSE #undef TRUE #ifndef __STM32F10x_MAP_H -#include "stm32lib/stm32f10x_map.h" +#include "stm32f10x_map.h" #endif #define FALSE 0 #define TRUE (!FALSE) diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h deleted file mode 100644 index 822d01910..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/cortexm3_macro.h +++ /dev/null @@ -1,51 +0,0 @@ -/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** -* File Name : cortexm3_macro.h -* Author : MCD Application Team -* Version : V1.0 -* Date : 10/08/2007 -* Description : Header file for cortexm3_macro.s. -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __CORTEXM3_MACRO_H -#define __CORTEXM3_MACRO_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_type.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void __WFI(void); -void __WFE(void); -void __SEV(void); -void __ISB(void); -void __DSB(void); -void __DMB(void); -void __SVC(void); -u32 __MRS_CONTROL(void); -void __MSR_CONTROL(u32 Control); -u32 __MRS_PSP(void); -void __MSR_PSP(u32 TopOfProcessStack); -u32 __MRS_MSP(void); -void __MSR_MSP(u32 TopOfMainStack); -void __SETPRIMASK(void); -void __RESETPRIMASK(void); -void __SETFAULTMASK(void); -void __RESETFAULTMASK(void); -void __BASEPRICONFIG(u32 NewPriority); -u32 __GetBASEPRI(void); -u16 __REV_HalfWord(u16 Data); -u32 __REV_Word(u32 Data); - -#endif /* __CORTEXM3_MACRO_H */ - -/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h new file mode 100644 index 000000000..b26807f92 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h @@ -0,0 +1,53 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : cortexm3_macro.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : Header file for cortexm3_macro.s. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CORTEXM3_MACRO_H +#define __CORTEXM3_MACRO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void __WFI(void); +void __WFE(void); +void __SEV(void); +void __ISB(void); +void __DSB(void); +void __DMB(void); +void __SVC(void); +u32 __MRS_CONTROL(void); +void __MSR_CONTROL(u32 Control); +u32 __MRS_PSP(void); +void __MSR_PSP(u32 TopOfProcessStack); +u32 __MRS_MSP(void); +void __MSR_MSP(u32 TopOfMainStack); +void __RESETPRIMASK(void); +void __SETPRIMASK(void); +u32 __READ_PRIMASK(void); +void __RESETFAULTMASK(void); +void __SETFAULTMASK(void); +u32 __READ_FAULTMASK(void); +void __BASEPRICONFIG(u32 NewPriority); +u32 __GetBASEPRI(void); +u16 __REV_HalfWord(u16 Data); +u32 __REV_Word(u32 Data); + +#endif /* __CORTEXM3_MACRO_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h new file mode 100644 index 000000000..dcffed158 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h @@ -0,0 +1,174 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_conf.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : Library configuration file. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to compile the library in DEBUG mode, this will expanse + the "assert_param" macro in the firmware library code (see "Exported macro" + section below) */ +/*#define DEBUG 1*/ + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ADC ************************************/ +//#define _ADC +//#define _ADC1 +//#define _ADC2 +//#define _ADC3 + +/************************************* BKP ************************************/ +//#define _BKP + +/************************************* CAN ************************************/ +//#define _CAN + +/************************************* CRC ************************************/ +//#define _CRC + +/************************************* DAC ************************************/ +//#define _DAC + +/************************************* DBGMCU *********************************/ +//#define _DBGMCU + +/************************************* DMA ************************************/ +//#define _DMA +//#define _DMA1_Channel1 +//#define _DMA1_Channel2 +//#define _DMA1_Channel3 +//#define _DMA1_Channel4 +//#define _DMA1_Channel5 +//#define _DMA1_Channel6 +//#define _DMA1_Channel7 +//#define _DMA2_Channel1 +//#define _DMA2_Channel2 +//#define _DMA2_Channel3 +//#define _DMA2_Channel4 +//#define _DMA2_Channel5 + +/************************************* EXTI ***********************************/ +//#define _EXTI + +/************************************* FLASH and Option Bytes *****************/ +#define _FLASH +/* Uncomment the line below to enable FLASH program/erase/protections functions, + otherwise only FLASH configuration (latency, prefetch, half cycle) functions + are enabled */ +/* #define _FLASH_PROG */ + +/************************************* FSMC ***********************************/ +//#define _FSMC + +/************************************* GPIO ***********************************/ +#define _GPIO +#define _GPIOA +#define _GPIOB +#define _GPIOC +#define _GPIOD +//#define _GPIOE +//#define _GPIOF +//#define _GPIOG +//#define _AFIO + +/************************************* I2C ************************************/ +//#define _I2C +//#define _I2C1 +//#define _I2C2 + +/************************************* IWDG ***********************************/ +//#define _IWDG + +/************************************* NVIC ***********************************/ +//#define _NVIC + +/************************************* PWR ************************************/ +//#define _PWR + +/************************************* RCC ************************************/ +#define _RCC + +/************************************* RTC ************************************/ +//#define _RTC + +/************************************* SDIO ***********************************/ +//#define _SDIO + +/************************************* SPI ************************************/ +//#define _SPI +//#define _SPI1 +//#define _SPI2 +//#define _SPI3 + +/************************************* SysTick ********************************/ +//#define _SysTick + +/************************************* TIM ************************************/ +//#define _TIM +//#define _TIM1 +//#define _TIM2 +//#define _TIM3 +//#define _TIM4 +//#define _TIM5 +//#define _TIM6 +//#define _TIM7 +//#define _TIM8 + +/************************************* USART **********************************/ +#define _USART +#define _USART1 +#define _USART2 +#define _USART3 +//#define _UART4 +//#define _UART5 + +/************************************* WWDG ***********************************/ +//#define _WWDG + +/* In the following line adjust the value of External High Speed oscillator (HSE) + used in your application */ +#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ + +/* In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value */ +#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef DEBUG +/******************************************************************************* +* Macro Name : assert_param +* Description : The assert_param macro is used for function's parameters check. +* It is used only if the library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define assert_param(expr) ((void)0) +#endif /* DEBUG */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h new file mode 100644 index 000000000..851dff410 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h @@ -0,0 +1,7603 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_map.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the peripheral register's definitions, +* bits definitions and memory mapping. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_MAP_H +#define __STM32F10x_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_conf.h" +#include "stm32f10x_type.h" +#include "cortexm3_macro.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Peripheral registers structures */ +/******************************************************************************/ + +/*------------------------ Analog to Digital Converter -----------------------*/ +typedef struct +{ + vu32 SR; + vu32 CR1; + vu32 CR2; + vu32 SMPR1; + vu32 SMPR2; + vu32 JOFR1; + vu32 JOFR2; + vu32 JOFR3; + vu32 JOFR4; + vu32 HTR; + vu32 LTR; + vu32 SQR1; + vu32 SQR2; + vu32 SQR3; + vu32 JSQR; + vu32 JDR1; + vu32 JDR2; + vu32 JDR3; + vu32 JDR4; + vu32 DR; +} ADC_TypeDef; + +/*------------------------ Backup Registers ----------------------------------*/ +typedef struct +{ + u32 RESERVED0; + vu16 DR1; + u16 RESERVED1; + vu16 DR2; + u16 RESERVED2; + vu16 DR3; + u16 RESERVED3; + vu16 DR4; + u16 RESERVED4; + vu16 DR5; + u16 RESERVED5; + vu16 DR6; + u16 RESERVED6; + vu16 DR7; + u16 RESERVED7; + vu16 DR8; + u16 RESERVED8; + vu16 DR9; + u16 RESERVED9; + vu16 DR10; + u16 RESERVED10; + vu16 RTCCR; + u16 RESERVED11; + vu16 CR; + u16 RESERVED12; + vu16 CSR; + u16 RESERVED13[5]; + vu16 DR11; + u16 RESERVED14; + vu16 DR12; + u16 RESERVED15; + vu16 DR13; + u16 RESERVED16; + vu16 DR14; + u16 RESERVED17; + vu16 DR15; + u16 RESERVED18; + vu16 DR16; + u16 RESERVED19; + vu16 DR17; + u16 RESERVED20; + vu16 DR18; + u16 RESERVED21; + vu16 DR19; + u16 RESERVED22; + vu16 DR20; + u16 RESERVED23; + vu16 DR21; + u16 RESERVED24; + vu16 DR22; + u16 RESERVED25; + vu16 DR23; + u16 RESERVED26; + vu16 DR24; + u16 RESERVED27; + vu16 DR25; + u16 RESERVED28; + vu16 DR26; + u16 RESERVED29; + vu16 DR27; + u16 RESERVED30; + vu16 DR28; + u16 RESERVED31; + vu16 DR29; + u16 RESERVED32; + vu16 DR30; + u16 RESERVED33; + vu16 DR31; + u16 RESERVED34; + vu16 DR32; + u16 RESERVED35; + vu16 DR33; + u16 RESERVED36; + vu16 DR34; + u16 RESERVED37; + vu16 DR35; + u16 RESERVED38; + vu16 DR36; + u16 RESERVED39; + vu16 DR37; + u16 RESERVED40; + vu16 DR38; + u16 RESERVED41; + vu16 DR39; + u16 RESERVED42; + vu16 DR40; + u16 RESERVED43; + vu16 DR41; + u16 RESERVED44; + vu16 DR42; + u16 RESERVED45; +} BKP_TypeDef; + +/*------------------------ Controller Area Network ---------------------------*/ +typedef struct +{ + vu32 TIR; + vu32 TDTR; + vu32 TDLR; + vu32 TDHR; +} CAN_TxMailBox_TypeDef; + +typedef struct +{ + vu32 RIR; + vu32 RDTR; + vu32 RDLR; + vu32 RDHR; +} CAN_FIFOMailBox_TypeDef; + +typedef struct +{ + vu32 FR1; + vu32 FR2; +} CAN_FilterRegister_TypeDef; + +typedef struct +{ + vu32 MCR; + vu32 MSR; + vu32 TSR; + vu32 RF0R; + vu32 RF1R; + vu32 IER; + vu32 ESR; + vu32 BTR; + u32 RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + u32 RESERVED1[12]; + vu32 FMR; + vu32 FM1R; + u32 RESERVED2; + vu32 FS1R; + u32 RESERVED3; + vu32 FFA1R; + u32 RESERVED4; + vu32 FA1R; + u32 RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/*------------------------ CRC calculation unit ------------------------------*/ +typedef struct +{ + vu32 DR; + vu8 IDR; + u8 RESERVED0; + u16 RESERVED1; + vu32 CR; +} CRC_TypeDef; + + +/*------------------------ Digital to Analog Converter -----------------------*/ +typedef struct +{ + vu32 CR; + vu32 SWTRIGR; + vu32 DHR12R1; + vu32 DHR12L1; + vu32 DHR8R1; + vu32 DHR12R2; + vu32 DHR12L2; + vu32 DHR8R2; + vu32 DHR12RD; + vu32 DHR12LD; + vu32 DHR8RD; + vu32 DOR1; + vu32 DOR2; +} DAC_TypeDef; + +/*------------------------ Debug MCU -----------------------------------------*/ +typedef struct +{ + vu32 IDCODE; + vu32 CR; +}DBGMCU_TypeDef; + +/*------------------------ DMA Controller ------------------------------------*/ +typedef struct +{ + vu32 CCR; + vu32 CNDTR; + vu32 CPAR; + vu32 CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + vu32 ISR; + vu32 IFCR; +} DMA_TypeDef; + +/*------------------------ External Interrupt/Event Controller ---------------*/ +typedef struct +{ + vu32 IMR; + vu32 EMR; + vu32 RTSR; + vu32 FTSR; + vu32 SWIER; + vu32 PR; +} EXTI_TypeDef; + +/*------------------------ FLASH and Option Bytes Registers ------------------*/ +typedef struct +{ + vu32 ACR; + vu32 KEYR; + vu32 OPTKEYR; + vu32 SR; + vu32 CR; + vu32 AR; + vu32 RESERVED; + vu32 OBR; + vu32 WRPR; +} FLASH_TypeDef; + +typedef struct +{ + vu16 RDP; + vu16 USER; + vu16 Data0; + vu16 Data1; + vu16 WRP0; + vu16 WRP1; + vu16 WRP2; + vu16 WRP3; +} OB_TypeDef; + +/*------------------------ Flexible Static Memory Controller -----------------*/ +typedef struct +{ + vu32 BTCR[8]; +} FSMC_Bank1_TypeDef; + +typedef struct +{ + vu32 BWTR[7]; +} FSMC_Bank1E_TypeDef; + +typedef struct +{ + vu32 PCR2; + vu32 SR2; + vu32 PMEM2; + vu32 PATT2; + u32 RESERVED0; + vu32 ECCR2; +} FSMC_Bank2_TypeDef; + +typedef struct +{ + vu32 PCR3; + vu32 SR3; + vu32 PMEM3; + vu32 PATT3; + u32 RESERVED0; + vu32 ECCR3; +} FSMC_Bank3_TypeDef; + +typedef struct +{ + vu32 PCR4; + vu32 SR4; + vu32 PMEM4; + vu32 PATT4; + vu32 PIO4; +} FSMC_Bank4_TypeDef; + +/*------------------------ General Purpose and Alternate Function IO ---------*/ +typedef struct +{ + vu32 CRL; + vu32 CRH; + vu32 IDR; + vu32 ODR; + vu32 BSRR; + vu32 BRR; + vu32 LCKR; +} GPIO_TypeDef; + +typedef struct +{ + vu32 EVCR; + vu32 MAPR; + vu32 EXTICR[4]; +} AFIO_TypeDef; + +/*------------------------ Inter-integrated Circuit Interface ----------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 OAR1; + u16 RESERVED2; + vu16 OAR2; + u16 RESERVED3; + vu16 DR; + u16 RESERVED4; + vu16 SR1; + u16 RESERVED5; + vu16 SR2; + u16 RESERVED6; + vu16 CCR; + u16 RESERVED7; + vu16 TRISE; + u16 RESERVED8; +} I2C_TypeDef; + +/*------------------------ Independent WATCHDOG ------------------------------*/ +typedef struct +{ + vu32 KR; + vu32 PR; + vu32 RLR; + vu32 SR; +} IWDG_TypeDef; + +/*------------------------ Nested Vectored Interrupt Controller --------------*/ +typedef struct +{ + vu32 ISER[2]; + u32 RESERVED0[30]; + vu32 ICER[2]; + u32 RSERVED1[30]; + vu32 ISPR[2]; + u32 RESERVED2[30]; + vu32 ICPR[2]; + u32 RESERVED3[30]; + vu32 IABR[2]; + u32 RESERVED4[62]; + vu32 IPR[15]; +} NVIC_TypeDef; + +typedef struct +{ + vuc32 CPUID; + vu32 ICSR; + vu32 VTOR; + vu32 AIRCR; + vu32 SCR; + vu32 CCR; + vu32 SHPR[3]; + vu32 SHCSR; + vu32 CFSR; + vu32 HFSR; + vu32 DFSR; + vu32 MMFAR; + vu32 BFAR; + vu32 AFSR; +} SCB_TypeDef; + +/*------------------------ Power Control -------------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CSR; +} PWR_TypeDef; + +/*------------------------ Reset and Clock Control ---------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFGR; + vu32 CIR; + vu32 APB2RSTR; + vu32 APB1RSTR; + vu32 AHBENR; + vu32 APB2ENR; + vu32 APB1ENR; + vu32 BDCR; + vu32 CSR; +} RCC_TypeDef; + +/*------------------------ Real-Time Clock -----------------------------------*/ +typedef struct +{ + vu16 CRH; + u16 RESERVED0; + vu16 CRL; + u16 RESERVED1; + vu16 PRLH; + u16 RESERVED2; + vu16 PRLL; + u16 RESERVED3; + vu16 DIVH; + u16 RESERVED4; + vu16 DIVL; + u16 RESERVED5; + vu16 CNTH; + u16 RESERVED6; + vu16 CNTL; + u16 RESERVED7; + vu16 ALRH; + u16 RESERVED8; + vu16 ALRL; + u16 RESERVED9; +} RTC_TypeDef; + +/*------------------------ SD host Interface ---------------------------------*/ +typedef struct +{ + vu32 POWER; + vu32 CLKCR; + vu32 ARG; + vu32 CMD; + vuc32 RESPCMD; + vuc32 RESP1; + vuc32 RESP2; + vuc32 RESP3; + vuc32 RESP4; + vu32 DTIMER; + vu32 DLEN; + vu32 DCTRL; + vuc32 DCOUNT; + vuc32 STA; + vu32 ICR; + vu32 MASK; + u32 RESERVED0[2]; + vuc32 FIFOCNT; + u32 RESERVED1[13]; + vu32 FIFO; +} SDIO_TypeDef; + +/*------------------------ Serial Peripheral Interface -----------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SR; + u16 RESERVED2; + vu16 DR; + u16 RESERVED3; + vu16 CRCPR; + u16 RESERVED4; + vu16 RXCRCR; + u16 RESERVED5; + vu16 TXCRCR; + u16 RESERVED6; + vu16 I2SCFGR; + u16 RESERVED7; + vu16 I2SPR; + u16 RESERVED8; +} SPI_TypeDef; + +/*------------------------ SystemTick ----------------------------------------*/ +typedef struct +{ + vu32 CTRL; + vu32 LOAD; + vu32 VAL; + vuc32 CALIB; +} SysTick_TypeDef; + +/*------------------------ TIM -----------------------------------------------*/ +typedef struct +{ + vu16 CR1; + u16 RESERVED0; + vu16 CR2; + u16 RESERVED1; + vu16 SMCR; + u16 RESERVED2; + vu16 DIER; + u16 RESERVED3; + vu16 SR; + u16 RESERVED4; + vu16 EGR; + u16 RESERVED5; + vu16 CCMR1; + u16 RESERVED6; + vu16 CCMR2; + u16 RESERVED7; + vu16 CCER; + u16 RESERVED8; + vu16 CNT; + u16 RESERVED9; + vu16 PSC; + u16 RESERVED10; + vu16 ARR; + u16 RESERVED11; + vu16 RCR; + u16 RESERVED12; + vu16 CCR1; + u16 RESERVED13; + vu16 CCR2; + u16 RESERVED14; + vu16 CCR3; + u16 RESERVED15; + vu16 CCR4; + u16 RESERVED16; + vu16 BDTR; + u16 RESERVED17; + vu16 DCR; + u16 RESERVED18; + vu16 DMAR; + u16 RESERVED19; +} TIM_TypeDef; + +/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ +typedef struct +{ + vu16 SR; + u16 RESERVED0; + vu16 DR; + u16 RESERVED1; + vu16 BRR; + u16 RESERVED2; + vu16 CR1; + u16 RESERVED3; + vu16 CR2; + u16 RESERVED4; + vu16 CR3; + u16 RESERVED5; + vu16 GTPR; + u16 RESERVED6; +} USART_TypeDef; + +/*------------------------ Window WATCHDOG -----------------------------------*/ +typedef struct +{ + vu32 CR; + vu32 CFR; + vu32 SR; +} WWDG_TypeDef; + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Peripheral and SRAM base address in the alias region */ +#define PERIPH_BB_BASE ((u32)0x42000000) +#define SRAM_BB_BASE ((u32)0x22000000) + +/* Peripheral and SRAM base address in the bit-band region */ +#define SRAM_BASE ((u32)0x20000000) +#define PERIPH_BASE ((u32)0x40000000) + +/* FSMC registers base address */ +#define FSMC_R_BASE ((u32)0xA0000000) + +/* Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN_BASE (APB1PERIPH_BASE + 0x6400) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +/* Flash registers base address */ +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +/* Flash Option Bytes base address */ +#define OB_BASE ((u32)0x1FFFF800) + +/* FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((u32)0xE0042000) + +/* System Control Space memory map */ +#define SCS_BASE ((u32)0xE000E000) + +#define SysTick_BASE (SCS_BASE + 0x0010) +#define NVIC_BASE (SCS_BASE + 0x0100) +#define SCB_BASE (SCS_BASE + 0x0D00) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/*------------------------ Non Debug Mode ------------------------------------*/ +#ifndef DEBUG +#ifdef _TIM2 + #define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#endif /*_TIM2 */ + +#ifdef _TIM3 + #define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#endif /*_TIM3 */ + +#ifdef _TIM4 + #define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#endif /*_TIM4 */ + +#ifdef _TIM5 + #define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#endif /*_TIM5 */ + +#ifdef _TIM6 + #define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#endif /*_TIM6 */ + +#ifdef _TIM7 + #define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#endif /*_TIM7 */ + +#ifdef _RTC + #define RTC ((RTC_TypeDef *) RTC_BASE) +#endif /*_RTC */ + +#ifdef _WWDG + #define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#endif /*_WWDG */ + +#ifdef _IWDG + #define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#endif /*_IWDG */ + +#ifdef _SPI2 + #define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#endif /*_SPI2 */ + +#ifdef _SPI3 + #define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#endif /*_SPI3 */ + +#ifdef _USART2 + #define USART2 ((USART_TypeDef *) USART2_BASE) +#endif /*_USART2 */ + +#ifdef _USART3 + #define USART3 ((USART_TypeDef *) USART3_BASE) +#endif /*_USART3 */ + +#ifdef _UART4 + #define UART4 ((USART_TypeDef *) UART4_BASE) +#endif /*_UART4 */ + +#ifdef _UART5 + #define UART5 ((USART_TypeDef *) UART5_BASE) +#endif /*_USART5 */ + +#ifdef _I2C1 + #define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#endif /*_I2C1 */ + +#ifdef _I2C2 + #define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#endif /*_I2C2 */ + +#ifdef _CAN + #define CAN ((CAN_TypeDef *) CAN_BASE) +#endif /*_CAN */ + +#ifdef _BKP + #define BKP ((BKP_TypeDef *) BKP_BASE) +#endif /*_BKP */ + +#ifdef _PWR + #define PWR ((PWR_TypeDef *) PWR_BASE) +#endif /*_PWR */ + +#ifdef _DAC + #define DAC ((DAC_TypeDef *) DAC_BASE) +#endif /*_DAC */ + +#ifdef _AFIO + #define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#endif /*_AFIO */ + +#ifdef _EXTI + #define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#endif /*_EXTI */ + +#ifdef _GPIOA + #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#endif /*_GPIOA */ + +#ifdef _GPIOB + #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#endif /*_GPIOB */ + +#ifdef _GPIOC + #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#endif /*_GPIOC */ + +#ifdef _GPIOD + #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#endif /*_GPIOD */ + +#ifdef _GPIOE + #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#endif /*_GPIOE */ + +#ifdef _GPIOF + #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#endif /*_GPIOF */ + +#ifdef _GPIOG + #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#endif /*_GPIOG */ + +#ifdef _ADC1 + #define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#endif /*_ADC1 */ + +#ifdef _ADC2 + #define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#endif /*_ADC2 */ + +#ifdef _TIM1 + #define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#endif /*_TIM1 */ + +#ifdef _SPI1 + #define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#endif /*_SPI1 */ + +#ifdef _TIM8 + #define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#endif /*_TIM8 */ + +#ifdef _USART1 + #define USART1 ((USART_TypeDef *) USART1_BASE) +#endif /*_USART1 */ + +#ifdef _ADC3 + #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#endif /*_ADC3 */ + +#ifdef _SDIO + #define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#endif /*_SDIO */ + +#ifdef _DMA + #define DMA1 ((DMA_TypeDef *) DMA1_BASE) + #define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#endif /*_DMA */ + +#ifdef _DMA1_Channel1 + #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#endif /*_DMA1_Channel1 */ + +#ifdef _DMA1_Channel2 + #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#endif /*_DMA1_Channel2 */ + +#ifdef _DMA1_Channel3 + #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#endif /*_DMA1_Channel3 */ + +#ifdef _DMA1_Channel4 + #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#endif /*_DMA1_Channel4 */ + +#ifdef _DMA1_Channel5 + #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#endif /*_DMA1_Channel5 */ + +#ifdef _DMA1_Channel6 + #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#endif /*_DMA1_Channel6 */ + +#ifdef _DMA1_Channel7 + #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#endif /*_DMA1_Channel7 */ + +#ifdef _DMA2_Channel1 + #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#endif /*_DMA2_Channel1 */ + +#ifdef _DMA2_Channel2 + #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#endif /*_DMA2_Channel2 */ + +#ifdef _DMA2_Channel3 + #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#endif /*_DMA2_Channel3 */ + +#ifdef _DMA2_Channel4 + #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#endif /*_DMA2_Channel4 */ + +#ifdef _DMA2_Channel5 + #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#endif /*_DMA2_Channel5 */ + +#ifdef _RCC + #define RCC ((RCC_TypeDef *) RCC_BASE) +#endif /*_RCC */ + +#ifdef _CRC + #define CRC ((CRC_TypeDef *) CRC_BASE) +#endif /*_CRC */ + +#ifdef _FLASH + #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) + #define OB ((OB_TypeDef *) OB_BASE) +#endif /*_FLASH */ + +#ifdef _FSMC + #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) + #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) + #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) + #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#endif /*_FSMC */ + +#ifdef _DBGMCU + #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#endif /*_DBGMCU */ + +#ifdef _SysTick + #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#endif /*_SysTick */ + +#ifdef _NVIC + #define NVIC ((NVIC_TypeDef *) NVIC_BASE) + #define SCB ((SCB_TypeDef *) SCB_BASE) +#endif /*_NVIC */ + +/*------------------------ Debug Mode ----------------------------------------*/ +#else /* DEBUG */ +#ifdef _TIM2 + EXT TIM_TypeDef *TIM2; +#endif /*_TIM2 */ + +#ifdef _TIM3 + EXT TIM_TypeDef *TIM3; +#endif /*_TIM3 */ + +#ifdef _TIM4 + EXT TIM_TypeDef *TIM4; +#endif /*_TIM4 */ + +#ifdef _TIM5 + EXT TIM_TypeDef *TIM5; +#endif /*_TIM5 */ + +#ifdef _TIM6 + EXT TIM_TypeDef *TIM6; +#endif /*_TIM6 */ + +#ifdef _TIM7 + EXT TIM_TypeDef *TIM7; +#endif /*_TIM7 */ + +#ifdef _RTC + EXT RTC_TypeDef *RTC; +#endif /*_RTC */ + +#ifdef _WWDG + EXT WWDG_TypeDef *WWDG; +#endif /*_WWDG */ + +#ifdef _IWDG + EXT IWDG_TypeDef *IWDG; +#endif /*_IWDG */ + +#ifdef _SPI2 + EXT SPI_TypeDef *SPI2; +#endif /*_SPI2 */ + +#ifdef _SPI3 + EXT SPI_TypeDef *SPI3; +#endif /*_SPI3 */ + +#ifdef _USART2 + EXT USART_TypeDef *USART2; +#endif /*_USART2 */ + +#ifdef _USART3 + EXT USART_TypeDef *USART3; +#endif /*_USART3 */ + +#ifdef _UART4 + EXT USART_TypeDef *UART4; +#endif /*_UART4 */ + +#ifdef _UART5 + EXT USART_TypeDef *UART5; +#endif /*_UART5 */ + +#ifdef _I2C1 + EXT I2C_TypeDef *I2C1; +#endif /*_I2C1 */ + +#ifdef _I2C2 + EXT I2C_TypeDef *I2C2; +#endif /*_I2C2 */ + +#ifdef _CAN + EXT CAN_TypeDef *CAN; +#endif /*_CAN */ + +#ifdef _BKP + EXT BKP_TypeDef *BKP; +#endif /*_BKP */ + +#ifdef _PWR + EXT PWR_TypeDef *PWR; +#endif /*_PWR */ + +#ifdef _DAC + EXT DAC_TypeDef *DAC; +#endif /*_DAC */ + +#ifdef _AFIO + EXT AFIO_TypeDef *AFIO; +#endif /*_AFIO */ + +#ifdef _EXTI + EXT EXTI_TypeDef *EXTI; +#endif /*_EXTI */ + +#ifdef _GPIOA + EXT GPIO_TypeDef *GPIOA; +#endif /*_GPIOA */ + +#ifdef _GPIOB + EXT GPIO_TypeDef *GPIOB; +#endif /*_GPIOB */ + +#ifdef _GPIOC + EXT GPIO_TypeDef *GPIOC; +#endif /*_GPIOC */ + +#ifdef _GPIOD + EXT GPIO_TypeDef *GPIOD; +#endif /*_GPIOD */ + +#ifdef _GPIOE + EXT GPIO_TypeDef *GPIOE; +#endif /*_GPIOE */ + +#ifdef _GPIOF + EXT GPIO_TypeDef *GPIOF; +#endif /*_GPIOF */ + +#ifdef _GPIOG + EXT GPIO_TypeDef *GPIOG; +#endif /*_GPIOG */ + +#ifdef _ADC1 + EXT ADC_TypeDef *ADC1; +#endif /*_ADC1 */ + +#ifdef _ADC2 + EXT ADC_TypeDef *ADC2; +#endif /*_ADC2 */ + +#ifdef _TIM1 + EXT TIM_TypeDef *TIM1; +#endif /*_TIM1 */ + +#ifdef _SPI1 + EXT SPI_TypeDef *SPI1; +#endif /*_SPI1 */ + +#ifdef _TIM8 + EXT TIM_TypeDef *TIM8; +#endif /*_TIM8 */ + +#ifdef _USART1 + EXT USART_TypeDef *USART1; +#endif /*_USART1 */ + +#ifdef _ADC3 + EXT ADC_TypeDef *ADC3; +#endif /*_ADC3 */ + +#ifdef _SDIO + EXT SDIO_TypeDef *SDIO; +#endif /*_SDIO */ + +#ifdef _DMA + EXT DMA_TypeDef *DMA1; + EXT DMA_TypeDef *DMA2; +#endif /*_DMA */ + +#ifdef _DMA1_Channel1 + EXT DMA_Channel_TypeDef *DMA1_Channel1; +#endif /*_DMA1_Channel1 */ + +#ifdef _DMA1_Channel2 + EXT DMA_Channel_TypeDef *DMA1_Channel2; +#endif /*_DMA1_Channel2 */ + +#ifdef _DMA1_Channel3 + EXT DMA_Channel_TypeDef *DMA1_Channel3; +#endif /*_DMA1_Channel3 */ + +#ifdef _DMA1_Channel4 + EXT DMA_Channel_TypeDef *DMA1_Channel4; +#endif /*_DMA1_Channel4 */ + +#ifdef _DMA1_Channel5 + EXT DMA_Channel_TypeDef *DMA1_Channel5; +#endif /*_DMA1_Channel5 */ + +#ifdef _DMA1_Channel6 + EXT DMA_Channel_TypeDef *DMA1_Channel6; +#endif /*_DMA1_Channel6 */ + +#ifdef _DMA1_Channel7 + EXT DMA_Channel_TypeDef *DMA1_Channel7; +#endif /*_DMA1_Channel7 */ + +#ifdef _DMA2_Channel1 + EXT DMA_Channel_TypeDef *DMA2_Channel1; +#endif /*_DMA2_Channel1 */ + +#ifdef _DMA2_Channel2 + EXT DMA_Channel_TypeDef *DMA2_Channel2; +#endif /*_DMA2_Channel2 */ + +#ifdef _DMA2_Channel3 + EXT DMA_Channel_TypeDef *DMA2_Channel3; +#endif /*_DMA2_Channel3 */ + +#ifdef _DMA2_Channel4 + EXT DMA_Channel_TypeDef *DMA2_Channel4; +#endif /*_DMA2_Channel4 */ + +#ifdef _DMA2_Channel5 + EXT DMA_Channel_TypeDef *DMA2_Channel5; +#endif /*_DMA2_Channel5 */ + +#ifdef _RCC + EXT RCC_TypeDef *RCC; +#endif /*_RCC */ + +#ifdef _CRC + EXT CRC_TypeDef *CRC; +#endif /*_CRC */ + +#ifdef _FLASH + EXT FLASH_TypeDef *FLASH; + EXT OB_TypeDef *OB; +#endif /*_FLASH */ + +#ifdef _FSMC + EXT FSMC_Bank1_TypeDef *FSMC_Bank1; + EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E; + EXT FSMC_Bank2_TypeDef *FSMC_Bank2; + EXT FSMC_Bank3_TypeDef *FSMC_Bank3; + EXT FSMC_Bank4_TypeDef *FSMC_Bank4; +#endif /*_FSMC */ + +#ifdef _DBGMCU + EXT DBGMCU_TypeDef *DBGMCU; +#endif /*_DBGMCU */ + +#ifdef _SysTick + EXT SysTick_TypeDef *SysTick; +#endif /*_SysTick */ + +#ifdef _NVIC + EXT NVIC_TypeDef *NVIC; + EXT SCB_TypeDef *SCB; +#endif /*_NVIC */ + +#endif /* DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((u32)0xFFFFFFFF) /* Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((u8)0xFF) /* General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((u8)0x01) /* RESET bit */ + + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((u16)0x0001) /* Low-Power Deepsleep */ +#define PWR_CR_PDDS ((u16)0x0002) /* Power Down Deepsleep */ +#define PWR_CR_CWUF ((u16)0x0004) /* Clear Wakeup Flag */ +#define PWR_CR_CSBF ((u16)0x0008) /* Clear Standby Flag */ +#define PWR_CR_PVDE ((u16)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((u16)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((u16)0x0020) /* Bit 0 */ +#define PWR_CR_PLS_1 ((u16)0x0040) /* Bit 1 */ +#define PWR_CR_PLS_2 ((u16)0x0080) /* Bit 2 */ + +/* PVD level configuration */ +#define PWR_CR_PLS_2V2 ((u16)0x0000) /* PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((u16)0x0020) /* PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((u16)0x0040) /* PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((u16)0x0060) /* PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((u16)0x0080) /* PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((u16)0x00A0) /* PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((u16)0x00C0) /* PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((u16)0x00E0) /* PVD level 2.9V */ + +#define PWR_CR_DBP ((u16)0x0100) /* Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((u16)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((u16)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((u16)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((u16)0x0100) /* Enable WKUP pin */ + + + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((u16)0xFFFF) /* Backup data */ + + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((u16)0xFFFF) /* Backup data */ + + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((u16)0xFFFF) /* Backup data */ + + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((u16)0x007F) /* Calibration value */ +#define BKP_RTCCR_CCO ((u16)0x0080) /* Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((u16)0x0100) /* Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((u16)0x0200) /* Alarm or Second Output Selection */ + + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((u8)0x01) /* TAMPER pin enable */ +#define BKP_CR_TPAL ((u8)0x02) /* TAMPER pin active level */ + + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((u16)0x0001) /* Clear Tamper event */ +#define BKP_CSR_CTI ((u16)0x0002) /* Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((u16)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((u16)0x0100) /* Tamper Event Flag */ +#define BKP_CSR_TIF ((u16)0x0200) /* Tamper Interrupt Flag */ + + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((u32)0x00000001) /* Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((u32)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((u32)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((u32)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((u32)0x00010000) /* External High Speed clock enable */ +#define RCC_CR_HSERDY ((u32)0x00020000) /* External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((u32)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CR_CSSON ((u32)0x00080000) /* Clock Security System enable */ +#define RCC_CR_PLLON ((u32)0x01000000) /* PLL enable */ +#define RCC_CR_PLLRDY ((u32)0x02000000) /* PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +#define RCC_CFGR_SW ((u32)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((u32)0x00000001) /* Bit 0 */ +#define RCC_CFGR_SW_1 ((u32)0x00000002) /* Bit 1 */ + +/* SW configuration */ +#define RCC_CFGR_SW_HSI ((u32)0x00000000) /* HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((u32)0x00000001) /* HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((u32)0x00000002) /* PLL selected as system clock */ + +#define RCC_CFGR_SWS ((u32)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((u32)0x00000004) /* Bit 0 */ +#define RCC_CFGR_SWS_1 ((u32)0x00000008) /* Bit 1 */ + +/* SWS configuration */ +#define RCC_CFGR_SWS_HSI ((u32)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((u32)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((u32)0x00000008) /* PLL used as system clock */ + +#define RCC_CFGR_HPRE ((u32)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((u32)0x00000010) /* Bit 0 */ +#define RCC_CFGR_HPRE_1 ((u32)0x00000020) /* Bit 1 */ +#define RCC_CFGR_HPRE_2 ((u32)0x00000040) /* Bit 2 */ +#define RCC_CFGR_HPRE_3 ((u32)0x00000080) /* Bit 3 */ + +/* HPRE configuration */ +#define RCC_CFGR_HPRE_DIV1 ((u32)0x00000000) /* SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((u32)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((u32)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((u32)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((u32)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((u32)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((u32)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((u32)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((u32)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_CFGR_PPRE1 ((u32)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((u32)0x00000100) /* Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((u32)0x00000200) /* Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((u32)0x00000400) /* Bit 2 */ + +/* PPRE1 configuration */ +#define RCC_CFGR_PPRE1_DIV1 ((u32)0x00000000) /* HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((u32)0x00000400) /* HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((u32)0x00000500) /* HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((u32)0x00000600) /* HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((u32)0x00000700) /* HCLK divided by 16 */ + +#define RCC_CFGR_PPRE2 ((u32)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((u32)0x00000800) /* Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((u32)0x00001000) /* Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((u32)0x00002000) /* Bit 2 */ + +/* PPRE2 configuration */ +#define RCC_CFGR_PPRE2_DIV1 ((u32)0x00000000) /* HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((u32)0x00002000) /* HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((u32)0x00002800) /* HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((u32)0x00003000) /* HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((u32)0x00003800) /* HCLK divided by 16 */ + +#define RCC_CFGR_ADCPRE ((u32)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((u32)0x00004000) /* Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((u32)0x00008000) /* Bit 1 */ + +/* ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_DIV2 ((u32)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((u32)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((u32)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((u32)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((u32)0x00010000) /* PLL entry clock source */ +#define RCC_CFGR_PLLXTPRE ((u32)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_CFGR_PLLMULL ((u32)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((u32)0x00040000) /* Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((u32)0x00080000) /* Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((u32)0x00100000) /* Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((u32)0x00200000) /* Bit 3 */ + +/* PLLMUL configuration */ +#define RCC_CFGR_PLLMULL2 ((u32)0x00000000) /* PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3 ((u32)0x00040000) /* PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4 ((u32)0x00080000) /* PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5 ((u32)0x000C0000) /* PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6 ((u32)0x00100000) /* PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7 ((u32)0x00140000) /* PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8 ((u32)0x00180000) /* PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9 ((u32)0x001C0000) /* PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10 ((u32)0x00200000) /* PLL input clock10 */ +#define RCC_CFGR_PLLMULL11 ((u32)0x00240000) /* PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12 ((u32)0x00280000) /* PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13 ((u32)0x002C0000) /* PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14 ((u32)0x00300000) /* PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15 ((u32)0x00340000) /* PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16 ((u32)0x00380000) /* PLL input clock*16 */ + +#define RCC_CFGR_USBPRE ((u32)0x00400000) /* USB prescaler */ + +#define RCC_CFGR_MCO ((u32)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 ((u32)0x01000000) /* Bit 0 */ +#define RCC_CFGR_MCO_1 ((u32)0x02000000) /* Bit 1 */ +#define RCC_CFGR_MCO_2 ((u32)0x04000000) /* Bit 2 */ + +/* MCO configuration */ +#define RCC_CFGR_MCO_NOCLOCK ((u32)0x00000000) /* No clock */ +#define RCC_CFGR_MCO_SYSCLK ((u32)0x04000000) /* System clock selected */ +#define RCC_CFGR_MCO_HSI ((u32)0x05000000) /* Internal 8 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCO_HSE ((u32)0x06000000) /* External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCO_PLL ((u32)0x07000000) /* PLL clock divided by 2 selected*/ + + +/******************* Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((u32)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((u32)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((u32)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((u32)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((u32)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((u32)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((u32)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((u32)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((u32)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((u32)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((u32)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((u32)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((u32)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((u32)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((u32)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((u32)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((u32)0x00800000) /* Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((u16)0x0001) /* Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((u16)0x0004) /* I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((u16)0x0008) /* IO port B reset */ +#define RCC_APB2RSTR_IOPCRST ((u16)0x0010) /* IO port C reset */ +#define RCC_APB2RSTR_IOPDRST ((u16)0x0020) /* IO port D reset */ +#define RCC_APB2RSTR_IOPERST ((u16)0x0040) /* IO port E reset */ +#define RCC_APB2RSTR_IOPFRST ((u16)0x0080) /* IO port F reset */ +#define RCC_APB2RSTR_IOPGRST ((u16)0x0100) /* IO port G reset */ +#define RCC_APB2RSTR_ADC1RST ((u16)0x0200) /* ADC 1 interface reset */ +#define RCC_APB2RSTR_ADC2RST ((u16)0x0400) /* ADC 2 interface reset */ +#define RCC_APB2RSTR_TIM1RST ((u16)0x0800) /* TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((u16)0x1000) /* SPI 1 reset */ +#define RCC_APB2RSTR_TIM8RST ((u16)0x2000) /* TIM8 Timer reset */ +#define RCC_APB2RSTR_USART1RST ((u16)0x4000) /* USART1 reset */ +#define RCC_APB2RSTR_ADC3RST ((u16)0x8000) /* ADC3 interface reset */ + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((u32)0x00000001) /* Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((u32)0x00000002) /* Timer 3 reset */ +#define RCC_APB1RSTR_TIM4RST ((u32)0x00000004) /* Timer 4 reset */ +#define RCC_APB1RSTR_TIM5RST ((u32)0x00000008) /* Timer 5 reset */ +#define RCC_APB1RSTR_TIM6RST ((u32)0x00000010) /* Timer 6 reset */ +#define RCC_APB1RSTR_TIM7RST ((u32)0x00000020) /* Timer 7 reset */ +#define RCC_APB1RSTR_WWDGRST ((u32)0x00000800) /* Window Watchdog reset */ +#define RCC_APB1RSTR_SPI2RST ((u32)0x00004000) /* SPI 2 reset */ +#define RCC_APB1RSTR_SPI3RST ((u32)0x00008000) /* SPI 3 reset */ +#define RCC_APB1RSTR_USART2RST ((u32)0x00020000) /* USART 2 reset */ +#define RCC_APB1RSTR_USART3RST ((u32)0x00040000) /* RUSART 3 reset */ +#define RCC_APB1RSTR_UART4RST ((u32)0x00080000) /* USART 4 reset */ +#define RCC_APB1RSTR_UART5RST ((u32)0x00100000) /* USART 5 reset */ +#define RCC_APB1RSTR_I2C1RST ((u32)0x00200000) /* I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST ((u32)0x00400000) /* I2C 2 reset */ +#define RCC_APB1RSTR_USBRST ((u32)0x00800000) /* USB reset */ +#define RCC_APB1RSTR_CANRST ((u32)0x02000000) /* CAN reset */ +#define RCC_APB1RSTR_BKPRST ((u32)0x08000000) /* Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((u32)0x10000000) /* Power interface reset */ +#define RCC_APB1RSTR_DACRST ((u32)0x20000000) /* DAC interface reset */ + + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((u16)0x0001) /* DMA1 clock enable */ +#define RCC_AHBENR_DMA2EN ((u16)0x0002) /* DMA2 clock enable */ +#define RCC_AHBENR_SRAMEN ((u16)0x0004) /* SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((u16)0x0010) /* FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((u16)0x0040) /* CRC clock enable */ +#define RCC_AHBENR_FSMCEN ((u16)0x0100) /* FSMC clock enable */ +#define RCC_AHBENR_SDIOEN ((u16)0x0400) /* SDIO clock enable */ + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((u16)0x0001) /* Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((u16)0x0004) /* I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((u16)0x0008) /* I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((u16)0x0010) /* I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((u16)0x0020) /* I/O port D clock enable */ +#define RCC_APB2ENR_IOPEEN ((u16)0x0040) /* I/O port E clock enable */ +#define RCC_APB2ENR_IOPFEN ((u16)0x0080) /* I/O port F clock enable */ +#define RCC_APB2ENR_IOPGEN ((u16)0x0100) /* I/O port G clock enable */ +#define RCC_APB2ENR_ADC1EN ((u16)0x0200) /* ADC 1 interface clock enable */ +#define RCC_APB2ENR_ADC2EN ((u16)0x0400) /* ADC 2 interface clock enable */ +#define RCC_APB2ENR_TIM1EN ((u16)0x0800) /* TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((u16)0x1000) /* SPI 1 clock enable */ +#define RCC_APB2ENR_TIM8EN ((u16)0x2000) /* TIM8 Timer clock enable */ +#define RCC_APB2ENR_USART1EN ((u16)0x4000) /* USART1 clock enable */ +#define RCC_APB2ENR_ADC3EN ((u16)0x8000) /* DMA1 clock enable */ + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((u32)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((u32)0x00000002) /* Timer 3 clock enable */ +#define RCC_APB1ENR_TIM4EN ((u32)0x00000004) /* Timer 4 clock enable */ +#define RCC_APB1ENR_TIM5EN ((u32)0x00000008) /* Timer 5 clock enable */ +#define RCC_APB1ENR_TIM6EN ((u32)0x00000010) /* Timer 6 clock enable */ +#define RCC_APB1ENR_TIM7EN ((u32)0x00000020) /* Timer 7 clock enable */ +#define RCC_APB1ENR_WWDGEN ((u32)0x00000800) /* Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN ((u32)0x00004000) /* SPI 2 clock enable */ +#define RCC_APB1ENR_SPI3EN ((u32)0x00008000) /* SPI 3 clock enable */ +#define RCC_APB1ENR_USART2EN ((u32)0x00020000) /* USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN ((u32)0x00040000) /* USART 3 clock enable */ +#define RCC_APB1ENR_UART4EN ((u32)0x00080000) /* USART 4 clock enable */ +#define RCC_APB1ENR_UART5EN ((u32)0x00100000) /* USART 5 clock enable */ +#define RCC_APB1ENR_I2C1EN ((u32)0x00200000) /* I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN ((u32)0x00400000) /* I2C 2 clock enable */ +#define RCC_APB1ENR_USBEN ((u32)0x00800000) /* USB clock enable */ +#define RCC_APB1ENR_CANEN ((u32)0x02000000) /* CAN clock enable */ +#define RCC_APB1ENR_BKPEN ((u32)0x08000000) /* Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((u32)0x10000000) /* Power interface clock enable */ +#define RCC_APB1ENR_DACEN ((u32)0x20000000) /* DAC interface clock enable */ + + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((u32)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((u32)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((u32)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((u32)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((u32)0x00000100) /* Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((u32)0x00000200) /* Bit 1 */ +/* RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((u32)0x00000000) /* No clock */ +#define RCC_BDCR_RTCSEL_LSE ((u32)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((u32)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((u32)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((u32)0x00008000) /* RTC clock enable */ +#define RCC_BDCR_BDRST ((u32)0x00010000) /* Backup domain software reset */ + + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((u32)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((u32)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((u32)0x01000000) /* Remove reset flag */ +#define RCC_CSR_PINRSTF ((u32)0x04000000) /* PIN reset flag */ +#define RCC_CSR_PORRSTF ((u32)0x08000000) /* POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((u32)0x10000000) /* Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((u32)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((u32)0x40000000) /* Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((u32)0x80000000) /* Low-Power reset flag */ + + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function IO */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((u32)0x33333333) /* Port x mode bits */ + +#define GPIO_CRL_MODE0 ((u32)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((u32)0x00000001) /* Bit 0 */ +#define GPIO_CRL_MODE0_1 ((u32)0x00000002) /* Bit 1 */ + +#define GPIO_CRL_MODE1 ((u32)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((u32)0x00000010) /* Bit 0 */ +#define GPIO_CRL_MODE1_1 ((u32)0x00000020) /* Bit 1 */ + +#define GPIO_CRL_MODE2 ((u32)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((u32)0x00000100) /* Bit 0 */ +#define GPIO_CRL_MODE2_1 ((u32)0x00000200) /* Bit 1 */ + +#define GPIO_CRL_MODE3 ((u32)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((u32)0x00001000) /* Bit 0 */ +#define GPIO_CRL_MODE3_1 ((u32)0x00002000) /* Bit 1 */ + +#define GPIO_CRL_MODE4 ((u32)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((u32)0x00010000) /* Bit 0 */ +#define GPIO_CRL_MODE4_1 ((u32)0x00020000) /* Bit 1 */ + +#define GPIO_CRL_MODE5 ((u32)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((u32)0x00100000) /* Bit 0 */ +#define GPIO_CRL_MODE5_1 ((u32)0x00200000) /* Bit 1 */ + +#define GPIO_CRL_MODE6 ((u32)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((u32)0x01000000) /* Bit 0 */ +#define GPIO_CRL_MODE6_1 ((u32)0x02000000) /* Bit 1 */ + +#define GPIO_CRL_MODE7 ((u32)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((u32)0x10000000) /* Bit 0 */ +#define GPIO_CRL_MODE7_1 ((u32)0x20000000) /* Bit 1 */ + + +#define GPIO_CRL_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((u32)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((u32)0x00000004) /* Bit 0 */ +#define GPIO_CRL_CNF0_1 ((u32)0x00000008) /* Bit 1 */ + +#define GPIO_CRL_CNF1 ((u32)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((u32)0x00000040) /* Bit 0 */ +#define GPIO_CRL_CNF1_1 ((u32)0x00000080) /* Bit 1 */ + +#define GPIO_CRL_CNF2 ((u32)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((u32)0x00000400) /* Bit 0 */ +#define GPIO_CRL_CNF2_1 ((u32)0x00000800) /* Bit 1 */ + +#define GPIO_CRL_CNF3 ((u32)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((u32)0x00004000) /* Bit 0 */ +#define GPIO_CRL_CNF3_1 ((u32)0x00008000) /* Bit 1 */ + +#define GPIO_CRL_CNF4 ((u32)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((u32)0x00040000) /* Bit 0 */ +#define GPIO_CRL_CNF4_1 ((u32)0x00080000) /* Bit 1 */ + +#define GPIO_CRL_CNF5 ((u32)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((u32)0x00400000) /* Bit 0 */ +#define GPIO_CRL_CNF5_1 ((u32)0x00800000) /* Bit 1 */ + +#define GPIO_CRL_CNF6 ((u32)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((u32)0x04000000) /* Bit 0 */ +#define GPIO_CRL_CNF6_1 ((u32)0x08000000) /* Bit 1 */ + +#define GPIO_CRL_CNF7 ((u32)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((u32)0x40000000) /* Bit 0 */ +#define GPIO_CRL_CNF7_1 ((u32)0x80000000) /* Bit 1 */ + + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((u32)0x33333333) /* Port x mode bits */ + +#define GPIO_CRH_MODE8 ((u32)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((u32)0x00000001) /* Bit 0 */ +#define GPIO_CRH_MODE8_1 ((u32)0x00000002) /* Bit 1 */ + +#define GPIO_CRH_MODE9 ((u32)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((u32)0x00000010) /* Bit 0 */ +#define GPIO_CRH_MODE9_1 ((u32)0x00000020) /* Bit 1 */ + +#define GPIO_CRH_MODE10 ((u32)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((u32)0x00000100) /* Bit 0 */ +#define GPIO_CRH_MODE10_1 ((u32)0x00000200) /* Bit 1 */ + +#define GPIO_CRH_MODE11 ((u32)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((u32)0x00001000) /* Bit 0 */ +#define GPIO_CRH_MODE11_1 ((u32)0x00002000) /* Bit 1 */ + +#define GPIO_CRH_MODE12 ((u32)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((u32)0x00010000) /* Bit 0 */ +#define GPIO_CRH_MODE12_1 ((u32)0x00020000) /* Bit 1 */ + +#define GPIO_CRH_MODE13 ((u32)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((u32)0x00100000) /* Bit 0 */ +#define GPIO_CRH_MODE13_1 ((u32)0x00200000) /* Bit 1 */ + +#define GPIO_CRH_MODE14 ((u32)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((u32)0x01000000) /* Bit 0 */ +#define GPIO_CRH_MODE14_1 ((u32)0x02000000) /* Bit 1 */ + +#define GPIO_CRH_MODE15 ((u32)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((u32)0x10000000) /* Bit 0 */ +#define GPIO_CRH_MODE15_1 ((u32)0x20000000) /* Bit 1 */ + + +#define GPIO_CRH_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((u32)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((u32)0x00000004) /* Bit 0 */ +#define GPIO_CRH_CNF8_1 ((u32)0x00000008) /* Bit 1 */ + +#define GPIO_CRH_CNF9 ((u32)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((u32)0x00000040) /* Bit 0 */ +#define GPIO_CRH_CNF9_1 ((u32)0x00000080) /* Bit 1 */ + +#define GPIO_CRH_CNF10 ((u32)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((u32)0x00000400) /* Bit 0 */ +#define GPIO_CRH_CNF10_1 ((u32)0x00000800) /* Bit 1 */ + +#define GPIO_CRH_CNF11 ((u32)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((u32)0x00004000) /* Bit 0 */ +#define GPIO_CRH_CNF11_1 ((u32)0x00008000) /* Bit 1 */ + +#define GPIO_CRH_CNF12 ((u32)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((u32)0x00040000) /* Bit 0 */ +#define GPIO_CRH_CNF12_1 ((u32)0x00080000) /* Bit 1 */ + +#define GPIO_CRH_CNF13 ((u32)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((u32)0x00400000) /* Bit 0 */ +#define GPIO_CRH_CNF13_1 ((u32)0x00800000) /* Bit 1 */ + +#define GPIO_CRH_CNF14 ((u32)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((u32)0x04000000) /* Bit 0 */ +#define GPIO_CRH_CNF14_1 ((u32)0x08000000) /* Bit 1 */ + +#define GPIO_CRH_CNF15 ((u32)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((u32)0x40000000) /* Bit 0 */ +#define GPIO_CRH_CNF15_1 ((u32)0x80000000) /* Bit 1 */ + + +/******************* Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((u16)0x0001) /* Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((u16)0x0002) /* Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((u16)0x0004) /* Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((u16)0x0008) /* Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((u16)0x0010) /* Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((u16)0x0020) /* Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((u16)0x0040) /* Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((u16)0x0080) /* Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((u16)0x0100) /* Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((u16)0x0200) /* Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((u16)0x0400) /* Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((u16)0x0800) /* Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((u16)0x1000) /* Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((u16)0x2000) /* Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((u16)0x4000) /* Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((u16)0x8000) /* Port input data, bit 15 */ + + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((u16)0x0001) /* Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((u16)0x0002) /* Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((u16)0x0004) /* Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((u16)0x0008) /* Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((u16)0x0010) /* Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((u16)0x0020) /* Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((u16)0x0040) /* Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((u16)0x0080) /* Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((u16)0x0100) /* Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((u16)0x0200) /* Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((u16)0x0400) /* Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((u16)0x0800) /* Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((u16)0x1000) /* Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((u16)0x2000) /* Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((u16)0x4000) /* Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((u16)0x8000) /* Port output data, bit 15 */ + + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((u32)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((u32)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((u32)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((u32)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((u32)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((u32)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((u32)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((u32)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((u32)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((u32)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((u32)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((u32)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((u32)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((u32)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((u32)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((u32)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((u32)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((u32)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((u32)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((u32)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((u32)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((u32)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((u32)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((u32)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((u32)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((u32)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((u32)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((u32)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((u32)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((u32)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((u32)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((u32)0x80000000) /* Port x Reset bit 15 */ + + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((u16)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((u16)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((u16)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((u16)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((u16)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((u16)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((u16)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((u16)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((u16)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((u16)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((u16)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((u16)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((u16)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((u16)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((u16)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((u16)0x8000) /* Port x Reset bit 15 */ + + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((u32)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((u32)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((u32)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((u32)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((u32)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((u32)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((u32)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((u32)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((u32)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((u32)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((u32)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((u32)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((u32)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((u32)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((u32)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((u32)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((u32)0x00010000) /* Lock key */ + + +/*----------------------------------------------------------------------------*/ + + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((u8)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((u8)0x01) /* Bit 0 */ +#define AFIO_EVCR_PIN_1 ((u8)0x02) /* Bit 1 */ +#define AFIO_EVCR_PIN_2 ((u8)0x04) /* Bit 2 */ +#define AFIO_EVCR_PIN_3 ((u8)0x08) /* Bit 3 */ + +/* PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((u8)0x00) /* Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((u8)0x01) /* Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((u8)0x02) /* Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((u8)0x03) /* Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((u8)0x04) /* Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((u8)0x05) /* Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((u8)0x06) /* Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((u8)0x07) /* Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((u8)0x08) /* Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((u8)0x09) /* Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((u8)0x0A) /* Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((u8)0x0B) /* Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((u8)0x0C) /* Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((u8)0x0D) /* Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((u8)0x0E) /* Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((u8)0x0F) /* Pin 15 selected */ + +#define AFIO_EVCR_PORT ((u8)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((u8)0x10) /* Bit 0 */ +#define AFIO_EVCR_PORT_1 ((u8)0x20) /* Bit 1 */ +#define AFIO_EVCR_PORT_2 ((u8)0x40) /* Bit 2 */ + +/* PORT configuration */ +#define AFIO_EVCR_PORT_PA ((u8)0x00) /* Port A selected */ +#define AFIO_EVCR_PORT_PB ((u8)0x10) /* Port B selected */ +#define AFIO_EVCR_PORT_PC ((u8)0x20) /* Port C selected */ +#define AFIO_EVCR_PORT_PD ((u8)0x30) /* Port D selected */ +#define AFIO_EVCR_PORT_PE ((u8)0x40) /* Port E selected */ + +#define AFIO_EVCR_EVOE ((u8)0x80) /* Event Output Enable */ + + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1 _REMAP ((u32)0x00000001) /* SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((u32)0x00000002) /* I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((u32)0x00000004) /* USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((u32)0x00000008) /* USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((u32)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((u32)0x00000010) /* Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((u32)0x00000020) /* Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((u32)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((u32)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((u32)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((u32)0x00000040) /* Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((u32)0x00000080) /* Bit 1 */ + +/* TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((u32)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((u32)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((u32)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((u32)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((u32)0x00000100) /* Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((u32)0x00000200) /* Bit 1 */ + +/* TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((u32)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((u32)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((u32)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((u32)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((u32)0x00000400) /* Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((u32)0x00000800) /* Bit 1 */ + +/* TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((u32)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((u32)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((u32)0x00001000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +#define AFIO_MAPR_CAN_REMAP ((u32)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((u32)0x00002000) /* Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((u32)0x00004000) /* Bit 1 */ + +/* CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((u32)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((u32)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((u32)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((u32)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((u32)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((u32)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((u32)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((u32)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((u32)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_MAPR_SWJ_CFG ((u32)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((u32)0x01000000) /* Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((u32)0x02000000) /* Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((u32)0x04000000) /* Bit 2 */ + +/* SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_RESET ((u32)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((u32)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((u32)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((u32)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((u16)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((u16)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((u16)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((u16)0xF000) /* EXTI 3 configuration */ + +/* EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((u16)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((u16)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((u16)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((u16)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((u16)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((u16)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((u16)0x0006) /* PG[0] pin */ + +/* EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((u16)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((u16)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((u16)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((u16)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((u16)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((u16)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((u16)0x0060) /* PG[1] pin */ + +/* EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((u16)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((u16)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((u16)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((u16)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((u16)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((u16)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((u16)0x0600) /* PG[2] pin */ + +/* EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((u16)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((u16)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((u16)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((u16)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((u16)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((u16)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((u16)0x6000) /* PG[3] pin */ + + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((u16)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((u16)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((u16)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((u16)0xF000) /* EXTI 7 configuration */ + +/* EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((u16)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((u16)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((u16)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((u16)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((u16)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((u16)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((u16)0x0006) /* PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((u16)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((u16)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((u16)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((u16)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((u16)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((u16)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((u16)0x0060) /* PG[5] pin */ + +/* EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((u16)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((u16)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((u16)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((u16)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((u16)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((u16)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((u16)0x0600) /* PG[6] pin */ + +/* EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((u16)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((u16)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((u16)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((u16)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((u16)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((u16)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((u16)0x6000) /* PG[7] pin */ + + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((u16)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((u16)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((u16)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((u16)0xF000) /* EXTI 11 configuration */ + +/* EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((u16)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((u16)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((u16)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((u16)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((u16)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((u16)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((u16)0x0006) /* PG[8] pin */ + +/* EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((u16)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((u16)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((u16)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((u16)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((u16)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((u16)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((u16)0x0060) /* PG[9] pin */ + +/* EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((u16)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((u16)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((u16)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((u16)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((u16)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((u16)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((u16)0x0600) /* PG[10] pin */ + +/* EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((u16)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((u16)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((u16)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((u16)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((u16)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((u16)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((u16)0x6000) /* PG[11] pin */ + + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((u16)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((u16)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((u16)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((u16)0xF000) /* EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((u16)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((u16)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((u16)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((u16)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((u16)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((u16)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((u16)0x0006) /* PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((u16)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((u16)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((u16)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((u16)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((u16)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((u16)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((u16)0x0060) /* PG[13] pin */ + +/* EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((u16)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((u16)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((u16)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((u16)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((u16)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((u16)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((u16)0x0600) /* PG[14] pin */ + +/* EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((u16)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((u16)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((u16)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((u16)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((u16)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((u16)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((u16)0x6000) /* PG[15] pin */ + + + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */ +#define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */ +#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */ + + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ + + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */ + + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */ + + + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((u32)0xFFFFFFFF) /* Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ISER_SETENA_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ISER_SETENA_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ISER_SETENA_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ISER_SETENA_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ISER_SETENA_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ISER_SETENA_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ISER_SETENA_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ISER_SETENA_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ISER_SETENA_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ISER_SETENA_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ISER_SETENA_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ISER_SETENA_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ISER_SETENA_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ISER_SETENA_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ISER_SETENA_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ISER_SETENA_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ISER_SETENA_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ISER_SETENA_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ISER_SETENA_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ISER_SETENA_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ISER_SETENA_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ISER_SETENA_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ISER_SETENA_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ISER_SETENA_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ISER_SETENA_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ISER_SETENA_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ISER_SETENA_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ISER_SETENA_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ISER_SETENA_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ISER_SETENA_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ISER_SETENA_31 ((u32)0x80000000) /* bit 31 */ + + + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((u32)0xFFFFFFFF) /* Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ICER_CLRENA_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ICER_CLRENA_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ICER_CLRENA_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ICER_CLRENA_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ICER_CLRENA_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ICER_CLRENA_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ICER_CLRENA_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ICER_CLRENA_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ICER_CLRENA_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ICER_CLRENA_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ICER_CLRENA_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ICER_CLRENA_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ICER_CLRENA_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ICER_CLRENA_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ICER_CLRENA_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ICER_CLRENA_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ICER_CLRENA_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ICER_CLRENA_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ICER_CLRENA_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ICER_CLRENA_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ICER_CLRENA_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ICER_CLRENA_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ICER_CLRENA_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ICER_CLRENA_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ICER_CLRENA_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ICER_CLRENA_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ICER_CLRENA_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ICER_CLRENA_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ICER_CLRENA_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ICER_CLRENA_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ICER_CLRENA_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((u32)0xFFFFFFFF) /* Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((u32)0xFFFFFFFF) /* Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((u32)0xFFFFFFFF) /* Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((u32)0x00000001) /* bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((u32)0x00000002) /* bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((u32)0x00000004) /* bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((u32)0x00000008) /* bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((u32)0x00000010) /* bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((u32)0x00000020) /* bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((u32)0x00000040) /* bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((u32)0x00000080) /* bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((u32)0x00000100) /* bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((u32)0x00000200) /* bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((u32)0x00000400) /* bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((u32)0x00000800) /* bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((u32)0x00001000) /* bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((u32)0x00002000) /* bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((u32)0x00004000) /* bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((u32)0x00008000) /* bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((u32)0x00010000) /* bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((u32)0x00020000) /* bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((u32)0x00040000) /* bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((u32)0x00080000) /* bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((u32)0x00100000) /* bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((u32)0x00200000) /* bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((u32)0x00400000) /* bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((u32)0x00800000) /* bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((u32)0x01000000) /* bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((u32)0x02000000) /* bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((u32)0x04000000) /* bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((u32)0x08000000) /* bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((u32)0x10000000) /* bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((u32)0x20000000) /* bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((u32)0x40000000) /* bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((u32)0x80000000) /* bit 31 */ + + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((u32)0x000000FF) /* Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((u32)0x0000FF00) /* Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((u32)0x00FF0000) /* Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((u32)0xFF000000) /* Priority of interrupt 3 */ + + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((u32)0x000000FF) /* Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((u32)0x0000FF00) /* Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((u32)0x00FF0000) /* Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((u32)0xFF000000) /* Priority of interrupt 7 */ + + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((u32)0x000000FF) /* Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((u32)0x0000FF00) /* Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((u32)0x00FF0000) /* Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((u32)0xFF000000) /* Priority of interrupt 11 */ + + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((u32)0x000000FF) /* Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((u32)0x0000FF00) /* Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((u32)0x00FF0000) /* Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((u32)0xFF000000) /* Priority of interrupt 15 */ + + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((u32)0x000000FF) /* Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((u32)0x0000FF00) /* Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((u32)0x00FF0000) /* Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((u32)0xFF000000) /* Priority of interrupt 19 */ + + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((u32)0x000000FF) /* Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((u32)0x0000FF00) /* Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((u32)0x00FF0000) /* Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((u32)0xFF000000) /* Priority of interrupt 23 */ + + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((u32)0x000000FF) /* Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((u32)0x0000FF00) /* Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((u32)0x00FF0000) /* Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((u32)0xFF000000) /* Priority of interrupt 27 */ + + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((u32)0x000000FF) /* Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((u32)0x0000FF00) /* Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((u32)0x00FF0000) /* Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((u32)0xFF000000) /* Priority of interrupt 31 */ + + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((u32)0x0000000F) /* Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((u32)0x0000FFF0) /* Number of processor within family */ +#define SCB_CPUID_Constant ((u32)0x000F0000) /* Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((u32)0x00F00000) /* Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((u32)0xFF000000) /* Implementer code. ARM is 0x41 */ + + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((u32)0x000001FF) /* Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((u32)0x00000800) /* All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((u32)0x003FF000) /* Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((u32)0x00400000) /* Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((u32)0x00800000) /* It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((u32)0x02000000) /* Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((u32)0x04000000) /* Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((u32)0x08000000) /* Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((u32)0x10000000) /* Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((u32)0x80000000) /* Set pending NMI bit */ + + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((u32)0x1FFFFF80) /* Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((u32)0x20000000) /* Table base in code(0) or RAM(1) */ + + +/****************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((u32)0x00000001) /* System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((u32)0x00000002) /* Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((u32)0x00000004) /* Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((u32)0x00000700) /* PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((u32)0x00000100) /* Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((u32)0x00000200) /* Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((u32)0x00000400) /* Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((u32)0x00000000) /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((u32)0x00000100) /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((u32)0x00000200) /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((u32)0x00000300) /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((u32)0x00000400) /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((u32)0x00000500) /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((u8)0x02) /* Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((u8)0x04) /* Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((u8)0x10) /* Wake up from WFE */ + + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((u16)0x0001) /* Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((u16)0x0002) /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((u16)0x0008) /* Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((u16)0x0010) /* Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((u16)0x0100) /* Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((u16)0x0200) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((u32)0x000000FF) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((u32)0x0000FF00) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((u32)0x00FF0000) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((u32)0xFF000000) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((u32)0x00000001) /* MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((u32)0x00000002) /* BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((u32)0x00000008) /* UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((u32)0x00000080) /* SVCall is active */ +#define SCB_SHCSR_MONITORACT ((u32)0x00000100) /* Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((u32)0x00000400) /* PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((u32)0x00000800) /* SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((u32)0x00001000) /* Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((u32)0x00002000) /* MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((u32)0x00004000) /* Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((u32)0x00008000) /* SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((u32)0x00010000) /* MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((u32)0x00020000) /* Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((u32)0x00040000) /* UsageFault enable */ + + +/******************* Bit definition for SCB_CFSR register *******************/ +/* MFSR */ +#define SCB_CFSR_IACCVIOL ((u32)0x00000001) /* Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((u32)0x00000002) /* Data access violation */ +#define SCB_CFSR_MUNSTKERR ((u32)0x00000008) /* Unstacking error */ +#define SCB_CFSR_MSTKERR ((u32)0x00000010) /* Stacking error */ +#define SCB_CFSR_MMARVALID ((u32)0x00000080) /* Memory Manage Address Register address valid flag */ +/* BFSR */ +#define SCB_CFSR_IBUSERR ((u32)0x00000100) /* Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((u32)0x00000200) /* Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((u32)0x00000400) /* Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((u32)0x00000800) /* Unstacking error */ +#define SCB_CFSR_STKERR ((u32)0x00001000) /* Stacking error */ +#define SCB_CFSR_BFARVALID ((u32)0x00008000) /* Bus Fault Address Register address valid flag */ +/* UFSR */ +#define SCB_CFSR_UNDEFINSTR ((u32)0x00010000) /* The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((u32)0x00020000) /* Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((u32)0x00040000) /* Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((u32)0x00080000) /* Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((u32)0x01000000) /* Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((u32)0x02000000) /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((u32)0x00000002) /* Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((u32)0x40000000) /* Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((u32)0x80000000) /* Fault related to debug */ + + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((u8)0x01) /* Halt request flag */ +#define SCB_DFSR_BKPT ((u8)0x02) /* BKPT flag */ +#define SCB_DFSR_DWTTRAP ((u8)0x04) /* Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((u8)0x08) /* Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((u8)0x10) /* External debug request flag */ + + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((u32)0xFFFFFFFF) /* Mem Manage fault address field */ + + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((u32)0xFFFFFFFF) /* Bus fault address field */ + + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((u32)0xFFFFFFFF) /* Implementation defined */ + + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((u32)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((u32)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((u32)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((u32)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((u32)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((u32)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((u32)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((u32)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((u32)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((u32)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((u32)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((u32)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((u32)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((u32)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((u32)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((u32)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((u32)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((u32)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((u32)0x00040000) /* Interrupt Mask on line 18 */ + + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((u32)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((u32)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((u32)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((u32)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((u32)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((u32)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((u32)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((u32)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((u32)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((u32)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((u32)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((u32)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((u32)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((u32)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((u32)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((u32)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((u32)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((u32)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((u32)0x00040000) /* Event Mask on line 18 */ + + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((u32)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((u32)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((u32)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((u32)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((u32)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((u32)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((u32)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((u32)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((u32)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((u32)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((u32)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((u32)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((u32)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((u32)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((u32)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((u32)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((u32)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((u32)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((u32)0x00040000) /* Rising trigger event configuration bit of line 18 */ + + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((u32)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((u32)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((u32)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((u32)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((u32)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((u32)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((u32)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((u32)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((u32)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((u32)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((u32)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((u32)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((u32)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((u32)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((u32)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((u32)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((u32)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((u32)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((u32)0x00040000) /* Falling trigger event configuration bit of line 18 */ + + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((u32)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((u32)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((u32)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((u32)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((u32)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((u32)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((u32)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((u32)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((u32)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((u32)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((u32)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((u32)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((u32)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((u32)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((u32)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((u32)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((u32)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((u32)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((u32)0x00040000) /* Software Interrupt on line 18 */ + + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((u32)0x00000001) /* Pending bit 0 */ +#define EXTI_PR_PR1 ((u32)0x00000002) /* Pending bit 1 */ +#define EXTI_PR_PR2 ((u32)0x00000004) /* Pending bit 2 */ +#define EXTI_PR_PR3 ((u32)0x00000008) /* Pending bit 3 */ +#define EXTI_PR_PR4 ((u32)0x00000010) /* Pending bit 4 */ +#define EXTI_PR_PR5 ((u32)0x00000020) /* Pending bit 5 */ +#define EXTI_PR_PR6 ((u32)0x00000040) /* Pending bit 6 */ +#define EXTI_PR_PR7 ((u32)0x00000080) /* Pending bit 7 */ +#define EXTI_PR_PR8 ((u32)0x00000100) /* Pending bit 8 */ +#define EXTI_PR_PR9 ((u32)0x00000200) /* Pending bit 9 */ +#define EXTI_PR_PR10 ((u32)0x00000400) /* Pending bit 10 */ +#define EXTI_PR_PR11 ((u32)0x00000800) /* Pending bit 11 */ +#define EXTI_PR_PR12 ((u32)0x00001000) /* Pending bit 12 */ +#define EXTI_PR_PR13 ((u32)0x00002000) /* Pending bit 13 */ +#define EXTI_PR_PR14 ((u32)0x00004000) /* Pending bit 14 */ +#define EXTI_PR_PR15 ((u32)0x00008000) /* Pending bit 15 */ +#define EXTI_PR_PR16 ((u32)0x00010000) /* Pending bit 16 */ +#define EXTI_PR_PR17 ((u32)0x00020000) /* Pending bit 17 */ +#define EXTI_PR_PR18 ((u32)0x00040000) /* Trigger request occurred on the external interrupt line 18 */ + + + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((u32)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((u32)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((u32)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((u32)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((u32)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((u32)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((u32)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error flag */ + + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((u32)0x00000001) /* Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((u32)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((u32)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((u32)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((u32)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((u32)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((u32)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error clear */ + + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((u16)0x0001) /* Channel enable*/ +#define DMA_CCR1_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR1_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR1_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR1_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR1_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR1_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR1_PL ((u16)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR1_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR2_TCIE ((u16)0x0002) /* ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR2_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR2_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR2_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR2_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR2_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR2_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR2_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR3_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR3_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR3_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR3_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR3_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR3_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR3_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR3_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR4_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR4_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR4_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR4_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR4_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR4_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR4_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR4_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR5_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR5_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR5_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR5_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR5_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR5_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR5_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR5_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ + + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR6_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR6_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR6_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR6_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR6_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR6_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR6_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR6_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ + + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((u16)0x0001) /* Channel enable */ +#define DMA_CCR7_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((u16)0x0010) /* Data transfer direction */ +#define DMA_CCR7_CIRC ((u16)0x0020) /* Circular mode */ +#define DMA_CCR7_PINC ((u16)0x0040) /* Peripheral increment mode */ +#define DMA_CCR7_MINC ((u16)0x0080) /* Memory increment mode */ + +#define DMA_CCR7_PSIZE , ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((u16)0x0100) /* Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((u16)0x0200) /* Bit 1 */ + +#define DMA_CCR7_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((u16)0x0400) /* Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((u16)0x0800) /* Bit 1 */ + +#define DMA_CCR7_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((u16)0x1000) /* Bit 0 */ +#define DMA_CCR7_PL_1 ((u16)0x2000) /* Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ + + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((u16)0xFFFF) /* Number of data to Transfer */ + + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ + + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((u32)0xFFFFFFFF) /* Memory Address */ + + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((u8)0x01) /* Analog watchdog flag */ +#define ADC_SR_EOC ((u8)0x02) /* End of conversion */ +#define ADC_SR_JEOC ((u8)0x04) /* Injected channel end of conversion */ +#define ADC_SR_JSTRT ((u8)0x08) /* Injected channel Start flag */ +#define ADC_SR_STRT ((u8)0x10) /* Regular channel Start flag */ + + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((u32)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_CR1_AWDCH_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_CR1_AWDCH_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_CR1_AWDCH_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_CR1_AWDCH_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_CR1_EOCIE ((u32)0x00000020) /* Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((u32)0x00000040) /* AAnalog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((u32)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((u32)0x00000100) /* Scan mode */ +#define ADC_CR1_AWDSGL ((u32)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((u32)0x00000400) /* Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((u32)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((u32)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((u32)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((u32)0x00002000) /* Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((u32)0x00004000) /* Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((u32)0x00008000) /* Bit 2 */ + +#define ADC_CR1_DUALMOD ((u32)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((u32)0x00010000) /* Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((u32)0x00020000) /* Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((u32)0x00040000) /* Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((u32)0x00080000) /* Bit 3 */ + +#define ADC_CR1_JAWDEN ((u32)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((u32)0x00800000) /* Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((u32)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((u32)0x00000002) /* Continuous Conversion */ +#define ADC_CR2_CAL ((u32)0x00000004) /* A/D Calibration */ +#define ADC_CR2_RSTCAL ((u32)0x00000008) /* Reset Calibration */ +#define ADC_CR2_DMA ((u32)0x00000100) /* Direct Memory access mode */ +#define ADC_CR2_ALIGN ((u32)0x00000800) /* Data Alignment */ + +#define ADC_CR2_JEXTSEL ((u32)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((u32)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((u32)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((u32)0x00020000) /* Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((u32)0x00040000) /* Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((u32)0x00080000) /* Bit 2 */ + +#define ADC_CR2_EXTTRIG ((u32)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((u32)0x00200000) /* Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((u32)0x00400000) /* Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((u32)0x00800000) /* Temperature Sensor and VREFINT Enable */ + + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((u32)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((u32)0x00000004) /* Bit 2 */ + +#define ADC_SMPR1_SMP11 ((u32)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((u32)0x00000008) /* Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((u32)0x00000010) /* Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((u32)0x00000020) /* Bit 2 */ + +#define ADC_SMPR1_SMP12 ((u32)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((u32)0x00000040) /* Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((u32)0x00000080) /* Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((u32)0x00000100) /* Bit 2 */ + +#define ADC_SMPR1_SMP13 ((u32)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((u32)0x00000200) /* Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((u32)0x00000400) /* Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((u32)0x00000800) /* Bit 2 */ + +#define ADC_SMPR1_SMP14 ((u32)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_SMPR1_SMP15 ((u32)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((u32)0x00020000) /* Bit 2 */ + +#define ADC_SMPR1_SMP16 ((u32)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((u32)0x00040000) /* Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((u32)0x00080000) /* Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((u32)0x00100000) /* Bit 2 */ + +#define ADC_SMPR1_SMP17 ((u32)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((u32)0x00200000) /* Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((u32)0x00400000) /* Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((u32)0x00800000) /* Bit 2 */ + + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((u32)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((u32)0x00000004) /* Bit 2 */ + +#define ADC_SMPR2_SMP1 ((u32)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((u32)0x00000008) /* Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((u32)0x00000010) /* Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((u32)0x00000020) /* Bit 2 */ + +#define ADC_SMPR2_SMP2 ((u32)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((u32)0x00000040) /* Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((u32)0x00000080) /* Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((u32)0x00000100) /* Bit 2 */ + +#define ADC_SMPR2_SMP3 ((u32)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((u32)0x00000200) /* Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((u32)0x00000400) /* Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((u32)0x00000800) /* Bit 2 */ + +#define ADC_SMPR2_SMP4 ((u32)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((u32)0x00001000) /* Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((u32)0x00002000) /* Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((u32)0x00004000) /* Bit 2 */ + +#define ADC_SMPR2_SMP5 ((u32)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((u32)0x00020000) /* Bit 2 */ + +#define ADC_SMPR2_SMP6 ((u32)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((u32)0x00040000) /* Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((u32)0x00080000) /* Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((u32)0x00100000) /* Bit 2 */ + +#define ADC_SMPR2_SMP7 ((u32)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((u32)0x00200000) /* Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((u32)0x00400000) /* Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((u32)0x00800000) /* Bit 2 */ + +#define ADC_SMPR2_SMP8 ((u32)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((u32)0x01000000) /* Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((u32)0x02000000) /* Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((u32)0x04000000) /* Bit 2 */ + +#define ADC_SMPR2_SMP9 ((u32)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((u32)0x08000000) /* Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((u32)0x10000000) /* Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((u32)0x20000000) /* Bit 2 */ + + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((u16)0x0FFF) /* Data offset for injected channel 1 */ + + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((u16)0x0FFF) /* Data offset for injected channel 2 */ + + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((u16)0x0FFF) /* Data offset for injected channel 3 */ + + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((u16)0x0FFF) /* Data offset for injected channel 4 */ + + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((u16)0x0FFF) /* Analog watchdog high threshold */ + + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((u16)0x0FFF) /* Analog watchdog low threshold */ + + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((u32)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR1_SQ13_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR1_SQ13_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR1_SQ13_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR1_SQ13_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR1_SQ14 ((u32)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR1_SQ14_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR1_SQ14_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR1_SQ14_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR1_SQ14_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR1_SQ15 ((u32)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR1_SQ15_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR1_SQ15_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR1_SQ15_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR1_SQ15_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR1_SQ16 ((u32)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR1_SQ16_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR1_SQ16_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR1_SQ16_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR1_SQ16_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR1_L ((u32)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR1_L_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR1_L_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR1_L_3 ((u32)0x00800000) /* Bit 3 */ + + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((u32)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR2_SQ7_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR2_SQ7_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR2_SQ7_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR2_SQ7_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR2_SQ8 ((u32)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR2_SQ8_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR2_SQ8_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR2_SQ8_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR2_SQ8_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR2_SQ9 ((u32)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR2_SQ9_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR2_SQ9_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR2_SQ9_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR2_SQ9_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR2_SQ10 ((u32)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR2_SQ10_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR2_SQ10_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR2_SQ10_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR2_SQ10_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR2_SQ11 ((u32)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR2_SQ11_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR2_SQ11_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR2_SQ11_3 ((u32)0x00800000) /* Bit 3 */ +#define ADC_SQR2_SQ11_4 ((u32)0x01000000) /* Bit 4 */ + +#define ADC_SQR2_SQ12 ((u32)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((u32)0x02000000) /* Bit 0 */ +#define ADC_SQR2_SQ12_1 ((u32)0x04000000) /* Bit 1 */ +#define ADC_SQR2_SQ12_2 ((u32)0x08000000) /* Bit 2 */ +#define ADC_SQR2_SQ12_3 ((u32)0x10000000) /* Bit 3 */ +#define ADC_SQR2_SQ12_4 ((u32)0x20000000) /* Bit 4 */ + + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((u32)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_SQR3_SQ1_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_SQR3_SQ1_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_SQR3_SQ1_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_SQR3_SQ1_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_SQR3_SQ2 ((u32)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_SQR3_SQ2_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_SQR3_SQ2_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_SQR3_SQ2_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_SQR3_SQ2_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_SQR3_SQ3 ((u32)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_SQR3_SQ3_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_SQR3_SQ3_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_SQR3_SQ3_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_SQR3_SQ3_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_SQR3_SQ4 ((u32)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_SQR3_SQ4_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_SQR3_SQ4_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_SQR3_SQ4_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_SQR3_SQ4_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_SQR3_SQ5 ((u32)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_SQR3_SQ5_1 ((u32)0x00200000) /* Bit 1 */ +#define ADC_SQR3_SQ5_2 ((u32)0x00400000) /* Bit 2 */ +#define ADC_SQR3_SQ5_3 ((u32)0x00800000) /* Bit 3 */ +#define ADC_SQR3_SQ5_4 ((u32)0x01000000) /* Bit 4 */ + +#define ADC_SQR3_SQ6 ((u32)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((u32)0x02000000) /* Bit 0 */ +#define ADC_SQR3_SQ6_1 ((u32)0x04000000) /* Bit 1 */ +#define ADC_SQR3_SQ6_2 ((u32)0x08000000) /* Bit 2 */ +#define ADC_SQR3_SQ6_3 ((u32)0x10000000) /* Bit 3 */ +#define ADC_SQR3_SQ6_4 ((u32)0x20000000) /* Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((u32)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((u32)0x00000001) /* Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((u32)0x00000002) /* Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((u32)0x00000004) /* Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((u32)0x00000008) /* Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((u32)0x00000010) /* Bit 4 */ + +#define ADC_JSQR_JSQ2 ((u32)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((u32)0x00000020) /* Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((u32)0x00000040) /* Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((u32)0x00000080) /* Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((u32)0x00000100) /* Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((u32)0x00000200) /* Bit 4 */ + +#define ADC_JSQR_JSQ3 ((u32)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((u32)0x00000400) /* Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((u32)0x00000800) /* Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((u32)0x00001000) /* Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((u32)0x00002000) /* Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((u32)0x00004000) /* Bit 4 */ + +#define ADC_JSQR_JSQ4 ((u32)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((u32)0x00008000) /* Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((u32)0x00010000) /* Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((u32)0x00020000) /* Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((u32)0x00040000) /* Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((u32)0x00080000) /* Bit 4 */ + +#define ADC_JSQR_JL ((u32)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((u32)0x00100000) /* Bit 0 */ +#define ADC_JSQR_JL_1 ((u32)0x00200000) /* Bit 1 */ + + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((u16)0xFFFF) /* Injected data */ + + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((u32)0x0000FFFF) /* Regular data */ +#define ADC_DR_ADC2DATA ((u32)0xFFFF0000) /* ADC2 data */ + + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((u32)0x00000001) /* DAC channel1 enable */ +#define DAC_CR_BOFF1 ((u32)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((u32)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((u32)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((u32)0x00000008) /* Bit 0 */ +#define DAC_CR_TSEL1_1 ((u32)0x00000010) /* Bit 1 */ +#define DAC_CR_TSEL1_2 ((u32)0x00000020) /* Bit 2 */ + +#define DAC_CR_WAVE1 ((u32)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((u32)0x00000040) /* Bit 0 */ +#define DAC_CR_WAVE1_1 ((u32)0x00000080) /* Bit 1 */ + +#define DAC_CR_MAMP1 ((u32)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((u32)0x00000100) /* Bit 0 */ +#define DAC_CR_MAMP1_1 ((u32)0x00000200) /* Bit 1 */ +#define DAC_CR_MAMP1_2 ((u32)0x00000400) /* Bit 2 */ +#define DAC_CR_MAMP1_3 ((u32)0x00000800) /* Bit 3 */ + +#define DAC_CR_DMAEN1 ((u32)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((u32)0x00010000) /* DAC channel2 enable */ +#define DAC_CR_BOFF2 ((u32)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((u32)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((u32)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((u32)0x00080000) /* Bit 0 */ +#define DAC_CR_TSEL2_1 ((u32)0x00100000) /* Bit 1 */ +#define DAC_CR_TSEL2_2 ((u32)0x00200000) /* Bit 2 */ + +#define DAC_CR_WAVE2 ((u32)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((u32)0x00400000) /* Bit 0 */ +#define DAC_CR_WAVE2_1 ((u32)0x00800000) /* Bit 1 */ + +#define DAC_CR_MAMP2 ((u32)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((u32)0x01000000) /* Bit 0 */ +#define DAC_CR_MAMP2_1 ((u32)0x02000000) /* Bit 1 */ +#define DAC_CR_MAMP2_2 ((u32)0x04000000) /* Bit 2 */ +#define DAC_CR_MAMP2_3 ((u32)0x08000000) /* Bit 3 */ + +#define DAC_CR_DMAEN2 ((u32)0x10000000) /* DAC channel2 DMA enabled */ + + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((u8)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((u8)0x02) /* DAC channel2 software trigger */ + + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((u16)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((u16)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((u8)0xFF) /* DAC channel1 8-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((u16)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((u16)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((u8)0xFF) /* DAC channel2 8-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((u32)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((u32)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((u32)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((u32)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((u16)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((u16)0xFF00) /* DAC channel2 8-bit Right aligned data */ + + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((u16)0x0FFF) /* DAC channel1 data output */ + + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((u16)0x0FFF) /* DAC channel2 data output */ + + + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((u16)0x0001) /* Counter enable */ +#define TIM_CR1_UDIS ((u16)0x0002) /* Update disable */ +#define TIM_CR1_URS ((u16)0x0004) /* Update request source */ +#define TIM_CR1_OPM ((u16)0x0008) /* One pulse mode */ +#define TIM_CR1_DIR ((u16)0x0010) /* Direction */ + +#define TIM_CR1_CMS ((u16)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((u16)0x0020) /* Bit 0 */ +#define TIM_CR1_CMS_1 ((u16)0x0040) /* Bit 1 */ + +#define TIM_CR1_ARPE ((u16)0x0080) /* Auto-reload preload enable */ + +#define TIM_CR1_CKD ((u16)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CR1_CKD_1 ((u16)0x0200) /* Bit 1 */ + + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((u16)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((u16)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((u16)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((u16)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CR2_MMS_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CR2_MMS_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CR2_TI1S ((u16)0x0080) /* TI1 Selection */ +#define TIM_CR2_OIS1 ((u16)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((u16)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((u16)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((u16)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((u16)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((u16)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((u16)0x4000) /* Output Idle state 4 (OC4 output) */ + + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((u16)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_SMCR_SMS_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_SMCR_SMS_2 ((u16)0x0004) /* Bit 2 */ + +#define TIM_SMCR_TS ((u16)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_SMCR_TS_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_SMCR_TS_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_SMCR_MSM ((u16)0x0080) /* Master/slave mode */ + +#define TIM_SMCR_ETF ((u16)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_SMCR_ETF_1 ((u16)0x0200) /* Bit 1 */ +#define TIM_SMCR_ETF_2 ((u16)0x0400) /* Bit 2 */ +#define TIM_SMCR_ETF_3 ((u16)0x0800) /* Bit 3 */ + +#define TIM_SMCR_ETPS ((u16)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_SMCR_ETPS_1 ((u16)0x2000) /* Bit 1 */ + +#define TIM_SMCR_ECE ((u16)0x4000) /* External clock enable */ +#define TIM_SMCR_ETP ((u16)0x8000) /* External trigger polarity */ + + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((u16)0x0001) /* Update interrupt enable */ +#define TIM_DIER_CC1IE ((u16)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((u16)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((u16)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((u16)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((u16)0x0020) /* COM interrupt enable */ +#define TIM_DIER_TIE ((u16)0x0040) /* Trigger interrupt enable */ +#define TIM_DIER_BIE ((u16)0x0080) /* Break interrupt enable */ +#define TIM_DIER_UDE ((u16)0x0100) /* Update DMA request enable */ +#define TIM_DIER_CC1DE ((u16)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((u16)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((u16)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((u16)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((u16)0x2000) /* COM DMA request enable */ +#define TIM_DIER_TDE ((u16)0x4000) /* Trigger DMA request enable */ + + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((u16)0x0001) /* Update interrupt Flag */ +#define TIM_SR_CC1IF ((u16)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((u16)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((u16)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((u16)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((u16)0x0020) /* COM interrupt Flag */ +#define TIM_SR_TIF ((u16)0x0040) /* Trigger interrupt Flag */ +#define TIM_SR_BIF ((u16)0x0080) /* Break interrupt Flag */ +#define TIM_SR_CC1OF ((u16)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((u16)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((u16)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((u16)0x1000) /* Capture/Compare 4 Overcapture Flag */ + + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((u8)0x01) /* Update Generation */ +#define TIM_EGR_CC1G ((u8)0x02) /* Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((u8)0x04) /* Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((u8)0x08) /* Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((u8)0x10) /* Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((u8)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((u8)0x40) /* Trigger Generation */ +#define TIM_EGR_BG ((u8)0x80) /* Break Generation */ + + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((u16)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((u16)0x0002) /* Bit 1 */ + +#define TIM_CCMR1_OC1FE ((u16)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((u16)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((u16)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CCMR1_OC1CE ((u16)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((u16)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_CCMR1_OC2FE ((u16)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((u16)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((u16)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((u16)0x4000) /* Bit 2 */ + +#define TIM_CCMR1_OC2CE ((u16)0x8000) /* Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((u16)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((u16)0x0004) /* Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((u16)0x0008) /* Bit 1 */ + +#define TIM_CCMR1_IC1F ((u16)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((u16)0x0040) /* Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((u16)0x0080) /* Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((u16)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((u16)0x0400) /* Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((u16)0x0800) /* Bit 1 */ + +#define TIM_CCMR1_IC2F ((u16)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((u16)0x4000) /* Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((u16)0x8000) /* Bit 3 */ + + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((u16)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((u16)0x0002) /* Bit 1 */ + +#define TIM_CCMR2_OC3FE ((u16)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((u16)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((u16)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((u16)0x0040) /* Bit 2 */ + +#define TIM_CCMR2_OC3CE ((u16)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((u16)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_CCMR2_OC4FE ((u16)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((u16)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((u16)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((u16)0x4000) /* Bit 2 */ + +#define TIM_CCMR2_OC4CE ((u16)0x8000) /* Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((u16)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((u16)0x0004) /* Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((u16)0x0008) /* Bit 1 */ + +#define TIM_CCMR2_IC3F ((u16)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((u16)0x0010) /* Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((u16)0x0020) /* Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((u16)0x0040) /* Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((u16)0x0080) /* Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((u16)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((u16)0x0400) /* Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((u16)0x0800) /* Bit 1 */ + +#define TIM_CCMR2_IC4F ((u16)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((u16)0x1000) /* Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((u16)0x2000) /* Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((u16)0x4000) /* Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((u16)0x8000) /* Bit 3 */ + + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((u16)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((u16)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((u16)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((u16)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((u16)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((u16)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((u16)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((u16)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((u16)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((u16)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((u16)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((u16)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((u16)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((u16)0x2000) /* Capture/Compare 4 output Polarity */ + + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((u16)0xFFFF) /* Counter Value */ + + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((u16)0xFFFF) /* Prescaler Value */ + + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((u16)0xFFFF) /* actual auto-reload Value */ + + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((u8)0xFF) /* Repetition Counter Value */ + + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((u16)0xFFFF) /* Capture/Compare 1 Value */ + + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((u16)0xFFFF) /* Capture/Compare 2 Value */ + + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((u16)0xFFFF) /* Capture/Compare 3 Value */ + + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((u16)0xFFFF) /* Capture/Compare 4 Value */ + + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((u16)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_BDTR_DTG_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_BDTR_DTG_2 ((u16)0x0004) /* Bit 2 */ +#define TIM_BDTR_DTG_3 ((u16)0x0008) /* Bit 3 */ +#define TIM_BDTR_DTG_4 ((u16)0x0010) /* Bit 4 */ +#define TIM_BDTR_DTG_5 ((u16)0x0020) /* Bit 5 */ +#define TIM_BDTR_DTG_6 ((u16)0x0040) /* Bit 6 */ +#define TIM_BDTR_DTG_7 ((u16)0x0080) /* Bit 7 */ + +#define TIM_BDTR_LOCK ((u16)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_BDTR_LOCK_1 ((u16)0x0200) /* Bit 1 */ + +#define TIM_BDTR_OSSI ((u16)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((u16)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((u16)0x1000) /* Break enable */ +#define TIM_BDTR_BKP ((u16)0x2000) /* Break Polarity */ +#define TIM_BDTR_AOE ((u16)0x4000) /* Automatic Output enable */ +#define TIM_BDTR_MOE ((u16)0x8000) /* Main Output enable */ + + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((u16)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((u16)0x0001) /* Bit 0 */ +#define TIM_DCR_DBA_1 ((u16)0x0002) /* Bit 1 */ +#define TIM_DCR_DBA_2 ((u16)0x0004) /* Bit 2 */ +#define TIM_DCR_DBA_3 ((u16)0x0008) /* Bit 3 */ +#define TIM_DCR_DBA_4 ((u16)0x0010) /* Bit 4 */ + +#define TIM_DCR_DBL ((u16)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((u16)0x0100) /* Bit 0 */ +#define TIM_DCR_DBL_1 ((u16)0x0200) /* Bit 1 */ +#define TIM_DCR_DBL_2 ((u16)0x0400) /* Bit 2 */ +#define TIM_DCR_DBL_3 ((u16)0x0800) /* Bit 3 */ +#define TIM_DCR_DBL_4 ((u16)0x1000) /* Bit 4 */ + + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((u16)0xFFFF) /* DMA register for burst accesses */ + + + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((u8)0x01) /* Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((u8)0x02) /* Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((u8)0x04) /* OverfloW Interrupt Enable */ + + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((u8)0x01) /* Second Flag */ +#define RTC_CRL_ALRF ((u8)0x02) /* Alarm Flag */ +#define RTC_CRL_OWF ((u8)0x04) /* OverfloW Flag */ +#define RTC_CRL_RSF ((u8)0x08) /* Registers Synchronized Flag */ +#define RTC_CRL_CNF ((u8)0x10) /* Configuration Flag */ +#define RTC_CRL_RTOFF ((u8)0x20) /* RTC operation OFF */ + + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((u16)0x000F) /* RTC Prescaler Reload Value High */ + + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((u16)0xFFFF) /* RTC Prescaler Reload Value Low */ + + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((u16)0x000F) /* RTC Clock Divider High */ + + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((u16)0xFFFF) /* RTC Clock Divider Low */ + + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((u16)0xFFFF) /* RTC Counter High */ + + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((u16)0xFFFF) /* RTC Counter Low */ + + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((u16)0xFFFF) /* RTC Alarm High */ + + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((u16)0xFFFF) /* RTC Alarm Low */ + + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((u16)0xFFFF) /* Key value (write only, read 0000h) */ + + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((u8)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((u8)0x01) /* Bit 0 */ +#define IWDG_PR_PR_1 ((u8)0x02) /* Bit 1 */ +#define IWDG_PR_PR_2 ((u8)0x04) /* Bit 2 */ + + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((u16)0x0FFF) /* Watchdog counter reload value */ + + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((u8)0x01) /* Watchdog prescaler value update */ +#define IWDG_SR_RVU ((u8)0x02) /* Watchdog counter reload value update */ + + + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((u8)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((u8)0x01) /* Bit 0 */ +#define WWDG_CR_T1 ((u8)0x02) /* Bit 1 */ +#define WWDG_CR_T2 ((u8)0x04) /* Bit 2 */ +#define WWDG_CR_T3 ((u8)0x08) /* Bit 3 */ +#define WWDG_CR_T4 ((u8)0x10) /* Bit 4 */ +#define WWDG_CR_T5 ((u8)0x20) /* Bit 5 */ +#define WWDG_CR_T6 ((u8)0x40) /* Bit 6 */ + +#define WWDG_CR_WDGA ((u8)0x80) /* Activation bit */ + + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((u16)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((u16)0x0001) /* Bit 0 */ +#define WWDG_CFR_W1 ((u16)0x0002) /* Bit 1 */ +#define WWDG_CFR_W2 ((u16)0x0004) /* Bit 2 */ +#define WWDG_CFR_W3 ((u16)0x0008) /* Bit 3 */ +#define WWDG_CFR_W4 ((u16)0x0010) /* Bit 4 */ +#define WWDG_CFR_W5 ((u16)0x0020) /* Bit 5 */ +#define WWDG_CFR_W6 ((u16)0x0040) /* Bit 6 */ + +#define WWDG_CFR_WDGTB ((u16)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((u16)0x0080) /* Bit 0 */ +#define WWDG_CFR_WDGTB1 ((u16)0x0100) /* Bit 1 */ + +#define WWDG_CFR_EWI ((u16)0x0200) /* Early Wakeup Interrupt */ + + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((u8)0x01) /* Early Wakeup Interrupt Flag */ + + + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR1_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR1_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR1_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR1_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR1_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR1_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR1_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR2_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR2_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR2_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR2_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR2_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR2_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR2_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR3_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR3_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR3_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR3_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR3_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR3_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR3_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((u32)0x00000004) /* Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((u32)0x00000008) /* Bit 1 */ + +#define FSMC_BCR4_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BCR4_MWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_BCR4_FACCEN ((u32)0x00000040) /* Flash access enable */ +#define FSMC_BCR4_BURSTEN ((u32)0x00000100) /* Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ +#define FSMC_BCR4_WREN ((u32)0x00001000) /* Write enable bit */ +#define FSMC_BCR4_WAITEN ((u32)0x00002000) /* Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((u32)0x00004000) /* Extended mode enable */ +#define FSMC_BCR4_CBURSTRW ((u32)0x00080000) /* Write burst enable */ + + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ + +#define FSMC_BWTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ + +#define FSMC_BWTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BWTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_BWTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_BWTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_BWTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ + +#define FSMC_BWTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ + + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR2_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR2_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR2_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR2_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR2_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR2_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR2_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR2_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR2_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR2_ECCPS ((u32)0x000E0000) /* ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR3_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR3_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR3_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR3_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR3_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR3_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR3_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR3_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR3_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR3_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((u32)0x00000008) /* Memory type */ + +#define FSMC_PCR4_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((u32)0x00000010) /* Bit 0 */ +#define FSMC_PCR4_PWID_1 ((u32)0x00000020) /* Bit 1 */ + +#define FSMC_PCR4_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ +#define FSMC_PCR4_ADLOW ((u32)0x00000100) /* Address low bit delivery */ + +#define FSMC_PCR4_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((u32)0x00000200) /* Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((u32)0x00000400) /* Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((u32)0x00000800) /* Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((u32)0x00001000) /* Bit 3 */ + +#define FSMC_PCR4_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((u32)0x00002000) /* Bit 0 */ +#define FSMC_PCR4_TAR_1 ((u32)0x00004000) /* Bit 1 */ +#define FSMC_PCR4_TAR_2 ((u32)0x00008000) /* Bit 2 */ +#define FSMC_PCR4_TAR_3 ((u32)0x00010000) /* Bit 3 */ + +#define FSMC_PCR4_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ + + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR2_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((u8)0x40) /* FIFO empty */ + + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR3_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((u8)0x40) /* FIFO empty */ + + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((u8)0x01) /* Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((u8)0x02) /* Interrupt Level status */ +#define FSMC_SR4_IFS ((u8)0x04) /* Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((u8)0x40) /* FIFO empty */ + + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((u32)0x000000FF) /* MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((u32)0x0000FF00) /* MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((u32)0x00FF0000) /* MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((u32)0xFF000000) /* MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((u32)0x000000FF) /* MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((u32)0x0000FF00) /* MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((u32)0x00FF0000) /* MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((u32)0xFF000000) /* MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((u32)0x000000FF) /* MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((u32)0x0000FF00) /* MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((u32)0x00FF0000) /* MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((u32)0xFF000000) /* MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((u32)0x000000FF) /* ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((u32)0x0000FF00) /* ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((u32)0x00FF0000) /* ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((u32)0xFF000000) /* ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((u32)0x000000FF) /* ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((u32)0x0000FF00) /* ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((u32)0x00FF0000) /* ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((u32)0xFF000000) /* ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((u32)0x000000FF) /* ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((u32)0x0000FF00) /* ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((u32)0x00FF0000) /* ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((u32)0xFF000000) /* ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((u32)0x000000FF) /* IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((u32)0x00000001) /* Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((u32)0x00000002) /* Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((u32)0x00000004) /* Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((u32)0x00000008) /* Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((u32)0x00000010) /* Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((u32)0x00000020) /* Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((u32)0x00000040) /* Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((u32)0x00000080) /* Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((u32)0x0000FF00) /* IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((u32)0x00000100) /* Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((u32)0x00000200) /* Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((u32)0x00000400) /* Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((u32)0x00000800) /* Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((u32)0x00001000) /* Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((u32)0x00002000) /* Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((u32)0x00004000) /* Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((u32)0x00008000) /* Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((u32)0x00FF0000) /* IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((u32)0x00010000) /* Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((u32)0x00020000) /* Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((u32)0x00040000) /* Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((u32)0x00080000) /* Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((u32)0x00100000) /* Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((u32)0x00200000) /* Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((u32)0x00400000) /* Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((u32)0x00800000) /* Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((u32)0xFF000000) /* IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((u32)0x01000000) /* Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((u32)0x02000000) /* Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((u32)0x04000000) /* Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((u32)0x08000000) /* Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((u32)0x10000000) /* Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((u32)0x20000000) /* Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((u32)0x40000000) /* Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((u32)0x80000000) /* Bit 7 */ + + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((u32)0xFFFFFFFF) /* ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((u32)0xFFFFFFFF) /* ECC result */ + + + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((u8)0x03) /* PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((u8)0x01) /* Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((u8)0x02) /* Bit 1 */ + + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((u16)0x00FF) /* Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((u16)0x0100) /* Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((u16)0x0200) /* Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((u16)0x0400) /* Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((u16)0x1800) /* WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((u16)0x0800) /* Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((u16)0x1000) /* Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((u16)0x2000) /* SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((u16)0x4000) /* HW Flow Control enable */ + + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((u32)0xFFFFFFFF) /* Command argument */ + + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((u16)0x003F) /* Command Index */ + +#define SDIO_CMD_WAITRESP ((u16)0x00C0) /* WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((u16)0x0040) /* Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((u16)0x0080) /* Bit 1 */ + +#define SDIO_CMD_WAITINT ((u16)0x0100) /* CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((u16)0x0200) /* CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((u16)0x0400) /* Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((u16)0x0800) /* SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((u16)0x1000) /* Enable CMD completion */ +#define SDIO_CMD_NIEN ((u16)0x2000) /* Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((u16)0x4000) /* CE-ATA command */ + + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((u8)0x3F) /* Response command index */ + + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((u32)0xFFFFFFFF) /* Card Status */ + + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((u32)0xFFFFFFFF) /* Data timeout period. */ + + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((u32)0x01FFFFFF) /* Data length value */ + + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((u16)0x0001) /* Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((u16)0x0002) /* Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((u16)0x0004) /* Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((u16)0x0008) /* DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((u16)0x00F0) /* DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((u16)0x0010) /* Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((u16)0x0020) /* Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((u16)0x0040) /* Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((u16)0x0080) /* Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((u16)0x0100) /* Read wait start */ +#define SDIO_DCTRL_RWSTOP ((u16)0x0200) /* Read wait stop */ +#define SDIO_DCTRL_RWMOD ((u16)0x0400) /* Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((u16)0x0800) /* SD I/O enable functions */ + + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((u32)0x01FFFFFF) /* Data count value */ + + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((u32)0x00000001) /* Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((u32)0x00000002) /* Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((u32)0x00000004) /* Command response timeout */ +#define SDIO_STA_DTIMEOUT ((u32)0x00000008) /* Data timeout */ +#define SDIO_STA_TXUNDERR ((u32)0x00000010) /* Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((u32)0x00000020) /* Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((u32)0x00000040) /* Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((u32)0x00000080) /* Command sent (no response required) */ +#define SDIO_STA_DATAEND ((u32)0x00000100) /* Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((u32)0x00000200) /* Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((u32)0x00000400) /* Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((u32)0x00000800) /* Command transfer in progress */ +#define SDIO_STA_TXACT ((u32)0x00001000) /* Data transmit in progress */ +#define SDIO_STA_RXACT ((u32)0x00002000) /* Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((u32)0x00004000) /* Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((u32)0x00008000) /* Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((u32)0x00010000) /* Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((u32)0x00020000) /* Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((u32)0x00040000) /* Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((u32)0x00080000) /* Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((u32)0x00100000) /* Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((u32)0x00200000) /* Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((u32)0x00400000) /* SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((u32)0x00800000) /* CE-ATA command completion signal received for CMD61 */ + + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((u32)0x00000001) /* CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((u32)0x00000002) /* DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((u32)0x00000004) /* CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((u32)0x00000008) /* DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((u32)0x00000010) /* TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((u32)0x00000020) /* RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((u32)0x00000040) /* CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((u32)0x00000080) /* CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((u32)0x00000100) /* DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((u32)0x00000200) /* STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((u32)0x00000400) /* DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((u32)0x00400000) /* SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((u32)0x00800000) /* CEATAEND flag clear bit */ + + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((u32)0x00000001) /* Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((u32)0x00000002) /* Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((u32)0x00000004) /* Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((u32)0x00000008) /* Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((u32)0x00000010) /* Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((u32)0x00000020) /* Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((u32)0x00000040) /* Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((u32)0x00000080) /* Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((u32)0x00000100) /* Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((u32)0x00000200) /* Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((u32)0x00000400) /* Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((u32)0x00000800) /* CCommand Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((u32)0x00001000) /* Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((u32)0x00002000) /* Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((u32)0x00004000) /* Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((u32)0x00008000) /* Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((u32)0x00010000) /* Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((u32)0x00020000) /* Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((u32)0x00040000) /* Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((u32)0x00080000) /* Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((u32)0x00100000) /* Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((u32)0x00200000) /* Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((u32)0x00400000) /* SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((u32)0x00800000) /* CE-ATA command completion signal received Interrupt Enable */ + + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((u32)0x00FFFFFF) /* Remaining number of words to be written to or read from the FIFO */ + + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((u32)0xFFFFFFFF) /* Receive and transmit FIFO data */ + + + +/******************************************************************************/ +/* */ +/* USB */ +/* */ +/******************************************************************************/ + +/* Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP0R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP0R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP0R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP0R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP1R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP1R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP1R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP1R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP2R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP2R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP2R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP2R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP3R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP3R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP3R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP3R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP4R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP4R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP4R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP4R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP5R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP5R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP5R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP5R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP6R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP6R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP6R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP6R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((u16)0x000F) /* Endpoint Address */ + +#define USB_EP7R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ + +#define USB_EP7R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ + +#define USB_EP7R_SETUP ((u16)0x0800) /* Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ + +#define USB_EP7R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ + + +/* Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((u16)0x0001) /* Force USB Reset */ +#define USB_CNTR_PDWN ((u16)0x0002) /* Power down */ +#define USB_CNTR_LP_MODE ((u16)0x0004) /* Low-power mode */ +#define USB_CNTR_FSUSP ((u16)0x0008) /* Force suspend */ +#define USB_CNTR_RESUME ((u16)0x0010) /* Resume request */ +#define USB_CNTR_ESOFM ((u16)0x0100) /* Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((u16)0x0200) /* Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((u16)0x0400) /* RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((u16)0x0800) /* Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((u16)0x1000) /* Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((u16)0x2000) /* Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((u16)0x4000) /* Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((u16)0x8000) /* Correct Transfer Interrupt Mask */ + + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((u16)0x000F) /* Endpoint Identifier */ +#define USB_ISTR_DIR ((u16)0x0010) /* Direction of transaction */ +#define USB_ISTR_ESOF ((u16)0x0100) /* Expected Start Of Frame */ +#define USB_ISTR_SOF ((u16)0x0200) /* Start Of Frame */ +#define USB_ISTR_RESET ((u16)0x0400) /* USB RESET request */ +#define USB_ISTR_SUSP ((u16)0x0800) /* Suspend mode request */ +#define USB_ISTR_WKUP ((u16)0x1000) /* Wake up */ +#define USB_ISTR_ERR ((u16)0x2000) /* Error */ +#define USB_ISTR_PMAOVR ((u16)0x4000) /* Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((u16)0x8000) /* Correct Transfer */ + + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((u16)0x07FF) /* Frame Number */ +#define USB_FNR_LSOF ((u16)0x1800) /* Lost SOF */ +#define USB_FNR_LCK ((u16)0x2000) /* Locked */ +#define USB_FNR_RXDM ((u16)0x4000) /* Receive Data - Line Status */ +#define USB_FNR_RXDP ((u16)0x8000) /* Receive Data + Line Status */ + + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((u8)0x7F) /* ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((u8)0x01) /* Bit 0 */ +#define USB_DADDR_ADD1 ((u8)0x02) /* Bit 1 */ +#define USB_DADDR_ADD2 ((u8)0x04) /* Bit 2 */ +#define USB_DADDR_ADD3 ((u8)0x08) /* Bit 3 */ +#define USB_DADDR_ADD4 ((u8)0x10) /* Bit 4 */ +#define USB_DADDR_ADD5 ((u8)0x20) /* Bit 5 */ +#define USB_DADDR_ADD6 ((u8)0x40) /* Bit 6 */ + +#define USB_DADDR_EF ((u8)0x80) /* Enable Function */ + + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((u16)0xFFF8) /* Buffer Table */ + + +/* Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((u16)0xFFFE) /* Transmission Buffer Address 0 */ + + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((u16)0xFFFE) /* Transmission Buffer Address 1 */ + + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((u16)0xFFFE) /* Transmission Buffer Address 2 */ + + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((u16)0xFFFE) /* Transmission Buffer Address 3 */ + + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((u16)0xFFFE) /* Transmission Buffer Address 4 */ + + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((u16)0xFFFE) /* Transmission Buffer Address 5 */ + + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((u16)0xFFFE) /* Transmission Buffer Address 6 */ + + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((u16)0xFFFE) /* Transmission Buffer Address 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((u16)0x03FF) /* Transmission Byte Count 0 */ + + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((u16)0x03FF) /* Transmission Byte Count 1 */ + + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((u16)0x03FF) /* Transmission Byte Count 2 */ + + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((u16)0x03FF) /* Transmission Byte Count 3 */ + + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((u16)0x03FF) /* Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((u16)0x03FF) /* Transmission Byte Count 5 */ + + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((u16)0x03FF) /* Transmission Byte Count 6 */ + + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((u16)0x03FF) /* Transmission Byte Count 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 0 (high) */ + + + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 1 (high) */ + + + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 2 (high) */ + + + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((u16)0x000003FF) /* Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((u16)0x03FF0000) /* Transmission Byte Count 3 (high) */ + + + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 4 (high) */ + + + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 5 (high) */ + + + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 6 (high) */ + + + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 7 (high) */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((u16)0xFFFE) /* Reception Buffer Address 0 */ + + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((u16)0xFFFE) /* Reception Buffer Address 1 */ + + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((u16)0xFFFE) /* Reception Buffer Address 2 */ + + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((u16)0xFFFE) /* Reception Buffer Address 3 */ + + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((u16)0xFFFE) /* Reception Buffer Address 4 */ + + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((u16)0xFFFE) /* Reception Buffer Address 5 */ + + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((u16)0xFFFE) /* Reception Buffer Address 6 */ + + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((u16)0xFFFE) /* Reception Buffer Address 7 */ + + +/*----------------------------------------------------------------------------*/ + + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((u16)0x03FF) /* Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ + + +/*----------------------------------------------------------------------------*/ + + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ + + + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/* CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((u16)0x0001) /* Initialization Request */ +#define CAN_MCR_SLEEP ((u16)0x0002) /* Sleep Mode Request */ +#define CAN_MCR_TXFP ((u16)0x0004) /* Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((u16)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((u16)0x0010) /* No Automatic Retransmission */ +#define CAN_MCR_AWUM ((u16)0x0020) /* Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((u16)0x0040) /* Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((u16)0x0080) /* Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((u16)0x8000) /* bxCAN software master reset */ + + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((u16)0x0001) /* Initialization Acknowledge */ +#define CAN_MSR_SLAK ((u16)0x0002) /* Sleep Acknowledge */ +#define CAN_MSR_ERRI ((u16)0x0004) /* Error Interrupt */ +#define CAN_MSR_WKUI ((u16)0x0008) /* Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((u16)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((u16)0x0100) /* Transmit Mode */ +#define CAN_MSR_RXM ((u16)0x0200) /* Receive Mode */ +#define CAN_MSR_SAMP ((u16)0x0400) /* Last Sample Point */ +#define CAN_MSR_RX ((u16)0x0800) /* CAN Rx Signal */ + + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((u32)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((u32)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((u32)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((u32)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((u32)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((u32)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((u32)0x03000000) /* Mailbox Code */ + +#define CAN_TSR_TME ((u32)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((u32)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((u32)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((u32)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((u32)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((u8)0x03) /* FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((u8)0x08) /* FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((u8)0x10) /* FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((u8)0x20) /* Release FIFO 0 Output Mailbox */ + + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((u8)0x03) /* FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((u8)0x08) /* FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((u8)0x10) /* FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((u8)0x20) /* Release FIFO 1 Output Mailbox */ + + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((u32)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((u32)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((u32)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((u32)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((u32)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((u32)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((u32)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((u32)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((u32)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((u32)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((u32)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((u32)0x00008000) /* Error Interrupt Enable */ +#define CAN_IER_WKUIE ((u32)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((u32)0x00020000) /* Sleep Interrupt Enable */ + + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((u32)0x00000001) /* Error Warning Flag */ +#define CAN_ESR_EPVF ((u32)0x00000002) /* Error Passive Flag */ +#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-Off Flag */ + +#define CAN_ESR_LEC ((u32)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((u32)0x00000010) /* Bit 0 */ +#define CAN_ESR_LEC_1 ((u32)0x00000020) /* Bit 1 */ +#define CAN_ESR_LEC_2 ((u32)0x00000040) /* Bit 2 */ + +#define CAN_ESR_TEC ((u32)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((u32)0xFF000000) /* Receive Error Counter */ + + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((u32)0x000003FF) /* Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((u32)0x000F0000) /* Time Segment 1 */ +#define CAN_BTR_TS2 ((u32)0x00700000) /* Time Segment 2 */ +#define CAN_BTR_SJW ((u32)0x03000000) /* Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((u32)0x40000000) /* Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((u32)0x80000000) /* Silent Mode */ + + +/* Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI0R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_TI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT0R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI1R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI1R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_TI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT1R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_TI2R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_TI2R_EXID ((u32)0x001FFFF8) /* Extended identifier */ +#define CAN_TI2R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_TDT2R_TGT ((u32)0x00000100) /* Transmit Global Time */ +#define CAN_TDT2R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_TDL2R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_TDL2R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_TDL2R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_TDH2R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_TDH2R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_TDH2R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_RI0R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_RI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ +#define CAN_RI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_RDT0R_FMI ((u32)0x0000FF00) /* Filter Match Index */ +#define CAN_RDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_RDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_RDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_RDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_RDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_RDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_RDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ +#define CAN_RI1R_IDE ((u32)0x00000004) /* Identifier Extension */ +#define CAN_RI1R_EXID ((u32)0x001FFFF8) /* Extended identifier */ +#define CAN_RI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ + + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ +#define CAN_RDT1R_FMI ((u32)0x0000FF00) /* Filter Match Index */ +#define CAN_RDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ + + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ +#define CAN_RDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ +#define CAN_RDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ +#define CAN_RDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ + + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ +#define CAN_RDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ +#define CAN_RDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ +#define CAN_RDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ + +/* CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((u8)0x01) /* Filter Init Mode */ + + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((u16)0x3FFF) /* Filter Mode */ +#define CAN_FM1R_FBM0 ((u16)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((u16)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((u16)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((u16)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((u16)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((u16)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((u16)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((u16)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((u16)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((u16)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((u16)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((u16)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((u16)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((u16)0x2000) /* Filter Init Mode bit 13 */ + + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((u16)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((u16)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((u16)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((u16)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((u16)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((u16)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((u16)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((u16)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((u16)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((u16)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((u16)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((u16)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((u16)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((u16)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((u16)0x2000) /* Filter Scale Configuration bit 13 */ + + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((u16)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((u16)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((u16)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((u16)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((u16)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((u16)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((u16)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((u16)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((u16)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((u16)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((u16)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((u16)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((u16)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((u16)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((u16)0x2000) /* Filter FIFO Assignment for Filter 13 */ + + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((u16)0x3FFF) /* Filter Active */ +#define CAN_FA1R_FACT0 ((u16)0x0001) /* Filter 0 Active */ +#define CAN_FA1R_FACT1 ((u16)0x0002) /* Filter 1 Active */ +#define CAN_FA1R_FACT2 ((u16)0x0004) /* Filter 2 Active */ +#define CAN_FA1R_FACT3 ((u16)0x0008) /* Filter 3 Active */ +#define CAN_FA1R_FACT4 ((u16)0x0010) /* Filter 4 Active */ +#define CAN_FA1R_FACT5 ((u16)0x0020) /* Filter 5 Active */ +#define CAN_FA1R_FACT6 ((u16)0x0040) /* Filter 6 Active */ +#define CAN_FA1R_FACT7 ((u16)0x0080) /* Filter 7 Active */ +#define CAN_FA1R_FACT8 ((u16)0x0100) /* Filter 8 Active */ +#define CAN_FA1R_FACT9 ((u16)0x0200) /* Filter 9 Active */ +#define CAN_FA1R_FACT10 ((u16)0x0400) /* Filter 10 Active */ +#define CAN_FA1R_FACT11 ((u16)0x0800) /* Filter 11 Active */ +#define CAN_FA1R_FACT12 ((u16)0x1000) /* Filter 12 Active */ +#define CAN_FA1R_FACT13 ((u16)0x2000) /* Filter 13 Active */ + + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ + + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((u16)0x0001) /* Clock Phase */ +#define SPI_CR1_CPOL ((u16)0x0002) /* Clock Polarity */ +#define SPI_CR1_MSTR ((u16)0x0004) /* Master Selection */ + +#define SPI_CR1_BR ((u16)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((u16)0x0008) /* Bit 0 */ +#define SPI_CR1_BR_1 ((u16)0x0010) /* Bit 1 */ +#define SPI_CR1_BR_2 ((u16)0x0020) /* Bit 2 */ + +#define SPI_CR1_SPE ((u16)0x0040) /* SPI Enable */ +#define SPI_CR1_LSBFIRST ((u16)0x0080) /* Frame Format */ +#define SPI_CR1_SSI ((u16)0x0100) /* Internal slave select */ +#define SPI_CR1_SSM ((u16)0x0200) /* Software slave management */ +#define SPI_CR1_RXONLY ((u16)0x0400) /* Receive only */ +#define SPI_CR1_DFF ((u16)0x0800) /* Data Frame Format */ +#define SPI_CR1_CRCNEXT ((u16)0x1000) /* Transmit CRC next */ +#define SPI_CR1_CRCEN ((u16)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((u16)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((u16)0x8000) /* Bidirectional data mode enable */ + + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((u8)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((u8)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((u8)0x04) /* SS Output Enable */ +#define SPI_CR2_ERRIE ((u8)0x20) /* Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((u8)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((u8)0x80) /* Tx buffer Empty Interrupt Enable */ + + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((u8)0x01) /* Receive buffer Not Empty */ +#define SPI_SR_TXE ((u8)0x02) /* Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((u8)0x04) /* Channel side */ +#define SPI_SR_UDR ((u8)0x08) /* Underrun flag */ +#define SPI_SR_CRCERR ((u8)0x10) /* CRC Error flag */ +#define SPI_SR_MODF ((u8)0x20) /* Mode fault */ +#define SPI_SR_OVR ((u8)0x40) /* Overrun flag */ +#define SPI_SR_BSY ((u8)0x80) /* Busy flag */ + + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((u16)0xFFFF) /* Data Register */ + + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((u16)0xFFFF) /* CRC polynomial register */ + + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((u16)0xFFFF) /* Rx CRC Register */ + + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((u16)0xFFFF) /* Tx CRC Register */ + + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((u16)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((u16)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((u16)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((u16)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((u16)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((u16)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((u16)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((u16)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((u16)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((u16)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((u16)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((u16)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((u16)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((u16)0x0800) /* I2S mode selection */ + + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((u16)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((u16)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((u16)0x0200) /* Master Clock Output Enable */ + + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((u16)0x0001) /* Peripheral Enable */ +#define I2C_CR1_SMBUS ((u16)0x0002) /* SMBus Mode */ +#define I2C_CR1_SMBTYPE ((u16)0x0008) /* SMBus Type */ +#define I2C_CR1_ENARP ((u16)0x0010) /* ARP Enable */ +#define I2C_CR1_ENPEC ((u16)0x0020) /* PEC Enable */ +#define I2C_CR1_ENGC ((u16)0x0040) /* General Call Enable */ +#define I2C_CR1_NOSTRETCH ((u16)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((u16)0x0100) /* Start Generation */ +#define I2C_CR1_STOP ((u16)0x0200) /* Stop Generation */ +#define I2C_CR1_ACK ((u16)0x0400) /* Acknowledge Enable */ +#define I2C_CR1_POS ((u16)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((u16)0x1000) /* Packet Error Checking */ +#define I2C_CR1_ALERT ((u16)0x2000) /* SMBus Alert */ +#define I2C_CR1_SWRST ((u16)0x8000) /* Software Reset */ + + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((u16)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((u16)0x0001) /* Bit 0 */ +#define I2C_CR2_FREQ_1 ((u16)0x0002) /* Bit 1 */ +#define I2C_CR2_FREQ_2 ((u16)0x0004) /* Bit 2 */ +#define I2C_CR2_FREQ_3 ((u16)0x0008) /* Bit 3 */ +#define I2C_CR2_FREQ_4 ((u16)0x0010) /* Bit 4 */ +#define I2C_CR2_FREQ_5 ((u16)0x0020) /* Bit 5 */ + +#define I2C_CR2_ITERREN ((u16)0x0100) /* Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((u16)0x0200) /* Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((u16)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((u16)0x0800) /* DMA Requests Enable */ +#define I2C_CR2_LAST ((u16)0x1000) /* DMA Last Transfer */ + + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((u16)0x00FE) /* Interface Address */ +#define I2C_OAR1_ADD8_9 ((u16)0x0300) /* Interface Address */ + +#define I2C_OAR1_ADD0 ((u16)0x0001) /* Bit 0 */ +#define I2C_OAR1_ADD1 ((u16)0x0002) /* Bit 1 */ +#define I2C_OAR1_ADD2 ((u16)0x0004) /* Bit 2 */ +#define I2C_OAR1_ADD3 ((u16)0x0008) /* Bit 3 */ +#define I2C_OAR1_ADD4 ((u16)0x0010) /* Bit 4 */ +#define I2C_OAR1_ADD5 ((u16)0x0020) /* Bit 5 */ +#define I2C_OAR1_ADD6 ((u16)0x0040) /* Bit 6 */ +#define I2C_OAR1_ADD7 ((u16)0x0080) /* Bit 7 */ +#define I2C_OAR1_ADD8 ((u16)0x0100) /* Bit 8 */ +#define I2C_OAR1_ADD9 ((u16)0x0200) /* Bit 9 */ + +#define I2C_OAR1_ADDMODE ((u16)0x8000) /* Addressing Mode (Slave mode) */ + + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((u8)0x01) /* Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((u8)0xFE) /* Interface address */ + + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((u8)0xFF) /* 8-bit Data Register */ + + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((u16)0x0001) /* Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((u16)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((u16)0x0004) /* Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((u16)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((u16)0x0010) /* Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((u16)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((u16)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((u16)0x0100) /* Bus Error */ +#define I2C_SR1_ARLO ((u16)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((u16)0x0400) /* Acknowledge Failure */ +#define I2C_SR1_OVR ((u16)0x0800) /* Overrun/Underrun */ +#define I2C_SR1_PECERR ((u16)0x1000) /* PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((u16)0x4000) /* Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((u16)0x8000) /* SMBus Alert */ + + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((u16)0x0001) /* Master/Slave */ +#define I2C_SR2_BUSY ((u16)0x0002) /* Bus Busy */ +#define I2C_SR2_TRA ((u16)0x0004) /* Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((u16)0x0010) /* General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((u16)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((u16)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((u16)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((u16)0xFF00) /* Packet Error Checking Register */ + + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((u16)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((u16)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((u16)0x8000) /* I2C Master Mode Selection */ + + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((u8)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + + + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((u16)0x0001) /* Parity Error */ +#define USART_SR_FE ((u16)0x0002) /* Framing Error */ +#define USART_SR_NE ((u16)0x0004) /* Noise Error Flag */ +#define USART_SR_ORE ((u16)0x0008) /* OverRun Error */ +#define USART_SR_IDLE ((u16)0x0010) /* IDLE line detected */ +#define USART_SR_RXNE ((u16)0x0020) /* Read Data Register Not Empty */ +#define USART_SR_TC ((u16)0x0040) /* Transmission Complete */ +#define USART_SR_TXE ((u16)0x0080) /* Transmit Data Register Empty */ +#define USART_SR_LBD ((u16)0x0100) /* LIN Break Detection Flag */ +#define USART_SR_CTS ((u16)0x0200) /* CTS Flag */ + + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((u16)0x01FF) /* Data value */ + + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((u16)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((u16)0xFFF0) /* Mantissa of USARTDIV */ + + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((u16)0x0001) /* Send Break */ +#define USART_CR1_RWU ((u16)0x0002) /* Receiver wakeup */ +#define USART_CR1_RE ((u16)0x0004) /* Receiver Enable */ +#define USART_CR1_TE ((u16)0x0008) /* Transmitter Enable */ +#define USART_CR1_IDLEIE ((u16)0x0010) /* IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((u16)0x0020) /* RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((u16)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((u16)0x0080) /* PE Interrupt Enable */ +#define USART_CR1_PEIE ((u16)0x0100) /* PE Interrupt Enable */ +#define USART_CR1_PS ((u16)0x0200) /* Parity Selection */ +#define USART_CR1_PCE ((u16)0x0400) /* Parity Control Enable */ +#define USART_CR1_WAKE ((u16)0x0800) /* Wakeup method */ +#define USART_CR1_M ((u16)0x1000) /* Word length */ +#define USART_CR1_UE ((u16)0x2000) /* USART Enable */ + + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((u16)0x000F) /* Address of the USART node */ +#define USART_CR2_LBDL ((u16)0x0020) /* LIN Break Detection Length */ +#define USART_CR2_LBDIE ((u16)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((u16)0x0100) /* Last Bit Clock pulse */ +#define USART_CR2_CPHA ((u16)0x0200) /* Clock Phase */ +#define USART_CR2_CPOL ((u16)0x0400) /* Clock Polarity */ +#define USART_CR2_CLKEN ((u16)0x0800) /* Clock Enable */ + +#define USART_CR2_STOP ((u16)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((u16)0x1000) /* Bit 0 */ +#define USART_CR2_STOP_1 ((u16)0x2000) /* Bit 1 */ + +#define USART_CR2_LINEN ((u16)0x4000) /* LIN mode enable */ + + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((u16)0x0001) /* Error Interrupt Enable */ +#define USART_CR3_IREN ((u16)0x0002) /* IrDA mode Enable */ +#define USART_CR3_IRLP ((u16)0x0004) /* IrDA Low-Power */ +#define USART_CR3_HDSEL ((u16)0x0008) /* Half-Duplex Selection */ +#define USART_CR3_NACK ((u16)0x0010) /* Smartcard NACK enable */ +#define USART_CR3_SCEN ((u16)0x0020) /* Smartcard mode enable */ +#define USART_CR3_DMAR ((u16)0x0040) /* DMA Enable Receiver */ +#define USART_CR3_DMAT ((u16)0x0080) /* DMA Enable Transmitter */ +#define USART_CR3_RTSE ((u16)0x0100) /* RTS Enable */ +#define USART_CR3_CTSE ((u16)0x0200) /* CTS Enable */ +#define USART_CR3_CTSIE ((u16)0x0400) /* CTS Interrupt Enable */ + + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((u16)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((u16)0x0001) /* Bit 0 */ +#define USART_GTPR_PSC_1 ((u16)0x0002) /* Bit 1 */ +#define USART_GTPR_PSC_2 ((u16)0x0004) /* Bit 2 */ +#define USART_GTPR_PSC_3 ((u16)0x0008) /* Bit 3 */ +#define USART_GTPR_PSC_4 ((u16)0x0010) /* Bit 4 */ +#define USART_GTPR_PSC_5 ((u16)0x0020) /* Bit 5 */ +#define USART_GTPR_PSC_6 ((u16)0x0040) /* Bit 6 */ +#define USART_GTPR_PSC_7 ((u16)0x0080) /* Bit 7 */ + +#define USART_GTPR_GT ((u16)0xFF00) /* Guard time value */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((u32)0x00000FFF) /* Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((u32)0xFFFF0000) /* REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((u32)0x00010000) /* Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((u32)0x00020000) /* Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((u32)0x00040000) /* Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((u32)0x00080000) /* Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((u32)0x00100000) /* Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((u32)0x00200000) /* Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((u32)0x00400000) /* Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((u32)0x00800000) /* Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((u32)0x01000000) /* Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((u32)0x02000000) /* Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((u32)0x04000000) /* Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((u32)0x08000000) /* Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((u32)0x10000000) /* Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((u32)0x20000000) /* Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((u32)0x40000000) /* Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((u32)0x80000000) /* Bit 15 */ + + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((u32)0x00000001) /* Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((u32)0x00000002) /* Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((u32)0x00000004) /* Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((u32)0x00000020) /* Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((u32)0x000000C0) /* TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((u32)0x00000040) /* Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((u32)0x00000080) /* Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((u32)0x00000100) /* Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((u32)0x00000200) /* Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((u32)0x00000400) /* TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((u32)0x00000800) /* TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((u32)0x00001000) /* TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((u32)0x00002000) /* TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN_STOP ((u32)0x00004000) /* Debug CAN stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((u32)0x00008000) /* SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((u32)0x00010000) /* SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((u32)0x00020000) /* TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((u32)0x00040000) /* TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((u32)0x00080000) /* TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((u32)0x00100000) /* TIM8 counter stopped when core is halted */ + + + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((u8)0x07) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((u8)0x01) /* Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((u8)0x02) /* Bit 1 */ +#define FLASH_ACR_LATENCY_2 ((u8)0x04) /* Bit 2 */ + +#define FLASH_ACR_HLFCYA ((u8)0x08) /* Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((u8)0x10) /* Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((u8)0x20) /* Prefetch Buffer Status */ + + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((u32)0xFFFFFFFF) /* FPEC Key */ + + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((u32)0xFFFFFFFF) /* Option Byte Key */ + + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((u8)0x01) /* Busy */ +#define FLASH_SR_PGERR ((u8)0x04) /* Programming Error */ +#define FLASH_SR_WRPRTERR ((u8)0x10) /* Write Protection Error */ +#define FLASH_SR_EOP ((u8)0x20) /* End of operation */ + + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((u16)0x0001) /* Programming */ +#define FLASH_CR_PER ((u16)0x0002) /* Page Erase */ +#define FLASH_CR_MER ((u16)0x0004) /* Mass Erase */ +#define FLASH_CR_OPTPG ((u16)0x0010) /* Option Byte Programming */ +#define FLASH_CR_OPTER ((u16)0x0020) /* Option Byte Erase */ +#define FLASH_CR_STRT ((u16)0x0040) /* Start */ +#define FLASH_CR_LOCK ((u16)0x0080) /* Lock */ +#define FLASH_CR_OPTWRE ((u16)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((u16)0x0400) /* Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((u16)0x1000) /* End of operation interrupt enable */ + + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((u32)0xFFFFFFFF) /* Flash Address */ + + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((u16)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((u16)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((u16)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((u16)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((u16)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((u16)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_Notused ((u16)0x03E0) /* Not used */ + + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((u32)0xFFFFFFFF) /* Write Protect */ + + +/*----------------------------------------------------------------------------*/ + + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((u32)0x000000FF) /* Read protection option byte */ +#define FLASH_RDP_nRDP ((u32)0x0000FF00) /* Read protection complemented option byte */ + + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((u32)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((u32)0xFF000000) /* User complemented option byte */ + + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((u32)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((u32)0x0000FF00) /* User data storage complemented option byte */ + + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((u32)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((u32)0xFF000000) /* User data storage complemented option byte */ + + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((u32)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((u32)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ + + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ + + +/* Exported macro ------------------------------------------------------------*/ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = 0x0) + +#define WRITE_REG(REG, VAL) ((REG) = VAL) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK))) + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_MAP_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h new file mode 100644 index 000000000..5a3ce7ef1 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h @@ -0,0 +1,287 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_nvic.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* NVIC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_NVIC_H +#define __STM32F10x_NVIC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* NVIC Init Structure definition */ +typedef struct +{ + u8 NVIC_IRQChannel; + u8 NVIC_IRQChannelPreemptionPriority; + u8 NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* IRQ Channels --------------------------------------------------------------*/ +#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ +#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ +#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ +#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ +#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ +#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ +#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ +#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ +#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ +#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ +#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ +#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */ +#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */ +#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */ +#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */ +#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */ +#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */ +#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */ +#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */ +#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ +#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ +#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ +#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ +#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ +#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ +#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ +#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ +#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ +#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ +#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ +#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ +#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ +#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ +#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ +#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ +#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ +#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ +#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ +#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ +#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ +#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ +#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ +#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ +#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */ +#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */ +#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */ +#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */ +#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */ +#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */ +#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */ +#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */ +#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */ +#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */ +#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */ +#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */ +#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */ +#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */ +#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */ +#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */ +#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */ + + +#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \ + ((CHANNEL) == PVD_IRQChannel) || \ + ((CHANNEL) == TAMPER_IRQChannel) || \ + ((CHANNEL) == RTC_IRQChannel) || \ + ((CHANNEL) == FLASH_IRQChannel) || \ + ((CHANNEL) == RCC_IRQChannel) || \ + ((CHANNEL) == EXTI0_IRQChannel) || \ + ((CHANNEL) == EXTI1_IRQChannel) || \ + ((CHANNEL) == EXTI2_IRQChannel) || \ + ((CHANNEL) == EXTI3_IRQChannel) || \ + ((CHANNEL) == EXTI4_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel1_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel2_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel3_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel4_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel5_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel6_IRQChannel) || \ + ((CHANNEL) == DMA1_Channel7_IRQChannel) || \ + ((CHANNEL) == ADC1_2_IRQChannel) || \ + ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \ + ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \ + ((CHANNEL) == CAN_RX1_IRQChannel) || \ + ((CHANNEL) == CAN_SCE_IRQChannel) || \ + ((CHANNEL) == EXTI9_5_IRQChannel) || \ + ((CHANNEL) == TIM1_BRK_IRQChannel) || \ + ((CHANNEL) == TIM1_UP_IRQChannel) || \ + ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \ + ((CHANNEL) == TIM1_CC_IRQChannel) || \ + ((CHANNEL) == TIM2_IRQChannel) || \ + ((CHANNEL) == TIM3_IRQChannel) || \ + ((CHANNEL) == TIM4_IRQChannel) || \ + ((CHANNEL) == I2C1_EV_IRQChannel) || \ + ((CHANNEL) == I2C1_ER_IRQChannel) || \ + ((CHANNEL) == I2C2_EV_IRQChannel) || \ + ((CHANNEL) == I2C2_ER_IRQChannel) || \ + ((CHANNEL) == SPI1_IRQChannel) || \ + ((CHANNEL) == SPI2_IRQChannel) || \ + ((CHANNEL) == USART1_IRQChannel) || \ + ((CHANNEL) == USART2_IRQChannel) || \ + ((CHANNEL) == USART3_IRQChannel) || \ + ((CHANNEL) == EXTI15_10_IRQChannel) || \ + ((CHANNEL) == RTCAlarm_IRQChannel) || \ + ((CHANNEL) == USBWakeUp_IRQChannel) || \ + ((CHANNEL) == TIM8_BRK_IRQChannel) || \ + ((CHANNEL) == TIM8_UP_IRQChannel) || \ + ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \ + ((CHANNEL) == TIM8_CC_IRQChannel) || \ + ((CHANNEL) == ADC3_IRQChannel) || \ + ((CHANNEL) == FSMC_IRQChannel) || \ + ((CHANNEL) == SDIO_IRQChannel) || \ + ((CHANNEL) == TIM5_IRQChannel) || \ + ((CHANNEL) == SPI3_IRQChannel) || \ + ((CHANNEL) == UART4_IRQChannel) || \ + ((CHANNEL) == UART5_IRQChannel) || \ + ((CHANNEL) == TIM6_IRQChannel) || \ + ((CHANNEL) == TIM7_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel1_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel2_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel3_IRQChannel) || \ + ((CHANNEL) == DMA2_Channel4_5_IRQChannel)) + + +/* System Handlers -----------------------------------------------------------*/ +#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ +#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ +#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ +#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ +#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ +#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ +#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ +#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ +#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ + +#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault)) + +#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_SVCall) || \ + ((HANDLER) == SystemHandler_DebugMonitor) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_SVCall)) + +#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_SVCall) || \ + ((HANDLER) == SystemHandler_DebugMonitor) || \ + ((HANDLER) == SystemHandler_PSV) || \ + ((HANDLER) == SystemHandler_SysTick)) + +#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \ + ((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault) || \ + ((HANDLER) == SystemHandler_UsageFault) || \ + ((HANDLER) == SystemHandler_DebugMonitor)) + +#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ + ((HANDLER) == SystemHandler_BusFault)) + + +/* Vector Table Base ---------------------------------------------------------*/ +#define NVIC_VectTab_RAM ((u32)0x20000000) +#define NVIC_VectTab_FLASH ((u32)0x08000000) + +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) + +/* System Low Power ----------------------------------------------------------*/ +#define NVIC_LP_SEVONPEND ((u8)0x10) +#define NVIC_LP_SLEEPDEEP ((u8)0x04) +#define NVIC_LP_SLEEPONEXIT ((u8)0x02) + +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) + +/* Preemption Priority Group -------------------------------------------------*/ +#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) +#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void NVIC_DeInit(void); +void NVIC_SCBDeInit(void); +void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SETPRIMASK(void); +void NVIC_RESETPRIMASK(void); +void NVIC_SETFAULTMASK(void); +void NVIC_RESETFAULTMASK(void); +void NVIC_BASEPRICONFIG(u32 NewPriority); +u32 NVIC_GetBASEPRI(void); +u16 NVIC_GetCurrentPendingIRQChannel(void); +ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); +void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); +void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); +u16 NVIC_GetCurrentActiveHandler(void); +ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); +u32 NVIC_GetCPUID(void); +void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); +void NVIC_GenerateSystemReset(void); +void NVIC_GenerateCoreReset(void); +void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); +void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); +void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, + u8 SystemHandlerSubPriority); +ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); +void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); +void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); +ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); +u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); +u32 NVIC_GetFaultAddress(u32 SystemHandler); + +#endif /* __STM32F10x_NVIC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h new file mode 100644 index 000000000..1ca3e5261 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h @@ -0,0 +1,80 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_type.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the common data types used for the +* STM32F10x firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TYPE_H +#define __STM32F10x_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum {FALSE = 0, TRUE = !FALSE} bool; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32F10x_TYPE_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h deleted file mode 100644 index 681abcffe..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_conf.h +++ /dev/null @@ -1,142 +0,0 @@ -/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** -* File Name : stm32f10x_conf.h -* Author : MCD Application Team -* Version : V1.0 -* Date : 10/08/2007 -* Description : Library configuration file. -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CONF_H -#define __STM32F10x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_type.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to compile the library in DEBUG mode, this will expanse - the "assert_param" macro in the firmware library code (see "Exported macro" - section below) */ -/* #define DEBUG 1*/ - -/* Comment the line below to disable the specific peripheral inclusion */ -/************************************* ADC ************************************/ -//#define _ADC -//#define _ADC1 -//#define _ADC2 - -/************************************* BKP ************************************/ -//#define _BKP - -/************************************* CAN ************************************/ -//#define _CAN - -/************************************* DMA ************************************/ -//#define _DMA -//#define _DMA_Channel1 -//#define _DMA_Channel2 -//#define _DMA_Channel3 -//#define _DMA_Channel4 -//#define _DMA_Channel5 -//#define _DMA_Channel6 -//#define _DMA_Channel7 - -/************************************* EXTI ***********************************/ -//#define _EXTI - -/************************************* FLASH and Option Bytes *****************/ -#define _FLASH -/* Uncomment the line below to enable FLASH program/erase/protections functions, - otherwise only FLASH configuration (latency, prefetch, half cycle) functions - are enabled */ -/* #define _FLASH_PROG */ - -/************************************* GPIO ***********************************/ -#define _GPIO -#define _GPIOA -#define _GPIOB -#define _GPIOC -#define _GPIOD -//#define _GPIOE -//#define _AFIO - -/************************************* I2C ************************************/ -//#define _I2C -//#define _I2C1 -//#define _I2C2 - -/************************************* IWDG ***********************************/ -//#define _IWDG - -/************************************* NVIC ***********************************/ -//#define _NVIC - -/************************************* PWR ************************************/ -//#define _PWR - -/************************************* RCC ************************************/ -#define _RCC - -/************************************* RTC ************************************/ -//#define _RTC - -/************************************* SPI ************************************/ -//#define _SPI -//#define _SPI1 -//#define _SPI2 - -/************************************* SysTick ********************************/ -//#define _SysTick - -/************************************* TIM1 ***********************************/ -//#define _TIM1 - -/************************************* TIM ************************************/ -//#define _TIM -//#define _TIM2 -//#define _TIM3 -//#define _TIM4 - -/************************************* USART **********************************/ -#define _USART -#define _USART1 -#define _USART2 -#define _USART3 - -/************************************* WWDG ***********************************/ -//#define _WWDG - -/* In the following line adjust the value of External High Speed oscillator (HSE) - used in your application */ -#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef DEBUG -/******************************************************************************* -* Macro Name : assert_param -* Description : The assert_param macro is used for function's parameters check. -* It is used only if the library is compiled in DEBUG mode. -* Input : - expr: If expr is false, it calls assert_failed function -* which reports the name of the source file and the source -* line number of the call that failed. -* If expr is true, it returns no value. -* Return : None -*******************************************************************************/ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(u8* file, u32 line); -#else - #define assert_param(expr) ((void)0) -#endif /* DEBUG */ - -#endif /* __STM32F10x_CONF_H */ - -/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h deleted file mode 100644 index 410d78a6a..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_map.h +++ /dev/null @@ -1,857 +0,0 @@ -/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** -* File Name : stm32f10x_map.h -* Author : MCD Application Team -* Version : V1.0 -* Date : 10/08/2007 -* Description : This file contains all the peripheral register's definitions -* and memory mapping. -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_MAP_H -#define __STM32F10x_MAP_H - -#ifndef EXT - #define EXT extern -#endif /* EXT */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_conf.h" -#include "stm32f10x_type.h" -#include "cortexm3_macro.h" - -/* Exported types ------------------------------------------------------------*/ -/******************************************************************************/ -/* Peripheral registers structures */ -/******************************************************************************/ - -/*------------------------ Analog to Digital Converter -----------------------*/ -typedef struct -{ - vu32 SR; - vu32 CR1; - vu32 CR2; - vu32 SMPR1; - vu32 SMPR2; - vu32 JOFR1; - vu32 JOFR2; - vu32 JOFR3; - vu32 JOFR4; - vu32 HTR; - vu32 LTR; - vu32 SQR1; - vu32 SQR2; - vu32 SQR3; - vu32 JSQR; - vu32 JDR1; - vu32 JDR2; - vu32 JDR3; - vu32 JDR4; - vu32 DR; -} ADC_TypeDef; - -/*------------------------ Backup Registers ----------------------------------*/ -typedef struct -{ - u32 RESERVED0; - vu16 DR1; - u16 RESERVED1; - vu16 DR2; - u16 RESERVED2; - vu16 DR3; - u16 RESERVED3; - vu16 DR4; - u16 RESERVED4; - vu16 DR5; - u16 RESERVED5; - vu16 DR6; - u16 RESERVED6; - vu16 DR7; - u16 RESERVED7; - vu16 DR8; - u16 RESERVED8; - vu16 DR9; - u16 RESERVED9; - vu16 DR10; - u16 RESERVED10; - vu16 RTCCR; - u16 RESERVED11; - vu16 CR; - u16 RESERVED12; - vu16 CSR; - u16 RESERVED13; -} BKP_TypeDef; - -/*------------------------ Controller Area Network ---------------------------*/ -typedef struct -{ - vu32 TIR; - vu32 TDTR; - vu32 TDLR; - vu32 TDHR; -} CAN_TxMailBox_TypeDef; - -typedef struct -{ - vu32 RIR; - vu32 RDTR; - vu32 RDLR; - vu32 RDHR; -} CAN_FIFOMailBox_TypeDef; - -typedef struct -{ - vu32 FR0; - vu32 FR1; -} CAN_FilterRegister_TypeDef; - -typedef struct -{ - vu32 MCR; - vu32 MSR; - vu32 TSR; - vu32 RF0R; - vu32 RF1R; - vu32 IER; - vu32 ESR; - vu32 BTR; - u32 RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - u32 RESERVED1[12]; - vu32 FMR; - vu32 FM0R; - u32 RESERVED2[1]; - vu32 FS0R; - u32 RESERVED3[1]; - vu32 FFA0R; - u32 RESERVED4[1]; - vu32 FA0R; - u32 RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[14]; -} CAN_TypeDef; - -/*------------------------ DMA Controller ------------------------------------*/ -typedef struct -{ - vu32 CCR; - vu32 CNDTR; - vu32 CPAR; - vu32 CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - vu32 ISR; - vu32 IFCR; -} DMA_TypeDef; - -/*------------------------ External Interrupt/Event Controller ---------------*/ -typedef struct -{ - vu32 IMR; - vu32 EMR; - vu32 RTSR; - vu32 FTSR; - vu32 SWIER; - vu32 PR; -} EXTI_TypeDef; - -/*------------------------ FLASH and Option Bytes Registers ------------------*/ -typedef struct -{ - vu32 ACR; - vu32 KEYR; - vu32 OPTKEYR; - vu32 SR; - vu32 CR; - vu32 AR; - vu32 RESERVED; - vu32 OBR; - vu32 WRPR; -} FLASH_TypeDef; - -typedef struct -{ - vu16 RDP; - vu16 USER; - vu16 Data0; - vu16 Data1; - vu16 WRP0; - vu16 WRP1; - vu16 WRP2; - vu16 WRP3; -} OB_TypeDef; - -/*------------------------ General Purpose and Alternate Function IO ---------*/ -typedef struct -{ - vu32 CRL; - vu32 CRH; - vu32 IDR; - vu32 ODR; - vu32 BSRR; - vu32 BRR; - vu32 LCKR; -} GPIO_TypeDef; - -typedef struct -{ - vu32 EVCR; - vu32 MAPR; - vu32 EXTICR[4]; -} AFIO_TypeDef; - -/*------------------------ Inter-integrated Circuit Interface ----------------*/ -typedef struct -{ - vu16 CR1; - u16 RESERVED0; - vu16 CR2; - u16 RESERVED1; - vu16 OAR1; - u16 RESERVED2; - vu16 OAR2; - u16 RESERVED3; - vu16 DR; - u16 RESERVED4; - vu16 SR1; - u16 RESERVED5; - vu16 SR2; - u16 RESERVED6; - vu16 CCR; - u16 RESERVED7; - vu16 TRISE; - u16 RESERVED8; -} I2C_TypeDef; - -/*------------------------ Independent WATCHDOG ------------------------------*/ -typedef struct -{ - vu32 KR; - vu32 PR; - vu32 RLR; - vu32 SR; -} IWDG_TypeDef; - -/*------------------------ Nested Vectored Interrupt Controller --------------*/ -typedef struct -{ - vu32 ISER[2]; - u32 RESERVED0[30]; - vu32 ICER[2]; - u32 RSERVED1[30]; - vu32 ISPR[2]; - u32 RESERVED2[30]; - vu32 ICPR[2]; - u32 RESERVED3[30]; - vu32 IABR[2]; - u32 RESERVED4[62]; - vu32 IPR[11]; -} NVIC_TypeDef; - -typedef struct -{ - vuc32 CPUID; - vu32 ICSR; - vu32 VTOR; - vu32 AIRCR; - vu32 SCR; - vu32 CCR; - vu32 SHPR[3]; - vu32 SHCSR; - vu32 CFSR; - vu32 HFSR; - vu32 DFSR; - vu32 MMFAR; - vu32 BFAR; - vu32 AFSR; -} SCB_TypeDef; - -/*------------------------ Power Control -------------------------------------*/ -typedef struct -{ - vu32 CR; - vu32 CSR; -} PWR_TypeDef; - -/*------------------------ Reset and Clock Control ---------------------------*/ -typedef struct -{ - vu32 CR; - vu32 CFGR; - vu32 CIR; - vu32 APB2RSTR; - vu32 APB1RSTR; - vu32 AHBENR; - vu32 APB2ENR; - vu32 APB1ENR; - vu32 BDCR; - vu32 CSR; -} RCC_TypeDef; - -/*------------------------ Real-Time Clock -----------------------------------*/ -typedef struct -{ - vu16 CRH; - u16 RESERVED0; - vu16 CRL; - u16 RESERVED1; - vu16 PRLH; - u16 RESERVED2; - vu16 PRLL; - u16 RESERVED3; - vu16 DIVH; - u16 RESERVED4; - vu16 DIVL; - u16 RESERVED5; - vu16 CNTH; - u16 RESERVED6; - vu16 CNTL; - u16 RESERVED7; - vu16 ALRH; - u16 RESERVED8; - vu16 ALRL; - u16 RESERVED9; -} RTC_TypeDef; - -/*------------------------ Serial Peripheral Interface -----------------------*/ -typedef struct -{ - vu16 CR1; - u16 RESERVED0; - vu16 CR2; - u16 RESERVED1; - vu16 SR; - u16 RESERVED2; - vu16 DR; - u16 RESERVED3; - vu16 CRCPR; - u16 RESERVED4; - vu16 RXCRCR; - u16 RESERVED5; - vu16 TXCRCR; - u16 RESERVED6; -} SPI_TypeDef; - -/*------------------------ SystemTick ----------------------------------------*/ -typedef struct -{ - vu32 CTRL; - vu32 LOAD; - vu32 VAL; - vuc32 CALIB; -} SysTick_TypeDef; - -/*------------------------ Advanced Control Timer ----------------------------*/ -typedef struct -{ - vu16 CR1; - u16 RESERVED0; - vu16 CR2; - u16 RESERVED1; - vu16 SMCR; - u16 RESERVED2; - vu16 DIER; - u16 RESERVED3; - vu16 SR; - u16 RESERVED4; - vu16 EGR; - u16 RESERVED5; - vu16 CCMR1; - u16 RESERVED6; - vu16 CCMR2; - u16 RESERVED7; - vu16 CCER; - u16 RESERVED8; - vu16 CNT; - u16 RESERVED9; - vu16 PSC; - u16 RESERVED10; - vu16 ARR; - u16 RESERVED11; - vu16 RCR; - u16 RESERVED12; - vu16 CCR1; - u16 RESERVED13; - vu16 CCR2; - u16 RESERVED14; - vu16 CCR3; - u16 RESERVED15; - vu16 CCR4; - u16 RESERVED16; - vu16 BDTR; - u16 RESERVED17; - vu16 DCR; - u16 RESERVED18; - vu16 DMAR; - u16 RESERVED19; -} TIM1_TypeDef; - -/*------------------------ General Purpose Timer -----------------------------*/ -typedef struct -{ - vu16 CR1; - u16 RESERVED0; - vu16 CR2; - u16 RESERVED1; - vu16 SMCR; - u16 RESERVED2; - vu16 DIER; - u16 RESERVED3; - vu16 SR; - u16 RESERVED4; - vu16 EGR; - u16 RESERVED5; - vu16 CCMR1; - u16 RESERVED6; - vu16 CCMR2; - u16 RESERVED7; - vu16 CCER; - u16 RESERVED8; - vu16 CNT; - u16 RESERVED9; - vu16 PSC; - u16 RESERVED10; - vu16 ARR; - u16 RESERVED11[3]; - vu16 CCR1; - u16 RESERVED12; - vu16 CCR2; - u16 RESERVED13; - vu16 CCR3; - u16 RESERVED14; - vu16 CCR4; - u16 RESERVED15[3]; - vu16 DCR; - u16 RESERVED16; - vu16 DMAR; - u16 RESERVED17; -} TIM_TypeDef; - -/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ -typedef struct -{ - vu16 SR; - u16 RESERVED0; - vu16 DR; - u16 RESERVED1; - vu16 BRR; - u16 RESERVED2; - vu16 CR1; - u16 RESERVED3; - vu16 CR2; - u16 RESERVED4; - vu16 CR3; - u16 RESERVED5; - vu16 GTPR; - u16 RESERVED6; -} USART_TypeDef; - -/*------------------------ Window WATCHDOG -----------------------------------*/ -typedef struct -{ - vu32 CR; - vu32 CFR; - vu32 SR; -} WWDG_TypeDef; - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Peripheral and SRAM base address in the alias region */ -#define PERIPH_BB_BASE ((u32)0x42000000) -#define SRAM_BB_BASE ((u32)0x22000000) - -/* Peripheral and SRAM base address in the bit-band region */ -#define SRAM_BASE ((u32)0x20000000) -#define PERIPH_BASE ((u32)0x40000000) - -/* Flash refisters base address */ -#define FLASH_BASE ((u32)0x40022000) -/* Flash Option Bytes base address */ -#define OB_BASE ((u32)0x1FFFF800) - -/* Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN_BASE (APB1PERIPH_BASE + 0x6400) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define DMA_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) - -/* System Control Space memory map */ -#define SCS_BASE ((u32)0xE000E000) - -#define SysTick_BASE (SCS_BASE + 0x0010) -#define NVIC_BASE (SCS_BASE + 0x0100) -#define SCB_BASE (SCS_BASE + 0x0D00) - - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ - -/*------------------------ Non Debug Mode ------------------------------------*/ -#ifndef DEBUG -#ifdef _TIM2 - #define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#endif /*_TIM2 */ - -#ifdef _TIM3 - #define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#endif /*_TIM3 */ - -#ifdef _TIM4 - #define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#endif /*_TIM4 */ - -#ifdef _RTC - #define RTC ((RTC_TypeDef *) RTC_BASE) -#endif /*_RTC */ - -#ifdef _WWDG - #define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#endif /*_WWDG */ - -#ifdef _IWDG - #define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#endif /*_IWDG */ - -#ifdef _SPI2 - #define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#endif /*_SPI2 */ - -#ifdef _USART2 - #define USART2 ((USART_TypeDef *) USART2_BASE) -#endif /*_USART2 */ - -#ifdef _USART3 - #define USART3 ((USART_TypeDef *) USART3_BASE) -#endif /*_USART3 */ - -#ifdef _I2C1 - #define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#endif /*_I2C1 */ - -#ifdef _I2C2 - #define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#endif /*_I2C2 */ - -#ifdef _CAN - #define CAN ((CAN_TypeDef *) CAN_BASE) -#endif /*_CAN */ - -#ifdef _BKP - #define BKP ((BKP_TypeDef *) BKP_BASE) -#endif /*_BKP */ - -#ifdef _PWR - #define PWR ((PWR_TypeDef *) PWR_BASE) -#endif /*_PWR */ - -#ifdef _AFIO - #define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#endif /*_AFIO */ - -#ifdef _EXTI - #define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#endif /*_EXTI */ - -#ifdef _GPIOA - #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#endif /*_GPIOA */ - -#ifdef _GPIOB - #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#endif /*_GPIOB */ - -#ifdef _GPIOC - #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#endif /*_GPIOC */ - -#ifdef _GPIOD - #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#endif /*_GPIOD */ - -#ifdef _GPIOE - #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#endif /*_GPIOE */ - -#ifdef _ADC1 - #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#endif /*_ADC1 */ - -#ifdef _ADC2 - #define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#endif /*_ADC2 */ - -#ifdef _TIM1 - #define TIM1 ((TIM1_TypeDef *) TIM1_BASE) -#endif /*_TIM1 */ - -#ifdef _SPI1 - #define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#endif /*_SPI1 */ - -#ifdef _USART1 - #define USART1 ((USART_TypeDef *) USART1_BASE) -#endif /*_USART1 */ - -#ifdef _DMA - #define DMA ((DMA_TypeDef *) DMA_BASE) -#endif /*_DMA */ - -#ifdef _DMA_Channel1 - #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE) -#endif /*_DMA_Channel1 */ - -#ifdef _DMA_Channel2 - #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE) -#endif /*_DMA_Channel2 */ - -#ifdef _DMA_Channel3 - #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE) -#endif /*_DMA_Channel3 */ - -#ifdef _DMA_Channel4 - #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE) -#endif /*_DMA_Channel4 */ - -#ifdef _DMA_Channel5 - #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE) -#endif /*_DMA_Channel5 */ - -#ifdef _DMA_Channel6 - #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE) -#endif /*_DMA_Channel6 */ - -#ifdef _DMA_Channel7 - #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE) -#endif /*_DMA_Channel7 */ - -#ifdef _FLASH - #define FLASH ((FLASH_TypeDef *) FLASH_BASE) - #define OB ((OB_TypeDef *) OB_BASE) -#endif /*_FLASH */ - -#ifdef _RCC - #define RCC ((RCC_TypeDef *) RCC_BASE) -#endif /*_RCC */ - -#ifdef _SysTick - #define SysTick ((SysTick_TypeDef *) SysTick_BASE) -#endif /*_SysTick */ - -#ifdef _NVIC - #define NVIC ((NVIC_TypeDef *) NVIC_BASE) - #define SCB ((SCB_TypeDef *) SCB_BASE) -#endif /*_NVIC */ - -/*------------------------ Debug Mode ----------------------------------------*/ -#else /* DEBUG */ -#ifdef _TIM2 - EXT TIM_TypeDef *TIM2; -#endif /*_TIM2 */ - -#ifdef _TIM3 - EXT TIM_TypeDef *TIM3; -#endif /*_TIM3 */ - -#ifdef _TIM4 - EXT TIM_TypeDef *TIM4; -#endif /*_TIM4 */ - -#ifdef _RTC - EXT RTC_TypeDef *RTC; -#endif /*_RTC */ - -#ifdef _WWDG - EXT WWDG_TypeDef *WWDG; -#endif /*_WWDG */ - -#ifdef _IWDG - EXT IWDG_TypeDef *IWDG; -#endif /*_IWDG */ - -#ifdef _SPI2 - EXT SPI_TypeDef *SPI2; -#endif /*_SPI2 */ - -#ifdef _USART2 - EXT USART_TypeDef *USART2; -#endif /*_USART2 */ - -#ifdef _USART3 - EXT USART_TypeDef *USART3; -#endif /*_USART3 */ - -#ifdef _I2C1 - EXT I2C_TypeDef *I2C1; -#endif /*_I2C1 */ - -#ifdef _I2C2 - EXT I2C_TypeDef *I2C2; -#endif /*_I2C2 */ - -#ifdef _CAN - EXT CAN_TypeDef *CAN; -#endif /*_CAN */ - -#ifdef _BKP - EXT BKP_TypeDef *BKP; -#endif /*_BKP */ - -#ifdef _PWR - EXT PWR_TypeDef *PWR; -#endif /*_PWR */ - -#ifdef _AFIO - EXT AFIO_TypeDef *AFIO; -#endif /*_AFIO */ - -#ifdef _EXTI - EXT EXTI_TypeDef *EXTI; -#endif /*_EXTI */ - -#ifdef _GPIOA - EXT GPIO_TypeDef *GPIOA; -#endif /*_GPIOA */ - -#ifdef _GPIOB - EXT GPIO_TypeDef *GPIOB; -#endif /*_GPIOB */ - -#ifdef _GPIOC - EXT GPIO_TypeDef *GPIOC; -#endif /*_GPIOC */ - -#ifdef _GPIOD - EXT GPIO_TypeDef *GPIOD; -#endif /*_GPIOD */ - -#ifdef _GPIOE - EXT GPIO_TypeDef *GPIOE; -#endif /*_GPIOE */ - -#ifdef _ADC1 - EXT ADC_TypeDef *ADC1; -#endif /*_ADC1 */ - -#ifdef _ADC2 - EXT ADC_TypeDef *ADC2; -#endif /*_ADC2 */ - -#ifdef _TIM1 - EXT TIM1_TypeDef *TIM1; -#endif /*_TIM1 */ - -#ifdef _SPI1 - EXT SPI_TypeDef *SPI1; -#endif /*_SPI1 */ - -#ifdef _USART1 - EXT USART_TypeDef *USART1; -#endif /*_USART1 */ - -#ifdef _DMA - EXT DMA_TypeDef *DMA; -#endif /*_DMA */ - -#ifdef _DMA_Channel1 - EXT DMA_Channel_TypeDef *DMA_Channel1; -#endif /*_DMA_Channel1 */ - -#ifdef _DMA_Channel2 - EXT DMA_Channel_TypeDef *DMA_Channel2; -#endif /*_DMA_Channel2 */ - -#ifdef _DMA_Channel3 - EXT DMA_Channel_TypeDef *DMA_Channel3; -#endif /*_DMA_Channel3 */ - -#ifdef _DMA_Channel4 - EXT DMA_Channel_TypeDef *DMA_Channel4; -#endif /*_DMA_Channel4 */ - -#ifdef _DMA_Channel5 - EXT DMA_Channel_TypeDef *DMA_Channel5; -#endif /*_DMA_Channel5 */ - -#ifdef _DMA_Channel6 - EXT DMA_Channel_TypeDef *DMA_Channel6; -#endif /*_DMA_Channel6 */ - -#ifdef _DMA_Channel7 - EXT DMA_Channel_TypeDef *DMA_Channel7; -#endif /*_DMA_Channel7 */ - -#ifdef _FLASH - EXT FLASH_TypeDef *FLASH; - EXT OB_TypeDef *OB; -#endif /*_FLASH */ - -#ifdef _RCC - EXT RCC_TypeDef *RCC; -#endif /*_RCC */ - -#ifdef _SysTick - EXT SysTick_TypeDef *SysTick; -#endif /*_SysTick */ - -#ifdef _NVIC - EXT NVIC_TypeDef *NVIC; - EXT SCB_TypeDef *SCB; -#endif /*_NVIC */ - -#endif /* DEBUG */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __STM32F10x_MAP_H */ - -/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h deleted file mode 100644 index 4d14ef493..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_nvic.h +++ /dev/null @@ -1,251 +0,0 @@ -/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** -* File Name : stm32f10x_nvic.h -* Author : MCD Application Team -* Version : V1.0 -* Date : 10/08/2007 -* Description : This file contains all the functions prototypes for the -* NVIC firmware library. -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_NVIC_H -#define __STM32F10x_NVIC_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* NVIC Init Structure definition */ -typedef struct -{ - u8 NVIC_IRQChannel; - u8 NVIC_IRQChannelPreemptionPriority; - u8 NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* IRQ Channels --------------------------------------------------------------*/ -#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ -#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ -#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ -#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ -#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ -#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ -#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ -#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ -#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ -#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ -#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ -#define DMAChannel1_IRQChannel ((u8)0x0B) /* DMA Channel 1 global Interrupt */ -#define DMAChannel2_IRQChannel ((u8)0x0C) /* DMA Channel 2 global Interrupt */ -#define DMAChannel3_IRQChannel ((u8)0x0D) /* DMA Channel 3 global Interrupt */ -#define DMAChannel4_IRQChannel ((u8)0x0E) /* DMA Channel 4 global Interrupt */ -#define DMAChannel5_IRQChannel ((u8)0x0F) /* DMA Channel 5 global Interrupt */ -#define DMAChannel6_IRQChannel ((u8)0x10) /* DMA Channel 6 global Interrupt */ -#define DMAChannel7_IRQChannel ((u8)0x11) /* DMA Channel 7 global Interrupt */ -#define ADC_IRQChannel ((u8)0x12) /* ADC global Interrupt */ -#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ -#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ -#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ -#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ -#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ -#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ -#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ -#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ -#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ -#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ -#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ -#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ -#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ -#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ -#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ -#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ -#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ -#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ -#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ -#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ -#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ -#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ -#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ -#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ - -#define IS_NVIC_IRQ_CHANNEL(CHANNEL) ((CHANNEL == WWDG_IRQChannel) || \ - (CHANNEL == PVD_IRQChannel) || \ - (CHANNEL == TAMPER_IRQChannel) || \ - (CHANNEL == RTC_IRQChannel) || \ - (CHANNEL == FLASH_IRQChannel) || \ - (CHANNEL == RCC_IRQChannel) || \ - (CHANNEL == EXTI0_IRQChannel) || \ - (CHANNEL == EXTI1_IRQChannel) || \ - (CHANNEL == EXTI2_IRQChannel) || \ - (CHANNEL == EXTI3_IRQChannel) || \ - (CHANNEL == EXTI4_IRQChannel) || \ - (CHANNEL == DMAChannel1_IRQChannel) || \ - (CHANNEL == DMAChannel2_IRQChannel) || \ - (CHANNEL == DMAChannel3_IRQChannel) || \ - (CHANNEL == DMAChannel4_IRQChannel) || \ - (CHANNEL == DMAChannel5_IRQChannel) || \ - (CHANNEL == DMAChannel6_IRQChannel) || \ - (CHANNEL == DMAChannel7_IRQChannel) || \ - (CHANNEL == ADC_IRQChannel) || \ - (CHANNEL == USB_HP_CAN_TX_IRQChannel) || \ - (CHANNEL == USB_LP_CAN_RX0_IRQChannel) || \ - (CHANNEL == CAN_RX1_IRQChannel) || \ - (CHANNEL == CAN_SCE_IRQChannel) || \ - (CHANNEL == EXTI9_5_IRQChannel) || \ - (CHANNEL == TIM1_BRK_IRQChannel) || \ - (CHANNEL == TIM1_UP_IRQChannel) || \ - (CHANNEL == TIM1_TRG_COM_IRQChannel) || \ - (CHANNEL == TIM1_CC_IRQChannel) || \ - (CHANNEL == TIM2_IRQChannel) || \ - (CHANNEL == TIM3_IRQChannel) || \ - (CHANNEL == TIM4_IRQChannel) || \ - (CHANNEL == I2C1_EV_IRQChannel) || \ - (CHANNEL == I2C1_ER_IRQChannel) || \ - (CHANNEL == I2C2_EV_IRQChannel) || \ - (CHANNEL == I2C2_ER_IRQChannel) || \ - (CHANNEL == SPI1_IRQChannel) || \ - (CHANNEL == SPI2_IRQChannel) || \ - (CHANNEL == USART1_IRQChannel) || \ - (CHANNEL == USART2_IRQChannel) || \ - (CHANNEL == USART3_IRQChannel) || \ - (CHANNEL == EXTI15_10_IRQChannel) || \ - (CHANNEL == RTCAlarm_IRQChannel) || \ - (CHANNEL == USBWakeUp_IRQChannel)) - -/* System Handlers -----------------------------------------------------------*/ -#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ -#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ -#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ -#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ -#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ -#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ -#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ -#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ -#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ - -#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ - (HANDLER == SystemHandler_BusFault) || \ - (HANDLER == SystemHandler_UsageFault)) - -#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ - (HANDLER == SystemHandler_BusFault) || \ - (HANDLER == SystemHandler_UsageFault) || \ - (HANDLER == SystemHandler_SVCall) || \ - (HANDLER == SystemHandler_DebugMonitor) || \ - (HANDLER == SystemHandler_PSV) || \ - (HANDLER == SystemHandler_SysTick)) - -#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ - (HANDLER == SystemHandler_BusFault) || \ - (HANDLER == SystemHandler_SVCall)) - -#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_NMI) || \ - (HANDLER == SystemHandler_PSV) || \ - (HANDLER == SystemHandler_SysTick)) - -#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_PSV) || \ - (HANDLER == SystemHandler_SysTick)) - -#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ - (HANDLER == SystemHandler_BusFault) || \ - (HANDLER == SystemHandler_UsageFault) || \ - (HANDLER == SystemHandler_SVCall) || \ - (HANDLER == SystemHandler_DebugMonitor) || \ - (HANDLER == SystemHandler_PSV) || \ - (HANDLER == SystemHandler_SysTick)) - -#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_HardFault) || \ - (HANDLER == SystemHandler_MemoryManage) || \ - (HANDLER == SystemHandler_BusFault) || \ - (HANDLER == SystemHandler_UsageFault) || \ - (HANDLER == SystemHandler_DebugMonitor)) - -#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) ((HANDLER == SystemHandler_MemoryManage) || \ - (HANDLER == SystemHandler_BusFault)) - - -/* Vector Table Base ---------------------------------------------------------*/ -#define NVIC_VectTab_RAM ((u32)0x20000000) -#define NVIC_VectTab_FLASH ((u32)0x08000000) - -#define IS_NVIC_VECTTAB(VECTTAB) ((VECTTAB == NVIC_VectTab_RAM) || \ - (VECTTAB == NVIC_VectTab_FLASH)) - -/* System Low Power ----------------------------------------------------------*/ -#define NVIC_LP_SEVONPEND ((u8)0x10) -#define NVIC_LP_SLEEPDEEP ((u8)0x04) -#define NVIC_LP_SLEEPONEXIT ((u8)0x02) - -#define IS_NVIC_LP(LP) ((LP == NVIC_LP_SEVONPEND) || \ - (LP == NVIC_LP_SLEEPDEEP) || \ - (LP == NVIC_LP_SLEEPONEXIT)) - -/* Preemption Priority Group -------------------------------------------------*/ -#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) ((GROUP == NVIC_PriorityGroup_0) || \ - (GROUP == NVIC_PriorityGroup_1) || \ - (GROUP == NVIC_PriorityGroup_2) || \ - (GROUP == NVIC_PriorityGroup_3) || \ - (GROUP == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) (PRIORITY < 0x10) -#define IS_NVIC_SUB_PRIORITY(PRIORITY) (PRIORITY < 0x10) -#define IS_NVIC_OFFSET(OFFSET) (OFFSET < 0x0001FFFF) -#define IS_NVIC_BASE_PRI(PRI) ((PRI > 0x00) && (PRI < 0x10)) - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void NVIC_DeInit(void); -void NVIC_SCBDeInit(void); -void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SETPRIMASK(void); -void NVIC_RESETPRIMASK(void); -void NVIC_SETFAULTMASK(void); -void NVIC_RESETFAULTMASK(void); -void NVIC_BASEPRICONFIG(u32 NewPriority); -u32 NVIC_GetBASEPRI(void); -u16 NVIC_GetCurrentPendingIRQChannel(void); -ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); -void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); -void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); -u16 NVIC_GetCurrentActiveHandler(void); -ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); -u32 NVIC_GetCPUID(void); -void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); -void NVIC_GenerateSystemReset(void); -void NVIC_GenerateCoreReset(void); -void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); -void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); -void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, - u8 SystemHandlerSubPriority); -ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); -void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); -void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); -ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); -u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); -u32 NVIC_GetFaultAddress(u32 SystemHandler); - -#endif /* __STM32F10x_NVIC_H */ - -/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h deleted file mode 100644 index 92c8579e1..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32f10x_type.h +++ /dev/null @@ -1,80 +0,0 @@ -/******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** -* File Name : stm32f10x_type.h -* Author : MCD Application Team -* Version : V1.0 -* Date : 10/08/2007 -* Description : This file contains all the common data types used for the -* STM32F10x firmware library. -******************************************************************************** -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_TYPE_H -#define __STM32F10x_TYPE_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef signed long const sc32; /* Read Only */ -typedef signed short const sc16; /* Read Only */ -typedef signed char const sc8; /* Read Only */ - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -typedef volatile signed long const vsc32; /* Read Only */ -typedef volatile signed short const vsc16; /* Read Only */ -typedef volatile signed char const vsc8; /* Read Only */ - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef unsigned long const uc32; /* Read Only */ -typedef unsigned short const uc16; /* Read Only */ -typedef unsigned char const uc8; /* Read Only */ - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile unsigned long const vuc32; /* Read Only */ -typedef volatile unsigned short const vuc16; /* Read Only */ -typedef volatile unsigned char const vuc8; /* Read Only */ - -typedef enum {FALSE = 0, TRUE = !FALSE} bool; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) ((STATE == DISABLE) || (STATE == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -#define U8_MAX ((u8)255) -#define S8_MAX ((s8)127) -#define S8_MIN ((s8)-128) -#define U16_MAX ((u16)65535u) -#define S16_MAX ((s16)32767) -#define S16_MIN ((s16)-32768) -#define U32_MAX ((u32)4294967295uL) -#define S32_MAX ((s32)2147483647) -#define S32_MIN ((s32)2147483648uL) - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __STM32F10x_TYPE_H */ - -/******************* (C) COPYRIGHT 2007 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3 From a6c8e0930fd88d3834662e2bf7eb7c98a8c0bb9c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 8 Feb 2009 12:36:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@746 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 19 ++++++++++++ .../stm32lib/inc/stm32f10x_conf.h | 36 +++++++++++----------- demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk | 25 +++++++++++++++ 3 files changed, 62 insertions(+), 18 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index a669ad3d5..c476d8cda 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -31,6 +31,10 @@ MCU = cortex-m3 # Enable this if you want the linker to remove unused code and data LINK_GC = yes +# Enable this if you really want to use the STM FWLib. ChibiOS/RT does not +# require it and does not support the library except for this Makefile option. +USE_FWLIB = no + # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -69,6 +73,9 @@ UADEFS = # Imported source files include ../../src/kernel.mk include ../../test/test.mk +ifeq ($(USE_FWLIB),yes) +include ./stm32lib/stm32lib.mk +endif # List ARM-mode C source files here SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ @@ -78,6 +85,10 @@ SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ ../../src/lib/evtimer.c \ board.c main.c +ifeq ($(USE_FWLIB),yes) +SRC += ${STM32SRC} +endif + # List ASM source files here ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s @@ -97,10 +108,18 @@ ULIBS = # chconf.h. # NOTE: -falign-functions=16 may improve the performance, not always, but # increases the code size. +# NOTE: Add -fno-strict-aliasing if you are tired to see all the warnings +# generated by the STM FWLib, this option increases code size too. OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu #OPT += -ffixed-r7 OPT += -falign-functions=16 +ifeq ($(USE_FWLIB),yes) +# The thing generates a lot of aliasing warnings, this disables an optimization +# and the warning disappears, the code is a bit larger however. +OPT += -fno-strict-aliasing +endif + # Define warning options here WARN = -Wall -Wstrict-prototypes diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h index dcffed158..3bfc763f4 100644 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h @@ -29,28 +29,28 @@ /* Comment the line below to disable the specific peripheral inclusion */ /************************************* ADC ************************************/ -//#define _ADC -//#define _ADC1 +#define _ADC +#define _ADC1 //#define _ADC2 //#define _ADC3 /************************************* BKP ************************************/ -//#define _BKP +#define _BKP /************************************* CAN ************************************/ -//#define _CAN +#define _CAN /************************************* CRC ************************************/ -//#define _CRC +#define _CRC /************************************* DAC ************************************/ -//#define _DAC +#define _DAC /************************************* DBGMCU *********************************/ -//#define _DBGMCU +#define _DBGMCU /************************************* DMA ************************************/ -//#define _DMA +#define _DMA //#define _DMA1_Channel1 //#define _DMA1_Channel2 //#define _DMA1_Channel3 @@ -65,7 +65,7 @@ //#define _DMA2_Channel5 /************************************* EXTI ***********************************/ -//#define _EXTI +#define _EXTI /************************************* FLASH and Option Bytes *****************/ #define _FLASH @@ -75,7 +75,7 @@ /* #define _FLASH_PROG */ /************************************* FSMC ***********************************/ -//#define _FSMC +#define _FSMC /************************************* GPIO ***********************************/ #define _GPIO @@ -86,7 +86,7 @@ //#define _GPIOE //#define _GPIOF //#define _GPIOG -//#define _AFIO +#define _AFIO /************************************* I2C ************************************/ //#define _I2C @@ -94,22 +94,22 @@ //#define _I2C2 /************************************* IWDG ***********************************/ -//#define _IWDG +#define _IWDG /************************************* NVIC ***********************************/ -//#define _NVIC +#define _NVIC /************************************* PWR ************************************/ -//#define _PWR +#define _PWR /************************************* RCC ************************************/ #define _RCC /************************************* RTC ************************************/ -//#define _RTC +#define _RTC /************************************* SDIO ***********************************/ -//#define _SDIO +#define _SDIO /************************************* SPI ************************************/ //#define _SPI @@ -118,7 +118,7 @@ //#define _SPI3 /************************************* SysTick ********************************/ -//#define _SysTick +#define _SysTick /************************************* TIM ************************************/ //#define _TIM @@ -140,7 +140,7 @@ //#define _UART5 /************************************* WWDG ***********************************/ -//#define _WWDG +#define _WWDG /* In the following line adjust the value of External High Speed oscillator (HSE) used in your application */ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk new file mode 100644 index 000000000..ed7ec62fb --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk @@ -0,0 +1,25 @@ +# STM32 FWLib files. +STM32SRC = stm32lib/src/stm32f10x_adc.c \ + stm32lib/src/stm32f10x_bkp.c \ + stm32lib/src/stm32f10x_can.c \ + stm32lib/src/stm32f10x_crc.c \ + stm32lib/src/stm32f10x_dac.c \ + stm32lib/src/stm32f10x_dbgmcu.c \ + stm32lib/src/stm32f10x_dma.c \ + stm32lib/src/stm32f10x_exti.c \ + stm32lib/src/stm32f10x_flash.c \ + stm32lib/src/stm32f10x_fsmc.c \ + stm32lib/src/stm32f10x_gpio.c \ + stm32lib/src/stm32f10x_i2c.c \ + stm32lib/src/stm32f10x_iwdg.c \ + stm32lib/src/stm32f10x_lib.c \ + stm32lib/src/stm32f10x_nvic.c \ + stm32lib/src/stm32f10x_pwr.c \ + stm32lib/src/stm32f10x_rcc.c \ + stm32lib/src/stm32f10x_rtc.c \ + stm32lib/src/stm32f10x_sdio.c \ + stm32lib/src/stm32f10x_spi.c \ + stm32lib/src/stm32f10x_systick.c \ + stm32lib/src/stm32f10x_tim.c \ + stm32lib/src/stm32f10x_usart.c \ + stm32lib/src/stm32f10x_wwdg.c -- cgit v1.2.3 From c4c192b0273454e81cd9cb91441c747abaabf6ec Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 9 Feb 2009 22:01:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@750 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 7 ++++++- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index ba64e335e..21e9665f2 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -24,7 +24,12 @@ #include -extern void FiqHandler(void); +/* + * FIQ Handler, unused in this demo. + */ +__attribute__((interrupt("FIQ"))) +static void FiqHandler(void) { +} static CH_IRQ_HANDLER(SpuriousHandler) { diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 5f49016e0..8f9a45af4 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -25,7 +25,12 @@ #include #include -extern void FiqHandler(void); +/* + * FIQ Handler, unused in this demo. + */ +__attribute__((interrupt("FIQ"))) +static void FiqHandler(void) { +} static CH_IRQ_HANDLER(SpuriousHandler) { -- cgit v1.2.3 From d70f848b0867fa5f7748a242d06e95d140fd7736 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Feb 2009 06:54:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@759 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 57 +++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 24 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index c476d8cda..12a819086 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -12,6 +12,29 @@ # To rebuild project do "make clean" and "make all". # +############################################################################################## +# OS, compiler and demo options + +# Compiler options here +OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 + +# Enable this if you want the linker to remove unused code and data +LINK_GC = yes + +# Enable this if you really want to use the STM FWLib. ChibiOS/RT does not +# require it and does not support the library except for this Makefile option. +USE_FWLIB = no + +# Enable register caching optimization. This option greatly improves both +# code size and execution speed but is incompatible with libraries compiled +# without the very same options. The register R7 becomes a global variable +# and MUST NOT be used anywhere in the code. +USE_CURRP_CACHING = no + +# +# End of OS and demo options +############################################################################################## + ############################################################################################## # Start of default section # @@ -28,13 +51,6 @@ BIN = $(CP) -O binary MCU = cortex-m3 -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes - -# Enable this if you really want to use the STM FWLib. ChibiOS/RT does not -# require it and does not support the library except for this Makefile option. -USE_FWLIB = no - # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -103,23 +119,6 @@ ULIBDIR = # List all user libraries here ULIBS = -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -# NOTE: Add -fno-strict-aliasing if you are tired to see all the warnings -# generated by the STM FWLib, this option increases code size too. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -OPT += -falign-functions=16 - -ifeq ($(USE_FWLIB),yes) -# The thing generates a lot of aliasing warnings, this disables an optimization -# and the warning disappears, the code is a bit larger however. -OPT += -fno-strict-aliasing -endif - # Define warning options here WARN = -Wall -Wstrict-prototypes @@ -127,6 +126,16 @@ WARN = -Wall -Wstrict-prototypes # End of user defines ############################################################################################## +ifeq ($(USE_CURRP_CACHING),yes) +OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' +endif + +ifeq ($(USE_FWLIB),yes) +# The thing generates a lot of aliasing warnings, this disables an optimization +# and the warning disappears, the code is a bit larger however. +OPT += -fno-strict-aliasing +endif + ifeq ($(LINK_GC),yes) OPT += -ffunction-sections -fdata-sections endif -- cgit v1.2.3 From fa9b36aff3676a897503a359314d08db8fc5a09d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Feb 2009 18:20:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@766 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 25 +++++++++++++++++-------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 25 +++++++++++++++++-------- demos/ARM7-LPC214x-G++/chconf.h | 25 +++++++++++++++++-------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 25 +++++++++++++++++-------- demos/ARM7-LPC214x-GCC/chconf.h | 25 +++++++++++++++++-------- demos/ARMCM3-STM32F103-GCC/chconf.h | 25 +++++++++++++++++-------- demos/AVR-AT90CANx-GCC/chconf.h | 25 +++++++++++++++++-------- demos/AVR-ATmega128-GCC/chconf.h | 25 +++++++++++++++++-------- demos/MSP430-MSP430x1611-GCC/chconf.h | 25 +++++++++++++++++-------- demos/Win32-MinGW/chconf.h | 25 +++++++++++++++++-------- 10 files changed, 170 insertions(+), 80 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index f05f8b0b5..588445ee0 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index f05f8b0b5..588445ee0 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index f05f8b0b5..588445ee0 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 03352998a..bebe419b2 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index f05f8b0b5..588445ee0 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index f05f8b0b5..588445ee0 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 5e787d675..da4744a16 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 5e787d675..da4744a16 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index f24019fcd..e270a6ccf 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index ac7131871..396f8d9a1 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -310,21 +310,30 @@ #endif /** - * Debug option, if enableed includes basic debug support to the kernel. - * @note The debug support is port-dependent, it may be not present on some - * targets. In that case stub functions will be included. + * Debug option, if enabled all the assertions in the kernel code are + * activated. This includes function parameters checks and consistency + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_USE_DEBUG -#define CH_USE_DEBUG FALSE +#ifndef CH_DBG_ENABLE_ASSERTS +#define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * Debug option, includes the threads context switch tracing feature. + * Debug option, if enabled the context switch circular trace buffer is + * activated. * @note The default is @p FALSE. */ -#ifndef CH_USE_TRACE -#define CH_USE_TRACE FALSE +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#ifndef CH_DBG_FILL_THREADS +#define CH_DBG_FILL_THREADS FALSE #endif /** -- cgit v1.2.3 From 8a865a9a0a0c34f52e3555e98fd42c9235472e8d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 17 Feb 2009 18:25:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@775 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/board.c | 18 +++++++++--------- demos/ARM7-LPC214x-GCC-minimal/board.c | 18 +++++++++--------- demos/ARM7-LPC214x-GCC/board.c | 18 +++++++++--------- 3 files changed, 27 insertions(+), 27 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index 0e54eeb71..dc0cfb4f9 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -79,17 +79,17 @@ void hwinit0(void) { * PLL setup for Fosc=12MHz and CCLK=48MHz. * P=2 M=3. */ - PLL *pll = PLLBase; - pll->PLL0_CFG = 0x23; /* P and M values. */ - pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - while (!(pll->PLL0_STAT & 0x400)) + PLL *pll = PLL0Base; + pll->PLL_CFG = 0x23; /* P and M values. */ + pll->PLL_CON = 0x1; /* Enables the PLL 0. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; + while (!(pll->PLL_STAT & 0x400)) ; /* Wait for PLL lock. */ - pll->PLL0_CON = 0x3; /* Connects the PLL. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; + pll->PLL_CON = 0x3; /* Connects the PLL. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; /* * VPB setup. diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index e34bb3c55..50f553fa3 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -79,17 +79,17 @@ void hwinit0(void) { * PLL setup for Fosc=12MHz and CCLK=48MHz. * P=2 M=3. */ - PLL *pll = PLLBase; - pll->PLL0_CFG = 0x23; /* P and M values. */ - pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - while (!(pll->PLL0_STAT & 0x400)) + PLL *pll = PLL0Base; + pll->PLL_CFG = 0x23; /* P and M values. */ + pll->PLL_CON = 0x1; /* Enables the PLL 0. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; + while (!(pll->PLL_STAT & 0x400)) ; /* Wait for PLL lock. */ - pll->PLL0_CON = 0x3; /* Connects the PLL. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; + pll->PLL_CON = 0x3; /* Connects the PLL. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; /* * VPB setup. diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 69aed08f3..0db657b29 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -79,17 +79,17 @@ void hwinit0(void) { * PLL setup for Fosc=12MHz and CCLK=48MHz. * P=2 M=3. */ - PLL *pll = PLLBase; - pll->PLL0_CFG = 0x23; /* P and M values. */ - pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; - while (!(pll->PLL0_STAT & 0x400)) + PLL *pll = PLL0Base; + pll->PLL_CFG = 0x23; /* P and M values. */ + pll->PLL_CON = 0x1; /* Enables the PLL 0. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; + while (!(pll->PLL_STAT & 0x400)) ; /* Wait for PLL lock. */ - pll->PLL0_CON = 0x3; /* Connects the PLL. */ - pll->PLL0_FEED = 0xAA; - pll->PLL0_FEED = 0x55; + pll->PLL_CON = 0x3; /* Connects the PLL. */ + pll->PLL_FEED = 0xAA; + pll->PLL_FEED = 0x55; /* * VPB setup. -- cgit v1.2.3 From 7fe2bf4789935d592c24dbbe2aaba18c34c021cf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 17 Feb 2009 19:43:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@777 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 216 ++++++++++++++++----------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 216 ++++++++++++++++----------- demos/ARM7-LPC214x-G++/chconf.h | 216 ++++++++++++++++----------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 256 +++++++++++++++++++------------- demos/ARM7-LPC214x-GCC/chconf.h | 216 ++++++++++++++++----------- demos/ARMCM3-STM32F103-GCC/chconf.h | 216 ++++++++++++++++----------- demos/Win32-MinGW/chconf.h | 216 ++++++++++++++++----------- 7 files changed, 937 insertions(+), 615 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 588445ee0..7c3520830 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXESS TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 0 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 588445ee0..7c3520830 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXESS TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 0 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 588445ee0..7c3520830 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXESS TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 0 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index bebe419b2..7c3520830 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED FALSE +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,24 +66,71 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN -#define CH_USE_ROUNDROBIN FALSE +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" #endif +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT -#define CH_USE_WAITEXIT FALSE +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE #endif /** * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES -#define CH_USE_SEMAPHORES FALSE +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE #endif /** @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,8 +149,8 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW -#define CH_USE_SEMSW FALSE +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE #endif /** @@ -101,16 +159,16 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT -#define CH_USE_SEMAPHORES_TIMEOUT FALSE +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES -#define CH_USE_MUTEXES FALSE +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE #endif /** @@ -118,8 +176,8 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS -#define CH_USE_CONDVARS FALSE +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE #endif /** @@ -127,16 +185,16 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT -#define CH_USE_CONDVARS_TIMEOUT FALSE +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS -#define CH_USE_EVENTS FALSE +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE #endif /** @@ -145,16 +203,16 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT -#define CH_USE_EVENTS_TIMEOUT FALSE +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE #endif /** * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES -#define CH_USE_MESSAGES FALSE +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE #endif /** @@ -163,8 +221,8 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT -#define CH_USE_MESSAGES_EVENT FALSE +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_EVENT TRUE #endif /** @@ -172,17 +230,26 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXESS TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES -#define CH_USE_QUEUES FALSE +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE #endif /** @@ -190,8 +257,8 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX -#define CH_USE_QUEUES_HALFDUPLEX FALSE +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) +#define CH_USE_QUEUES_HALFDUPLEX TRUE #endif /** @@ -200,8 +267,8 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT -#define CH_USE_QUEUES_TIMEOUT FALSE +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_QUEUES_TIMEOUT TRUE #endif /** @@ -210,8 +277,8 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX -#define CH_USE_SERIAL_FULLDUPLEX FALSE +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) +#define CH_USE_SERIAL_FULLDUPLEX TRUE #endif /** @@ -220,8 +287,8 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX -#define CH_USE_SERIAL_HALFDUPLEX FALSE +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) +#define CH_USE_SERIAL_HALFDUPLEX TRUE #endif /** @@ -230,19 +297,8 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP -#define CH_USE_HEAP FALSE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 0 +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE #endif /** @@ -251,7 +307,7 @@ * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,8 +316,8 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS -#define CH_USE_MEMPOOLS FALSE +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE #endif /** @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC -#define CH_USE_DYNAMIC FALSE +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 588445ee0..7c3520830 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXESS TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 0 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 588445ee0..7c3520830 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXESS TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 0 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 396f8d9a1..e41f4410e 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0x20000 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXESS TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 0x20000 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -352,7 +398,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ chEvtInit(&tp->p_exitesource); \ @@ -363,7 +409,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ chEvtBroadcastI(&currp->p_exitesource); \ @@ -374,7 +420,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } -- cgit v1.2.3 From 3d2f2081cebee2936d8073ab6a55177b6549013e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 17 Feb 2009 19:58:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@778 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 4 +- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 4 +- demos/ARM7-LPC214x-G++/chconf.h | 4 +- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 4 +- demos/ARM7-LPC214x-GCC/chconf.h | 4 +- demos/ARMCM3-STM32F103-GCC/chconf.h | 4 +- demos/AVR-AT90CANx-GCC/chconf.h | 216 +++++++++++++++++++------------- demos/AVR-ATmega128-GCC/chconf.h | 216 +++++++++++++++++++------------- demos/MSP430-MSP430x1611-GCC/chconf.h | 216 +++++++++++++++++++------------- demos/Win32-MinGW/chconf.h | 4 +- 10 files changed, 407 insertions(+), 269 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 7c3520830..e8cc24807 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -239,8 +239,8 @@ * in the kernel. * @note The default is @p TRUE. */ -#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXESS TRUE +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE #endif /** diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 7c3520830..d91a2f743 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -239,8 +239,8 @@ * in the kernel. * @note The default is @p TRUE. */ -#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXESS TRUE +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE #endif /** diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 7c3520830..d91a2f743 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -239,8 +239,8 @@ * in the kernel. * @note The default is @p TRUE. */ -#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXESS TRUE +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE #endif /** diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 7c3520830..d91a2f743 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -239,8 +239,8 @@ * in the kernel. * @note The default is @p TRUE. */ -#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXESS TRUE +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE #endif /** diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 7c3520830..d91a2f743 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -239,8 +239,8 @@ * in the kernel. * @note The default is @p TRUE. */ -#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXESS TRUE +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE #endif /** diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 7c3520830..d91a2f743 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -239,8 +239,8 @@ * in the kernel. * @note The default is @p TRUE. */ -#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXESS TRUE +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE #endif /** diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index da4744a16..15ce1a80d 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 512 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 512 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index da4744a16..15ce1a80d 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 512 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 512 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index e270a6ccf..109135795 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -27,14 +27,25 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. */ -#ifndef CH_OPTIMIZE_SPEED -#define CH_OPTIMIZE_SPEED TRUE +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 #endif /** @@ -43,10 +54,10 @@ * For performance and code size reasons the recommended setting is to leave * this option disabled.
* You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * libraries that require nested lock/unlock operations. * @note The default is @p FALSE. */ -#ifndef CH_USE_NESTED_LOCKS +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif @@ -55,15 +66,62 @@ * on threads of equal priority. * @note The default is @p TRUE. */ -#ifndef CH_USE_ROUNDROBIN +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) #define CH_USE_ROUNDROBIN TRUE #endif +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 512 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + /** * If specified then the @p chThdWait() function is included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_WAITEXIT +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif @@ -71,7 +129,7 @@ * If specified then the Semaphores APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_SEMAPHORES +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif @@ -81,7 +139,7 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_PRIORITY +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif @@ -91,7 +149,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMSW +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif @@ -101,7 +159,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_SEMAPHORES_TIMEOUT +#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_TIMEOUT TRUE #endif @@ -109,7 +167,7 @@ * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MUTEXES +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif @@ -118,7 +176,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ -#ifndef CH_USE_CONDVARS +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif @@ -127,7 +185,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ -#ifndef CH_USE_CONDVARS_TIMEOUT +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif @@ -135,7 +193,7 @@ * If specified then the Event flags APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_EVENTS +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif @@ -145,7 +203,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ -#ifndef CH_USE_EVENTS_TIMEOUT +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif @@ -153,7 +211,7 @@ * If specified then the Synchronous Messages APIs are included in the kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MESSAGES +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif @@ -163,7 +221,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ -#ifndef CH_USE_MESSAGES_EVENT +#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_EVENT TRUE #endif @@ -172,16 +230,25 @@ * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ -#ifndef CH_USE_MESSAGES_PRIORITY +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + /** * If specified then the I/O queues APIs are included in the kernel. * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif @@ -190,7 +257,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ -#ifndef CH_USE_QUEUES_HALFDUPLEX +#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_QUEUES_HALFDUPLEX TRUE #endif @@ -200,7 +267,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ -#ifndef CH_USE_QUEUES_TIMEOUT +#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_QUEUES_TIMEOUT TRUE #endif @@ -210,7 +277,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES. */ -#ifndef CH_USE_SERIAL_FULLDUPLEX +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif @@ -220,7 +287,7 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ -#ifndef CH_USE_SERIAL_HALFDUPLEX +#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) #define CH_USE_SERIAL_HALFDUPLEX TRUE #endif @@ -230,28 +297,17 @@ * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#ifndef CH_USE_HEAP +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#ifndef CH_HEAP_SIZE -#define CH_HEAP_SIZE 512 -#endif - /** * If enabled enforces the use of the C-runtime @p malloc() and @p free() * functions as backend for the system heap allocator. * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. */ -#ifndef CH_USE_MALLOC_HEAP +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif @@ -260,7 +316,7 @@ * kernel. * @note The default is @p TRUE. */ -#ifndef CH_USE_MEMPOOLS +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif @@ -270,52 +326,21 @@ * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ -#ifndef CH_USE_DYNAMIC +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE #endif -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#ifndef CH_FREQUENCY -#define CH_FREQUENCY 100 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#ifndef CH_TIME_QUANTUM -#define CH_TIME_QUANTUM 10 -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ /** * Debug option, if enabled all the assertions in the kernel code are * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * checks inside the kernel. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_ASSERTS +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif @@ -324,22 +349,43 @@ * activated. * @note The default is @p FALSE. */ -#ifndef CH_DBG_ENABLE_TRACE +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + /** * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * pattern when a thread is created. */ -#ifndef CH_DBG_FILL_THREADS +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + /** * User fields added to the end of the @p Thread structure. */ -#ifndef THREAD_EXT_FIELDS +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ @@ -350,7 +396,7 @@ struct { \ * User initialization code added to the @p chThdInit() API. * @note It is invoked from within @p chThdInit(). */ -#ifndef THREAD_EXT_INIT +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ } @@ -360,7 +406,7 @@ struct { \ * User finalization code added to the @p chThdExit() API. * @note It is inserted into lock zone. */ -#ifndef THREAD_EXT_EXIT +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add thread finalization code here.*/ \ } @@ -370,7 +416,7 @@ struct { \ * Code inserted inside the idle thread loop immediately after an interrupt * resumed execution. */ -#ifndef IDLE_LOOP_HOOK +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index e41f4410e..761819bba 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -239,8 +239,8 @@ * in the kernel. * @note The default is @p TRUE. */ -#if !defined(CH_USE_MAILBOXESS) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXESS TRUE +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE #endif /** -- cgit v1.2.3 From ae93d8d3d76bd2ab220b126f761cb1a630e9fc5b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 17 Feb 2009 20:05:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@779 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 44 ++++++++++++++++----------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index d91a2f743..487710674 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -67,7 +67,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE +#define CH_USE_ROUNDROBIN FALSE #endif /** @@ -92,7 +92,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE +#define CH_OPTIMIZE_SPEED FALSE #endif /** @@ -122,7 +122,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE +#define CH_USE_WAITEXIT FALSE #endif /** @@ -130,7 +130,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE +#define CH_USE_SEMAPHORES FALSE #endif /** @@ -150,7 +150,7 @@ * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE +#define CH_USE_SEMSW FALSE #endif /** @@ -160,7 +160,7 @@ * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE +#define CH_USE_SEMAPHORES_TIMEOUT FALSE #endif /** @@ -168,7 +168,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE +#define CH_USE_MUTEXES FALSE #endif /** @@ -177,7 +177,7 @@ * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE +#define CH_USE_CONDVARS FALSE #endif /** @@ -186,7 +186,7 @@ * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE +#define CH_USE_CONDVARS_TIMEOUT FALSE #endif /** @@ -194,7 +194,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE +#define CH_USE_EVENTS FALSE #endif /** @@ -204,7 +204,7 @@ * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE +#define CH_USE_EVENTS_TIMEOUT FALSE #endif /** @@ -212,7 +212,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE +#define CH_USE_MESSAGES FALSE #endif /** @@ -222,7 +222,7 @@ * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. */ #if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE +#define CH_USE_MESSAGES_EVENT FALSE #endif /** @@ -240,7 +240,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE +#define CH_USE_MAILBOXES FALSE #endif /** @@ -249,7 +249,7 @@ * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE +#define CH_USE_QUEUES FALSE #endif /** @@ -258,7 +258,7 @@ * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE +#define CH_USE_QUEUES_HALFDUPLEX FALSE #endif /** @@ -268,7 +268,7 @@ * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. */ #if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE +#define CH_USE_QUEUES_TIMEOUT FALSE #endif /** @@ -278,7 +278,7 @@ * @note Requires @p CH_USE_QUEUES. */ #if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE +#define CH_USE_SERIAL_FULLDUPLEX FALSE #endif /** @@ -288,7 +288,7 @@ * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. */ #if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE +#define CH_USE_SERIAL_HALFDUPLEX FALSE #endif /** @@ -298,7 +298,7 @@ * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE +#define CH_USE_HEAP FALSE #endif /** @@ -317,7 +317,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE +#define CH_USE_MEMPOOLS FALSE #endif /** @@ -327,7 +327,7 @@ * @note Requires @p CH_USE_WAITEXIT. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE +#define CH_USE_DYNAMIC FALSE #endif /*===========================================================================*/ -- cgit v1.2.3 From b8089f6eca64267329a3930da32e6447e616ee56 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 18 Feb 2009 19:18:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@784 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 260 +++++++++--------------- demos/ARM7-AT91SAM7X-GCC/Makefile.thumb | 218 -------------------- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 273 ++++++++++---------------- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb | 233 ---------------------- demos/ARM7-LPC214x-GCC-minimal/Makefile | 253 +++++++++--------------- demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb | 215 -------------------- demos/ARM7-LPC214x-GCC/Makefile | 261 +++++++++--------------- demos/ARM7-LPC214x-GCC/Makefile.thumb | 219 --------------------- demos/ARMCM3-STM32F103-GCC/Makefile | 215 +++++++------------- 9 files changed, 464 insertions(+), 1683 deletions(-) delete mode 100644 demos/ARM7-AT91SAM7X-GCC/Makefile.thumb delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb delete mode 100644 demos/ARM7-LPC214x-GCC/Makefile.thumb (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 65219c2da..d7e30724a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -1,21 +1,87 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. # -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + # -# make clean = Clean project files. +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths # -# To rebuild project do "make clean" and "make all". + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + +# Sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +SRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ + at91lib/aic.c \ + board.c main.c + +# Sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ASRC = + +# Sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TSRC = + +# List ASM source files here +ASMSRC = ../../ports/ARM7/crt0.s \ + ../../ports/ARM7-AT91SAM7X/vectors.s \ + ../../ports/ARM7/chcoreasm.s + +INCDIR = $(KERNINC) $(TESTINC) \ + ../../src/lib \ + ../../ports/ARM7 \ + ../../ports/ARM7-AT91SAM7X + # +# Project, sources and paths +############################################################################## -############################################################################################## -# Start of default section +############################################################################## +# Compiler settings # +MCU = arm7tdmi + TRGT = arm-elf- CC = $(TRGT)gcc CP = $(TRGT)objcopy @@ -24,10 +90,22 @@ OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -MCU = arm7tdmi +# ARM-specific options here +AOPT = -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -46,49 +124,20 @@ DLIBS = # # End of default section -############################################################################################## +############################################################################## -############################################################################################## +############################################################################## # Start of user section # -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - # List all user C define here, like -D_DEBUG=1 UDEFS = # Define ASM defines here UADEFS = -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ASRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - at91lib/aic.c \ - board.c main.c - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-AT91SAM7X/vectors.s - # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X +UINCDIR = # List the user directory to look for the libraries here ULIBDIR = @@ -96,123 +145,8 @@ ULIBDIR = # List all user libraries here ULIBS = -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -#OPT += -falign-functions=16 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - # # End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +############################################################################## -# *** EOF *** +include ../../ports/ARM7/rules.mk diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb deleted file mode 100644 index 6d06e82a7..000000000 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile.thumb +++ /dev/null @@ -1,218 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ASRC = - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - at91lib/aic.c \ - board.c main.c - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-AT91SAM7X/vectors.s - -# List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -#OPT += -falign-functions=16 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - -# -# End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 74146d985..20d44a9d5 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -1,55 +1,34 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. # -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary -MCU = arm7tdmi +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif # Enable this if you want the linker to remove unused code and data -LINK_GC = yes - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif -# List the default directory to look for the libraries here -DLIBDIR = +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif -# List all default libraries here -DLIBS = +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif # -# End of default section -############################################################################################## +# Build global options +############################################################################## -############################################################################################## -# Start of user section +############################################################################## +# Project, sources and paths # # Define project name here @@ -58,12 +37,6 @@ PROJECT = ch # Define linker script file here LDSCRIPT= ch.ld -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - # Imported source files include ../../src/kernel.mk include ../../test/test.mk @@ -77,156 +50,116 @@ USRC = ../../ext/uip-1.0/uip/uip_arp.c \ ../../ext/uip-1.0/apps/webserver/httpd-fs.c \ ../../ext/uip-1.0/apps/webserver/httpd-cgi.c -# List ARM-mode C source files here -ASRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ${USRC} \ - ../../src/lib/evtimer.c \ - at91lib/aic.c \ - web/webthread.c \ - board.c main.c - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. +# Sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +SRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ${USRC} \ + ../../src/lib/evtimer.c \ + at91lib/aic.c \ + web/webthread.c \ + board.c main.c + +# Sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ASRC = + +# Sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. TSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-AT91SAM7X/vectors.s +ASMSRC = ../../ports/ARM7/crt0.s \ + ../../ports/ARM7-AT91SAM7X/vectors.s \ + ../../ports/ARM7/chcoreasm.s -# List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X \ - ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver +INCDIR = $(KERNINC) $(TESTINC) \ + ../../src/lib \ + ../../ports/ARM7 \ + ../../ports/ARM7-AT91SAM7X \ + ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver -# List the user directory to look for the libraries here -ULIBDIR = +# +# Project, sources and paths +############################################################################## -# List all user libraries here -ULIBS = +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +TRGT = arm-elf- +CC = $(TRGT)gcc +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary # ARM-specific options here AOPT = # THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -#OPT += -falign-functions=16 +TOPT = -mthumb -DTHUMB # Define warning options here WARN = -Wall -Wstrict-prototypes # -# End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif +# Compiler settings +############################################################################## -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif +############################################################################## +# Start of default section +# -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = -# -# Makefile rules -# +# List all default directories to look for include files here +DINCDIR = -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp +# List the default directory to look for the libraries here +DLIBDIR = -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ +# List all default libraries here +DLIBS = -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ +# +# End of default section +############################################################################## -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ +############################################################################## +# Start of user section +# -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ +# List all user C define here, like -D_DEBUG=1 +UDEFS = -%hex: %elf - $(HEX) $< $@ +# Define ASM defines here +UADEFS = -%bin: %elf - $(BIN) $< $@ +# List all user directories here +UINCDIR = -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ +# List the user directory to look for the libraries here +ULIBDIR = -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep +# List all user libraries here +ULIBS = # -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +# End of user defines +############################################################################## -# *** EOF *** +include ../../ports/ARM7/rules.mk diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb deleted file mode 100644 index e476abc6b..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile.thumb +++ /dev/null @@ -1,233 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List of the required uIP source files. -USRC = ../../ext/uip-1.0/uip/uip_arp.c \ - ../../ext/uip-1.0/uip/psock.c \ - ../../ext/uip-1.0/uip/timer.c \ - ../../ext/uip-1.0/uip/uip.c \ - ../../ext/uip-1.0/apps/webserver/httpd.c \ - ../../ext/uip-1.0/apps/webserver/http-strings.c \ - ../../ext/uip-1.0/apps/webserver/httpd-fs.c \ - ../../ext/uip-1.0/apps/webserver/httpd-cgi.c - -# List ARM-mode C source files here -ASRC = - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ${USRC} \ - ../../src/lib/evtimer.c \ - at91lib/aic.c \ - web/webthread.c \ - board.c main.c - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-AT91SAM7X/vectors.s - -# List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-AT91SAM7X \ - ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -#OPT += -falign-functions=16 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - -# -# End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index c584b1d69..67e41a385 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -1,21 +1,83 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. # -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + # -# make clean = Clean project files. +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths # -# To rebuild project do "make clean" and "make all". + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +include ../../src/kernel.mk +#include ../../test/test.mk + +# Sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +SRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ${KERNSRC} \ + board.c main.c + +# Sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ASRC = + +# Sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TSRC = + +# List ASM source files here +ASMSRC = ../../ports/ARM7/crt0.s \ + ../../ports/ARM7-LPC214x/vectors.s \ + ../../ports/ARM7/chcoreasm.s + +INCDIR = $(KERNINC) $(TESTINC) \ + ../../src/lib \ + ../../ports/ARM7 \ + ../../ports/ARM7-LPC214x + # +# Project, sources and paths +############################################################################## -############################################################################################## -# Start of default section +############################################################################## +# Compiler settings # +MCU = arm7tdmi + TRGT = arm-elf- CC = $(TRGT)gcc CP = $(TRGT)objcopy @@ -24,10 +86,22 @@ OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -MCU = arm7tdmi +# ARM-specific options here +AOPT = -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -46,46 +120,20 @@ DLIBS = # # End of default section -############################################################################################## +############################################################################## -############################################################################################## +############################################################################## # Start of user section # -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - # List all user C define here, like -D_DEBUG=1 UDEFS = # Define ASM defines here UADEFS = -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ASRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ${KERNSRC} \ - board.c main.c - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-LPC214x/vectors.s - # List all user directories here -UINCDIR = ../../src/include ../../src/lib \ - ../../ports/ARM7 ../../ports/ARM7-LPC214x +UINCDIR = # List the user directory to look for the libraries here ULIBDIR = @@ -93,123 +141,8 @@ ULIBDIR = # List all user libraries here ULIBS = -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -OPT += -falign-functions=16 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - # # End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +############################################################################## -# *** EOF *** +include ../../ports/ARM7/rules.mk diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb b/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb deleted file mode 100644 index 876298a3d..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile.thumb +++ /dev/null @@ -1,215 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ASRC = - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ${KERNSRC} \ - board.c main.c - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-LPC214x/vectors.s - -# List all user directories here -UINCDIR = ../../src/include ../../src/lib \ - ../../ports/ARM7 ../../ports/ARM7-LPC214x - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -OPT += -falign-functions=16 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - -# -# End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 478e9a287..ff75442f2 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -1,21 +1,87 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. # -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + # -# make clean = Clean project files. +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths # -# To rebuild project do "make clean" and "make all". + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + +# Sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +SRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ + board.c buzzer.c mmcsd.c main.c + +# Sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ASRC = + +# Sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TSRC = + +# List ASM source files here +ASMSRC = ../../ports/ARM7/crt0.s \ + ../../ports/ARM7-LPC214x/vectors.s \ + ../../ports/ARM7/chcoreasm.s + +INCDIR = $(KERNINC) $(TESTINC) \ + ../../src/lib \ + ../../ports/ARM7 \ + ../../ports/ARM7-LPC214x + # +# Project, sources and paths +############################################################################## -############################################################################################## -# Start of default section +############################################################################## +# Compiler settings # +MCU = arm7tdmi + TRGT = arm-elf- CC = $(TRGT)gcc CP = $(TRGT)objcopy @@ -24,10 +90,22 @@ OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -MCU = arm7tdmi +# ARM-specific options here +AOPT = -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -46,50 +124,20 @@ DLIBS = # # End of default section -############################################################################################## +############################################################################## -############################################################################################## +############################################################################## # Start of user section # -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - # List all user C define here, like -D_DEBUG=1 UDEFS = # Define ASM defines here UADEFS = -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ASRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c buzzer.c mmcsd.c main.c - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-LPC214x/vectors.s - # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-LPC214x +UINCDIR = # List the user directory to look for the libraries here ULIBDIR = @@ -97,123 +145,8 @@ ULIBDIR = # List all user libraries here ULIBS = -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -OPT += -falign-functions=16 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - # # End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +############################################################################## -# *** EOF *** +include ../../ports/ARM7/rules.mk diff --git a/demos/ARM7-LPC214x-GCC/Makefile.thumb b/demos/ARM7-LPC214x-GCC/Makefile.thumb deleted file mode 100644 index aa3046c20..000000000 --- a/demos/ARM7-LPC214x-GCC/Makefile.thumb +++ /dev/null @@ -1,219 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ASRC = - -# List THUMB-mode C sources here -# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is -# enabled for all modules and that lowers performance. -TSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c buzzer.c mmcsd.c main.c - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-LPC214x/vectors.s - -# List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-LPC214x - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -Os -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -OPT += -falign-functions=16 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - -# -# End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -AOBJS = $(ASRC:.c=.o) -TOBJS = $(TSRC:.c=.o) -OBJS = $(ASMOBJS) $(AOBJS) $(TOBJS) -ASMOBJS = $(ASMSRC:.s=.o) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(AOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TOBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(AOBJS) $(TOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ASRC:.c=.c.bak) - -rm -f $(ASRC:.c=.lst) - -rm -f $(TSRC:.c=.c.bak) - -rm -f $(TSRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 12a819086..2fd02d7f5 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -1,44 +1,75 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. # -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(LINK_GC),) + USE_LINK_GC = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + # -# To rebuild project do "make clean" and "make all". +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths # -############################################################################################## -# OS, compiler and demo options +# Define project name here +PROJECT = ch -# Compiler options here -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +# Define linker script file here +LDSCRIPT= ch.ld -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk -# Enable this if you really want to use the STM FWLib. ChibiOS/RT does not -# require it and does not support the library except for this Makefile option. -USE_FWLIB = no +# Sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +SRC = ../../ports/ARMCM3/chcore.c \ + ../../ports/ARMCM3/nvic.c \ + ../../ports/ARMCM3-STM32F103/stm32_serial.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ + board.c main.c -# Enable register caching optimization. This option greatly improves both -# code size and execution speed but is incompatible with libraries compiled -# without the very same options. The register R7 becomes a global variable -# and MUST NOT be used anywhere in the code. -USE_CURRP_CACHING = no +# List ASM source files here +ASMSRC = ../../ports/ARMCM3/crt0.s \ + ../../ports/ARMCM3-STM32F103/vectors.s +INCDIR = $(KERNINC) $(TESTINC) \ + ../../src/lib \ + ../../ports/ARMCM3 \ + ../../ports/ARMCM3-STM32F103 \ + ./stm32lib/inc # -# End of OS and demo options -############################################################################################## +# Project, sources and paths +############################################################################## -############################################################################################## -# Start of default section +############################################################################## +# Compiler settings # +MCU = cortex-m3 + #TRGT = arm-none-eabi- #TRGT = arm-eabi- TRGT = arm-elf- @@ -49,7 +80,16 @@ OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -MCU = cortex-m3 +# Define warning options here +WARN = -Wall -Wstrict-prototypes + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -68,9 +108,9 @@ DLIBS = # # End of default section -############################################################################################## +############################################################################## -############################################################################################## +############################################################################## # Start of user section # @@ -86,32 +126,8 @@ UDEFS = # Define ASM defines here UADEFS = -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk -ifeq ($(USE_FWLIB),yes) -include ./stm32lib/stm32lib.mk -endif - -# List ARM-mode C source files here -SRC = ../../ports/ARMCM3/chcore.c ../../ports/ARMCM3/nvic.c \ - ../../ports/ARMCM3-STM32F103/stm32_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c main.c - -ifeq ($(USE_FWLIB),yes) -SRC += ${STM32SRC} -endif - -# List ASM source files here -ASMSRC = ../../ports/ARMCM3/crt0.s ../../ports/ARMCM3-STM32F103/vectors.s - # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARMCM3 ../../ports/ARMCM3-STM32F103 \ - ./stm32lib/inc +UINCDIR = # List the user directory to look for the libraries here ULIBDIR = @@ -119,91 +135,8 @@ ULIBDIR = # List all user libraries here ULIBS = -# Define warning options here -WARN = -Wall -Wstrict-prototypes - # # End of user defines -############################################################################################## - -ifeq ($(USE_CURRP_CACHING),yes) -OPT += -ffixed-r7 -DCH_CURRP_REGISTER_CACHE='"r7"' -endif - -ifeq ($(USE_FWLIB),yes) -# The thing generates a lot of aliasing warnings, this disables an optimization -# and the warning disappears, the code is a bit larger however. -OPT += -fno-strict-aliasing -endif - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -COBJS = $(SRC:.c=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(COBJS) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) -mthumb - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(COBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(COBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +############################################################################## -# *** EOF *** +include ../../ports/ARMCM3/rules.mk -- cgit v1.2.3 From 3457abe3f7a7f5ddc533a4f33759efcd5fe5a516 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 18 Feb 2009 21:24:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@786 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 313 +++++++++++++--------------------- demos/ARM7-LPC214x-G++/Makefile.thumb | 256 --------------------------- demos/ARM7-LPC214x-GCC/Makefile | 60 +++++-- 3 files changed, 162 insertions(+), 467 deletions(-) delete mode 100644 demos/ARM7-LPC214x-G++/Makefile.thumb (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 56506f8f5..34c365e86 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -1,21 +1,105 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. # -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + # -# make clean = Clean project files. +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths # -# To rebuild project do "make clean" and "make all". + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ + board.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = ../../src/lib/ch.cpp main.cpp + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = ../../ports/ARM7/crt0.s \ + ../../ports/ARM7-LPC214x/vectors.s \ + ../../ports/ARM7/chcoreasm.s + +INCDIR = $(KERNINC) $(TESTINC) \ + ../../src/lib \ + ../../ports/ARM7 \ + ../../ports/ARM7-LPC214x + # +# Project, sources and paths +############################################################################## -############################################################################################## -# Start of default section +############################################################################## +# Compiler settings # +MCU = arm7tdmi + TRGT = arm-elf- CC = $(TRGT)gcc CPPC = $(TRGT)g++ @@ -30,10 +114,25 @@ OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -MCU = arm7tdmi +# ARM-specific options here +AOPT = -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -52,53 +151,20 @@ DLIBS = # # End of default section -############################################################################################## +############################################################################## -############################################################################################## +############################################################################## # Start of user section # -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - # List all user C define here, like -D_DEBUG=1 UDEFS = # Define ASM defines here UADEFS = -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ACSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c - -# List ARM-mode C++ source files here -ACPPSRC = ../../src/lib/ch.cpp main.cpp - -# List THUMB-mode C sources here -TCSRC = - -# List THUMB-mode C++ source files here -TCPPSRC = - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-LPC214x/vectors.s - # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-LPC214x +UINCDIR = # List the user directory to look for the libraries here ULIBDIR = @@ -106,151 +172,8 @@ ULIBDIR = # List all user libraries here ULIBS = -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -OPT += -falign-functions=16 - -# C++ specific options here -# NOTE: -fno-rtti saves a LOT of code space, remove it only if you really need -# RTTI. -CPPOPT = -fno-rtti - -# Define warning options here -WARN = -Wall - # # End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) -SRC = $(ASRC)$(TSRC) -ACOBJS = $(ACSRC:.c=.o) -ACPPOBJS = $(ACPPSRC:.cpp=.o) -TCOBJS = $(TCSRC:.c=.o) -TCPPOBJS = $(TCPPSRC:.cpp=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(WARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CFLAGS += -D THUMB_PRESENT - CPPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CFLAGS += -mthumb-interwork - CPPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - CPPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - CPPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CFLAGS += -MD -MP -MF .dep/$(@F).d -CPPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(ACPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TCPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ACOBJS) : %.o : %.c - @echo - $(CC) -c $(CFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TCOBJS) : %.o : %.c - @echo - $(CC) -c $(CFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(LD) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ACSRC:.c=.c.bak) - -rm -f $(ACSRC:.c=.lst) - -rm -f $(TCSRC:.c=.c.bak) - -rm -f $(TCSRC:.c=.lst) - -rm -f $(ACPPSRC:.cpp=.c.bak) - -rm -f $(ACPPSRC:.cpp=.lst) - -rm -f $(TCPPSRC:.cpp=.c.bak) - -rm -f $(TCPPSRC:.cpp=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +############################################################################## -# *** EOF *** +include ../../ports/ARM7/rules.mk diff --git a/demos/ARM7-LPC214x-G++/Makefile.thumb b/demos/ARM7-LPC214x-G++/Makefile.thumb deleted file mode 100644 index 6a5bdbaf2..000000000 --- a/demos/ARM7-LPC214x-G++/Makefile.thumb +++ /dev/null @@ -1,256 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = arm-elf- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -MCU = arm7tdmi - -# Enable this if you want the linker to remove unused code and data -LINK_GC = yes - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -ACSRC = - -# List ARM-mode C++ source files here -ACPPSRC = - -# List THUMB-mode C sources here -TCSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c - -# List THUMB-mode C++ source files here -TCPPSRC = ../../src/lib/ch.cpp main.cpp - -# List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chcoreasm.s \ - ../../ports/ARM7-LPC214x/vectors.s - -# List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test \ - ../../ports/ARM7 ../../ports/ARM7-LPC214x - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -D THUMB - -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -# NOTE: -falign-functions=16 may improve the performance, not always, but -# increases the code size. -OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -#OPT += -ffixed-r7 -OPT += -falign-functions=16 - -# C++ specific options here -# NOTE: -fno-rtti saves a LOT of code space, remove it only if you really need -# RTTI. -CPPOPT = -fno-rtti - -# Define warning options here -WARN = -Wall - -# -# End of user defines -############################################################################################## - -ifeq ($(LINK_GC),yes) - OPT += -ffunction-sections -fdata-sections -endif - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -ASRC = $(ACSRC)$(ACPPSRC) -TSRC = $(TCSRC)$(TCPPSRC) -SRC = $(ASRC)$(TSRC) -ACOBJS = $(ACSRC:.c=.o) -ACPPOBJS = $(ACPPSRC:.cpp=.o) -TCOBJS = $(TCSRC:.c=.o) -TCPPOBJS = $(TCPPSRC:.cpp=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mcpu=$(MCU) - -ODFLAGS = -x --syms -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(WARN) -Wa,-alms=$(<:.cpp=.lst) $(DEFS) -ifeq ($(LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LIBDIR) -else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Thumb interwork enabled only if needed because it kills performance. -ifneq ($(TSRC),) - CFLAGS += -D THUMB_PRESENT - CPPFLAGS += -D THUMB_PRESENT - ASFLAGS += -D THUMB_PRESENT - ifneq ($(ASRC),) - # Mixed ARM and THUMB case. - CFLAGS += -mthumb-interwork - CPPFLAGS += -mthumb-interwork - LDFLAGS += -mthumb-interwork - else - # Pure THUMB case, THUMB C code cannot be called by ARM asm code directly. - CFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - CPPFLAGS += -mno-thumb-interwork -D THUMB_NO_INTERWORKING - LDFLAGS += -mno-thumb-interwork -mthumb - ASFLAGS += -D THUMB_NO_INTERWORKING - endif -else - CPFLAGS += -mno-thumb-interwork - CPPFLAGS += -mno-thumb-interwork - LDFLAGS += -mno-thumb-interwork -endif - -# Generate dependency information -CFLAGS += -MD -MP -MF .dep/$(@F).d -CPPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# - -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(ACPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TCPPOBJS) : %.o : %.cpp - @echo - $(CPPC) -c $(CPPFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ACOBJS) : %.o : %.c - @echo - $(CC) -c $(CFLAGS) $(AOPT) -I . $(INCDIR) $< -o $@ - -$(TCOBJS) : %.o : %.c - @echo - $(CC) -c $(CFLAGS) $(TOPT) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(LD) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(ACSRC:.c=.c.bak) - -rm -f $(ACSRC:.c=.lst) - -rm -f $(TCSRC:.c=.c.bak) - -rm -f $(TCSRC:.c=.lst) - -rm -f $(ACPPSRC:.cpp=.c.bak) - -rm -f $(ACPPSRC:.cpp=.lst) - -rm -f $(TCPPSRC:.cpp=.c.bak) - -rm -f $(TCPPSRC:.cpp=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index ff75442f2..fc417a0cd 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + # Enable this if you want the linker to remove unused code and data ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes @@ -41,26 +46,40 @@ LDSCRIPT= ch.ld include ../../src/kernel.mk include ../../test/test.mk -# Sources that can be compiled in ARM or THUMB mode depending on the global +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/lpc214x_serial.c \ + ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ + board.c buzzer.c mmcsd.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -SRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c buzzer.c mmcsd.c main.c - -# Sources to be compiled in ARM mode regardless of the global setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -ASRC = +ACSRC = -# Sources to be compiled in THUMB mode regardless of the global setting. +# C++ sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -TSRC = +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = # List ASM source files here ASMSRC = ../../ports/ARM7/crt0.s \ @@ -84,6 +103,12 @@ MCU = arm7tdmi TRGT = arm-elf- CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump @@ -96,8 +121,11 @@ AOPT = # THUMB-specific options here TOPT = -mthumb -DTHUMB -# Define warning options here -WARN = -Wall -Wstrict-prototypes +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall # # Compiler settings -- cgit v1.2.3 From 896bbfd7ea6191100105e2c87a423c5487e55f35 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 18 Feb 2009 21:31:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@787 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 50 +++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 11 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 67e41a385..e802820ee 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -8,6 +8,11 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + # Enable this if you want the linker to remove unused code and data ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes @@ -41,22 +46,36 @@ LDSCRIPT= ch.ld include ../../src/kernel.mk #include ../../test/test.mk -# Sources that can be compiled in ARM or THUMB mode depending on the global +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-LPC214x/vic.c \ + ${KERNSRC} \ + board.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -SRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ${KERNSRC} \ - board.c main.c +CPPSRC = -# Sources to be compiled in ARM mode regardless of the global setting. +# C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -ASRC = +ACSRC = -# Sources to be compiled in THUMB mode regardless of the global setting. +# C++ sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -TSRC = +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = # List ASM source files here ASMSRC = ../../ports/ARM7/crt0.s \ @@ -80,6 +99,12 @@ MCU = arm7tdmi TRGT = arm-elf- CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump @@ -92,8 +117,11 @@ AOPT = # THUMB-specific options here TOPT = -mthumb -DTHUMB -# Define warning options here -WARN = -Wall -Wstrict-prototypes +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall # # Compiler settings -- cgit v1.2.3 From 3674e55f833c382562116693389daa097a28a8fc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 19 Feb 2009 18:30:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@789 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 63 ++++++++++++++------ demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 69 +++++++++++++++------- demos/ARM7-LPC214x-G++/Makefile | 2 +- demos/ARM7-LPC214x-GCC-minimal/Makefile | 2 +- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/Makefile | 100 +++++++++++++++++++++++++------- 6 files changed, 175 insertions(+), 63 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index d7e30724a..36df1cd51 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -5,7 +5,12 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti endif # Enable this if you want the linker to remove unused code and data @@ -41,26 +46,39 @@ LDSCRIPT= ch.ld include ../../src/kernel.mk include ../../test/test.mk -# Sources that can be compiled in ARM or THUMB mode depending on the global +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ + ${KERNSRC} \ + ${TESTSRC} \ + at91lib/aic.c \ + board.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -SRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - at91lib/aic.c \ - board.c main.c - -# Sources to be compiled in ARM mode regardless of the global setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -ASRC = +ACSRC = -# Sources to be compiled in THUMB mode regardless of the global setting. +# C++ sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -TSRC = +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = # List ASM source files here ASMSRC = ../../ports/ARM7/crt0.s \ @@ -84,6 +102,12 @@ MCU = arm7tdmi TRGT = arm-elf- CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump @@ -96,8 +120,11 @@ AOPT = # THUMB-specific options here TOPT = -mthumb -DTHUMB -# Define warning options here -WARN = -Wall -Wstrict-prototypes +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall # # Compiler settings @@ -149,4 +176,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM7/rules.mk +include ../../ports/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 20d44a9d5..c9a08306a 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -5,7 +5,12 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti endif # Enable this if you want the linker to remove unused code and data @@ -50,29 +55,42 @@ USRC = ../../ext/uip-1.0/uip/uip_arp.c \ ../../ext/uip-1.0/apps/webserver/httpd-fs.c \ ../../ext/uip-1.0/apps/webserver/httpd-cgi.c -# Sources that can be compiled in ARM or THUMB mode depending on the global +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ + ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ${USRC} \ + ../../src/lib/evtimer.c \ + at91lib/aic.c \ + web/webthread.c \ + board.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -SRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ${USRC} \ - ../../src/lib/evtimer.c \ - at91lib/aic.c \ - web/webthread.c \ - board.c main.c - -# Sources to be compiled in ARM mode regardless of the global setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -ASRC = +ACSRC = -# Sources to be compiled in THUMB mode regardless of the global setting. +# C++ sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler # option that results in lower performance and larger code size. -TSRC = +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = # List ASM source files here ASMSRC = ../../ports/ARM7/crt0.s \ @@ -97,6 +115,12 @@ MCU = arm7tdmi TRGT = arm-elf- CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump @@ -109,8 +133,11 @@ AOPT = # THUMB-specific options here TOPT = -mthumb -DTHUMB -# Define warning options here -WARN = -Wall -Wstrict-prototypes +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall # # Compiler settings @@ -162,4 +189,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM7/rules.mk +include ../../ports/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 34c365e86..24a8ce684 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -176,4 +176,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM7/rules.mk +include ../../ports/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index e802820ee..2ea142e81 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -173,4 +173,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM7/rules.mk +include ../../ports/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index fc417a0cd..6b3620e8a 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -177,4 +177,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM7/rules.mk +include ../../ports/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 2fd02d7f5..46aad57d1 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -8,23 +8,41 @@ ifeq ($(USE_OPT),) USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + # Enable this if you want the linker to remove unused code and data -ifeq ($(LINK_GC),) +ifeq ($(USE_LINK_GC),) USE_LINK_GC = yes endif +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + # Enable register caching optimization (read documentation). ifeq ($(USE_CURRP_CACHING),) USE_CURRP_CACHING = no endif +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + # Enable this if you really want to use the STM FWLib. ifeq ($(USE_FWLIB),) USE_FWLIB = no endif # -# Build global options +# Architecture or project specific options ############################################################################## ############################################################################## @@ -41,15 +59,39 @@ LDSCRIPT= ch.ld include ../../src/kernel.mk include ../../test/test.mk -# Sources that can be compiled in ARM or THUMB mode depending on the global +# C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -SRC = ../../ports/ARMCM3/chcore.c \ - ../../ports/ARMCM3/nvic.c \ - ../../ports/ARMCM3-STM32F103/stm32_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c main.c +CSRC = ../../ports/ARMCM3/chcore.c \ + ../../ports/ARMCM3/nvic.c \ + ../../ports/ARMCM3-STM32F103/stm32_serial.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ + board.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = ../../src/lib/ch.cpp + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = # List ASM source files here ASMSRC = ../../ports/ARMCM3/crt0.s \ @@ -60,6 +102,7 @@ INCDIR = $(KERNINC) $(TESTINC) \ ../../ports/ARMCM3 \ ../../ports/ARMCM3-STM32F103 \ ./stm32lib/inc + # # Project, sources and paths ############################################################################## @@ -70,18 +113,31 @@ INCDIR = $(KERNINC) $(TESTINC) \ MCU = cortex-m3 -#TRGT = arm-none-eabi- -#TRGT = arm-eabi- TRGT = arm-elf- CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -# Define warning options here -WARN = -Wall -Wstrict-prototypes +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall # # Compiler settings @@ -114,12 +170,6 @@ DLIBS = # Start of user section # -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - # List all user C define here, like -D_DEBUG=1 UDEFS = @@ -139,4 +189,12 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARMCM3/rules.mk +ifeq ($(USE_FWLIB),yes) + include ./stm32lib/stm32lib.mk + CSRC += ${STM32SRC} + # The thing generates a lot of aliasing warnings, this disables an + # optimization and the warning disappears, the code is a bit larger however. + USE_OPT += -fno-strict-aliasing +endif + +include ../../ports/ARM/rules.mk -- cgit v1.2.3 From daabc2b079b17a41ca2f1a2a6423373f811402ba Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 20 Feb 2009 20:14:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@791 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 15 ++++++++++++--- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 15 ++++++++++++--- demos/ARM7-LPC214x-G++/chconf.h | 15 ++++++++++++--- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 15 ++++++++++++--- demos/ARM7-LPC214x-GCC/chconf.h | 15 ++++++++++++--- demos/ARMCM3-STM32F103-GCC/chconf.h | 19 ++++++++++++++----- demos/AVR-AT90CANx-GCC/chconf.h | 15 ++++++++++++--- demos/AVR-ATmega128-GCC/chconf.h | 15 ++++++++++++--- demos/MSP430-MSP430x1611-GCC/chconf.h | 15 ++++++++++++--- demos/Win32-MinGW/chconf.h | 15 ++++++++++++--- 10 files changed, 122 insertions(+), 32 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index e8cc24807..84c581f3f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index d91a2f743..cb606580b 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index d91a2f743..cb606580b 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 487710674..934a5dd1b 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index d91a2f743..cb606580b 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index d91a2f743..72407ff5b 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -359,7 +368,7 @@ * may not be implemented at all. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -367,7 +376,7 @@ * pattern when a thread is created. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 15ce1a80d..ff98f4164 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 15ce1a80d..ff98f4164 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 109135795..7ce3cdbce 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 761819bba..40cb2e53d 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -335,9 +335,18 @@ /*===========================================================================*/ /** - * Debug option, if enabled all the assertions in the kernel code are - * activated. This includes function parameters checks and consistency - * checks inside the kernel. + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -- cgit v1.2.3 From 605d283b6aced9dd69f32b6d6ac0e9f0d25cd10e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 20 Feb 2009 20:21:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@792 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 029de3566..97f248a54 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -109,7 +109,7 @@ struct context { /** * Enforces a correct alignment for a stack area size value. */ -#define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1) +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) /** * Computes the thread working area global size. -- cgit v1.2.3 From 12d846c0094974aa79a8b2992d46d87c665fc8e6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 20 Feb 2009 21:29:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@794 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 72407ff5b..cb606580b 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -368,7 +368,7 @@ * may not be implemented at all. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -376,7 +376,7 @@ * pattern when a thread is created. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** -- cgit v1.2.3 From 73a6c86af1bb7f4c16f5aaf8d170176adc609fc8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 21 Feb 2009 11:14:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@798 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/main.cpp | 2 +- demos/ARM7-LPC214x-GCC-minimal/main.c | 4 ++-- demos/ARM7-LPC214x-GCC/chconf.h | 4 ++-- demos/ARM7-LPC214x-GCC/main.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index a269189ab..37d79c04d 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -80,7 +80,7 @@ static const seqop_t LED3_sequence[] = * Any sequencer is just an instance of this class, all the details are * totally encapsulated and hidden to the application level. */ -class SequencerThread : EnhancedThread<64> { +class SequencerThread : EnhancedThread<128> { private: const seqop_t *base, *curr; // Thread local variables. diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index b80264ed7..59dc04158 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -24,7 +24,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread1, 64); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { @@ -43,7 +43,7 @@ static msg_t Thread1(void *arg) { /* * Yellow LED blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread2, 64); +static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index cb606580b..72407ff5b 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -368,7 +368,7 @@ * may not be implemented at all. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -376,7 +376,7 @@ * pattern when a thread is created. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE +#define CH_DBG_FILL_THREADS TRUE #endif /** diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 96b117f8a..c83d9a419 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -29,7 +29,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread1, 64); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { @@ -48,7 +48,7 @@ static msg_t Thread1(void *arg) { /* * Yellow LED blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread2, 64); +static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { -- cgit v1.2.3 From 5954248a03a87a68cbb81ca4c830a31aa07d33e0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 21 Feb 2009 11:15:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@799 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/chconf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 72407ff5b..cb606580b 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -368,7 +368,7 @@ * may not be implemented at all. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** @@ -376,7 +376,7 @@ * pattern when a thread is created. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS FALSE #endif /** -- cgit v1.2.3 From 1fa657d77dde43a9c283a67bf86c57531f624437 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 22 Feb 2009 08:43:49 +0000 Subject: Removed unused port functionality port_puts(). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@800 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.c | 8 -------- demos/Win32-MinGW/chcore.h | 1 - 2 files changed, 9 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 446508e3c..a2194336c 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -93,14 +93,6 @@ void ChkIntSources(void) { } } -/** - * Prints a message on the system console. - * @param msg pointer to the message - */ -__attribute__((fastcall)) -void port_puts(char *msg) { -} - /** * Performs a context switch between two threads. * @param otp the thread to be switched out diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 97f248a54..276b935da 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -192,7 +192,6 @@ struct context { #ifdef __cplusplus extern "C" { #endif - __attribute__((fastcall)) void port_puts(char *msg); __attribute__((fastcall)) void port_switch(Thread *otp, Thread *ntp); __attribute__((fastcall)) void port_halt(void); void InitCore(void); -- cgit v1.2.3 From d425f2ec12b111f01dfe854c638c18da2a279881 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 22 Feb 2009 09:56:36 +0000 Subject: Improved MSP430 makefile. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@801 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 198 +++++++++++++++------------------- 1 file changed, 89 insertions(+), 109 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index b42da1da3..4f9d159c3 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -1,30 +1,102 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. # -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = no +endif + +# Enable register caching optimization (read documentation). +# Option not tested on MSP430, DO NOT USE. +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + # -# make clean = Clean project files. +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths # -# To rebuild project do "make clean" and "make all". + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= mspgcc/msp430x1611.x + +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + +# C sources here. +CSRC = ../../ports/MSP430/chcore.c \ + ../../ports/MSP430/msp430_serial.c \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../src/lib/evtimer.c \ + board.c main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = + +INCDIR = $(KERNINC) $(TESTINC) \ + ../../src/lib \ + ../../ports/MSP430 + # +# Project, sources and paths +############################################################################## -############################################################################################## -# Start of default section +############################################################################## +# Compiler settings # +MCU = msp430x1611 + TRGT = msp430- CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ CP = $(TRGT)objcopy AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -MCU = msp430x1611 +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -43,41 +115,20 @@ DLIBS = # # End of default section -############################################################################################## +############################################################################## -############################################################################################## +############################################################################## # Start of user section # -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= mspgcc/msp430x1611.x - # List all user C define here, like -D_DEBUG=1 UDEFS = # Define ASM defines here UADEFS = -# Imported source files -include ../../src/kernel.mk -include ../../test/test.mk - -# List ARM-mode C source files here -SRC = ../../ports/MSP430/chcore.c \ - ../../ports/MSP430/msp430_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ - board.c main.c - -# List ASM source files here -ASMSRC = - # List all user directories here -UINCDIR = ../../src/include ../../src/lib ../../test ../../ports/MSP430 +UINCDIR = # List the user directory to look for the libraries here ULIBDIR = @@ -85,79 +136,8 @@ ULIBDIR = # List all user libraries here ULIBS = -# Common options here -# NOTE: -ffixed-r7 is only needed if you enabled CH_CURRP_REGISTER_CACHE in -# chconf.h. -OPT = -O2 -ggdb -fomit-frame-pointer -#OPT += -ffixed-r7 - -# Define warning options here -WARN = -Wall -Wstrict-prototypes - # # End of user defines -############################################################################################## - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -COBJS = $(SRC:.c=.o) -ASMOBJS = $(ASMSRC:.s=.o) -OBJS = $(ASMOBJS) $(COBJS) -LIBS = $(DLIBS) $(ULIBS) -MCFLAGS = -mmcu=$(MCU) - -ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(MCFLAGS) $(OPT) $(WARN) -Wa,-alms=$(<:.c=.lst) $(DEFS) -LDFLAGS = $(MCFLAGS) -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -ODFLAGS = -x --syms - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# Makefile rules -# -all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).dmp - -$(COBJS) : %.o : %.c - @echo - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -$(ASMOBJS) : %.o : %.s - @echo - $(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@ - -%elf: $(OBJS) - @echo - $(CC) $(ASMOBJS) $(COBJS) $(LDFLAGS) $(LIBS) -o $@ - -%hex: %elf - $(HEX) $< $@ - -%bin: %elf - $(BIN) $< $@ - -%dmp: %elf - $(OD) $(ODFLAGS) $< > $@ - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT).elf - -rm -f $(PROJECT).dmp - -rm -f $(PROJECT).map - -rm -f $(PROJECT).hex - -rm -f $(PROJECT).bin - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASMSRC:.s=.s.bak) - -rm -f $(ASMSRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) +############################################################################## -# *** EOF *** +include ../../ports/MSP430/rules.mk -- cgit v1.2.3 From da4f9beaee8f1f8f344012b4d9a122462a6c802e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 10 Mar 2009 15:31:58 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@827 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 1d80b9d76..c2ac24868 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -194,7 +194,7 @@ static msg_t ShellThread(void *arg) { else if (stricmp(lp, "time") == 0) { if (checkend(sd)) continue; - sprintf(line, "Time: %d\r\n", chSysGetTime()); + sprintf(line, "Time: %d\r\n", chTimeNow()); PrintLineFDD(sd, line); } else if (stricmp(lp, "hello") == 0) { -- cgit v1.2.3 From 19e54114ecf114725575b2151b49d315e0696217 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 13 Mar 2009 17:45:04 +0000 Subject: Bug 2686347 fixed. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@836 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 1 - 1 file changed, 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 36df1cd51..728167a6d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -50,7 +50,6 @@ include ../../test/test.mk # setting. CSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ${KERNSRC} \ ${TESTSRC} \ at91lib/aic.c \ -- cgit v1.2.3 From ac4e799160b05fc1a9f39ce28fde891e749fddbc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 15 Mar 2009 09:27:36 +0000 Subject: Fixed bug 2687489. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@851 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 37d79c04d..2f89d5dcf 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -108,7 +108,7 @@ protected: } public: - SequencerThread(const seqop_t *sequence) : EnhancedThread<64>("sequencer") { + SequencerThread(const seqop_t *sequence) : EnhancedThread<128>("sequencer") { base = curr = sequence; } -- cgit v1.2.3 From 098780ea7b5df30187198d9970c70d1af9fb5725 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 28 Mar 2009 21:08:58 +0000 Subject: Fixed bug 2686451. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@857 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 46aad57d1..eb957c072 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -71,7 +71,7 @@ CSRC = ../../ports/ARMCM3/chcore.c \ # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CPPSRC = ../../src/lib/ch.cpp +CPPSRC = # C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -- cgit v1.2.3 From d209f631a56dcf5cf2032cb51054969221736a02 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 31 Mar 2009 15:03:25 +0000 Subject: Fixed bug 2700695. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@859 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 6 ++---- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 21e9665f2..43c624d9a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -25,11 +25,9 @@ #include /* - * FIQ Handler, unused in this demo. + * FIQ Handler weak symbol defined in vectors.s. */ -__attribute__((interrupt("FIQ"))) -static void FiqHandler(void) { -} +void FiqHandler(void); static CH_IRQ_HANDLER(SpuriousHandler) { diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 8f9a45af4..630a0ad5d 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -26,11 +26,9 @@ #include /* - * FIQ Handler, unused in this demo. + * FIQ Handler weak symbol defined in vectors.s. */ -__attribute__((interrupt("FIQ"))) -static void FiqHandler(void) { -} +void FiqHandler(void); static CH_IRQ_HANDLER(SpuriousHandler) { -- cgit v1.2.3 From a8a6649caa7a12aef55883d5c1907a7f5cbca386 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 9 Apr 2009 12:27:02 +0000 Subject: Fixed bug 2745153. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@882 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 4 ++-- demos/Win32-MinGW/chcore.c | 21 +++++++++++---------- 2 files changed, 13 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 841557827..c0e4afbca 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -77,7 +77,7 @@ ULIBDIR = ULIBS = # Define optimisation level here -OPT = -ggdb -O2 -fomit-frame-pointer +OPT = -ggdb -O0 -fomit-frame-pointer # # End of user defines @@ -93,7 +93,7 @@ LIBS = $(DLIBS) $(ULIBS) LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index a2194336c..081a02753 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -98,20 +98,21 @@ void ChkIntSources(void) { * @param otp the thread to be switched out * @param ntp the thread to be switched in */ -__attribute__((fastcall)) -void port_switch(Thread *otp, Thread *ntp) { - register struct intctx volatile *esp asm("esp"); - - asm volatile ("push %ebp \n\t" \ +__attribute__((used)) +static void __dummy(Thread *otp, Thread *ntp) { + asm volatile (".globl @port_switch@8 \n\t" \ + "@port_switch@8: \n\t" \ + "push %ebp \n\t" \ "push %esi \n\t" \ "push %edi \n\t" \ - "push %ebx"); - otp->p_ctx.esp = esp; - esp = ntp->p_ctx.esp; - asm volatile ("pop %ebx \n\t" \ + "push %ebx \n\t" \ + "movl %esp, 16(%ecx) \n\t" \ + "movl 16(%edx), %esp \n\t" \ + "pop %ebx \n\t" \ "pop %edi \n\t" \ "pop %esi \n\t" \ - "pop %ebp"); + "pop %ebp \n\t" \ + "ret"); } /** -- cgit v1.2.3 From 418d221cde3d0c5a4e2ff3c7e84e369af550f965 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 9 Apr 2009 13:12:17 +0000 Subject: Gcov support in MinGW demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@883 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index c0e4afbca..db72f2488 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -19,6 +19,7 @@ TRGT = mingw32- CC = $(TRGT)gcc AS = $(TRGT)gcc -x assembler-with-cpp +COV = gcov # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -77,7 +78,10 @@ ULIBDIR = ULIBS = # Define optimisation level here -OPT = -ggdb -O0 -fomit-frame-pointer +OPT = -ggdb -O2 -fomit-frame-pointer + +# Debug target options here +DOPT = -ggdb -O0 -fomit-frame-pointer -fprofile-arcs -ftest-coverage # # End of user defines @@ -94,9 +98,11 @@ LIBS = $(DLIBS) $(ULIBS) LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) +DCPFLAGS = $(DOPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d +DCPFLAGS += -MD -MP -MF .dep/$(@F).d # # makefile rules @@ -104,6 +110,10 @@ CPFLAGS += -MD -MP -MF .dep/$(@F).d all: $(OBJS) $(PROJECT).exe +debug: $(OBJS) $(PROJECT).exe +CPFLAGS = $(DCPFLAGS) +LDFLAGS += -lgcov + %o : %c $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ @@ -113,15 +123,23 @@ all: $(OBJS) $(PROJECT).exe %exe: $(OBJS) $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ +gcov: + -mkdir gcov + $(COV) -u $(subst /,\,$(SRC)) + -mv *.gcov ./gcov + clean: -rm -f $(OBJS) -rm -f $(PROJECT).exe -rm -f $(PROJECT).map -rm -f $(SRC:.c=.c.bak) -rm -f $(SRC:.c=.lst) + -rm -f $(SRC:.c=.gcno) + -rm -f $(SRC:.c=.gcda) -rm -f $(ASRC:.s=.s.bak) -rm -f $(ASRC:.s=.lst) -rm -fR .dep + -rm -fR gcov # # Include the dependency files, should be the last of the makefile -- cgit v1.2.3 From 00bfdd2bc7717a0e6d6e9e61906aad1e7461ee31 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 10 Apr 2009 19:32:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@886 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index db72f2488..ed66e51fd 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -19,7 +19,6 @@ TRGT = mingw32- CC = $(TRGT)gcc AS = $(TRGT)gcc -x assembler-with-cpp -COV = gcov # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -66,7 +65,7 @@ SRC = chcore.c main.c ../../ports/win32/simcom.c \ ${TESTSRC} # List ASM source files here -ASRC = +ASRC = # List all user directories here UINCDIR = ../../src/include @@ -80,9 +79,6 @@ ULIBS = # Define optimisation level here OPT = -ggdb -O2 -fomit-frame-pointer -# Debug target options here -DOPT = -ggdb -O0 -fomit-frame-pointer -fprofile-arcs -ftest-coverage - # # End of user defines ############################################################################################## @@ -98,11 +94,9 @@ LIBS = $(DLIBS) $(ULIBS) LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) -DCPFLAGS = $(DOPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d -DCPFLAGS += -MD -MP -MF .dep/$(@F).d # # makefile rules @@ -110,10 +104,6 @@ DCPFLAGS += -MD -MP -MF .dep/$(@F).d all: $(OBJS) $(PROJECT).exe -debug: $(OBJS) $(PROJECT).exe -CPFLAGS = $(DCPFLAGS) -LDFLAGS += -lgcov - %o : %c $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ @@ -134,12 +124,9 @@ clean: -rm -f $(PROJECT).map -rm -f $(SRC:.c=.c.bak) -rm -f $(SRC:.c=.lst) - -rm -f $(SRC:.c=.gcno) - -rm -f $(SRC:.c=.gcda) -rm -f $(ASRC:.s=.s.bak) -rm -f $(ASRC:.s=.lst) -rm -fR .dep - -rm -fR gcov # # Include the dependency files, should be the last of the makefile -- cgit v1.2.3 From f332c2881c4a2eef422ed1631a8335d07e9818ad Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 18 Apr 2009 10:34:23 +0000 Subject: Fixed bug 2772237. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@911 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index c9b3b395e..d064e1ef3 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -83,7 +83,7 @@ void clock_init(void) {} clock_time_t clock_time( void ) { - return chSysGetTime(); + return chTimeNow(); } /* -- cgit v1.2.3 From d62a644b1e910c7fccd65d768a838fcc651e4e80 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Apr 2009 07:15:05 +0000 Subject: Removed the chMsgSendWithEvent() function and the related configuration option. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@914 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 10 ---------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 10 ---------- demos/ARM7-LPC214x-G++/chconf.h | 10 ---------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 10 ---------- demos/ARM7-LPC214x-GCC/chconf.h | 10 ---------- demos/ARMCM3-STM32F103-GCC/chconf.h | 10 ---------- demos/AVR-AT90CANx-GCC/chconf.h | 10 ---------- demos/AVR-ATmega128-GCC/chconf.h | 10 ---------- demos/MSP430-MSP430x1611-GCC/chconf.h | 10 ---------- demos/Win32-MinGW/chconf.h | 10 ---------- 10 files changed, 100 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 84c581f3f..ac0b475e5 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index cb606580b..bffe5dc33 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index cb606580b..bffe5dc33 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 934a5dd1b..ea458f196 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES FALSE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT FALSE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index cb606580b..bffe5dc33 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index cb606580b..bffe5dc33 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index ff98f4164..2681f9563 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index ff98f4164..2681f9563 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 7ce3cdbce..75239717e 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 40cb2e53d..208c67a18 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -215,16 +215,6 @@ #define CH_USE_MESSAGES TRUE #endif -/** - * If specified then the @p chMsgSendWithEvent() function is included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MESSAGES and @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_MESSAGES_EVENT) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_EVENT TRUE -#endif - /** * If enabled then messages are served by priority rather than in FIFO order. * @note The default is @p FALSE. Enable this if you have special requirements. -- cgit v1.2.3 From 756658a69a1abca61281b4dbd84a6dada9fc91b5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 25 Apr 2009 14:56:16 +0000 Subject: Improved test code, architecture names added to the port code. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@918 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chcore.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'demos') diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h index 276b935da..fdeb245fb 100644 --- a/demos/Win32-MinGW/chcore.h +++ b/demos/Win32-MinGW/chcore.h @@ -30,6 +30,11 @@ */ #define CH_ARCHITECTURE_WIN32SIM +/** + * Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "WIN32 Simulator" + /** * 32 bit stack alignment. */ -- cgit v1.2.3 From c989a8967cdcbd54109d686678936a3581fd2c70 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 1 May 2009 13:11:26 +0000 Subject: Removed the CH_USE_SERIAL_HALFDUPLEX, CH_USE_QUEUES_TIMEOUT and CH_USE_QUEUES_HALFDUPLEX configuration options. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@927 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 29 ----------------------------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 29 ----------------------------- demos/ARM7-LPC214x-G++/chconf.h | 29 ----------------------------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 29 ----------------------------- demos/ARM7-LPC214x-GCC/chconf.h | 29 ----------------------------- demos/ARMCM3-STM32F103-GCC/chconf.h | 29 ----------------------------- demos/AVR-AT90CANx-GCC/chconf.h | 29 ----------------------------- demos/AVR-ATmega128-GCC/chconf.h | 29 ----------------------------- demos/MSP430-MSP430x1611-GCC/chconf.h | 29 ----------------------------- demos/Win32-MinGW/chconf.h | 29 ----------------------------- 10 files changed, 290 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index ac0b475e5..67f096a8c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index bffe5dc33..f06a537b2 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index bffe5dc33..f06a537b2 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index ea458f196..130ef5967 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES FALSE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX FALSE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT FALSE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX FALSE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX FALSE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index bffe5dc33..f06a537b2 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index bffe5dc33..f06a537b2 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 2681f9563..9c00191cc 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 2681f9563..9c00191cc 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 75239717e..616e39ac6 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 208c67a18..b11bff238 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -242,25 +242,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the half duplex queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_HALFDUPLEX TRUE -#endif - -/** - * If specified then the I/O queues with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES and @p CH_USE_SEMAPHORES_TIMEOUT. - */ -#if !defined(CH_USE_QUEUES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_QUEUES_TIMEOUT TRUE -#endif - /** * If specified then the full duplex serial driver APIs are included in the * kernel. @@ -271,16 +252,6 @@ #define CH_USE_SERIAL_FULLDUPLEX TRUE #endif -/** - * If specified then the half duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES_HALFDUPLEX. - */ -#if !defined(CH_USE_SERIAL_HALFDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_HALFDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. -- cgit v1.2.3 From 1f7dd2586a16b6f47ba6214faf954481de6c4086 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 3 May 2009 10:43:54 +0000 Subject: Adjusted LPC214x serial driver and MinGW demo because the latest changes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@942 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/main.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index c2ac24868..68dc4eb06 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -83,7 +83,7 @@ static bool_t GetLineFDD(FullDuplexDriver *sd, char *line, int size) { char *p = line; while (TRUE) { - short c = chIQGet(&sd->sd_iqueue); + short c = chIQGet(&sd->d2.iqueue); if (c < 0) return TRUE; if (c == 4) { @@ -162,8 +162,10 @@ static msg_t ShellThread(void *arg) { Thread *tp; WORKING_AREA(tarea, 2048); - chIQReset(&sd->sd_iqueue); - chOQReset(&sd->sd_oqueue); + chSysLock(); + chIQResetI(&sd->d2.iqueue); + chOQResetI(&sd->d2.oqueue); + chSysUnlock(); PrintLineFDD(sd, "ChibiOS/RT Command Shell\r\n\n"); while (TRUE) { PrintLineFDD(sd, "ch> "); @@ -241,8 +243,11 @@ static void COM1Handler(eventid_t id) { chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); chThdResume(s1); } - if ((flags & SD_DISCONNECTED) && (s1 != NULL)) - chIQReset(&COM1.sd_iqueue); + if ((flags & SD_DISCONNECTED) && (s1 != NULL)) { + chSysLock(); + chIQResetI(&COM1.d2.iqueue); + chSysUnlock(); + } } static WORKING_AREA(s2area, 4096); @@ -264,8 +269,11 @@ static void COM2Handler(eventid_t id) { chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); chThdResume(s2); } - if ((flags & SD_DISCONNECTED) && (s2 != NULL)) - chIQReset(&COM2.sd_iqueue); + if ((flags & SD_DISCONNECTED) && (s2 != NULL)) { + chSysLock(); + chIQResetI(&COM2.d2.iqueue); + chSysUnlock(); + } } static evhandler_t fhandlers[2] = { @@ -288,13 +296,13 @@ int main(void) { cprint("Console service started on COM1, COM2\n"); cprint(" - Listening for connections on COM1\n"); chFDDGetAndClearFlags(&COM1); - chEvtRegister(&COM1.sd_sevent, &c1fel, 0); + chEvtRegister(&COM1.d2.sevent, &c1fel, 0); cprint(" - Listening for connections on COM2\n"); chFDDGetAndClearFlags(&COM2); - chEvtRegister(&COM2.sd_sevent, &c2fel, 1); + chEvtRegister(&COM2.d2.sevent, &c2fel, 1); while (!chThdShouldTerminate()) chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); - chEvtUnregister(&COM2.sd_sevent, &c2fel); // Never invoked but this is an example... - chEvtUnregister(&COM1.sd_sevent, &c1fel); // Never invoked but this is an example... + chEvtUnregister(&COM2.d2.sevent, &c2fel); // Never invoked but this is an example... + chEvtUnregister(&COM1.d2.sevent, &c1fel); // Never invoked but this is an example... return 0; } -- cgit v1.2.3 From 7506cef74c79741c57cf9575ac8b3b400c50bf41 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 9 May 2009 15:44:17 +0000 Subject: Made CH_DBG_THREADS_PROFILING default to TRUE in all demos because the changes to the function test_cpu_pulse(). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@961 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 2 +- demos/ARM7-LPC214x-G++/chconf.h | 2 +- demos/ARM7-LPC214x-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F103-GCC/chconf.h | 2 +- demos/AVR-AT90CANx-GCC/chconf.h | 2 +- demos/AVR-ATmega128-GCC/chconf.h | 2 +- demos/MSP430-MSP430x1611-GCC/chconf.h | 2 +- demos/Win32-MinGW/chconf.h | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 67f096a8c..a72b427e4 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index f06a537b2..658842338 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index f06a537b2..658842338 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index f06a537b2..658842338 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index f06a537b2..658842338 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 9c00191cc..b4cccc474 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 9c00191cc..b4cccc474 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 616e39ac6..9ffe4401c 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index b11bff238..3712d1e6f 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -345,7 +345,7 @@ * counts the system ticks occurred while executing the thread. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE +#define CH_DBG_THREADS_PROFILING TRUE #endif /*===========================================================================*/ -- cgit v1.2.3 From a6feec221cd3050e0f2d56950abd39677790d79f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 9 May 2009 16:05:41 +0000 Subject: Removed the CH_USE_SEMAPHORES_TIMEOUT configuration option. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@962 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 10 ---------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 10 ---------- demos/ARM7-LPC214x-G++/chconf.h | 10 ---------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 10 ---------- demos/ARM7-LPC214x-GCC/chconf.h | 10 ---------- demos/ARMCM3-STM32F103-GCC/chconf.h | 10 ---------- demos/AVR-AT90CANx-GCC/chconf.h | 10 ---------- demos/AVR-ATmega128-GCC/chconf.h | 10 ---------- demos/MSP430-MSP430x1611-GCC/chconf.h | 10 ---------- demos/Win32-MinGW/chconf.h | 10 ---------- 10 files changed, 100 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index a72b427e4..fd9c18d69 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 658842338..8e6eda189 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 658842338..8e6eda189 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 130ef5967..42baa1f3d 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW FALSE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT FALSE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 658842338..8e6eda189 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 658842338..8e6eda189 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index b4cccc474..717a0ce09 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index b4cccc474..717a0ce09 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 9ffe4401c..14e6004c9 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 3712d1e6f..53ee70cc1 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -153,16 +153,6 @@ #define CH_USE_SEMSW TRUE #endif -/** - * If specified then the Semaphores with timeout APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_TIMEOUT TRUE -#endif - /** * If specified then the Mutexes APIs are included in the kernel. * @note The default is @p TRUE. -- cgit v1.2.3 From 957da89e719258a6cbb4b7c655baeef976d28cb9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 May 2009 09:03:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@983 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/Makefile | 136 ++++++++++++++ demos/GNU-Linux-GCC/chconf.h | 393 +++++++++++++++++++++++++++++++++++++++++ demos/GNU-Linux-GCC/chcore.c | 107 +++++++++++ demos/GNU-Linux-GCC/chcore.h | 209 ++++++++++++++++++++++ demos/GNU-Linux-GCC/chtypes.h | 47 +++++ demos/GNU-Linux-GCC/main.c | 53 ++++++ demos/GNU-Linux-GCC/readme.txt | 33 ++++ 7 files changed, 978 insertions(+) create mode 100644 demos/GNU-Linux-GCC/Makefile create mode 100644 demos/GNU-Linux-GCC/chconf.h create mode 100644 demos/GNU-Linux-GCC/chcore.c create mode 100644 demos/GNU-Linux-GCC/chcore.h create mode 100644 demos/GNU-Linux-GCC/chtypes.h create mode 100644 demos/GNU-Linux-GCC/main.c create mode 100644 demos/GNU-Linux-GCC/readme.txt (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/Makefile b/demos/GNU-Linux-GCC/Makefile new file mode 100644 index 000000000..988cf0364 --- /dev/null +++ b/demos/GNU-Linux-GCC/Makefile @@ -0,0 +1,136 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = i686-pc-cygwin- +CC = $(TRGT)gcc-4 +AS = $(TRGT)gcc-4 -x assembler-with-cpp + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# Imported source files +include ../../src/kernel.mk +include ../../test/test.mk + +# List C source files here +SRC = chcore.c main.c \ + ${KERNSRC} \ + ${TESTSRC} + +# List ASM source files here +ASRC = + +# List all user directories here +UINCDIR = ../../src/include + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -ggdb -O2 -fomit-frame-pointer + +# +# End of user defines +############################################################################################## + + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT).exe + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +%exe: $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +gcov: + -mkdir gcov + $(COV) -u $(subst /,\,$(SRC)) + -mv *.gcov ./gcov + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT).exe + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/GNU-Linux-GCC/chconf.h b/demos/GNU-Linux-GCC/chconf.h new file mode 100644 index 000000000..273ba602f --- /dev/null +++ b/demos/GNU-Linux-GCC/chconf.h @@ -0,0 +1,393 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file src/templates/chconf.h + * @brief Configuration file template. + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0x20000 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the full duplex serial driver APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_QUEUES. + */ +#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) +#define CH_USE_SERIAL_FULLDUPLEX TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * Debug option, if enabled the context switch circular trace buffer is + * activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add thread custom fields here.*/ \ + /* The thread termination \p EventSource.*/ \ + EventSource p_exitesource; \ +}; +#endif + +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add thread initialization code here.*/ \ + chEvtInit(&tp->p_exitesource); \ +} +#endif + +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ + chEvtBroadcastI(&currp->p_exitesource); \ +} +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/GNU-Linux-GCC/chcore.c b/demos/GNU-Linux-GCC/chcore.c new file mode 100644 index 000000000..b9aa187ab --- /dev/null +++ b/demos/GNU-Linux-GCC/chcore.c @@ -0,0 +1,107 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include +#include + +/** + * @addtogroup LINUXSIM_CORE + * @{ + */ + +#include + +static struct itimerval tempo; +static bool_t pending = FALSE; + +void timer(int numSignal) { + + pending = TRUE; +} + +/* + * Simulated HW initialization. + */ +void _init_core(void) { + + signal(SIGALRM, timer); + tempo.it_value.tv_sec = 0; + tempo.it_value.tv_usec = 10000; + tempo.it_interval.tv_sec = 0; + tempo.it_interval.tv_usec = 10000; + setitimer(ITIMER_REAL, &tempo, NULL); +} + +/* + * Interrupt simulation. + */ +void ChkIntSources(void) { + + if (pending) { + chSysTimerHandlerI(); + pending = FALSE; + } + + if (chSchRescRequiredI()) + chSchDoRescheduleI(); +} + +/** + * Performs a context switch between two threads. + * @param otp the thread to be switched out + * @param ntp the thread to be switched in + */ +__attribute__((used)) +static void __dummy(Thread *otp, Thread *ntp) { + asm volatile (".globl @port_switch@8 \n\t" \ + "@port_switch@8: \n\t" \ + "push %ebp \n\t" \ + "push %esi \n\t" \ + "push %edi \n\t" \ + "push %ebx \n\t" \ + "movl %esp, 16(%ecx) \n\t" \ + "movl 16(%edx), %esp \n\t" \ + "pop %ebx \n\t" \ + "pop %edi \n\t" \ + "pop %esi \n\t" \ + "pop %ebp \n\t" \ + "ret"); +} + +/** + * Halts the system. In this implementation it just exits the simulation. + */ +__attribute__((fastcall)) +void port_halt(void) { + + exit(2); +} + +/** + * Threads return point, it just invokes @p chThdExit(). + */ +void threadexit(void) { + + asm volatile ("push %eax \n\t" \ + "call _chThdExit"); +} + +/** @} */ diff --git a/demos/GNU-Linux-GCC/chcore.h b/demos/GNU-Linux-GCC/chcore.h new file mode 100644 index 000000000..fca0a03ea --- /dev/null +++ b/demos/GNU-Linux-GCC/chcore.h @@ -0,0 +1,209 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup WIN32SIM_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/** + * Macro defining the a simulated architecture into Win32. + */ +#define CH_ARCHITECTURE_WIN32SIM + +/** + * Name of the implemented architecture. + */ +#define CH_ARCHITECTURE_NAME "WIN32 Simulator" + +/** + * 32 bit stack alignment. + */ +typedef uint32_t stkalign_t; + +/** + * Generic x86 register. + */ +typedef void *regx86; + +/** + * Interrupt saved context. + * This structure represents the stack frame saved during a preemption-capable + * interrupt handler. + */ +struct extctx { +}; + +/** + * System saved context. + * @note In this demo the floating point registers are not saved. + */ +struct intctx { + regx86 ebx; + regx86 edi; + regx86 esi; + regx86 ebp; + regx86 eip; +}; + +/** + * Platform dependent part of the @p Thread structure. + * This structure usually contains just the saved stack pointer defined as a + * pointer to a @p intctx structure. + */ +struct context { + struct intctx volatile *esp; +}; + +#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) + +/** + * Platform dependent part of the @p chThdInit() API. + * This code usually setup the context switching frame represented by a + * @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + uint8_t *esp = (uint8_t *)workspace + wsize; \ + APUSH(esp, arg); \ + APUSH(esp, threadexit); \ + esp -= sizeof(struct intctx); \ + ((struct intctx *)esp)->eip = pf; \ + ((struct intctx *)esp)->ebx = 0; \ + ((struct intctx *)esp)->edi = 0; \ + ((struct intctx *)esp)->esi = 0; \ + ((struct intctx *)esp)->ebp = 0; \ + tp->p_ctx.esp = (struct intctx *)esp; \ +} + +/** + * Stack size for the system idle thread. + */ +#ifndef IDLE_THREAD_STACK_SIZE +#define IDLE_THREAD_STACK_SIZE 256 +#endif + +/** + * Per-thread stack overhead for interrupts servicing, it is used in the + * calculation of the correct working area size. + */ +#ifndef INT_REQUIRED_STACK +#define INT_REQUIRED_STACK 0x40000 +#endif + +/** + * Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + + /** + * Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(void *) * 2 + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (INT_REQUIRED_STACK)) + +/** + * Macro used to allocate a thread working area aligned as both position and + * size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; + +/** + * IRQ prologue code, inserted at the start of all IRQ handlers enabled to + * invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to + * invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() + +/** + * IRQ handler function declaration. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * Simulator initialization. + */ +#define port_init() _init_core() + +/** + * Does nothing in this simulator. + */ +#define port_lock() + +/** + * Does nothing in this simulator. + */ +#define port_unlock() + +/** + * Does nothing in this simulator. + */ +#define port_lock_from_isr() + +/** + * Does nothing in this simulator. + */ +#define port_unlock_from_isr() + +/** + * Does nothing in this simulator. + */ +#define port_disable() + +/** + * Does nothing in this simulator. + */ +#define port_suspend() + +/** + * Does nothing in this simulator. + */ +#define port_enable() + +/** + * In the simulator this does a polling pass on the simulated interrupt + * sources. + */ +#define port_wait_for_interrupt() ChkIntSources() + +#ifdef __cplusplus +extern "C" { +#endif + __attribute__((fastcall)) void port_switch(Thread *otp, Thread *ntp); + __attribute__((fastcall)) void port_halt(void); + void _init_core(void); + void ChkIntSources(void); + void threadexit(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/demos/GNU-Linux-GCC/chtypes.h b/demos/GNU-Linux-GCC/chtypes.h new file mode 100644 index 000000000..354da269e --- /dev/null +++ b/demos/GNU-Linux-GCC/chtypes.h @@ -0,0 +1,47 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#if !defined(_STDINT_H) && !defined(__STDINT_H_) +#include +#endif + +typedef int8_t bool_t; +typedef uint8_t tmode_t; +typedef uint8_t tstate_t; +typedef uint32_t tprio_t; +typedef int32_t msg_t; +typedef int32_t eventid_t; +typedef uint32_t eventmask_t; +typedef uint32_t systime_t; +typedef int32_t cnt_t; + +#define INLINE inline +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c new file mode 100644 index 000000000..15cb358fd --- /dev/null +++ b/demos/GNU-Linux-GCC/main.c @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include + +static WORKING_AREA(waThread1, 2048); +static msg_t Thread1(void *arg) { + + while (TRUE) { + chThdSleepMilliseconds(1000); + printf("Hello World!"); + } + return 0; +} + +/*------------------------------------------------------------------------* + * Simulator main, start here your threads, examples inside. * + *------------------------------------------------------------------------*/ +int main(void) { + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); + + /* + * Starting threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + while (TRUE) + chThdSleepSeconds(1); + + return 0; +} diff --git a/demos/GNU-Linux-GCC/readme.txt b/demos/GNU-Linux-GCC/readme.txt new file mode 100644 index 000000000..48bb35048 --- /dev/null +++ b/demos/GNU-Linux-GCC/readme.txt @@ -0,0 +1,33 @@ +***************************************************************************** +** ChibiOS/RT port for x86 into a Win32 process ** +***************************************************************************** + +** TARGET ** + +The demo runs under Linux as an application program. The serial I/O is +simulated over TCP/IP sockets. + +** The Demo ** + +The demo listens on the two serial ports, when a connection is detected a +thread is started that serves a small command shell. +The demo shows how create/terminate threads at runtime, how listen to events, +how ho work with serial ports, how use the messages. +You can develop your ChibiOS/RT application using this demo as a simulator +then you can recompile it for a different architecture. +See demo.c for details. + +** Build Procedure ** + +Makefile. + +** Connect to the demo ** + +In order to connect to the demo a telnet client is required. A good choice +is PuTTY: + +http://www.putty.org/ + +Host Name: 127.0.0.1 +Port: 29001 and/or 29002 +Connection Type: Raw -- cgit v1.2.3 From 3d64c337cb92683e21325df054da024732bd7199 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 May 2009 10:36:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@984 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/Makefile | 12 ++++++------ demos/GNU-Linux-GCC/chcore.c | 9 +++++---- demos/GNU-Linux-GCC/chcore.h | 2 +- demos/GNU-Linux-GCC/main.c | 2 +- 4 files changed, 13 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/Makefile b/demos/GNU-Linux-GCC/Makefile index 988cf0364..5483d4448 100644 --- a/demos/GNU-Linux-GCC/Makefile +++ b/demos/GNU-Linux-GCC/Makefile @@ -16,9 +16,9 @@ # Start of default section # -TRGT = i686-pc-cygwin- -CC = $(TRGT)gcc-4 -AS = $(TRGT)gcc-4 -x assembler-with-cpp +TRGT = +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp # List all default C defines here, like -D_DEBUG=1 DDEFS = @@ -102,7 +102,7 @@ CPFLAGS += -MD -MP -MF .dep/$(@F).d # makefile rules # -all: $(OBJS) $(PROJECT).exe +all: $(OBJS) $(PROJECT) %o : %c $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ @@ -110,7 +110,7 @@ all: $(OBJS) $(PROJECT).exe %o : %s $(AS) -c $(ASFLAGS) $< -o $@ -%exe: $(OBJS) +$(PROJECT): $(OBJS) $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ gcov: @@ -120,7 +120,7 @@ gcov: clean: -rm -f $(OBJS) - -rm -f $(PROJECT).exe + -rm -f $(PROJECT) -rm -f $(PROJECT).map -rm -f $(SRC:.c=.c.bak) -rm -f $(SRC:.c=.lst) diff --git a/demos/GNU-Linux-GCC/chcore.c b/demos/GNU-Linux-GCC/chcore.c index b9aa187ab..e75776e95 100644 --- a/demos/GNU-Linux-GCC/chcore.c +++ b/demos/GNU-Linux-GCC/chcore.c @@ -21,6 +21,7 @@ #include #include #include +#include /** * @addtogroup LINUXSIM_CORE @@ -34,7 +35,7 @@ static bool_t pending = FALSE; void timer(int numSignal) { - pending = TRUE; + pending = TRUE; } /* @@ -71,8 +72,8 @@ void ChkIntSources(void) { */ __attribute__((used)) static void __dummy(Thread *otp, Thread *ntp) { - asm volatile (".globl @port_switch@8 \n\t" \ - "@port_switch@8: \n\t" \ + asm volatile (".globl port_switch \n\t" \ + "port_switch: \n\t" \ "push %ebp \n\t" \ "push %esi \n\t" \ "push %edi \n\t" \ @@ -101,7 +102,7 @@ void port_halt(void) { void threadexit(void) { asm volatile ("push %eax \n\t" \ - "call _chThdExit"); + "call chThdExit"); } /** @} */ diff --git a/demos/GNU-Linux-GCC/chcore.h b/demos/GNU-Linux-GCC/chcore.h index fca0a03ea..48a052513 100644 --- a/demos/GNU-Linux-GCC/chcore.h +++ b/demos/GNU-Linux-GCC/chcore.h @@ -106,7 +106,7 @@ struct context { * calculation of the correct working area size. */ #ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 0x40000 +#define INT_REQUIRED_STACK 0x8000 #endif /** diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c index 15cb358fd..8d0d25879 100644 --- a/demos/GNU-Linux-GCC/main.c +++ b/demos/GNU-Linux-GCC/main.c @@ -26,7 +26,7 @@ static msg_t Thread1(void *arg) { while (TRUE) { chThdSleepMilliseconds(1000); - printf("Hello World!"); + printf("-\n"); } return 0; } -- cgit v1.2.3 From 9000e56245a5192a6966dd7e61008f81d9636f6f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 24 May 2009 07:23:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@986 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/readme.txt | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/readme.txt b/demos/GNU-Linux-GCC/readme.txt index 48bb35048..601358952 100644 --- a/demos/GNU-Linux-GCC/readme.txt +++ b/demos/GNU-Linux-GCC/readme.txt @@ -1,33 +1,15 @@ ***************************************************************************** -** ChibiOS/RT port for x86 into a Win32 process ** +** ChibiOS/RT port for x86 into a Linux process ** ***************************************************************************** ** TARGET ** -The demo runs under Linux as an application program. The serial I/O is -simulated over TCP/IP sockets. +The demo runs under Linux as an application program. ** The Demo ** -The demo listens on the two serial ports, when a connection is detected a -thread is started that serves a small command shell. -The demo shows how create/terminate threads at runtime, how listen to events, -how ho work with serial ports, how use the messages. -You can develop your ChibiOS/RT application using this demo as a simulator -then you can recompile it for a different architecture. -See demo.c for details. +The demo just creates a thread. It is not complete yet. ** Build Procedure ** Makefile. - -** Connect to the demo ** - -In order to connect to the demo a telnet client is required. A good choice -is PuTTY: - -http://www.putty.org/ - -Host Name: 127.0.0.1 -Port: 29001 and/or 29002 -Connection Type: Raw -- cgit v1.2.3 From d6eb57b8ea6c73a694cff33ded801af9e25ecff7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 24 May 2009 13:38:16 +0000 Subject: Fixed bugs 2796065, 2796069 and 2796081. Updated ARM test reports. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@987 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/ch.ld | 2 +- demos/ARM7-LPC214x-G++/main.cpp | 24 +++++++++++++++++++++--- 2 files changed, 22 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index 2bbea7477..a79694e7b 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0100; +__sys_stack_size__ = 0x0800; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 2f89d5dcf..647dee8a3 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -80,7 +80,7 @@ static const seqop_t LED3_sequence[] = * Any sequencer is just an instance of this class, all the details are * totally encapsulated and hidden to the application level. */ -class SequencerThread : EnhancedThread<128> { +class SequencerThread : public EnhancedThread<128> { private: const seqop_t *base, *curr; // Thread local variables. @@ -114,13 +114,31 @@ public: } }; +/* + * Tester thread class. This thread executes the test suite. + */ +class TesterThread : public EnhancedThread<128> { + +protected: + virtual msg_t Main(void) { + + return TestThread(&COM1); + } + +public: + TesterThread(void) : EnhancedThread<128>("tester") { + } +}; + /* * Executed as an event handler at 500mS intervals. */ static void TimerHandler(eventid_t id) { - if (!(IO0PIN & 0x00018000)) // Both buttons - TestThread(&COM1); + if (!(IO0PIN & 0x00018000)) { // Both buttons + TesterThread tester; + tester.Wait(); + }; } /* -- cgit v1.2.3 From c95d2b04d53e87a508ec502adc0f907fdd6de631 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 24 May 2009 13:51:52 +0000 Subject: Increased default main stack size for all the ARMx demos. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@988 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/ch.ld | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld | 2 +- demos/ARM7-LPC214x-GCC-minimal/ch.ld | 2 +- demos/ARM7-LPC214x-GCC/ch.ld | 2 +- demos/ARMCM3-STM32F103-GCC/ch.ld | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 89a2c2f2b..643453cd8 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0100; +__sys_stack_size__ = 0x0400; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld index 89a2c2f2b..643453cd8 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0100; +__sys_stack_size__ = 0x0400; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld index 2bbea7477..45bde5dea 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0100; +__sys_stack_size__ = 0x0400; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index 2bbea7477..45bde5dea 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0100; +__sys_stack_size__ = 0x0400; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index a68d88396..05fac9c8f 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -20,7 +20,7 @@ /* * ST32F103 memory setup. */ -__main_stack_size__ = 0x0200; +__main_stack_size__ = 0x0400; __process_stack_size__ = 0x0100; __stacks_total_size__ = __main_stack_size__ + __process_stack_size__; -- cgit v1.2.3 From c0bfa2bcd671d1c1b1f262eb95e51ce091463d8f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 30 May 2009 14:20:55 +0000 Subject: Fixed STM32 demo stack size. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@993 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/ch.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index 05fac9c8f..90a0093fe 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -20,8 +20,8 @@ /* * ST32F103 memory setup. */ -__main_stack_size__ = 0x0400; -__process_stack_size__ = 0x0100; +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0400; __stacks_total_size__ = __main_stack_size__ + __process_stack_size__; MEMORY -- cgit v1.2.3 From 8ada44e092e20e825b78c3d25ee016861cf886a9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Jun 2009 09:33:11 +0000 Subject: Modified the STM32 demo to use the new I/O port driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1010 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 12 ++++++------ demos/ARMCM3-STM32F103-GCC/main.c | 7 ++++--- 2 files changed, 10 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 680668cc2..ef1ecbdaf 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -123,13 +123,13 @@ /* * IO pins assignments. */ -#define GPIOA_BUTTON (1 << 0) +#define GPIOA_BUTTON IOPORT_BIT(0) -#define GPIOC_MMCWP (1 << 6) -#define GPIOC_MMCCP (1 << 7) -#define GPIOC_CANCNTL (1 << 10) -#define GPIOC_DISC (1 << 11) -#define GPIOC_LED (1 << 12) +#define GPIOC_MMCWP IOPORT_BIT(6) +#define GPIOC_MMCCP IOPORT_BIT(7) +#define GPIOC_CANCNTL IOPORT_BIT(10) +#define GPIOC_DISC IOPORT_BIT(11) +#define GPIOC_LED IOPORT_BIT(12) /* * All inputs with pullups unless otherwise specified. diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index ec59c4ffd..01e4eaab5 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -21,6 +21,7 @@ #include #include "board.h" +#include "ioports.h" #include "stm32_serial.h" /* @@ -30,9 +31,9 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - GPIOC->BRR = GPIOC_LED; + chPortClear(IOPORT_C, GPIOC_LED); chThdSleepMilliseconds(500); - GPIOC->BSRR = GPIOC_LED; + chPortSet(IOPORT_C, GPIOC_LED); chThdSleepMilliseconds(500); } return 0; @@ -54,7 +55,7 @@ int main(int argc, char **argv) { * sleeping in a loop and check the button state. */ while (TRUE) { - if (GPIOA->IDR & GPIOA_BUTTON) + if (chPortRead(IOPORT_A) & GPIOA_BUTTON) TestThread(&COM2); chThdSleepMilliseconds(500); } -- cgit v1.2.3 From 26ba1c43bbc3202354525a8e6c573d2a9f34fc50 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Jun 2009 09:38:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1012 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 7 +++++++ demos/ARMCM3-STM32F103-GCC/main.c | 1 - 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index ef1ecbdaf..d2aaa19f7 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -32,6 +32,13 @@ #define FALSE 0 #define TRUE (!FALSE) +/* + * This module requires the port driver. + */ +#ifndef _IOPORTS_LLD_H_ +#include "ioports.h" +#endif + #define BOARD_OLIMEX_STM32_P103 /* diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 01e4eaab5..81a9af702 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -21,7 +21,6 @@ #include #include "board.h" -#include "ioports.h" #include "stm32_serial.h" /* -- cgit v1.2.3 From 10ff25a6d35e23728ebb5f42788975452d8978a4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Jun 2009 09:54:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1013 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index d2aaa19f7..236b4787b 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -24,13 +24,13 @@ * Tricks required to make the TRUE/FALSE declaration inside the library * compatible. */ +#ifndef __STM32F10x_MAP_H #undef FALSE #undef TRUE -#ifndef __STM32F10x_MAP_H #include "stm32f10x_map.h" -#endif #define FALSE 0 #define TRUE (!FALSE) +#endif /* * This module requires the port driver. -- cgit v1.2.3 From 8020fc3d67244318840a337811f2f8a33185603a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Jun 2009 10:42:49 +0000 Subject: Added initialization function to the I/O port low level driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1014 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index d3e776d1a..7ce9248cd 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -61,7 +61,7 @@ void hwinit0(void) { /* * I/O ports initialization as specified in board.h. */ - RCC->APB2ENR = 0x0000003D; // Ports A-D enabled, AFIO enabled. + ioport_init(); GPIOA->CRL = VAL_GPIOACRL; GPIOA->CRH = VAL_GPIOACRH; GPIOA->ODR = VAL_GPIOAODR; -- cgit v1.2.3 From 1aa2773ad03807e3d5c9822ea108bc2e280281db Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Jun 2009 10:59:32 +0000 Subject: STM32 initialization cleanup. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1015 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 7ce9248cd..2c73879f7 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -59,24 +59,23 @@ void hwinit0(void) { ; /* - * I/O ports initialization as specified in board.h. + * I/O ports initialization as specified in board.h. Note that being this + * a low level initialization routine it is OK to invoke directly the + * low level port functions. */ - ioport_init(); - GPIOA->CRL = VAL_GPIOACRL; - GPIOA->CRH = VAL_GPIOACRH; - GPIOA->ODR = VAL_GPIOAODR; - - GPIOB->CRL = VAL_GPIOBCRL; - GPIOB->CRH = VAL_GPIOBCRH; - GPIOB->ODR = VAL_GPIOBODR; - - GPIOC->CRL = VAL_GPIOCCRL; - GPIOC->CRH = VAL_GPIOCCRH; - GPIOC->ODR = VAL_GPIOCODR; - - GPIOD->CRL = VAL_GPIODCRL; - GPIOD->CRH = VAL_GPIODCRH; - GPIOD->ODR = VAL_GPIODODR; + ioport_init_lld(); + + ioport_stm32_setup_lld(IOPORT_A, VAL_GPIOACRH, VAL_GPIOACRL); + ioport_write_lld(IOPORT_A, VAL_GPIOAODR); + + ioport_stm32_setup_lld(IOPORT_B, VAL_GPIOBCRH, VAL_GPIOBCRL); + ioport_write_lld(IOPORT_B, VAL_GPIOBODR); + + ioport_stm32_setup_lld(IOPORT_C, VAL_GPIOCCRH, VAL_GPIOCCRL); + ioport_write_lld(IOPORT_C, VAL_GPIOCODR); + + ioport_stm32_setup_lld(IOPORT_D, VAL_GPIODCRH, VAL_GPIODCRL); + ioport_write_lld(IOPORT_D, VAL_GPIODODR); } /* -- cgit v1.2.3 From 2a7941ee58016ce7641ab8010aff5fe711e0bedc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Jun 2009 13:41:38 +0000 Subject: I/O port driver for LPC214x added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1016 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/board.c | 17 +++++++++-------- demos/ARM7-LPC214x-G++/board.h | 21 +++++++++++++++++++++ demos/ARM7-LPC214x-G++/main.cpp | 21 +++++++++++---------- demos/ARM7-LPC214x-GCC-minimal/board.c | 9 +++++---- demos/ARM7-LPC214x-GCC-minimal/board.h | 20 ++++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/main.c | 14 +++++++------- demos/ARM7-LPC214x-GCC/board.c | 9 +++++---- demos/ARM7-LPC214x-GCC/board.h | 21 +++++++++++++++++++++ demos/ARM7-LPC214x-GCC/main.c | 22 +++++++++++----------- demos/ARM7-LPC214x-GCC/mmcsd.c | 6 +++--- 10 files changed, 113 insertions(+), 47 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index dc0cfb4f9..f188372b3 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -19,10 +19,10 @@ #include -#include -#include -#include -//#include "lpc214x_ssp.h" +#include "lpc214x.h" +#include "vic.h" +#include "lpc214x_serial.h" +#include "lpc214x_ssp.h" #include "board.h" //#include "mmcsd.h" @@ -103,10 +103,11 @@ void hwinit0(void) { PINSEL0 = VAL_PINSEL0; PINSEL1 = VAL_PINSEL1; PINSEL2 = VAL_PINSEL2; - IO0DIR = VAL_FIO0DIR; - IO0SET = 0xFFFFFFFF; - IO1DIR = VAL_FIO1DIR; - IO1SET = 0xFFFFFFFF; + ioport_init_lld(); + ioport_lpc214x_set_direction_lld(IOPORT_A, VAL_FIO0DIR); + ioport_write_lld(IOPORT_A, 0xFFFFFFFF); + ioport_lpc214x_set_direction_lld(IOPORT_B, VAL_FIO1DIR); + ioport_write_lld(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-G++/board.h b/demos/ARM7-LPC214x-G++/board.h index c9d3f01b3..ee30559c8 100644 --- a/demos/ARM7-LPC214x-G++/board.h +++ b/demos/ARM7-LPC214x-G++/board.h @@ -20,6 +20,14 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#ifndef _LPC214X_H_ +#include "lpc214x.h" +#endif + +#ifndef _IOPORTS_LLD_H_ +#include "ioports.h" +#endif + #define BOARD_OLIMEX_LCP_P2148 /* @@ -61,4 +69,17 @@ #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 +#define PA_LED1 IOPORT_BIT(10) +#define PA_LED2 IOPORT_BIT(11) +#define PA_BUZZ1 IOPORT_BIT(12) +#define PA_BUZZ2 IOPORT_BIT(13) +#define PA_BSL IOPORT_BIT(14) +#define PA_BUTTON1 IOPORT_BIT(15) +#define PA_BUTTON2 IOPORT_BIT(16) +#define PA_SSEL1 IOPORT_BIT(20) +#define PA_LEDUSB IOPORT_BIT(31) + +#define PB_WP1 IOPORT_BIT(24) +#define PB_CP1 IOPORT_BIT(25) + #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 647dee8a3..1a50f5936 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -18,11 +18,12 @@ */ #include +#include #include #include -#include +#include #include using namespace chibios_rt; @@ -47,9 +48,9 @@ typedef struct { // Flashing sequence for LED1. static const seqop_t LED1_sequence[] = { - {BITCLEAR, 0x00000400}, + {BITCLEAR, PA_LED1}, {SLEEP, 200}, - {BITSET, 0x00000400}, + {BITSET, PA_LED1}, {SLEEP, 1800}, {GOTO, 0} }; @@ -58,9 +59,9 @@ static const seqop_t LED1_sequence[] = static const seqop_t LED2_sequence[] = { {SLEEP, 1000}, - {BITCLEAR, 0x00000800}, + {BITCLEAR, PA_LED2}, {SLEEP, 200}, - {BITSET, 0x00000800}, + {BITSET, PA_LED2}, {SLEEP, 1800}, {GOTO, 1} }; @@ -68,9 +69,9 @@ static const seqop_t LED2_sequence[] = // Flashing sequence for LED3. static const seqop_t LED3_sequence[] = { - {BITCLEAR, 0x80000000}, + {BITCLEAR, PA_LEDUSB}, {SLEEP, 200}, - {BITSET, 0x80000000}, + {BITSET, PA_LEDUSB}, {SLEEP, 300}, {GOTO, 0} }; @@ -97,10 +98,10 @@ protected: case STOP: return 0; case BITCLEAR: - IO0CLR = curr->value; + chPortClear(IOPORT_A, curr->value); break; case BITSET: - IO0SET = curr->value; + chPortSet(IOPORT_A, curr->value); break; } curr++; @@ -135,7 +136,7 @@ public: */ static void TimerHandler(eventid_t id) { - if (!(IO0PIN & 0x00018000)) { // Both buttons + if (!(chPortRead(IOPORT_A) & (PA_BUTTON1 | PA_BUTTON2))) { // Both buttons TesterThread tester; tester.Wait(); }; diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index 50f553fa3..a06b24291 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -103,10 +103,11 @@ void hwinit0(void) { PINSEL0 = VAL_PINSEL0; PINSEL1 = VAL_PINSEL1; PINSEL2 = VAL_PINSEL2; - IO0DIR = VAL_FIO0DIR; - IO0SET = 0xFFFFFFFF; - IO1DIR = VAL_FIO1DIR; - IO1SET = 0xFFFFFFFF; + ioport_init_lld(); + ioport_lpc214x_set_direction_lld(IOPORT_A, VAL_FIO0DIR); + ioport_write_lld(IOPORT_A, 0xFFFFFFFF); + ioport_lpc214x_set_direction_lld(IOPORT_B, VAL_FIO1DIR); + ioport_write_lld(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h index c9d3f01b3..3cdc2a9af 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.h +++ b/demos/ARM7-LPC214x-GCC-minimal/board.h @@ -20,6 +20,14 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#ifndef _LPC214X_H_ +#include "lpc214x.h" +#endif + +#ifndef _IOPORTS_LLD_H_ +#include "ioports.h" +#endif + #define BOARD_OLIMEX_LCP_P2148 /* @@ -61,4 +69,16 @@ #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 +#define PA_LED1 IOPORT_BIT(10) +#define PA_LED2 IOPORT_BIT(11) +#define PA_BUZZ1 IOPORT_BIT(12) +#define PA_BUZZ2 IOPORT_BIT(13) +#define PA_BSL IOPORT_BIT(14) +#define PA_BUTTON1 IOPORT_BIT(15) +#define PA_BUTTON2 IOPORT_BIT(16) +#define PA_SSEL1 IOPORT_BIT(20) +#define PA_WP1 IOPORT_BIT(24) +#define PA_CP1 IOPORT_BIT(25) +#define PA_LEDUSB IOPORT_BIT(31) + #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 59dc04158..60035ffb7 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -19,7 +19,7 @@ #include -#include "lpc214x.h" +#include "board.h" /* * Red LEDs blinker thread, times are in milliseconds. @@ -28,13 +28,13 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - IO0CLR = 0x00000800; + chPortClear(IOPORT_A, PA_LED2); chThdSleepMilliseconds(200); - IO0SET = 0x00000C00; + chPortSet(IOPORT_A, PA_LED1 | PA_LED2); chThdSleepMilliseconds(800); - IO0CLR = 0x00000400; + chPortClear(IOPORT_A, PA_LED1); chThdSleepMilliseconds(200); - IO0SET = 0x00000C00; + chPortSet(IOPORT_A, PA_LED1 | PA_LED2); chThdSleepMilliseconds(800); } return 0; @@ -47,9 +47,9 @@ static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { - IO0CLR = 0x80000000; + chPortClear(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(200); - IO0SET = 0x80000000; + chPortSet(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(300); } return 0; diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 0db657b29..e1bf9369f 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -103,10 +103,11 @@ void hwinit0(void) { PINSEL0 = VAL_PINSEL0; PINSEL1 = VAL_PINSEL1; PINSEL2 = VAL_PINSEL2; - IO0DIR = VAL_FIO0DIR; - IO0SET = 0xFFFFFFFF; - IO1DIR = VAL_FIO1DIR; - IO1SET = 0xFFFFFFFF; + ioport_init_lld(); + ioport_lpc214x_set_direction_lld(IOPORT_A, VAL_FIO0DIR); + ioport_write_lld(IOPORT_A, 0xFFFFFFFF); + ioport_lpc214x_set_direction_lld(IOPORT_B, VAL_FIO1DIR); + ioport_write_lld(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-GCC/board.h b/demos/ARM7-LPC214x-GCC/board.h index c9d3f01b3..ee30559c8 100644 --- a/demos/ARM7-LPC214x-GCC/board.h +++ b/demos/ARM7-LPC214x-GCC/board.h @@ -20,6 +20,14 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#ifndef _LPC214X_H_ +#include "lpc214x.h" +#endif + +#ifndef _IOPORTS_LLD_H_ +#include "ioports.h" +#endif + #define BOARD_OLIMEX_LCP_P2148 /* @@ -61,4 +69,17 @@ #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 +#define PA_LED1 IOPORT_BIT(10) +#define PA_LED2 IOPORT_BIT(11) +#define PA_BUZZ1 IOPORT_BIT(12) +#define PA_BUZZ2 IOPORT_BIT(13) +#define PA_BSL IOPORT_BIT(14) +#define PA_BUTTON1 IOPORT_BIT(15) +#define PA_BUTTON2 IOPORT_BIT(16) +#define PA_SSEL1 IOPORT_BIT(20) +#define PA_LEDUSB IOPORT_BIT(31) + +#define PB_WP1 IOPORT_BIT(24) +#define PB_CP1 IOPORT_BIT(25) + #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index c83d9a419..3eafdba61 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -20,7 +20,7 @@ #include #include -#include "lpc214x.h" +#include "board.h" #include "lpc214x_serial.h" #include "mmcsd.h" #include "buzzer.h" @@ -33,13 +33,13 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - IO0CLR = 0x00000800; + chPortClear(IOPORT_A, PA_LED2); chThdSleepMilliseconds(200); - IO0SET = 0x00000C00; + chPortSet(IOPORT_A, PA_LED1 | PA_LED2); chThdSleepMilliseconds(800); - IO0CLR = 0x00000400; + chPortClear(IOPORT_A, PA_LED1); chThdSleepMilliseconds(200); - IO0SET = 0x00000C00; + chPortSet(IOPORT_A, PA_LED1 | PA_LED2); chThdSleepMilliseconds(800); } return 0; @@ -52,9 +52,9 @@ static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { - IO0CLR = 0x80000000; + chPortClear(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(200); - IO0SET = 0x80000000; + chPortSet(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(300); } return 0; @@ -67,16 +67,16 @@ static WORKING_AREA(waTestThread, 128); */ static void TimerHandler(eventid_t id) { - if (!(IO0PIN & 0x00018000)) { // Both buttons + if (!(chPortRead(IOPORT_A) & (PA_BUTTON1 | PA_BUTTON2))) { Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), NORMALPRIO, TestThread, &COM1); chThdWait(tp); PlaySound(500, MS2ST(100)); } else { - if (!(IO0PIN & 0x00008000)) // Button 1 + if (!(chPortRead(IOPORT_A) & PA_BUTTON1)) PlaySound(1000, MS2ST(100)); - if (!(IO0PIN & 0x00010000)) { // Button 2 + if (!(chPortRead(IOPORT_A) & PA_BUTTON2)) { chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); PlaySound(2000, MS2ST(100)); } @@ -129,7 +129,7 @@ int main(int argc, char **argv) { * If a button is pressed during the reset then the blinking leds threads * are not started in order to make accurate benchmarks. */ - if ((IO0PIN & 0x00018000) == 0x00018000) { + if (chPortRead(IOPORT_A) && (PA_BUTTON1 | PA_BUTTON2) == (PA_BUTTON1 | PA_BUTTON2)) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); } diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 292b450d5..bff2967d9 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -19,7 +19,7 @@ #include -#include "lpc214x.h" +#include "board.h" #include "lpc214x_ssp.h" #include "mmcsd.h" @@ -42,7 +42,7 @@ void InitMMC(void) { void tmrfunc(void *par) { if (cnt) { - if (!(IO1PIN & (1 << 25))) { + if (!(chPortRead(IOPORT_B) & PB_CP1)) { if (!--cnt) chEvtBroadcastI(&MMCInsertEventSource); } @@ -50,7 +50,7 @@ void tmrfunc(void *par) { cnt = POLLING_INTERVAL; } else { - if (IO1PIN & (1 << 25)) { + if (chPortRead(IOPORT_B) & PB_CP1) { cnt = POLLING_INTERVAL; chEvtBroadcastI(&MMCRemoveEventSource); } -- cgit v1.2.3 From 4fc5b696fad6b10620dcd49149bf64b829e38f77 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 7 Jun 2009 10:27:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1019 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 23 +++++++++++------------ demos/ARMCM3-STM32F103-GCC/board.h | 21 ++++++--------------- demos/ARMCM3-STM32F103-GCC/main.c | 7 ++++--- 3 files changed, 21 insertions(+), 30 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 2c73879f7..52701992a 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -18,6 +18,7 @@ */ #include +#include #include #include "board.h" @@ -59,23 +60,21 @@ void hwinit0(void) { ; /* - * I/O ports initialization as specified in board.h. Note that being this - * a low level initialization routine it is OK to invoke directly the - * low level port functions. + * I/O ports initialization as specified in board.h. */ - ioport_init_lld(); + palInit(); - ioport_stm32_setup_lld(IOPORT_A, VAL_GPIOACRH, VAL_GPIOACRL); - ioport_write_lld(IOPORT_A, VAL_GPIOAODR); + pal_lld_stm32_setup(IOPORT_A, VAL_GPIOACRH, VAL_GPIOACRL); + palWritePort(IOPORT_A, VAL_GPIOAODR); - ioport_stm32_setup_lld(IOPORT_B, VAL_GPIOBCRH, VAL_GPIOBCRL); - ioport_write_lld(IOPORT_B, VAL_GPIOBODR); + pal_lld_stm32_setup(IOPORT_B, VAL_GPIOBCRH, VAL_GPIOBCRL); + palWritePort(IOPORT_B, VAL_GPIOBODR); - ioport_stm32_setup_lld(IOPORT_C, VAL_GPIOCCRH, VAL_GPIOCCRL); - ioport_write_lld(IOPORT_C, VAL_GPIOCODR); + pal_lld_stm32_setup(IOPORT_C, VAL_GPIOCCRH, VAL_GPIOCCRL); + palWritePort(IOPORT_C, VAL_GPIOCODR); - ioport_stm32_setup_lld(IOPORT_D, VAL_GPIODCRH, VAL_GPIODCRL); - ioport_write_lld(IOPORT_D, VAL_GPIODODR); + pal_lld_stm32_setup(IOPORT_D, VAL_GPIODCRH, VAL_GPIODCRL); + palWritePort(IOPORT_D, VAL_GPIODODR); } /* diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 236b4787b..250b2b2d2 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -32,15 +32,6 @@ #define TRUE (!FALSE) #endif -/* - * This module requires the port driver. - */ -#ifndef _IOPORTS_LLD_H_ -#include "ioports.h" -#endif - -#define BOARD_OLIMEX_STM32_P103 - /* * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. */ @@ -130,13 +121,13 @@ /* * IO pins assignments. */ -#define GPIOA_BUTTON IOPORT_BIT(0) +#define GPIOA_BUTTON 0 -#define GPIOC_MMCWP IOPORT_BIT(6) -#define GPIOC_MMCCP IOPORT_BIT(7) -#define GPIOC_CANCNTL IOPORT_BIT(10) -#define GPIOC_DISC IOPORT_BIT(11) -#define GPIOC_LED IOPORT_BIT(12) +#define GPIOC_MMCWP 6 +#define GPIOC_MMCCP 7 +#define GPIOC_CANCNTL 10 +#define GPIOC_DISC 11 +#define GPIOC_LED 12 /* * All inputs with pullups unless otherwise specified. diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 81a9af702..f89131d37 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -18,6 +18,7 @@ */ #include +#include #include #include "board.h" @@ -30,9 +31,9 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - chPortClear(IOPORT_C, GPIOC_LED); + palClearPad(IOPORT_C, GPIOC_LED); chThdSleepMilliseconds(500); - chPortSet(IOPORT_C, GPIOC_LED); + palSetPad(IOPORT_C, GPIOC_LED); chThdSleepMilliseconds(500); } return 0; @@ -54,7 +55,7 @@ int main(int argc, char **argv) { * sleeping in a loop and check the button state. */ while (TRUE) { - if (chPortRead(IOPORT_A) & GPIOA_BUTTON) + if (palReadPad(IOPORT_A, GPIOA_BUTTON)) TestThread(&COM2); chThdSleepMilliseconds(500); } -- cgit v1.2.3 From a5df28e309adbccff162d67cfb9f55c653c73f7b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 7 Jun 2009 15:44:03 +0000 Subject: Revised port abstraction layer (PAL), STM32 support adjusted. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1023 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 1 + demos/ARMCM3-STM32F103-GCC/main.c | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index eb957c072..0fa07c91a 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -66,6 +66,7 @@ CSRC = ../../ports/ARMCM3/chcore.c \ ../../ports/ARMCM3-STM32F103/stm32_serial.c \ ${KERNSRC} \ ${TESTSRC} \ + ../../src/lib/pal.c \ ../../src/lib/evtimer.c \ board.c main.c diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index f89131d37..f599c3e73 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -24,6 +24,8 @@ #include "board.h" #include "stm32_serial.h" +static IOBUS_DECL(LedBus, IOPORT_C, 1, GPIOC_LED); + /* * Red LEDs blinker thread, times are in milliseconds. */ @@ -35,6 +37,30 @@ static msg_t Thread1(void *arg) { chThdSleepMilliseconds(500); palSetPad(IOPORT_C, GPIOC_LED); chThdSleepMilliseconds(500); + palTogglePad(IOPORT_C, GPIOC_LED); + chThdSleepMilliseconds(500); + palTogglePad(IOPORT_C, GPIOC_LED); + chThdSleepMilliseconds(500); + palWritePad(IOPORT_C, GPIOC_LED, PAL_LOW); + chThdSleepMilliseconds(500); + palWritePad(IOPORT_C, GPIOC_LED, PAL_HIGH); + chThdSleepMilliseconds(500); + palWriteGroup(IOPORT_C, 1, GPIOC_LED, PAL_LOW); + chThdSleepMilliseconds(500); + palWriteGroup(IOPORT_C, 1, GPIOC_LED, PAL_HIGH); + chThdSleepMilliseconds(500); + palClearPort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); + chThdSleepMilliseconds(500); + palSetPort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); + chThdSleepMilliseconds(500); + palTogglePort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); + chThdSleepMilliseconds(500); + palTogglePort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); + chThdSleepMilliseconds(500); + palWriteBus(&LedBus, PAL_LOW); + chThdSleepMilliseconds(500); + palWriteBus(&LedBus, PAL_HIGH); + chThdSleepMilliseconds(500); } return 0; } -- cgit v1.2.3 From b2e6f6a6a5ee0af322472c151565be6cba0e1fa0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 7 Jun 2009 16:54:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1025 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/board.c | 11 ++++++----- demos/ARM7-LPC214x-GCC-minimal/board.h | 26 +++++++++++--------------- demos/ARM7-LPC214x-GCC-minimal/main.c | 13 +++++++------ 3 files changed, 24 insertions(+), 26 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index a06b24291..2e56028cc 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "lpc214x.h" #include "vic.h" @@ -103,11 +104,11 @@ void hwinit0(void) { PINSEL0 = VAL_PINSEL0; PINSEL1 = VAL_PINSEL1; PINSEL2 = VAL_PINSEL2; - ioport_init_lld(); - ioport_lpc214x_set_direction_lld(IOPORT_A, VAL_FIO0DIR); - ioport_write_lld(IOPORT_A, 0xFFFFFFFF); - ioport_lpc214x_set_direction_lld(IOPORT_B, VAL_FIO1DIR); - ioport_write_lld(IOPORT_B, 0xFFFFFFFF); + palInit(); + pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); + palWritePort(IOPORT_A, 0xFFFFFFFF); + pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); + palWritePort(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h index 3cdc2a9af..8cee52946 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.h +++ b/demos/ARM7-LPC214x-GCC-minimal/board.h @@ -24,10 +24,6 @@ #include "lpc214x.h" #endif -#ifndef _IOPORTS_LLD_H_ -#include "ioports.h" -#endif - #define BOARD_OLIMEX_LCP_P2148 /* @@ -69,16 +65,16 @@ #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 -#define PA_LED1 IOPORT_BIT(10) -#define PA_LED2 IOPORT_BIT(11) -#define PA_BUZZ1 IOPORT_BIT(12) -#define PA_BUZZ2 IOPORT_BIT(13) -#define PA_BSL IOPORT_BIT(14) -#define PA_BUTTON1 IOPORT_BIT(15) -#define PA_BUTTON2 IOPORT_BIT(16) -#define PA_SSEL1 IOPORT_BIT(20) -#define PA_WP1 IOPORT_BIT(24) -#define PA_CP1 IOPORT_BIT(25) -#define PA_LEDUSB IOPORT_BIT(31) +#define PA_LED1 10 +#define PA_LED2 11 +#define PA_BUZZ1 12 +#define PA_BUZZ2 13 +#define PA_BSL 14 +#define PA_BUTTON1 15 +#define PA_BUTTON2 16 +#define PA_SSEL1 20 +#define PA_WP1 24 +#define PA_CP1 25 +#define PA_LEDUSB 31 #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 60035ffb7..83d192b91 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" @@ -28,13 +29,13 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - chPortClear(IOPORT_A, PA_LED2); + palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(200); - chPortSet(IOPORT_A, PA_LED1 | PA_LED2); + palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); - chPortClear(IOPORT_A, PA_LED1); + palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED1)); chThdSleepMilliseconds(200); - chPortSet(IOPORT_A, PA_LED1 | PA_LED2); + palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); } return 0; @@ -47,9 +48,9 @@ static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { - chPortClear(IOPORT_A, PA_LEDUSB); + palClearPad(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(200); - chPortSet(IOPORT_A, PA_LEDUSB); + palSetPad(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(300); } return 0; -- cgit v1.2.3 From be1e6b03d4a49b6fa16c3368435089f8706fb566 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 7 Jun 2009 17:53:23 +0000 Subject: Adjusted PAL support for LPC214x. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1026 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/board.c | 11 ++++++----- demos/ARM7-LPC214x-G++/board.h | 26 +++++++++++--------------- demos/ARM7-LPC214x-G++/main.cpp | 22 ++++++++++++---------- demos/ARM7-LPC214x-GCC-minimal/board.h | 5 +++-- demos/ARM7-LPC214x-GCC/Makefile | 1 + demos/ARM7-LPC214x-GCC/board.c | 11 ++++++----- demos/ARM7-LPC214x-GCC/board.h | 26 +++++++++++--------------- demos/ARM7-LPC214x-GCC/main.c | 23 +++++++++++++---------- demos/ARM7-LPC214x-GCC/mmcsd.c | 5 +++-- 9 files changed, 66 insertions(+), 64 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index f188372b3..c3c39a5a9 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "lpc214x.h" #include "vic.h" @@ -103,11 +104,11 @@ void hwinit0(void) { PINSEL0 = VAL_PINSEL0; PINSEL1 = VAL_PINSEL1; PINSEL2 = VAL_PINSEL2; - ioport_init_lld(); - ioport_lpc214x_set_direction_lld(IOPORT_A, VAL_FIO0DIR); - ioport_write_lld(IOPORT_A, 0xFFFFFFFF); - ioport_lpc214x_set_direction_lld(IOPORT_B, VAL_FIO1DIR); - ioport_write_lld(IOPORT_B, 0xFFFFFFFF); + palInit(); + pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); + palWritePort(IOPORT_A, 0xFFFFFFFF); + pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); + palWritePort(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-G++/board.h b/demos/ARM7-LPC214x-G++/board.h index ee30559c8..fee4baa61 100644 --- a/demos/ARM7-LPC214x-G++/board.h +++ b/demos/ARM7-LPC214x-G++/board.h @@ -24,10 +24,6 @@ #include "lpc214x.h" #endif -#ifndef _IOPORTS_LLD_H_ -#include "ioports.h" -#endif - #define BOARD_OLIMEX_LCP_P2148 /* @@ -69,17 +65,17 @@ #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 -#define PA_LED1 IOPORT_BIT(10) -#define PA_LED2 IOPORT_BIT(11) -#define PA_BUZZ1 IOPORT_BIT(12) -#define PA_BUZZ2 IOPORT_BIT(13) -#define PA_BSL IOPORT_BIT(14) -#define PA_BUTTON1 IOPORT_BIT(15) -#define PA_BUTTON2 IOPORT_BIT(16) -#define PA_SSEL1 IOPORT_BIT(20) -#define PA_LEDUSB IOPORT_BIT(31) +#define PA_LED1 10 +#define PA_LED2 11 +#define PA_BUZZ1 12 +#define PA_BUZZ2 13 +#define PA_BSL 14 +#define PA_BUTTON1 15 +#define PA_BUTTON2 16 +#define PA_SSEL1 20 +#define PA_LEDUSB 31 -#define PB_WP1 IOPORT_BIT(24) -#define PB_CP1 IOPORT_BIT(25) +#define PB_WP1 24 +#define PB_CP1 25 #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 1a50f5936..683c2675d 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -18,7 +18,7 @@ */ #include -#include +#include #include #include @@ -26,6 +26,8 @@ #include #include +#define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) + using namespace chibios_rt; /* @@ -48,9 +50,9 @@ typedef struct { // Flashing sequence for LED1. static const seqop_t LED1_sequence[] = { - {BITCLEAR, PA_LED1}, + {BITCLEAR, PAL_PORT_BIT(PA_LED1)}, {SLEEP, 200}, - {BITSET, PA_LED1}, + {BITSET, PAL_PORT_BIT(PA_LED1)}, {SLEEP, 1800}, {GOTO, 0} }; @@ -59,9 +61,9 @@ static const seqop_t LED1_sequence[] = static const seqop_t LED2_sequence[] = { {SLEEP, 1000}, - {BITCLEAR, PA_LED2}, + {BITCLEAR, PAL_PORT_BIT(PA_LED2)}, {SLEEP, 200}, - {BITSET, PA_LED2}, + {BITSET, PAL_PORT_BIT(PA_LED2)}, {SLEEP, 1800}, {GOTO, 1} }; @@ -69,9 +71,9 @@ static const seqop_t LED2_sequence[] = // Flashing sequence for LED3. static const seqop_t LED3_sequence[] = { - {BITCLEAR, PA_LEDUSB}, + {BITCLEAR, PAL_PORT_BIT(PA_LEDUSB)}, {SLEEP, 200}, - {BITSET, PA_LEDUSB}, + {BITSET, PAL_PORT_BIT(PA_LEDUSB)}, {SLEEP, 300}, {GOTO, 0} }; @@ -98,10 +100,10 @@ protected: case STOP: return 0; case BITCLEAR: - chPortClear(IOPORT_A, curr->value); + palClearPort(IOPORT_A, curr->value); break; case BITSET: - chPortSet(IOPORT_A, curr->value); + palSetPort(IOPORT_A, curr->value); break; } curr++; @@ -136,7 +138,7 @@ public: */ static void TimerHandler(eventid_t id) { - if (!(chPortRead(IOPORT_A) & (PA_BUTTON1 | PA_BUTTON2))) { // Both buttons + if (!(palReadPort(IOPORT_A) & BOTH_BUTTONS)) { // Both buttons TesterThread tester; tester.Wait(); }; diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h index 8cee52946..fee4baa61 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.h +++ b/demos/ARM7-LPC214x-GCC-minimal/board.h @@ -73,8 +73,9 @@ #define PA_BUTTON1 15 #define PA_BUTTON2 16 #define PA_SSEL1 20 -#define PA_WP1 24 -#define PA_CP1 25 #define PA_LEDUSB 31 +#define PB_WP1 24 +#define PB_CP1 25 + #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 6b3620e8a..c7bf868ef 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -55,6 +55,7 @@ CSRC = ../../ports/ARM7/chcore.c \ ${KERNSRC} \ ${TESTSRC} \ ../../src/lib/evtimer.c \ + ../../src/lib/pal.c \ board.c buzzer.c mmcsd.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index e1bf9369f..9eec8b06d 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "lpc214x.h" #include "vic.h" @@ -103,11 +104,11 @@ void hwinit0(void) { PINSEL0 = VAL_PINSEL0; PINSEL1 = VAL_PINSEL1; PINSEL2 = VAL_PINSEL2; - ioport_init_lld(); - ioport_lpc214x_set_direction_lld(IOPORT_A, VAL_FIO0DIR); - ioport_write_lld(IOPORT_A, 0xFFFFFFFF); - ioport_lpc214x_set_direction_lld(IOPORT_B, VAL_FIO1DIR); - ioport_write_lld(IOPORT_B, 0xFFFFFFFF); + palInit(); + pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); + palWritePort(IOPORT_A, 0xFFFFFFFF); + pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); + palWritePort(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-GCC/board.h b/demos/ARM7-LPC214x-GCC/board.h index ee30559c8..fee4baa61 100644 --- a/demos/ARM7-LPC214x-GCC/board.h +++ b/demos/ARM7-LPC214x-GCC/board.h @@ -24,10 +24,6 @@ #include "lpc214x.h" #endif -#ifndef _IOPORTS_LLD_H_ -#include "ioports.h" -#endif - #define BOARD_OLIMEX_LCP_P2148 /* @@ -69,17 +65,17 @@ #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 -#define PA_LED1 IOPORT_BIT(10) -#define PA_LED2 IOPORT_BIT(11) -#define PA_BUZZ1 IOPORT_BIT(12) -#define PA_BUZZ2 IOPORT_BIT(13) -#define PA_BSL IOPORT_BIT(14) -#define PA_BUTTON1 IOPORT_BIT(15) -#define PA_BUTTON2 IOPORT_BIT(16) -#define PA_SSEL1 IOPORT_BIT(20) -#define PA_LEDUSB IOPORT_BIT(31) +#define PA_LED1 10 +#define PA_LED2 11 +#define PA_BUZZ1 12 +#define PA_BUZZ2 13 +#define PA_BSL 14 +#define PA_BUTTON1 15 +#define PA_BUTTON2 16 +#define PA_SSEL1 20 +#define PA_LEDUSB 31 -#define PB_WP1 IOPORT_BIT(24) -#define PB_CP1 IOPORT_BIT(25) +#define PB_WP1 24 +#define PB_CP1 25 #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 3eafdba61..61ad4ea77 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -18,6 +18,7 @@ */ #include +#include #include #include "board.h" @@ -26,6 +27,8 @@ #include "buzzer.h" #include "evtimer.h" +#define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) + /* * Red LEDs blinker thread, times are in milliseconds. */ @@ -33,13 +36,13 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - chPortClear(IOPORT_A, PA_LED2); + palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(200); - chPortSet(IOPORT_A, PA_LED1 | PA_LED2); + palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); - chPortClear(IOPORT_A, PA_LED1); + palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED1)); chThdSleepMilliseconds(200); - chPortSet(IOPORT_A, PA_LED1 | PA_LED2); + palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); } return 0; @@ -52,9 +55,9 @@ static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { - chPortClear(IOPORT_A, PA_LEDUSB); + palClearPad(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(200); - chPortSet(IOPORT_A, PA_LEDUSB); + palSetPad(IOPORT_A, PA_LEDUSB); chThdSleepMilliseconds(300); } return 0; @@ -67,16 +70,16 @@ static WORKING_AREA(waTestThread, 128); */ static void TimerHandler(eventid_t id) { - if (!(chPortRead(IOPORT_A) & (PA_BUTTON1 | PA_BUTTON2))) { + if (!(palReadPort(IOPORT_A) & BOTH_BUTTONS)) { Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), NORMALPRIO, TestThread, &COM1); chThdWait(tp); PlaySound(500, MS2ST(100)); } else { - if (!(chPortRead(IOPORT_A) & PA_BUTTON1)) + if (!palReadPad(IOPORT_A, PA_BUTTON1)) PlaySound(1000, MS2ST(100)); - if (!(chPortRead(IOPORT_A) & PA_BUTTON2)) { + if (!palReadPad(IOPORT_A, PA_BUTTON2)) { chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); PlaySound(2000, MS2ST(100)); } @@ -129,7 +132,7 @@ int main(int argc, char **argv) { * If a button is pressed during the reset then the blinking leds threads * are not started in order to make accurate benchmarks. */ - if (chPortRead(IOPORT_A) && (PA_BUTTON1 | PA_BUTTON2) == (PA_BUTTON1 | PA_BUTTON2)) { + if ((palReadPort(IOPORT_A) & BOTH_BUTTONS) == BOTH_BUTTONS) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); } diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index bff2967d9..98ff2a23b 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" #include "lpc214x_ssp.h" @@ -42,7 +43,7 @@ void InitMMC(void) { void tmrfunc(void *par) { if (cnt) { - if (!(chPortRead(IOPORT_B) & PB_CP1)) { + if (!palReadPad(IOPORT_B, PB_CP1)) { if (!--cnt) chEvtBroadcastI(&MMCInsertEventSource); } @@ -50,7 +51,7 @@ void tmrfunc(void *par) { cnt = POLLING_INTERVAL; } else { - if (chPortRead(IOPORT_B) & PB_CP1) { + if (palReadPad(IOPORT_B, PB_CP1)) { cnt = POLLING_INTERVAL; chEvtBroadcastI(&MMCRemoveEventSource); } -- cgit v1.2.3 From 0d70a22f82a9e1ab1802524e2c821761a9ea569d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Jun 2009 06:40:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1028 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 27 ++++++++++-------- demos/ARM7-AT91SAM7X-GCC/board.h | 59 ++++++++++++++++++++++------------------ 2 files changed, 48 insertions(+), 38 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 43c624d9a..2b53c87b7 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" #include "at91lib/aic.h" @@ -97,11 +98,12 @@ void hwinit0(void) { ; /* - * I/O setup, enable clocks, initially all pins are inputs with pullups. + * PIO initialization. */ - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); + palInit(); +/* AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; - AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; + AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF;*/ } /* @@ -126,24 +128,25 @@ void hwinit1(void) { /* * LCD pins setup. */ - AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // Set to low. - AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL; // Configure as output. - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. + palClearPad(IOPORT_B, PIOB_LCD_BL); + AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL_MASK; // Configure as output. + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL_MASK; // Disable internal pullup resistor. - AT91C_BASE_PIOA->PIO_SODR = PIOA_LCD_RESET; // Set to high. - AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET; // Configure as output. - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET; // Disable internal pullup resistor. + palSetPad(IOPORT_A, PIOA_LCD_RESET); + AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET_MASK; // Configure as output. + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET_MASK; // Disable internal pullup resistor. /* * Joystick and buttons, disable pullups, already inputs. */ - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1 | PIOA_B2 | PIOA_B3 | PIOA_B4 | PIOA_B5; - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1 | PIOB_SW2; + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | + PIOA_B4_MASK | PIOA_B5_MASK; + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1_MASK | PIOB_SW2_MASK; /* * MMC/SD slot, disable pullups, already inputs. */ - AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP | PIOB_MMC_CP; + AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK; /* * PIT Initialization. diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h index 57629be2f..fe9219aa3 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -32,31 +32,38 @@ /* * I/O definitions. */ -#define PIOA_LCD_RESET (1 << 2) -#define PIOA_B1 (1 << 7) -#define PIOA_B2 (1 << 8) -#define PIOA_B3 (1 << 9) -#define PIOA_B4 (1 << 14) -#define PIOA_B5 (1 << 15) -#define PIOA_USB_PUP (1 << 25) -#define PIOA_USB_PR (1 << 26) -#define PIOA_PA27 (1 << 27) -#define PIOA_PA28 (1 << 28) -#define PIOA_PA29 (1 << 29) -#define PIOA_PA30 (1 << 30) - -#define PIOB_PHY_PD (1 << 18) -#define PIOB_AUDIO_OUT (1 << 19) -#define PIOB_LCD_BL (1 << 20) -#define PIOB_PB21 (1 << 21) -#define PIOB_MMC_WP (1 << 22) -#define PIOB_MMC_CP (1 << 23) -#define PIOB_SW1 (1 << 24) -#define PIOB_SW2 (1 << 25) -#define PIOB_PHY_IRQ (1 << 26) -#define PIOB_PB27_AD0 (1 << 27) -#define PIOB_PB28_AD1 (1 << 28) -#define PIOB_PB29_AD2 (1 << 29) -#define PIOB_PB30_AD3 (1 << 30) +#define PIOA_LCD_RESET 2 +#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) +#define PIOA_B1 7 +#define PIOA_B1_MASK (1 << PIOA_B1) +#define PIOA_B2 8 +#define PIOA_B2_MASK (1 << PIOA_B2) +#define PIOA_B3 9 +#define PIOA_B3_MASK (1 << PIOA_B3) +#define PIOA_B4 14 +#define PIOA_B4_MASK (1 << PIOA_B4) +#define PIOA_B5 15 +#define PIOA_B5_MASK (1 << PIOA_B5) +#define PIOA_USB_PUP 25 +#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) +#define PIOA_USB_PR 26 +#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) + +#define PIOB_PHY_PD 18 +#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) +#define PIOB_AUDIO_OUT 19 +#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) +#define PIOB_LCD_BL 20 +#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) +#define PIOB_MMC_WP 22 +#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) +#define PIOB_MMC_CP 23 +#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) +#define PIOB_SW1 24 +#define PIOB_SW1_MASK (1 << PIOB_SW1) +#define PIOB_SW2 25 +#define PIOB_SW2_MASK (1 << PIOB_SW2) +#define PIOB_PHY_IRQ 26 +#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) #endif /* _BOARD_H_ */ -- cgit v1.2.3 From c731a9477bd4fbbadb4ac7c19726c4d5f812f461 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Jun 2009 07:06:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1029 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 3 -- demos/ARM7-AT91SAM7X-GCC/main.c | 9 +++--- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 28 ++++++++--------- demos/ARM7-AT91SAM7X-WEB-GCC/board.h | 59 ++++++++++++++++++++---------------- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 9 +++--- 5 files changed, 57 insertions(+), 51 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 2b53c87b7..02ac5046d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -101,9 +101,6 @@ void hwinit0(void) { * PIO initialization. */ palInit(); -/* AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); - AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; - AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF;*/ } /* diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index c51c911c9..614b649cd 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -18,6 +18,7 @@ */ #include +#include #include #include "board.h" @@ -27,9 +28,9 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. + palSetPad(IOPORT_B, PIOB_LCD_BL); chThdSleepMilliseconds(100); - AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // LCD off. + palClearPad(IOPORT_B, PIOB_LCD_BL); chThdSleepMilliseconds(900); } return 0; @@ -51,9 +52,9 @@ int main(int argc, char **argv) { */ while (TRUE) { chThdSleepMilliseconds(500); - if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) + if (!palReadPad(IOPORT_B, PIOB_SW1)) chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); - if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW2)) + if (!palReadPad(IOPORT_B, PIOB_SW2)) TestThread(&COM1); } diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 630a0ad5d..e0b170120 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -18,6 +18,7 @@ */ #include +#include #include "board.h" #include "at91lib/aic.h" @@ -26,7 +27,7 @@ #include /* - * FIQ Handler weak symbol defined in vectors.s. + * FIQ Handler weak symbol defined in vectors.s. */ void FiqHandler(void); @@ -98,11 +99,9 @@ void hwinit0(void) { ; /* - * I/O setup, enable clocks, initially all pins are inputs with pullups. + * PIO initialization. */ - AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOB); - AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; - AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; + palInit(); } /* @@ -127,24 +126,25 @@ void hwinit1(void) { /* * LCD pins setup. */ - AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // Set to low. - AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL; // Configure as output. - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL; // Disable internal pullup resistor. + palClearPad(IOPORT_B, PIOB_LCD_BL); + AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL_MASK; // Configure as output. + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL_MASK; // Disable internal pullup resistor. - AT91C_BASE_PIOA->PIO_SODR = PIOA_LCD_RESET; // Set to high. - AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET; // Configure as output. - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET; // Disable internal pullup resistor. + palSetPad(IOPORT_A, PIOA_LCD_RESET); + AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET_MASK; // Configure as output. + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET_MASK; // Disable internal pullup resistor. /* * Joystick and buttons, disable pullups, already inputs. */ - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1 | PIOA_B2 | PIOA_B3 | PIOA_B4 | PIOA_B5; - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1 | PIOB_SW2; + AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | + PIOA_B4_MASK | PIOA_B5_MASK; + AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1_MASK | PIOB_SW2_MASK; /* * MMC/SD slot, disable pullups, already inputs. */ - AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP | PIOB_MMC_CP; + AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK; /* * PIT Initialization. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.h b/demos/ARM7-AT91SAM7X-WEB-GCC/board.h index 57629be2f..fe9219aa3 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.h @@ -32,31 +32,38 @@ /* * I/O definitions. */ -#define PIOA_LCD_RESET (1 << 2) -#define PIOA_B1 (1 << 7) -#define PIOA_B2 (1 << 8) -#define PIOA_B3 (1 << 9) -#define PIOA_B4 (1 << 14) -#define PIOA_B5 (1 << 15) -#define PIOA_USB_PUP (1 << 25) -#define PIOA_USB_PR (1 << 26) -#define PIOA_PA27 (1 << 27) -#define PIOA_PA28 (1 << 28) -#define PIOA_PA29 (1 << 29) -#define PIOA_PA30 (1 << 30) - -#define PIOB_PHY_PD (1 << 18) -#define PIOB_AUDIO_OUT (1 << 19) -#define PIOB_LCD_BL (1 << 20) -#define PIOB_PB21 (1 << 21) -#define PIOB_MMC_WP (1 << 22) -#define PIOB_MMC_CP (1 << 23) -#define PIOB_SW1 (1 << 24) -#define PIOB_SW2 (1 << 25) -#define PIOB_PHY_IRQ (1 << 26) -#define PIOB_PB27_AD0 (1 << 27) -#define PIOB_PB28_AD1 (1 << 28) -#define PIOB_PB29_AD2 (1 << 29) -#define PIOB_PB30_AD3 (1 << 30) +#define PIOA_LCD_RESET 2 +#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) +#define PIOA_B1 7 +#define PIOA_B1_MASK (1 << PIOA_B1) +#define PIOA_B2 8 +#define PIOA_B2_MASK (1 << PIOA_B2) +#define PIOA_B3 9 +#define PIOA_B3_MASK (1 << PIOA_B3) +#define PIOA_B4 14 +#define PIOA_B4_MASK (1 << PIOA_B4) +#define PIOA_B5 15 +#define PIOA_B5_MASK (1 << PIOA_B5) +#define PIOA_USB_PUP 25 +#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) +#define PIOA_USB_PR 26 +#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) + +#define PIOB_PHY_PD 18 +#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) +#define PIOB_AUDIO_OUT 19 +#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) +#define PIOB_LCD_BL 20 +#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) +#define PIOB_MMC_WP 22 +#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) +#define PIOB_MMC_CP 23 +#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) +#define PIOB_SW1 24 +#define PIOB_SW1_MASK (1 << PIOB_SW1) +#define PIOB_SW2 25 +#define PIOB_SW2_MASK (1 << PIOB_SW2) +#define PIOB_PHY_IRQ 26 +#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) #endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index 07af9b0bd..0eafb2260 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -18,6 +18,7 @@ */ #include +#include #include #include "board.h" @@ -32,9 +33,9 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - AT91C_BASE_PIOB->PIO_SODR = PIOB_LCD_BL; // LCD on. + palSetPad(IOPORT_B, PIOB_LCD_BL); chThdSleepMilliseconds(100); - AT91C_BASE_PIOB->PIO_CODR = PIOB_LCD_BL; // LCD off. + palClearPad(IOPORT_B, PIOB_LCD_BL); chThdSleepMilliseconds(900); } return 0; @@ -57,9 +58,9 @@ int main(int argc, char **argv) { */ while (TRUE) { chThdSleepMilliseconds(500); - if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW1)) + if (!palReadPad(IOPORT_B, PIOB_SW1)) chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); - if (!(AT91C_BASE_PIOB->PIO_PDSR & PIOB_SW2)) + if (!palReadPad(IOPORT_B, PIOB_SW2)) TestThread(&COM1); } -- cgit v1.2.3 From 6ab7ea31f114af0e0d98494156d456279dd5ecd4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 14 Jun 2009 13:10:38 +0000 Subject: PAL support for MSP430, various other fixes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1037 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 36 +++++++++++++++++------------------- demos/MSP430-MSP430x1611-GCC/board.h | 36 ++++++++++++++++++++---------------- demos/MSP430-MSP430x1611-GCC/main.c | 7 ++++--- 3 files changed, 41 insertions(+), 38 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 794070803..c94b4141b 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -18,6 +18,8 @@ */ #include +#include + #include #include "board.h" @@ -45,31 +47,27 @@ void hwinit(void) { BCSCTL2 = VAL_BCSCTL2; /* - * I/O ports initialization. + * I/O ports initialization. PxSEL registers are assumed to be cleared after + * the reset. */ - P1OUT = VAL_P1OUT; - P1DIR = VAL_P1DIR; - P1SEL = VAL_P1SEL; + palInit(); + palWritePort(IOPORT_A, VAL_P1OUT); + pal_lld_msp430_set_direction(IOPORT_A, VAL_P1DIR); - P2OUT = VAL_P2OUT; - P2DIR = VAL_P2DIR; - P2SEL = VAL_P2SEL; + palWritePort(IOPORT_B, VAL_P2OUT); + pal_lld_msp430_set_direction(IOPORT_B, VAL_P2DIR); - P3OUT = VAL_P3OUT; - P3DIR = VAL_P3DIR; - P3SEL = VAL_P3SEL; + palWritePort(IOPORT_C, VAL_P3OUT); + pal_lld_msp430_set_direction(IOPORT_C, VAL_P3DIR); - P4OUT = VAL_P4OUT; - P4DIR = VAL_P4DIR; - P4SEL = VAL_P4SEL; + palWritePort(IOPORT_D, VAL_P4OUT); + pal_lld_msp430_set_direction(IOPORT_D, VAL_P4DIR); - P5OUT = VAL_P5OUT; - P5DIR = VAL_P5DIR; - P5SEL = VAL_P5SEL; + palWritePort(IOPORT_E, VAL_P5OUT); + pal_lld_msp430_set_direction(IOPORT_E, VAL_P5DIR); - P6OUT = VAL_P6OUT; - P6DIR = VAL_P6DIR; - P6SEL = VAL_P6SEL; + palWritePort(IOPORT_F, VAL_P6OUT); + pal_lld_msp430_set_direction(IOPORT_F, VAL_P6DIR); /* * Timer 0 setup, uses SMCLK as source. diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index f7173f712..235a8303a 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -58,40 +58,44 @@ #endif /* - * Pin definitionsfor the Olimex MSP430-P1611 board. + * Pin definitions for the Olimex MSP430-P1611 board. */ -#define P3_O_TXD0 (1 << 4) -#define P3_I_RXD0 (1 << 5) -#define P6_O_LED (1 << 0) -#define P6_I_BUTTON (1 << 1) +#define P3_O_TXD0 4 +#define P3_O_TXD0_MASK (1 << P3_O_TXD0) +#define P3_I_RXD0 5 +#define P3_I_RXD0_MASK (1 << P3_I_RXD0) +#define P6_O_LED 0 +#define P6_O_LED_MASK (1 << P6_O_LED) +#define P6_I_BUTTON 1 +#define P6_I_BUTTON_MASK (1 << P6_I_BUTTON) /* * Initial I/O ports settings. */ #define VAL_P1OUT 0x00 #define VAL_P1DIR 0xFF -#define VAL_P1SEL 0x00 #define VAL_P2OUT 0x00 #define VAL_P2DIR 0xFF -#define VAL_P2SEL 0x00 -#define VAL_P3OUT P3_O_TXD0 -#define VAL_P3DIR ~P3_I_RXD0 -#define VAL_P3SEL 0x00 +#define VAL_P3OUT P3_O_TXD0_MASK +#define VAL_P3DIR ~P3_I_RXD0_MASK #define VAL_P4OUT 0x00 #define VAL_P4DIR 0xFF -#define VAL_P4SEL 0x00 #define VAL_P5OUT 0x00 #define VAL_P5DIR 0xFF -#define VAL_P5SEL 0x00 -#define VAL_P6OUT P6_O_LED -#define VAL_P6DIR ~P6_I_BUTTON -#define VAL_P6SEL 0x00 +#define VAL_P6OUT P6_O_LED_MASK +#define VAL_P6DIR ~P6_I_BUTTON_MASK -void hwinit(void); +#ifdef __cplusplus +extern "C" { +#endif + void hwinit(void); +#ifdef __cplusplus +} +#endif #endif /* _BOARD_H_ */ diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 4bc7d9895..2f9f6d8b9 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -18,6 +18,7 @@ */ #include +#include #include #include "board.h" @@ -30,9 +31,9 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - P6OUT |= P6_O_LED; + palSetPad(IOPORT_F, P6_O_LED); chThdSleepMilliseconds(500); - P6OUT &= ~P6_O_LED; + palClearPad(IOPORT_F, P6_O_LED); chThdSleepMilliseconds(500); } return 0; @@ -64,7 +65,7 @@ int main(int argc, char **argv) { * sleeping in a loop. */ while (TRUE) { - if (!(P6IN & P6_I_BUTTON)) + if (!palReadPad(IOPORT_F, P6_I_BUTTON)) TestThread(&COM1); chThdSleepMilliseconds(500); } -- cgit v1.2.3 From 1c7e52eb35c244e5855ea7978ab02d9540829e00 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Jun 2009 08:52:44 +0000 Subject: Added abstract port setup to PAL and to the MSP430 port. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1042 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 1 + demos/MSP430-MSP430x1611-GCC/board.c | 35 +++++++++++++++-------------------- 2 files changed, 16 insertions(+), 20 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 4f9d159c3..8cf693eb1 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -45,6 +45,7 @@ include ../../test/test.mk # C sources here. CSRC = ../../ports/MSP430/chcore.c \ ../../ports/MSP430/msp430_serial.c \ + ../../ports/MSP430/pal_lld.c \ ${KERNSRC} \ ${TESTSRC} \ ../../src/lib/evtimer.c \ diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index c94b4141b..d24bd29e2 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -25,6 +25,19 @@ #include "board.h" #include "msp430_serial.h" +/* + * Digital I/O ports static configuration. + */ +static const MSP430DIOConfig config = +{ + {VAL_P1OUT, VAL_P1DIR}, + {VAL_P2OUT, VAL_P2DIR}, + {VAL_P3OUT, VAL_P3DIR}, + {VAL_P4OUT, VAL_P4DIR}, + {VAL_P5OUT, VAL_P5DIR}, + {VAL_P6OUT, VAL_P6DIR}, +}; + /* * Hardware initialization goes here. * NOTE: Interrupts are still disabled. @@ -47,27 +60,9 @@ void hwinit(void) { BCSCTL2 = VAL_BCSCTL2; /* - * I/O ports initialization. PxSEL registers are assumed to be cleared after - * the reset. + * I/O ports initialization. */ - palInit(); - palWritePort(IOPORT_A, VAL_P1OUT); - pal_lld_msp430_set_direction(IOPORT_A, VAL_P1DIR); - - palWritePort(IOPORT_B, VAL_P2OUT); - pal_lld_msp430_set_direction(IOPORT_B, VAL_P2DIR); - - palWritePort(IOPORT_C, VAL_P3OUT); - pal_lld_msp430_set_direction(IOPORT_C, VAL_P3DIR); - - palWritePort(IOPORT_D, VAL_P4OUT); - pal_lld_msp430_set_direction(IOPORT_D, VAL_P4DIR); - - palWritePort(IOPORT_E, VAL_P5OUT); - pal_lld_msp430_set_direction(IOPORT_E, VAL_P5DIR); - - palWritePort(IOPORT_F, VAL_P6OUT); - pal_lld_msp430_set_direction(IOPORT_F, VAL_P6DIR); + palInit(&config); /* * Timer 0 setup, uses SMCLK as source. -- cgit v1.2.3 From 8183016f1cb574d923c83eab468ca37617051d78 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Jun 2009 09:35:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1043 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index d24bd29e2..2d5341beb 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -26,16 +26,16 @@ #include "msp430_serial.h" /* - * Digital I/O ports static configuration. + * Digital I/O ports static configuration as defined in @p board.h. */ static const MSP430DIOConfig config = { - {VAL_P1OUT, VAL_P1DIR}, - {VAL_P2OUT, VAL_P2DIR}, - {VAL_P3OUT, VAL_P3DIR}, - {VAL_P4OUT, VAL_P4DIR}, - {VAL_P5OUT, VAL_P5DIR}, - {VAL_P6OUT, VAL_P6DIR}, + {VAL_P1OUT, VAL_P1DIR}, + {VAL_P2OUT, VAL_P2DIR}, + {VAL_P3OUT, VAL_P3DIR}, + {VAL_P4OUT, VAL_P4DIR}, + {VAL_P5OUT, VAL_P5DIR}, + {VAL_P6OUT, VAL_P6DIR}, }; /* -- cgit v1.2.3 From 85118e378ca313a3e19f4e207fcc67a3bf75360b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Jun 2009 16:34:05 +0000 Subject: Ports setup PAL support for STM32. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1048 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 1 + demos/ARMCM3-STM32F103-GCC/board.c | 25 +- demos/ARMCM3-STM32F103-GCC/board.h | 37 +-- .../stm32lib/inc/stm32f10x_rcc.h | 288 +++++++++++++++++++++ 4 files changed, 320 insertions(+), 31 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 0fa07c91a..a6a0ecee5 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -64,6 +64,7 @@ include ../../test/test.mk CSRC = ../../ports/ARMCM3/chcore.c \ ../../ports/ARMCM3/nvic.c \ ../../ports/ARMCM3-STM32F103/stm32_serial.c \ + ../../ports/ARMCM3-STM32F103/pal_lld.c \ ${KERNSRC} \ ${TESTSRC} \ ../../src/lib/pal.c \ diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 52701992a..3e3776f4a 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -24,6 +24,17 @@ #include "board.h" #include "stm32_serial.h" +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const STM32GPIOConfig config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, +}; + /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -62,19 +73,7 @@ void hwinit0(void) { /* * I/O ports initialization as specified in board.h. */ - palInit(); - - pal_lld_stm32_setup(IOPORT_A, VAL_GPIOACRH, VAL_GPIOACRL); - palWritePort(IOPORT_A, VAL_GPIOAODR); - - pal_lld_stm32_setup(IOPORT_B, VAL_GPIOBCRH, VAL_GPIOBCRL); - palWritePort(IOPORT_B, VAL_GPIOBODR); - - pal_lld_stm32_setup(IOPORT_C, VAL_GPIOCCRH, VAL_GPIOCCRL); - palWritePort(IOPORT_C, VAL_GPIOCODR); - - pal_lld_stm32_setup(IOPORT_D, VAL_GPIODCRH, VAL_GPIODCRL); - palWritePort(IOPORT_D, VAL_GPIODODR); + palInit(&config); } /* diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 250b2b2d2..755e6e15d 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -28,6 +28,7 @@ #undef FALSE #undef TRUE #include "stm32f10x_map.h" +#include "stm32f10x_rcc.h" #define FALSE 0 #define TRUE (!FALSE) #endif @@ -121,31 +122,31 @@ /* * IO pins assignments. */ -#define GPIOA_BUTTON 0 +#define GPIOA_BUTTON 0 -#define GPIOC_MMCWP 6 -#define GPIOC_MMCCP 7 -#define GPIOC_CANCNTL 10 -#define GPIOC_DISC 11 -#define GPIOC_LED 12 +#define GPIOC_MMCWP 6 +#define GPIOC_MMCCP 7 +#define GPIOC_CANCNTL 10 +#define GPIOC_DISC 11 +#define GPIOC_LED 12 /* * All inputs with pullups unless otherwise specified. */ -#define VAL_GPIOACRL 0x88888884 // PA0:FI -#define VAL_GPIOACRH 0x88888888 -#define VAL_GPIOAODR 0xFFFFFFFF +#define VAL_GPIOACRL 0x88888884 // PA0:FI +#define VAL_GPIOACRH 0x88888888 +#define VAL_GPIOAODR 0xFFFFFFFF -#define VAL_GPIOBCRL 0x88883888 // PB3:PP -#define VAL_GPIOBCRH 0x88888888 -#define VAL_GPIOBODR 0xFFFFFFFF +#define VAL_GPIOBCRL 0x88883888 // PB3:PP +#define VAL_GPIOBCRH 0x88888888 +#define VAL_GPIOBODR 0xFFFFFFFF -#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI -#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP -#define VAL_GPIOCODR 0xFFFFFFFF +#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI +#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP +#define VAL_GPIOCODR 0xFFFFFFFF -#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI -#define VAL_GPIODCRH 0x88888888 -#define VAL_GPIODODR 0xFFFFFFFF +#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI +#define VAL_GPIODCRH 0x88888888 +#define VAL_GPIODODR 0xFFFFFFFF #endif /* _BOARD_H_ */ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h new file mode 100644 index 000000000..a256bc914 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h @@ -0,0 +1,288 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f10x_rcc.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file contains all the functions prototypes for the +* RCC firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_map.h" + +/* Exported types ------------------------------------------------------------*/ +typedef struct +{ + u32 SYSCLK_Frequency; + u32 HCLK_Frequency; + u32 PCLK1_Frequency; + u32 PCLK2_Frequency; + u32 ADCCLK_Frequency; +}RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/* HSE configuration */ +#define RCC_HSE_OFF ((u32)0x00000000) +#define RCC_HSE_ON ((u32)0x00010000) +#define RCC_HSE_Bypass ((u32)0x00040000) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/* PLL entry clock source */ +#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000) + +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) + +/* PLL multiplication factor */ +#define RCC_PLLMul_2 ((u32)0x00000000) +#define RCC_PLLMul_3 ((u32)0x00040000) +#define RCC_PLLMul_4 ((u32)0x00080000) +#define RCC_PLLMul_5 ((u32)0x000C0000) +#define RCC_PLLMul_6 ((u32)0x00100000) +#define RCC_PLLMul_7 ((u32)0x00140000) +#define RCC_PLLMul_8 ((u32)0x00180000) +#define RCC_PLLMul_9 ((u32)0x001C0000) +#define RCC_PLLMul_10 ((u32)0x00200000) +#define RCC_PLLMul_11 ((u32)0x00240000) +#define RCC_PLLMul_12 ((u32)0x00280000) +#define RCC_PLLMul_13 ((u32)0x002C0000) +#define RCC_PLLMul_14 ((u32)0x00300000) +#define RCC_PLLMul_15 ((u32)0x00340000) +#define RCC_PLLMul_16 ((u32)0x00380000) + +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +/* System clock source */ +#define RCC_SYSCLKSource_HSI ((u32)0x00000000) +#define RCC_SYSCLKSource_HSE ((u32)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002) + +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) + +/* AHB clock source */ +#define RCC_SYSCLK_Div1 ((u32)0x00000000) +#define RCC_SYSCLK_Div2 ((u32)0x00000080) +#define RCC_SYSCLK_Div4 ((u32)0x00000090) +#define RCC_SYSCLK_Div8 ((u32)0x000000A0) +#define RCC_SYSCLK_Div16 ((u32)0x000000B0) +#define RCC_SYSCLK_Div64 ((u32)0x000000C0) +#define RCC_SYSCLK_Div128 ((u32)0x000000D0) +#define RCC_SYSCLK_Div256 ((u32)0x000000E0) +#define RCC_SYSCLK_Div512 ((u32)0x000000F0) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) + +/* APB1/APB2 clock source */ +#define RCC_HCLK_Div1 ((u32)0x00000000) +#define RCC_HCLK_Div2 ((u32)0x00000400) +#define RCC_HCLK_Div4 ((u32)0x00000500) +#define RCC_HCLK_Div8 ((u32)0x00000600) +#define RCC_HCLK_Div16 ((u32)0x00000700) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) + +/* RCC Interrupt source */ +#define RCC_IT_LSIRDY ((u8)0x01) +#define RCC_IT_LSERDY ((u8)0x02) +#define RCC_IT_HSIRDY ((u8)0x04) +#define RCC_IT_HSERDY ((u8)0x08) +#define RCC_IT_PLLRDY ((u8)0x10) +#define RCC_IT_CSS ((u8)0x80) + +#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00)) + +/* USB clock source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01) + +#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) + +/* ADC clock source */ +#define RCC_PCLK2_Div2 ((u32)0x00000000) +#define RCC_PCLK2_Div4 ((u32)0x00004000) +#define RCC_PCLK2_Div6 ((u32)0x00008000) +#define RCC_PCLK2_Div8 ((u32)0x0000C000) + +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) + +/* LSE configuration */ +#define RCC_LSE_OFF ((u8)0x00) +#define RCC_LSE_ON ((u8)0x01) +#define RCC_LSE_Bypass ((u8)0x04) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) + +/* RTC clock source */ +#define RCC_RTCCLKSource_LSE ((u32)0x00000100) +#define RCC_RTCCLKSource_LSI ((u32)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300) + +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) + +/* AHB peripheral */ +#define RCC_AHBPeriph_DMA1 ((u32)0x00000001) +#define RCC_AHBPeriph_DMA2 ((u32)0x00000002) +#define RCC_AHBPeriph_SRAM ((u32)0x00000004) +#define RCC_AHBPeriph_FLITF ((u32)0x00000010) +#define RCC_AHBPeriph_CRC ((u32)0x00000040) +#define RCC_AHBPeriph_FSMC ((u32)0x00000100) +#define RCC_AHBPeriph_SDIO ((u32)0x00000400) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) + +/* APB2 peripheral */ +#define RCC_APB2Periph_AFIO ((u32)0x00000001) +#define RCC_APB2Periph_GPIOA ((u32)0x00000004) +#define RCC_APB2Periph_GPIOB ((u32)0x00000008) +#define RCC_APB2Periph_GPIOC ((u32)0x00000010) +#define RCC_APB2Periph_GPIOD ((u32)0x00000020) +#define RCC_APB2Periph_GPIOE ((u32)0x00000040) +#define RCC_APB2Periph_GPIOF ((u32)0x00000080) +#define RCC_APB2Periph_GPIOG ((u32)0x00000100) +#define RCC_APB2Periph_ADC1 ((u32)0x00000200) +#define RCC_APB2Periph_ADC2 ((u32)0x00000400) +#define RCC_APB2Periph_TIM1 ((u32)0x00000800) +#define RCC_APB2Periph_SPI1 ((u32)0x00001000) +#define RCC_APB2Periph_TIM8 ((u32)0x00002000) +#define RCC_APB2Periph_USART1 ((u32)0x00004000) +#define RCC_APB2Periph_ADC3 ((u32)0x00008000) +#define RCC_APB2Periph_ALL ((u32)0x0000FFFD) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) + +/* APB1 peripheral */ +#define RCC_APB1Periph_TIM2 ((u32)0x00000001) +#define RCC_APB1Periph_TIM3 ((u32)0x00000002) +#define RCC_APB1Periph_TIM4 ((u32)0x00000004) +#define RCC_APB1Periph_TIM5 ((u32)0x00000008) +#define RCC_APB1Periph_TIM6 ((u32)0x00000010) +#define RCC_APB1Periph_TIM7 ((u32)0x00000020) +#define RCC_APB1Periph_WWDG ((u32)0x00000800) +#define RCC_APB1Periph_SPI2 ((u32)0x00004000) +#define RCC_APB1Periph_SPI3 ((u32)0x00008000) +#define RCC_APB1Periph_USART2 ((u32)0x00020000) +#define RCC_APB1Periph_USART3 ((u32)0x00040000) +#define RCC_APB1Periph_UART4 ((u32)0x00080000) +#define RCC_APB1Periph_UART5 ((u32)0x00100000) +#define RCC_APB1Periph_I2C1 ((u32)0x00200000) +#define RCC_APB1Periph_I2C2 ((u32)0x00400000) +#define RCC_APB1Periph_USB ((u32)0x00800000) +#define RCC_APB1Periph_CAN ((u32)0x02000000) +#define RCC_APB1Periph_BKP ((u32)0x08000000) +#define RCC_APB1Periph_PWR ((u32)0x10000000) +#define RCC_APB1Periph_DAC ((u32)0x20000000) +#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) + +/* Clock source to output on MCO pin */ +#define RCC_MCO_NoClock ((u8)0x00) +#define RCC_MCO_SYSCLK ((u8)0x04) +#define RCC_MCO_HSI ((u8)0x05) +#define RCC_MCO_HSE ((u8)0x06) +#define RCC_MCO_PLLCLK_Div2 ((u8)0x07) + +#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) + +/* RCC Flag */ +#define RCC_FLAG_HSIRDY ((u8)0x21) +#define RCC_FLAG_HSERDY ((u8)0x31) +#define RCC_FLAG_PLLRDY ((u8)0x39) +#define RCC_FLAG_LSERDY ((u8)0x41) +#define RCC_FLAG_LSIRDY ((u8)0x61) +#define RCC_FLAG_PINRST ((u8)0x7A) +#define RCC_FLAG_PORRST ((u8)0x7B) +#define RCC_FLAG_SFTRST ((u8)0x7C) +#define RCC_FLAG_IWDGRST ((u8)0x7D) +#define RCC_FLAG_WWDGRST ((u8)0x7E) +#define RCC_FLAG_LPWRRST ((u8)0x7F) + +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void RCC_DeInit(void); +void RCC_HSEConfig(u32 RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource); +u8 RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(u32 RCC_SYSCLK); +void RCC_PCLK1Config(u32 RCC_HCLK); +void RCC_PCLK2Config(u32 RCC_HCLK); +void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(u32 RCC_USBCLKSource); +void RCC_ADCCLKConfig(u32 RCC_PCLK2); +void RCC_LSEConfig(u8 RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(u8 RCC_MCO); +FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(u8 RCC_IT); +void RCC_ClearITPendingBit(u8 RCC_IT); + +#endif /* __STM32F10x_RCC_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3 From c9c4259de8e3237a32027fc79766bcbcf00f8341 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Jun 2009 16:36:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1049 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../stm32lib/inc/stm32f10x_rcc.h | 288 --------------------- 1 file changed, 288 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h deleted file mode 100644 index a256bc914..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h +++ /dev/null @@ -1,288 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : stm32f10x_rcc.h -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : This file contains all the functions prototypes for the -* RCC firmware library. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RCC_H -#define __STM32F10x_RCC_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_map.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - u32 SYSCLK_Frequency; - u32 HCLK_Frequency; - u32 PCLK1_Frequency; - u32 PCLK2_Frequency; - u32 ADCCLK_Frequency; -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* HSE configuration */ -#define RCC_HSE_OFF ((u32)0x00000000) -#define RCC_HSE_ON ((u32)0x00010000) -#define RCC_HSE_Bypass ((u32)0x00040000) - -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/* PLL entry clock source */ -#define RCC_PLLSource_HSI_Div2 ((u32)0x00000000) -#define RCC_PLLSource_HSE_Div1 ((u32)0x00010000) -#define RCC_PLLSource_HSE_Div2 ((u32)0x00030000) - -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div2)) - -/* PLL multiplication factor */ -#define RCC_PLLMul_2 ((u32)0x00000000) -#define RCC_PLLMul_3 ((u32)0x00040000) -#define RCC_PLLMul_4 ((u32)0x00080000) -#define RCC_PLLMul_5 ((u32)0x000C0000) -#define RCC_PLLMul_6 ((u32)0x00100000) -#define RCC_PLLMul_7 ((u32)0x00140000) -#define RCC_PLLMul_8 ((u32)0x00180000) -#define RCC_PLLMul_9 ((u32)0x001C0000) -#define RCC_PLLMul_10 ((u32)0x00200000) -#define RCC_PLLMul_11 ((u32)0x00240000) -#define RCC_PLLMul_12 ((u32)0x00280000) -#define RCC_PLLMul_13 ((u32)0x002C0000) -#define RCC_PLLMul_14 ((u32)0x00300000) -#define RCC_PLLMul_15 ((u32)0x00340000) -#define RCC_PLLMul_16 ((u32)0x00380000) - -#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) - -/* System clock source */ -#define RCC_SYSCLKSource_HSI ((u32)0x00000000) -#define RCC_SYSCLKSource_HSE ((u32)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((u32)0x00000002) - -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) - -/* AHB clock source */ -#define RCC_SYSCLK_Div1 ((u32)0x00000000) -#define RCC_SYSCLK_Div2 ((u32)0x00000080) -#define RCC_SYSCLK_Div4 ((u32)0x00000090) -#define RCC_SYSCLK_Div8 ((u32)0x000000A0) -#define RCC_SYSCLK_Div16 ((u32)0x000000B0) -#define RCC_SYSCLK_Div64 ((u32)0x000000C0) -#define RCC_SYSCLK_Div128 ((u32)0x000000D0) -#define RCC_SYSCLK_Div256 ((u32)0x000000E0) -#define RCC_SYSCLK_Div512 ((u32)0x000000F0) - -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) - -/* APB1/APB2 clock source */ -#define RCC_HCLK_Div1 ((u32)0x00000000) -#define RCC_HCLK_Div2 ((u32)0x00000400) -#define RCC_HCLK_Div4 ((u32)0x00000500) -#define RCC_HCLK_Div8 ((u32)0x00000600) -#define RCC_HCLK_Div16 ((u32)0x00000700) - -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) - -/* RCC Interrupt source */ -#define RCC_IT_LSIRDY ((u8)0x01) -#define RCC_IT_LSERDY ((u8)0x02) -#define RCC_IT_HSIRDY ((u8)0x04) -#define RCC_IT_HSERDY ((u8)0x08) -#define RCC_IT_PLLRDY ((u8)0x10) -#define RCC_IT_CSS ((u8)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (u8)0xE0) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (u8)0x60) == 0x00) && ((IT) != 0x00)) - -/* USB clock source */ -#define RCC_USBCLKSource_PLLCLK_1Div5 ((u8)0x00) -#define RCC_USBCLKSource_PLLCLK_Div1 ((u8)0x01) - -#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) - -/* ADC clock source */ -#define RCC_PCLK2_Div2 ((u32)0x00000000) -#define RCC_PCLK2_Div4 ((u32)0x00004000) -#define RCC_PCLK2_Div6 ((u32)0x00008000) -#define RCC_PCLK2_Div8 ((u32)0x0000C000) - -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ - ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) - -/* LSE configuration */ -#define RCC_LSE_OFF ((u8)0x00) -#define RCC_LSE_ON ((u8)0x01) -#define RCC_LSE_Bypass ((u8)0x04) - -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) - -/* RTC clock source */ -#define RCC_RTCCLKSource_LSE ((u32)0x00000100) -#define RCC_RTCCLKSource_LSI ((u32)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((u32)0x00000300) - -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) - -/* AHB peripheral */ -#define RCC_AHBPeriph_DMA1 ((u32)0x00000001) -#define RCC_AHBPeriph_DMA2 ((u32)0x00000002) -#define RCC_AHBPeriph_SRAM ((u32)0x00000004) -#define RCC_AHBPeriph_FLITF ((u32)0x00000010) -#define RCC_AHBPeriph_CRC ((u32)0x00000040) -#define RCC_AHBPeriph_FSMC ((u32)0x00000100) -#define RCC_AHBPeriph_SDIO ((u32)0x00000400) - -#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) - -/* APB2 peripheral */ -#define RCC_APB2Periph_AFIO ((u32)0x00000001) -#define RCC_APB2Periph_GPIOA ((u32)0x00000004) -#define RCC_APB2Periph_GPIOB ((u32)0x00000008) -#define RCC_APB2Periph_GPIOC ((u32)0x00000010) -#define RCC_APB2Periph_GPIOD ((u32)0x00000020) -#define RCC_APB2Periph_GPIOE ((u32)0x00000040) -#define RCC_APB2Periph_GPIOF ((u32)0x00000080) -#define RCC_APB2Periph_GPIOG ((u32)0x00000100) -#define RCC_APB2Periph_ADC1 ((u32)0x00000200) -#define RCC_APB2Periph_ADC2 ((u32)0x00000400) -#define RCC_APB2Periph_TIM1 ((u32)0x00000800) -#define RCC_APB2Periph_SPI1 ((u32)0x00001000) -#define RCC_APB2Periph_TIM8 ((u32)0x00002000) -#define RCC_APB2Periph_USART1 ((u32)0x00004000) -#define RCC_APB2Periph_ADC3 ((u32)0x00008000) -#define RCC_APB2Periph_ALL ((u32)0x0000FFFD) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) - -/* APB1 peripheral */ -#define RCC_APB1Periph_TIM2 ((u32)0x00000001) -#define RCC_APB1Periph_TIM3 ((u32)0x00000002) -#define RCC_APB1Periph_TIM4 ((u32)0x00000004) -#define RCC_APB1Periph_TIM5 ((u32)0x00000008) -#define RCC_APB1Periph_TIM6 ((u32)0x00000010) -#define RCC_APB1Periph_TIM7 ((u32)0x00000020) -#define RCC_APB1Periph_WWDG ((u32)0x00000800) -#define RCC_APB1Periph_SPI2 ((u32)0x00004000) -#define RCC_APB1Periph_SPI3 ((u32)0x00008000) -#define RCC_APB1Periph_USART2 ((u32)0x00020000) -#define RCC_APB1Periph_USART3 ((u32)0x00040000) -#define RCC_APB1Periph_UART4 ((u32)0x00080000) -#define RCC_APB1Periph_UART5 ((u32)0x00100000) -#define RCC_APB1Periph_I2C1 ((u32)0x00200000) -#define RCC_APB1Periph_I2C2 ((u32)0x00400000) -#define RCC_APB1Periph_USB ((u32)0x00800000) -#define RCC_APB1Periph_CAN ((u32)0x02000000) -#define RCC_APB1Periph_BKP ((u32)0x08000000) -#define RCC_APB1Periph_PWR ((u32)0x10000000) -#define RCC_APB1Periph_DAC ((u32)0x20000000) -#define RCC_APB1Periph_ALL ((u32)0x3AFEC83F) - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) - -/* Clock source to output on MCO pin */ -#define RCC_MCO_NoClock ((u8)0x00) -#define RCC_MCO_SYSCLK ((u8)0x04) -#define RCC_MCO_HSI ((u8)0x05) -#define RCC_MCO_HSE ((u8)0x06) -#define RCC_MCO_PLLCLK_Div2 ((u8)0x07) - -#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2)) - -/* RCC Flag */ -#define RCC_FLAG_HSIRDY ((u8)0x21) -#define RCC_FLAG_HSERDY ((u8)0x31) -#define RCC_FLAG_PLLRDY ((u8)0x39) -#define RCC_FLAG_LSERDY ((u8)0x41) -#define RCC_FLAG_LSIRDY ((u8)0x61) -#define RCC_FLAG_PINRST ((u8)0x7A) -#define RCC_FLAG_PORRST ((u8)0x7B) -#define RCC_FLAG_SFTRST ((u8)0x7C) -#define RCC_FLAG_IWDGRST ((u8)0x7D) -#define RCC_FLAG_WWDGRST ((u8)0x7E) -#define RCC_FLAG_LPWRRST ((u8)0x7F) - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void RCC_DeInit(void); -void RCC_HSEConfig(u32 RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource); -u8 RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(u32 RCC_SYSCLK); -void RCC_PCLK1Config(u32 RCC_HCLK); -void RCC_PCLK2Config(u32 RCC_HCLK); -void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState); -void RCC_USBCLKConfig(u32 RCC_USBCLKSource); -void RCC_ADCCLKConfig(u32 RCC_PCLK2); -void RCC_LSEConfig(u8 RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(u8 RCC_MCO); -FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(u8 RCC_IT); -void RCC_ClearITPendingBit(u8 RCC_IT); - -#endif /* __STM32F10x_RCC_H */ - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3 From 255aea8bd2559833914ddc962a18f6365fabcd53 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Jun 2009 17:07:05 +0000 Subject: Modified the STM32 demo to use the bit definitions in the ST header file. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1050 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 23 ++++++++-------- demos/ARMCM3-STM32F103-GCC/board.h | 56 ++++++-------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 3e3776f4a..34349b827 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -46,28 +46,29 @@ void hwinit0(void) { * Clocks and PLL initialization. */ // HSI setup. - RCC->CR = HSITRIM_RESET_BITS | CR_HSION_MASK; - while (!(RCC->CR & CR_HSIRDY_MASK)) + RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION; + while (!(RCC->CR & RCC_CR_HSIRDY)) ; // Waits until HSI stable, it should already be. // HSE setup. - RCC->CR |= CR_HSEON_MASK; - while (!(RCC->CR & CR_HSERDY_MASK)) + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) ; // Waits until HSE stable. // PLL setup. - RCC->CFGR = PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; - RCC->CR |= CR_PLLON_MASK; - while (!(RCC->CR & CR_PLLRDY_MASK)) + RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) ; // Waits until PLL stable. // Clock sources. - RCC->CFGR |= HPRE_DIV1_BITS | PPRE1_DIV2_BITS | PPRE2_DIV2_BITS | - ADCPRE_DIV8_BITS | USBPREBITS | MCO_DISABLED_BITS; + RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 | + RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 | + RCC_CFGR_MCO_NOCLOCK | USBPREBITS; /* * Flash setup and final clock selection. */ FLASH->ACR = FLASHBITS; // Flash wait states depending on clock. - RCC->CFGR |= SW_PLL_BITS; // Switches on the PLL clock. - while ((RCC->CFGR & CFGR_SWS_MASK) != SWS_PLL_BITS) + RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock. + while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL) ; /* diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 755e6e15d..dcf8f8a33 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -28,7 +28,6 @@ #undef FALSE #undef TRUE #include "stm32f10x_map.h" -#include "stm32f10x_rcc.h" #define FALSE 0 #define TRUE (!FALSE) #endif @@ -62,62 +61,25 @@ #define PLLPREBITS ((PLLPRE - 1) << 17) #define PLLMULBITS ((PLLMUL - 2) << 18) #ifdef SYSCLK_48 - #define USBPREBITS USBPRE_DIV1_BITS + #define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS #define FLASHBITS 0x00000011 #else - #define USBPREBITS USBPRE_DIV1P5_BITS + #define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS #define FLASHBITS 0x00000012 #endif /* - * Definitions for RCC_CR register. + * Extra definitions for RCC_CR register (missing from the ST header file). */ -#define CR_HSION_MASK (0x1 << 0) -#define CR_HSIRDY_MASK (0x1 << 1) -#define CR_HSITRIM_MASK (0x1F << 3) -#define HSITRIM_RESET_BITS (0x10 << 3) -#define CR_HSICAL_MASK (0xFF << 8) -#define CR_HSEON_MASK (0x1 << 16) -#define CR_HSERDY_MASK (0x1 << 17) -#define CR_HSEBYP_MASK (0x1 << 18) -#define CR_CSSON_MASK (0x1 << 19) -#define CR_PLLON_MASK (0x1 << 24) -#define CR_PLLRDY_MASK (0x1 << 25) +#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3) /* - * Definitions for RCC_CFGR register. + * Extra definitions for RCC_CFGR register (missing from the ST header file). */ -#define CFGR_SW_MASK (0x3 << 0) -#define SW_HSI_BITS (0 << 0) -#define SW_HSE_BITS (1 << 0) -#define SW_PLL_BITS (2 << 0) -#define CFGR_SWS_MASK (0x3 << 2) -#define SWS_HSI_BITS (0 << 2) -#define SWS_HSE_BITS (1 << 2) -#define SWS_PLL_BITS (2 << 2) -#define CFGR_HPRE_MASK (0xF << 4) -#define HPRE_DIV1_BITS (0 << 4) -#define CFGR_PPRE1_MASK (0x7 << 8) -#define PPRE1_DIV1_BITS (0 << 8) -#define PPRE1_DIV2_BITS (4 << 8) -#define CFGR_PPRE2_MASK (0x7 << 11) -#define PPRE2_DIV1_BITS (0 << 11) -#define PPRE2_DIV2_BITS (4 << 11) -#define CFGR_ADCPRE_MASK (0x3 << 14) -#define ADCPRE_DIV2_BITS (0 << 14) -#define ADCPRE_DIV4_BITS (1 << 14) -#define ADCPRE_DIV6_BITS (2 << 14) -#define ADCPRE_DIV8_BITS (3 << 14) -#define CFGR_PLLSRC_MASK (0x1 << 16) -#define PLLSRC_HSI_BITS (0 << 16) -#define PLLSRC_HSE_BITS (1 << 16) -#define CFGR_PLLXTPRE_MASK (0x1 << 17) -#define CFGR_PLLMUL_MASK (0xF << 18) -#define CFGR_USBPRE_MASK (0x1 << 22) -#define USBPRE_DIV1P5_BITS (0 << 22) -#define USBPRE_DIV1_BITS (1 << 22) -#define CFGR_MCO_MASK (0x7 << 24) -#define MCO_DISABLED_BITS (0 << 24) +#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16) +#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16) +#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22) +#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22) /* * IO pins assignments. -- cgit v1.2.3 From 979da150361becdb50625d056915f81099710122 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Jul 2009 14:05:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1055 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 1 + demos/ARM7-LPC214x-GCC-minimal/board.c | 28 ++++++++++++++++++++-------- demos/ARM7-LPC214x-GCC-minimal/board.h | 2 ++ demos/ARMCM3-STM32F103-GCC/board.c | 8 ++++---- 4 files changed, 27 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 2ea142e81..a00eb9c65 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -50,6 +50,7 @@ include ../../src/kernel.mk # setting. CSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/pal_lld.c \ ${KERNSRC} \ board.c main.c diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index 2e56028cc..980626ab5 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -58,6 +58,18 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_EPILOGUE(); } +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const LPC214xFIOConfig config = +{ + VAL_PINSEL0, + VAL_PINSEL1, + VAL_PINSEL2, + {VAL_FIO0PIN, VAL_FIO0DIR}, + {VAL_FIO1PIN, VAL_FIO1DIR} +}; + /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -101,14 +113,14 @@ void hwinit0(void) { /* * I/O pins configuration. */ - PINSEL0 = VAL_PINSEL0; - PINSEL1 = VAL_PINSEL1; - PINSEL2 = VAL_PINSEL2; - palInit(); - pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); - palWritePort(IOPORT_A, 0xFFFFFFFF); - pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); - palWritePort(IOPORT_B, 0xFFFFFFFF); +// PINSEL0 = VAL_PINSEL0; +// PINSEL1 = VAL_PINSEL1; +// PINSEL2 = VAL_PINSEL2; + palInit(&config); +// pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); +// palWritePort(IOPORT_A, 0xFFFFFFFF); +// pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); +// palWritePort(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h index fee4baa61..ab4aa76f6 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.h +++ b/demos/ARM7-LPC214x-GCC-minimal/board.h @@ -64,6 +64,8 @@ #define VAL_PINSEL2 0x00000004 #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 +#define VAL_FIO0PIN 0x00000000 +#define VAL_FIO1PIN 0x00000000 #define PA_LED1 10 #define PA_LED2 11 diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 34349b827..0f6c5be6b 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -29,10 +29,10 @@ */ static const STM32GPIOConfig config = { - {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, - {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, - {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, - {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, }; /* -- cgit v1.2.3 From 2b5e0544c8285976d94abe21268342698c94dd85 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 4 Jul 2009 15:33:21 +0000 Subject: Completed PAL support for LPC214x. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1056 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 1 + demos/ARM7-LPC214x-G++/board.c | 21 +++++++++++++-------- demos/ARM7-LPC214x-G++/board.h | 4 ++-- demos/ARM7-LPC214x-GCC-minimal/board.c | 7 ------- demos/ARM7-LPC214x-GCC-minimal/board.h | 6 ++---- demos/ARM7-LPC214x-GCC/Makefile | 1 + demos/ARM7-LPC214x-GCC/board.c | 21 +++++++++++++-------- demos/ARM7-LPC214x-GCC/board.h | 4 ++-- 8 files changed, 34 insertions(+), 31 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 24a8ce684..894a37e61 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -50,6 +50,7 @@ include ../../test/test.mk # setting. CSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/pal_lld.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ${KERNSRC} \ ${TESTSRC} \ diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index c3c39a5a9..68b060dbd 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -58,6 +58,18 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_EPILOGUE(); } +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const LPC214xFIOConfig config = +{ + VAL_PINSEL0, + VAL_PINSEL1, + VAL_PINSEL2, + {VAL_FIO0PIN, VAL_FIO0DIR}, + {VAL_FIO1PIN, VAL_FIO1DIR} +}; + /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -101,14 +113,7 @@ void hwinit0(void) { /* * I/O pins configuration. */ - PINSEL0 = VAL_PINSEL0; - PINSEL1 = VAL_PINSEL1; - PINSEL2 = VAL_PINSEL2; - palInit(); - pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); - palWritePort(IOPORT_A, 0xFFFFFFFF); - pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); - palWritePort(IOPORT_B, 0xFFFFFFFF); + palInit(&config); } /* diff --git a/demos/ARM7-LPC214x-G++/board.h b/demos/ARM7-LPC214x-G++/board.h index fee4baa61..022383032 100644 --- a/demos/ARM7-LPC214x-G++/board.h +++ b/demos/ARM7-LPC214x-G++/board.h @@ -20,9 +20,7 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#ifndef _LPC214X_H_ #include "lpc214x.h" -#endif #define BOARD_OLIMEX_LCP_P2148 @@ -64,6 +62,8 @@ #define VAL_PINSEL2 0x00000004 #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 +#define VAL_FIO0PIN 0xFFFFFFFF +#define VAL_FIO1PIN 0xFFFFFFFF #define PA_LED1 10 #define PA_LED2 11 diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index 980626ab5..95732cfef 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -113,14 +113,7 @@ void hwinit0(void) { /* * I/O pins configuration. */ -// PINSEL0 = VAL_PINSEL0; -// PINSEL1 = VAL_PINSEL1; -// PINSEL2 = VAL_PINSEL2; palInit(&config); -// pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); -// palWritePort(IOPORT_A, 0xFFFFFFFF); -// pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); -// palWritePort(IOPORT_B, 0xFFFFFFFF); } /* diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h index ab4aa76f6..022383032 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.h +++ b/demos/ARM7-LPC214x-GCC-minimal/board.h @@ -20,9 +20,7 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#ifndef _LPC214X_H_ #include "lpc214x.h" -#endif #define BOARD_OLIMEX_LCP_P2148 @@ -64,8 +62,8 @@ #define VAL_PINSEL2 0x00000004 #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 -#define VAL_FIO0PIN 0x00000000 -#define VAL_FIO1PIN 0x00000000 +#define VAL_FIO0PIN 0xFFFFFFFF +#define VAL_FIO1PIN 0xFFFFFFFF #define PA_LED1 10 #define PA_LED2 11 diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index c7bf868ef..2185bbe94 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -50,6 +50,7 @@ include ../../test/test.mk # setting. CSRC = ../../ports/ARM7/chcore.c \ ../../ports/ARM7-LPC214x/vic.c \ + ../../ports/ARM7-LPC214x/pal_lld.c \ ../../ports/ARM7-LPC214x/lpc214x_serial.c \ ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ ${KERNSRC} \ diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 9eec8b06d..8be258a1a 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -58,6 +58,18 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_EPILOGUE(); } +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const LPC214xFIOConfig config = +{ + VAL_PINSEL0, + VAL_PINSEL1, + VAL_PINSEL2, + {VAL_FIO0PIN, VAL_FIO0DIR}, + {VAL_FIO1PIN, VAL_FIO1DIR} +}; + /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -101,14 +113,7 @@ void hwinit0(void) { /* * I/O pins configuration. */ - PINSEL0 = VAL_PINSEL0; - PINSEL1 = VAL_PINSEL1; - PINSEL2 = VAL_PINSEL2; - palInit(); - pal_lld_lpc214x_set_direction(IOPORT_A, VAL_FIO0DIR); - palWritePort(IOPORT_A, 0xFFFFFFFF); - pal_lld_lpc214x_set_direction(IOPORT_B, VAL_FIO1DIR); - palWritePort(IOPORT_B, 0xFFFFFFFF); + palInit(&config); } /* diff --git a/demos/ARM7-LPC214x-GCC/board.h b/demos/ARM7-LPC214x-GCC/board.h index fee4baa61..022383032 100644 --- a/demos/ARM7-LPC214x-GCC/board.h +++ b/demos/ARM7-LPC214x-GCC/board.h @@ -20,9 +20,7 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#ifndef _LPC214X_H_ #include "lpc214x.h" -#endif #define BOARD_OLIMEX_LCP_P2148 @@ -64,6 +62,8 @@ #define VAL_PINSEL2 0x00000004 #define VAL_FIO0DIR 0xB0703C00 #define VAL_FIO1DIR 0x00000000 +#define VAL_FIO0PIN 0xFFFFFFFF +#define VAL_FIO1PIN 0xFFFFFFFF #define PA_LED1 10 #define PA_LED2 11 -- cgit v1.2.3 From 43def70685c2b8cfc998a4a906d6b209aeb974ac Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 11 Jul 2009 14:36:20 +0000 Subject: Completed PAL support for AT91SAM7X. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1057 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 1 + demos/ARM7-AT91SAM7X-GCC/board.c | 33 ++++++++++++++++++++++----------- demos/ARM7-AT91SAM7X-GCC/board.h | 13 +++++++++++-- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 1 + demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 33 ++++++++++++++++++++++----------- demos/ARM7-AT91SAM7X-WEB-GCC/board.h | 13 +++++++++++-- demos/ARMCM3-STM32F103-GCC/board.c | 2 +- 7 files changed, 69 insertions(+), 27 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 728167a6d..db19978c8 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -49,6 +49,7 @@ include ../../test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-AT91SAM7X/pal_lld.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ${KERNSRC} \ ${TESTSRC} \ diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 02ac5046d..aac51cf0c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -57,6 +57,15 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_EPILOGUE(); } +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const AT91SAM7XPIOConfig config = +{ + {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, + {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +}; + /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -100,7 +109,7 @@ void hwinit0(void) { /* * PIO initialization. */ - palInit(); + palInit(&config); } /* @@ -126,24 +135,26 @@ void hwinit1(void) { * LCD pins setup. */ palClearPad(IOPORT_B, PIOB_LCD_BL); - AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL_MASK; // Configure as output. - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL_MASK; // Disable internal pullup resistor. + palSetPadMode(IOPORT_B, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); palSetPad(IOPORT_A, PIOA_LCD_RESET); - AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET_MASK; // Configure as output. - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET_MASK; // Disable internal pullup resistor. + palSetPadMode(IOPORT_A, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); /* - * Joystick and buttons, disable pullups, already inputs. + * Joystick and buttons setup. */ - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | - PIOA_B4_MASK | PIOA_B5_MASK; - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1_MASK | PIOB_SW2_MASK; + palSetGroupMode(IOPORT_A, + PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | + PIOA_B4_MASK | PIOA_B5_MASK, + PAL_MODE_INPUT); + palSetGroupMode(IOPORT_B, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); /* - * MMC/SD slot, disable pullups, already inputs. + * MMC/SD slot setup. */ - AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK; + palSetGroupMode(IOPORT_B, + PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, + PAL_MODE_INPUT); /* * PIT Initialization. diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h index fe9219aa3..c56f50258 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -20,15 +20,24 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#ifndef AT91SAM7X256_H #include "at91lib/AT91SAM7X256.h" -#endif #define BOARD_OLIMEX_SAM7_EX256 #define CLK 18432000 #define MCK 48054857 +/* + * Initial I/O setup. + */ +#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOA_OSR 0x00000000 /* Direction. */ +#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ + +#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOB_OSR 0x00000000 /* Direction. */ +#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ + /* * I/O definitions. */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index c9a08306a..4b0aad5a1 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -58,6 +58,7 @@ USRC = ../../ext/uip-1.0/uip/uip_arp.c \ # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ../../ports/ARM7/chcore.c \ + ../../ports/ARM7-AT91SAM7X/pal_lld.c \ ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ ${KERNSRC} \ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index e0b170120..4557d3c91 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -58,6 +58,15 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_EPILOGUE(); } +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const AT91SAM7XPIOConfig config = +{ + {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, + {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +}; + /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -101,7 +110,7 @@ void hwinit0(void) { /* * PIO initialization. */ - palInit(); + palInit(&config); } /* @@ -127,24 +136,26 @@ void hwinit1(void) { * LCD pins setup. */ palClearPad(IOPORT_B, PIOB_LCD_BL); - AT91C_BASE_PIOB->PIO_OER = PIOB_LCD_BL_MASK; // Configure as output. - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_LCD_BL_MASK; // Disable internal pullup resistor. + palSetPadMode(IOPORT_B, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); palSetPad(IOPORT_A, PIOA_LCD_RESET); - AT91C_BASE_PIOA->PIO_OER = PIOA_LCD_RESET_MASK; // Configure as output. - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_LCD_RESET_MASK; // Disable internal pullup resistor. + palSetPadMode(IOPORT_A, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); /* - * Joystick and buttons, disable pullups, already inputs. + * Joystick and buttons setup. */ - AT91C_BASE_PIOA->PIO_PPUDR = PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | - PIOA_B4_MASK | PIOA_B5_MASK; - AT91C_BASE_PIOB->PIO_PPUDR = PIOB_SW1_MASK | PIOB_SW2_MASK; + palSetGroupMode(IOPORT_A, + PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | + PIOA_B4_MASK | PIOA_B5_MASK, + PAL_MODE_INPUT); + palSetGroupMode(IOPORT_B, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); /* - * MMC/SD slot, disable pullups, already inputs. + * MMC/SD slot setup. */ - AT91C_BASE_SYS->PIOB_PPUDR = PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK; + palSetGroupMode(IOPORT_B, + PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, + PAL_MODE_INPUT); /* * PIT Initialization. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.h b/demos/ARM7-AT91SAM7X-WEB-GCC/board.h index fe9219aa3..c56f50258 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.h @@ -20,15 +20,24 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#ifndef AT91SAM7X256_H #include "at91lib/AT91SAM7X256.h" -#endif #define BOARD_OLIMEX_SAM7_EX256 #define CLK 18432000 #define MCK 48054857 +/* + * Initial I/O setup. + */ +#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOA_OSR 0x00000000 /* Direction. */ +#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ + +#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOB_OSR 0x00000000 /* Direction. */ +#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ + /* * I/O definitions. */ diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 0f6c5be6b..25b88511f 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -32,7 +32,7 @@ static const STM32GPIOConfig config = {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, - {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH} }; /* -- cgit v1.2.3 From 4a35a0cd1ba60a4639356ed988cd17ed41f2bd2b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 11 Jul 2009 14:48:38 +0000 Subject: Removed some test code from a file. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1059 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/main.c | 26 -------------------------- 1 file changed, 26 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index f599c3e73..f89131d37 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -24,8 +24,6 @@ #include "board.h" #include "stm32_serial.h" -static IOBUS_DECL(LedBus, IOPORT_C, 1, GPIOC_LED); - /* * Red LEDs blinker thread, times are in milliseconds. */ @@ -37,30 +35,6 @@ static msg_t Thread1(void *arg) { chThdSleepMilliseconds(500); palSetPad(IOPORT_C, GPIOC_LED); chThdSleepMilliseconds(500); - palTogglePad(IOPORT_C, GPIOC_LED); - chThdSleepMilliseconds(500); - palTogglePad(IOPORT_C, GPIOC_LED); - chThdSleepMilliseconds(500); - palWritePad(IOPORT_C, GPIOC_LED, PAL_LOW); - chThdSleepMilliseconds(500); - palWritePad(IOPORT_C, GPIOC_LED, PAL_HIGH); - chThdSleepMilliseconds(500); - palWriteGroup(IOPORT_C, 1, GPIOC_LED, PAL_LOW); - chThdSleepMilliseconds(500); - palWriteGroup(IOPORT_C, 1, GPIOC_LED, PAL_HIGH); - chThdSleepMilliseconds(500); - palClearPort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); - chThdSleepMilliseconds(500); - palSetPort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); - chThdSleepMilliseconds(500); - palTogglePort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); - chThdSleepMilliseconds(500); - palTogglePort(IOPORT_C, PAL_PORT_BIT(GPIOC_LED)); - chThdSleepMilliseconds(500); - palWriteBus(&LedBus, PAL_LOW); - chThdSleepMilliseconds(500); - palWriteBus(&LedBus, PAL_HIGH); - chThdSleepMilliseconds(500); } return 0; } -- cgit v1.2.3 From 6d390a7c46baaea0ca99efb09fb872ceea37623e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 18 Jul 2009 11:50:53 +0000 Subject: Removed obsolete ST library files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1062 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../stm32lib/inc/cortexm3_macro.h | 53 - .../stm32lib/inc/stm32f10x_conf.h | 174 - .../stm32lib/inc/stm32f10x_map.h | 7603 -------------------- .../stm32lib/inc/stm32f10x_nvic.h | 287 - .../stm32lib/inc/stm32f10x_type.h | 80 - 5 files changed, 8197 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h deleted file mode 100644 index b26807f92..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/cortexm3_macro.h +++ /dev/null @@ -1,53 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : cortexm3_macro.h -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : Header file for cortexm3_macro.s. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __CORTEXM3_MACRO_H -#define __CORTEXM3_MACRO_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_type.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void __WFI(void); -void __WFE(void); -void __SEV(void); -void __ISB(void); -void __DSB(void); -void __DMB(void); -void __SVC(void); -u32 __MRS_CONTROL(void); -void __MSR_CONTROL(u32 Control); -u32 __MRS_PSP(void); -void __MSR_PSP(u32 TopOfProcessStack); -u32 __MRS_MSP(void); -void __MSR_MSP(u32 TopOfMainStack); -void __RESETPRIMASK(void); -void __SETPRIMASK(void); -u32 __READ_PRIMASK(void); -void __RESETFAULTMASK(void); -void __SETFAULTMASK(void); -u32 __READ_FAULTMASK(void); -void __BASEPRICONFIG(u32 NewPriority); -u32 __GetBASEPRI(void); -u16 __REV_HalfWord(u16 Data); -u32 __REV_Word(u32 Data); - -#endif /* __CORTEXM3_MACRO_H */ - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h deleted file mode 100644 index 3bfc763f4..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h +++ /dev/null @@ -1,174 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : stm32f10x_conf.h -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : Library configuration file. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CONF_H -#define __STM32F10x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_type.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to compile the library in DEBUG mode, this will expanse - the "assert_param" macro in the firmware library code (see "Exported macro" - section below) */ -/*#define DEBUG 1*/ - -/* Comment the line below to disable the specific peripheral inclusion */ -/************************************* ADC ************************************/ -#define _ADC -#define _ADC1 -//#define _ADC2 -//#define _ADC3 - -/************************************* BKP ************************************/ -#define _BKP - -/************************************* CAN ************************************/ -#define _CAN - -/************************************* CRC ************************************/ -#define _CRC - -/************************************* DAC ************************************/ -#define _DAC - -/************************************* DBGMCU *********************************/ -#define _DBGMCU - -/************************************* DMA ************************************/ -#define _DMA -//#define _DMA1_Channel1 -//#define _DMA1_Channel2 -//#define _DMA1_Channel3 -//#define _DMA1_Channel4 -//#define _DMA1_Channel5 -//#define _DMA1_Channel6 -//#define _DMA1_Channel7 -//#define _DMA2_Channel1 -//#define _DMA2_Channel2 -//#define _DMA2_Channel3 -//#define _DMA2_Channel4 -//#define _DMA2_Channel5 - -/************************************* EXTI ***********************************/ -#define _EXTI - -/************************************* FLASH and Option Bytes *****************/ -#define _FLASH -/* Uncomment the line below to enable FLASH program/erase/protections functions, - otherwise only FLASH configuration (latency, prefetch, half cycle) functions - are enabled */ -/* #define _FLASH_PROG */ - -/************************************* FSMC ***********************************/ -#define _FSMC - -/************************************* GPIO ***********************************/ -#define _GPIO -#define _GPIOA -#define _GPIOB -#define _GPIOC -#define _GPIOD -//#define _GPIOE -//#define _GPIOF -//#define _GPIOG -#define _AFIO - -/************************************* I2C ************************************/ -//#define _I2C -//#define _I2C1 -//#define _I2C2 - -/************************************* IWDG ***********************************/ -#define _IWDG - -/************************************* NVIC ***********************************/ -#define _NVIC - -/************************************* PWR ************************************/ -#define _PWR - -/************************************* RCC ************************************/ -#define _RCC - -/************************************* RTC ************************************/ -#define _RTC - -/************************************* SDIO ***********************************/ -#define _SDIO - -/************************************* SPI ************************************/ -//#define _SPI -//#define _SPI1 -//#define _SPI2 -//#define _SPI3 - -/************************************* SysTick ********************************/ -#define _SysTick - -/************************************* TIM ************************************/ -//#define _TIM -//#define _TIM1 -//#define _TIM2 -//#define _TIM3 -//#define _TIM4 -//#define _TIM5 -//#define _TIM6 -//#define _TIM7 -//#define _TIM8 - -/************************************* USART **********************************/ -#define _USART -#define _USART1 -#define _USART2 -#define _USART3 -//#define _UART4 -//#define _UART5 - -/************************************* WWDG ***********************************/ -#define _WWDG - -/* In the following line adjust the value of External High Speed oscillator (HSE) - used in your application */ -#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ - -/* In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value */ -#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef DEBUG -/******************************************************************************* -* Macro Name : assert_param -* Description : The assert_param macro is used for function's parameters check. -* It is used only if the library is compiled in DEBUG mode. -* Input : - expr: If expr is false, it calls assert_failed function -* which reports the name of the source file and the source -* line number of the call that failed. -* If expr is true, it returns no value. -* Return : None -*******************************************************************************/ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(u8* file, u32 line); -#else - #define assert_param(expr) ((void)0) -#endif /* DEBUG */ - -#endif /* __STM32F10x_CONF_H */ - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h deleted file mode 100644 index 851dff410..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_map.h +++ /dev/null @@ -1,7603 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : stm32f10x_map.h -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : This file contains all the peripheral register's definitions, -* bits definitions and memory mapping. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_MAP_H -#define __STM32F10x_MAP_H - -#ifndef EXT - #define EXT extern -#endif /* EXT */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_conf.h" -#include "stm32f10x_type.h" -#include "cortexm3_macro.h" - -/* Exported types ------------------------------------------------------------*/ -/******************************************************************************/ -/* Peripheral registers structures */ -/******************************************************************************/ - -/*------------------------ Analog to Digital Converter -----------------------*/ -typedef struct -{ - vu32 SR; - vu32 CR1; - vu32 CR2; - vu32 SMPR1; - vu32 SMPR2; - vu32 JOFR1; - vu32 JOFR2; - vu32 JOFR3; - vu32 JOFR4; - vu32 HTR; - vu32 LTR; - vu32 SQR1; - vu32 SQR2; - vu32 SQR3; - vu32 JSQR; - vu32 JDR1; - vu32 JDR2; - vu32 JDR3; - vu32 JDR4; - vu32 DR; -} ADC_TypeDef; - -/*------------------------ Backup Registers ----------------------------------*/ -typedef struct -{ - u32 RESERVED0; - vu16 DR1; - u16 RESERVED1; - vu16 DR2; - u16 RESERVED2; - vu16 DR3; - u16 RESERVED3; - vu16 DR4; - u16 RESERVED4; - vu16 DR5; - u16 RESERVED5; - vu16 DR6; - u16 RESERVED6; - vu16 DR7; - u16 RESERVED7; - vu16 DR8; - u16 RESERVED8; - vu16 DR9; - u16 RESERVED9; - vu16 DR10; - u16 RESERVED10; - vu16 RTCCR; - u16 RESERVED11; - vu16 CR; - u16 RESERVED12; - vu16 CSR; - u16 RESERVED13[5]; - vu16 DR11; - u16 RESERVED14; - vu16 DR12; - u16 RESERVED15; - vu16 DR13; - u16 RESERVED16; - vu16 DR14; - u16 RESERVED17; - vu16 DR15; - u16 RESERVED18; - vu16 DR16; - u16 RESERVED19; - vu16 DR17; - u16 RESERVED20; - vu16 DR18; - u16 RESERVED21; - vu16 DR19; - u16 RESERVED22; - vu16 DR20; - u16 RESERVED23; - vu16 DR21; - u16 RESERVED24; - vu16 DR22; - u16 RESERVED25; - vu16 DR23; - u16 RESERVED26; - vu16 DR24; - u16 RESERVED27; - vu16 DR25; - u16 RESERVED28; - vu16 DR26; - u16 RESERVED29; - vu16 DR27; - u16 RESERVED30; - vu16 DR28; - u16 RESERVED31; - vu16 DR29; - u16 RESERVED32; - vu16 DR30; - u16 RESERVED33; - vu16 DR31; - u16 RESERVED34; - vu16 DR32; - u16 RESERVED35; - vu16 DR33; - u16 RESERVED36; - vu16 DR34; - u16 RESERVED37; - vu16 DR35; - u16 RESERVED38; - vu16 DR36; - u16 RESERVED39; - vu16 DR37; - u16 RESERVED40; - vu16 DR38; - u16 RESERVED41; - vu16 DR39; - u16 RESERVED42; - vu16 DR40; - u16 RESERVED43; - vu16 DR41; - u16 RESERVED44; - vu16 DR42; - u16 RESERVED45; -} BKP_TypeDef; - -/*------------------------ Controller Area Network ---------------------------*/ -typedef struct -{ - vu32 TIR; - vu32 TDTR; - vu32 TDLR; - vu32 TDHR; -} CAN_TxMailBox_TypeDef; - -typedef struct -{ - vu32 RIR; - vu32 RDTR; - vu32 RDLR; - vu32 RDHR; -} CAN_FIFOMailBox_TypeDef; - -typedef struct -{ - vu32 FR1; - vu32 FR2; -} CAN_FilterRegister_TypeDef; - -typedef struct -{ - vu32 MCR; - vu32 MSR; - vu32 TSR; - vu32 RF0R; - vu32 RF1R; - vu32 IER; - vu32 ESR; - vu32 BTR; - u32 RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - u32 RESERVED1[12]; - vu32 FMR; - vu32 FM1R; - u32 RESERVED2; - vu32 FS1R; - u32 RESERVED3; - vu32 FFA1R; - u32 RESERVED4; - vu32 FA1R; - u32 RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[14]; -} CAN_TypeDef; - -/*------------------------ CRC calculation unit ------------------------------*/ -typedef struct -{ - vu32 DR; - vu8 IDR; - u8 RESERVED0; - u16 RESERVED1; - vu32 CR; -} CRC_TypeDef; - - -/*------------------------ Digital to Analog Converter -----------------------*/ -typedef struct -{ - vu32 CR; - vu32 SWTRIGR; - vu32 DHR12R1; - vu32 DHR12L1; - vu32 DHR8R1; - vu32 DHR12R2; - vu32 DHR12L2; - vu32 DHR8R2; - vu32 DHR12RD; - vu32 DHR12LD; - vu32 DHR8RD; - vu32 DOR1; - vu32 DOR2; -} DAC_TypeDef; - -/*------------------------ Debug MCU -----------------------------------------*/ -typedef struct -{ - vu32 IDCODE; - vu32 CR; -}DBGMCU_TypeDef; - -/*------------------------ DMA Controller ------------------------------------*/ -typedef struct -{ - vu32 CCR; - vu32 CNDTR; - vu32 CPAR; - vu32 CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - vu32 ISR; - vu32 IFCR; -} DMA_TypeDef; - -/*------------------------ External Interrupt/Event Controller ---------------*/ -typedef struct -{ - vu32 IMR; - vu32 EMR; - vu32 RTSR; - vu32 FTSR; - vu32 SWIER; - vu32 PR; -} EXTI_TypeDef; - -/*------------------------ FLASH and Option Bytes Registers ------------------*/ -typedef struct -{ - vu32 ACR; - vu32 KEYR; - vu32 OPTKEYR; - vu32 SR; - vu32 CR; - vu32 AR; - vu32 RESERVED; - vu32 OBR; - vu32 WRPR; -} FLASH_TypeDef; - -typedef struct -{ - vu16 RDP; - vu16 USER; - vu16 Data0; - vu16 Data1; - vu16 WRP0; - vu16 WRP1; - vu16 WRP2; - vu16 WRP3; -} OB_TypeDef; - -/*------------------------ Flexible Static Memory Controller -----------------*/ -typedef struct -{ - vu32 BTCR[8]; -} FSMC_Bank1_TypeDef; - -typedef struct -{ - vu32 BWTR[7]; -} FSMC_Bank1E_TypeDef; - -typedef struct -{ - vu32 PCR2; - vu32 SR2; - vu32 PMEM2; - vu32 PATT2; - u32 RESERVED0; - vu32 ECCR2; -} FSMC_Bank2_TypeDef; - -typedef struct -{ - vu32 PCR3; - vu32 SR3; - vu32 PMEM3; - vu32 PATT3; - u32 RESERVED0; - vu32 ECCR3; -} FSMC_Bank3_TypeDef; - -typedef struct -{ - vu32 PCR4; - vu32 SR4; - vu32 PMEM4; - vu32 PATT4; - vu32 PIO4; -} FSMC_Bank4_TypeDef; - -/*------------------------ General Purpose and Alternate Function IO ---------*/ -typedef struct -{ - vu32 CRL; - vu32 CRH; - vu32 IDR; - vu32 ODR; - vu32 BSRR; - vu32 BRR; - vu32 LCKR; -} GPIO_TypeDef; - -typedef struct -{ - vu32 EVCR; - vu32 MAPR; - vu32 EXTICR[4]; -} AFIO_TypeDef; - -/*------------------------ Inter-integrated Circuit Interface ----------------*/ -typedef struct -{ - vu16 CR1; - u16 RESERVED0; - vu16 CR2; - u16 RESERVED1; - vu16 OAR1; - u16 RESERVED2; - vu16 OAR2; - u16 RESERVED3; - vu16 DR; - u16 RESERVED4; - vu16 SR1; - u16 RESERVED5; - vu16 SR2; - u16 RESERVED6; - vu16 CCR; - u16 RESERVED7; - vu16 TRISE; - u16 RESERVED8; -} I2C_TypeDef; - -/*------------------------ Independent WATCHDOG ------------------------------*/ -typedef struct -{ - vu32 KR; - vu32 PR; - vu32 RLR; - vu32 SR; -} IWDG_TypeDef; - -/*------------------------ Nested Vectored Interrupt Controller --------------*/ -typedef struct -{ - vu32 ISER[2]; - u32 RESERVED0[30]; - vu32 ICER[2]; - u32 RSERVED1[30]; - vu32 ISPR[2]; - u32 RESERVED2[30]; - vu32 ICPR[2]; - u32 RESERVED3[30]; - vu32 IABR[2]; - u32 RESERVED4[62]; - vu32 IPR[15]; -} NVIC_TypeDef; - -typedef struct -{ - vuc32 CPUID; - vu32 ICSR; - vu32 VTOR; - vu32 AIRCR; - vu32 SCR; - vu32 CCR; - vu32 SHPR[3]; - vu32 SHCSR; - vu32 CFSR; - vu32 HFSR; - vu32 DFSR; - vu32 MMFAR; - vu32 BFAR; - vu32 AFSR; -} SCB_TypeDef; - -/*------------------------ Power Control -------------------------------------*/ -typedef struct -{ - vu32 CR; - vu32 CSR; -} PWR_TypeDef; - -/*------------------------ Reset and Clock Control ---------------------------*/ -typedef struct -{ - vu32 CR; - vu32 CFGR; - vu32 CIR; - vu32 APB2RSTR; - vu32 APB1RSTR; - vu32 AHBENR; - vu32 APB2ENR; - vu32 APB1ENR; - vu32 BDCR; - vu32 CSR; -} RCC_TypeDef; - -/*------------------------ Real-Time Clock -----------------------------------*/ -typedef struct -{ - vu16 CRH; - u16 RESERVED0; - vu16 CRL; - u16 RESERVED1; - vu16 PRLH; - u16 RESERVED2; - vu16 PRLL; - u16 RESERVED3; - vu16 DIVH; - u16 RESERVED4; - vu16 DIVL; - u16 RESERVED5; - vu16 CNTH; - u16 RESERVED6; - vu16 CNTL; - u16 RESERVED7; - vu16 ALRH; - u16 RESERVED8; - vu16 ALRL; - u16 RESERVED9; -} RTC_TypeDef; - -/*------------------------ SD host Interface ---------------------------------*/ -typedef struct -{ - vu32 POWER; - vu32 CLKCR; - vu32 ARG; - vu32 CMD; - vuc32 RESPCMD; - vuc32 RESP1; - vuc32 RESP2; - vuc32 RESP3; - vuc32 RESP4; - vu32 DTIMER; - vu32 DLEN; - vu32 DCTRL; - vuc32 DCOUNT; - vuc32 STA; - vu32 ICR; - vu32 MASK; - u32 RESERVED0[2]; - vuc32 FIFOCNT; - u32 RESERVED1[13]; - vu32 FIFO; -} SDIO_TypeDef; - -/*------------------------ Serial Peripheral Interface -----------------------*/ -typedef struct -{ - vu16 CR1; - u16 RESERVED0; - vu16 CR2; - u16 RESERVED1; - vu16 SR; - u16 RESERVED2; - vu16 DR; - u16 RESERVED3; - vu16 CRCPR; - u16 RESERVED4; - vu16 RXCRCR; - u16 RESERVED5; - vu16 TXCRCR; - u16 RESERVED6; - vu16 I2SCFGR; - u16 RESERVED7; - vu16 I2SPR; - u16 RESERVED8; -} SPI_TypeDef; - -/*------------------------ SystemTick ----------------------------------------*/ -typedef struct -{ - vu32 CTRL; - vu32 LOAD; - vu32 VAL; - vuc32 CALIB; -} SysTick_TypeDef; - -/*------------------------ TIM -----------------------------------------------*/ -typedef struct -{ - vu16 CR1; - u16 RESERVED0; - vu16 CR2; - u16 RESERVED1; - vu16 SMCR; - u16 RESERVED2; - vu16 DIER; - u16 RESERVED3; - vu16 SR; - u16 RESERVED4; - vu16 EGR; - u16 RESERVED5; - vu16 CCMR1; - u16 RESERVED6; - vu16 CCMR2; - u16 RESERVED7; - vu16 CCER; - u16 RESERVED8; - vu16 CNT; - u16 RESERVED9; - vu16 PSC; - u16 RESERVED10; - vu16 ARR; - u16 RESERVED11; - vu16 RCR; - u16 RESERVED12; - vu16 CCR1; - u16 RESERVED13; - vu16 CCR2; - u16 RESERVED14; - vu16 CCR3; - u16 RESERVED15; - vu16 CCR4; - u16 RESERVED16; - vu16 BDTR; - u16 RESERVED17; - vu16 DCR; - u16 RESERVED18; - vu16 DMAR; - u16 RESERVED19; -} TIM_TypeDef; - -/*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ -typedef struct -{ - vu16 SR; - u16 RESERVED0; - vu16 DR; - u16 RESERVED1; - vu16 BRR; - u16 RESERVED2; - vu16 CR1; - u16 RESERVED3; - vu16 CR2; - u16 RESERVED4; - vu16 CR3; - u16 RESERVED5; - vu16 GTPR; - u16 RESERVED6; -} USART_TypeDef; - -/*------------------------ Window WATCHDOG -----------------------------------*/ -typedef struct -{ - vu32 CR; - vu32 CFR; - vu32 SR; -} WWDG_TypeDef; - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Peripheral and SRAM base address in the alias region */ -#define PERIPH_BB_BASE ((u32)0x42000000) -#define SRAM_BB_BASE ((u32)0x22000000) - -/* Peripheral and SRAM base address in the bit-band region */ -#define SRAM_BASE ((u32)0x20000000) -#define PERIPH_BASE ((u32)0x40000000) - -/* FSMC registers base address */ -#define FSMC_R_BASE ((u32)0xA0000000) - -/* Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN_BASE (APB1PERIPH_BASE + 0x6400) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -/* Flash registers base address */ -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) -/* Flash Option Bytes base address */ -#define OB_BASE ((u32)0x1FFFF800) - -/* FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((u32)0xE0042000) - -/* System Control Space memory map */ -#define SCS_BASE ((u32)0xE000E000) - -#define SysTick_BASE (SCS_BASE + 0x0010) -#define NVIC_BASE (SCS_BASE + 0x0100) -#define SCB_BASE (SCS_BASE + 0x0D00) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ - -/*------------------------ Non Debug Mode ------------------------------------*/ -#ifndef DEBUG -#ifdef _TIM2 - #define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#endif /*_TIM2 */ - -#ifdef _TIM3 - #define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#endif /*_TIM3 */ - -#ifdef _TIM4 - #define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#endif /*_TIM4 */ - -#ifdef _TIM5 - #define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#endif /*_TIM5 */ - -#ifdef _TIM6 - #define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#endif /*_TIM6 */ - -#ifdef _TIM7 - #define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#endif /*_TIM7 */ - -#ifdef _RTC - #define RTC ((RTC_TypeDef *) RTC_BASE) -#endif /*_RTC */ - -#ifdef _WWDG - #define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#endif /*_WWDG */ - -#ifdef _IWDG - #define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#endif /*_IWDG */ - -#ifdef _SPI2 - #define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#endif /*_SPI2 */ - -#ifdef _SPI3 - #define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#endif /*_SPI3 */ - -#ifdef _USART2 - #define USART2 ((USART_TypeDef *) USART2_BASE) -#endif /*_USART2 */ - -#ifdef _USART3 - #define USART3 ((USART_TypeDef *) USART3_BASE) -#endif /*_USART3 */ - -#ifdef _UART4 - #define UART4 ((USART_TypeDef *) UART4_BASE) -#endif /*_UART4 */ - -#ifdef _UART5 - #define UART5 ((USART_TypeDef *) UART5_BASE) -#endif /*_USART5 */ - -#ifdef _I2C1 - #define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#endif /*_I2C1 */ - -#ifdef _I2C2 - #define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#endif /*_I2C2 */ - -#ifdef _CAN - #define CAN ((CAN_TypeDef *) CAN_BASE) -#endif /*_CAN */ - -#ifdef _BKP - #define BKP ((BKP_TypeDef *) BKP_BASE) -#endif /*_BKP */ - -#ifdef _PWR - #define PWR ((PWR_TypeDef *) PWR_BASE) -#endif /*_PWR */ - -#ifdef _DAC - #define DAC ((DAC_TypeDef *) DAC_BASE) -#endif /*_DAC */ - -#ifdef _AFIO - #define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#endif /*_AFIO */ - -#ifdef _EXTI - #define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#endif /*_EXTI */ - -#ifdef _GPIOA - #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#endif /*_GPIOA */ - -#ifdef _GPIOB - #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#endif /*_GPIOB */ - -#ifdef _GPIOC - #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#endif /*_GPIOC */ - -#ifdef _GPIOD - #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#endif /*_GPIOD */ - -#ifdef _GPIOE - #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#endif /*_GPIOE */ - -#ifdef _GPIOF - #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#endif /*_GPIOF */ - -#ifdef _GPIOG - #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#endif /*_GPIOG */ - -#ifdef _ADC1 - #define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#endif /*_ADC1 */ - -#ifdef _ADC2 - #define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#endif /*_ADC2 */ - -#ifdef _TIM1 - #define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#endif /*_TIM1 */ - -#ifdef _SPI1 - #define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#endif /*_SPI1 */ - -#ifdef _TIM8 - #define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#endif /*_TIM8 */ - -#ifdef _USART1 - #define USART1 ((USART_TypeDef *) USART1_BASE) -#endif /*_USART1 */ - -#ifdef _ADC3 - #define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#endif /*_ADC3 */ - -#ifdef _SDIO - #define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#endif /*_SDIO */ - -#ifdef _DMA - #define DMA1 ((DMA_TypeDef *) DMA1_BASE) - #define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#endif /*_DMA */ - -#ifdef _DMA1_Channel1 - #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#endif /*_DMA1_Channel1 */ - -#ifdef _DMA1_Channel2 - #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#endif /*_DMA1_Channel2 */ - -#ifdef _DMA1_Channel3 - #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#endif /*_DMA1_Channel3 */ - -#ifdef _DMA1_Channel4 - #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#endif /*_DMA1_Channel4 */ - -#ifdef _DMA1_Channel5 - #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#endif /*_DMA1_Channel5 */ - -#ifdef _DMA1_Channel6 - #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#endif /*_DMA1_Channel6 */ - -#ifdef _DMA1_Channel7 - #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#endif /*_DMA1_Channel7 */ - -#ifdef _DMA2_Channel1 - #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#endif /*_DMA2_Channel1 */ - -#ifdef _DMA2_Channel2 - #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#endif /*_DMA2_Channel2 */ - -#ifdef _DMA2_Channel3 - #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#endif /*_DMA2_Channel3 */ - -#ifdef _DMA2_Channel4 - #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#endif /*_DMA2_Channel4 */ - -#ifdef _DMA2_Channel5 - #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#endif /*_DMA2_Channel5 */ - -#ifdef _RCC - #define RCC ((RCC_TypeDef *) RCC_BASE) -#endif /*_RCC */ - -#ifdef _CRC - #define CRC ((CRC_TypeDef *) CRC_BASE) -#endif /*_CRC */ - -#ifdef _FLASH - #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) - #define OB ((OB_TypeDef *) OB_BASE) -#endif /*_FLASH */ - -#ifdef _FSMC - #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) - #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) - #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) - #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) - #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#endif /*_FSMC */ - -#ifdef _DBGMCU - #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) -#endif /*_DBGMCU */ - -#ifdef _SysTick - #define SysTick ((SysTick_TypeDef *) SysTick_BASE) -#endif /*_SysTick */ - -#ifdef _NVIC - #define NVIC ((NVIC_TypeDef *) NVIC_BASE) - #define SCB ((SCB_TypeDef *) SCB_BASE) -#endif /*_NVIC */ - -/*------------------------ Debug Mode ----------------------------------------*/ -#else /* DEBUG */ -#ifdef _TIM2 - EXT TIM_TypeDef *TIM2; -#endif /*_TIM2 */ - -#ifdef _TIM3 - EXT TIM_TypeDef *TIM3; -#endif /*_TIM3 */ - -#ifdef _TIM4 - EXT TIM_TypeDef *TIM4; -#endif /*_TIM4 */ - -#ifdef _TIM5 - EXT TIM_TypeDef *TIM5; -#endif /*_TIM5 */ - -#ifdef _TIM6 - EXT TIM_TypeDef *TIM6; -#endif /*_TIM6 */ - -#ifdef _TIM7 - EXT TIM_TypeDef *TIM7; -#endif /*_TIM7 */ - -#ifdef _RTC - EXT RTC_TypeDef *RTC; -#endif /*_RTC */ - -#ifdef _WWDG - EXT WWDG_TypeDef *WWDG; -#endif /*_WWDG */ - -#ifdef _IWDG - EXT IWDG_TypeDef *IWDG; -#endif /*_IWDG */ - -#ifdef _SPI2 - EXT SPI_TypeDef *SPI2; -#endif /*_SPI2 */ - -#ifdef _SPI3 - EXT SPI_TypeDef *SPI3; -#endif /*_SPI3 */ - -#ifdef _USART2 - EXT USART_TypeDef *USART2; -#endif /*_USART2 */ - -#ifdef _USART3 - EXT USART_TypeDef *USART3; -#endif /*_USART3 */ - -#ifdef _UART4 - EXT USART_TypeDef *UART4; -#endif /*_UART4 */ - -#ifdef _UART5 - EXT USART_TypeDef *UART5; -#endif /*_UART5 */ - -#ifdef _I2C1 - EXT I2C_TypeDef *I2C1; -#endif /*_I2C1 */ - -#ifdef _I2C2 - EXT I2C_TypeDef *I2C2; -#endif /*_I2C2 */ - -#ifdef _CAN - EXT CAN_TypeDef *CAN; -#endif /*_CAN */ - -#ifdef _BKP - EXT BKP_TypeDef *BKP; -#endif /*_BKP */ - -#ifdef _PWR - EXT PWR_TypeDef *PWR; -#endif /*_PWR */ - -#ifdef _DAC - EXT DAC_TypeDef *DAC; -#endif /*_DAC */ - -#ifdef _AFIO - EXT AFIO_TypeDef *AFIO; -#endif /*_AFIO */ - -#ifdef _EXTI - EXT EXTI_TypeDef *EXTI; -#endif /*_EXTI */ - -#ifdef _GPIOA - EXT GPIO_TypeDef *GPIOA; -#endif /*_GPIOA */ - -#ifdef _GPIOB - EXT GPIO_TypeDef *GPIOB; -#endif /*_GPIOB */ - -#ifdef _GPIOC - EXT GPIO_TypeDef *GPIOC; -#endif /*_GPIOC */ - -#ifdef _GPIOD - EXT GPIO_TypeDef *GPIOD; -#endif /*_GPIOD */ - -#ifdef _GPIOE - EXT GPIO_TypeDef *GPIOE; -#endif /*_GPIOE */ - -#ifdef _GPIOF - EXT GPIO_TypeDef *GPIOF; -#endif /*_GPIOF */ - -#ifdef _GPIOG - EXT GPIO_TypeDef *GPIOG; -#endif /*_GPIOG */ - -#ifdef _ADC1 - EXT ADC_TypeDef *ADC1; -#endif /*_ADC1 */ - -#ifdef _ADC2 - EXT ADC_TypeDef *ADC2; -#endif /*_ADC2 */ - -#ifdef _TIM1 - EXT TIM_TypeDef *TIM1; -#endif /*_TIM1 */ - -#ifdef _SPI1 - EXT SPI_TypeDef *SPI1; -#endif /*_SPI1 */ - -#ifdef _TIM8 - EXT TIM_TypeDef *TIM8; -#endif /*_TIM8 */ - -#ifdef _USART1 - EXT USART_TypeDef *USART1; -#endif /*_USART1 */ - -#ifdef _ADC3 - EXT ADC_TypeDef *ADC3; -#endif /*_ADC3 */ - -#ifdef _SDIO - EXT SDIO_TypeDef *SDIO; -#endif /*_SDIO */ - -#ifdef _DMA - EXT DMA_TypeDef *DMA1; - EXT DMA_TypeDef *DMA2; -#endif /*_DMA */ - -#ifdef _DMA1_Channel1 - EXT DMA_Channel_TypeDef *DMA1_Channel1; -#endif /*_DMA1_Channel1 */ - -#ifdef _DMA1_Channel2 - EXT DMA_Channel_TypeDef *DMA1_Channel2; -#endif /*_DMA1_Channel2 */ - -#ifdef _DMA1_Channel3 - EXT DMA_Channel_TypeDef *DMA1_Channel3; -#endif /*_DMA1_Channel3 */ - -#ifdef _DMA1_Channel4 - EXT DMA_Channel_TypeDef *DMA1_Channel4; -#endif /*_DMA1_Channel4 */ - -#ifdef _DMA1_Channel5 - EXT DMA_Channel_TypeDef *DMA1_Channel5; -#endif /*_DMA1_Channel5 */ - -#ifdef _DMA1_Channel6 - EXT DMA_Channel_TypeDef *DMA1_Channel6; -#endif /*_DMA1_Channel6 */ - -#ifdef _DMA1_Channel7 - EXT DMA_Channel_TypeDef *DMA1_Channel7; -#endif /*_DMA1_Channel7 */ - -#ifdef _DMA2_Channel1 - EXT DMA_Channel_TypeDef *DMA2_Channel1; -#endif /*_DMA2_Channel1 */ - -#ifdef _DMA2_Channel2 - EXT DMA_Channel_TypeDef *DMA2_Channel2; -#endif /*_DMA2_Channel2 */ - -#ifdef _DMA2_Channel3 - EXT DMA_Channel_TypeDef *DMA2_Channel3; -#endif /*_DMA2_Channel3 */ - -#ifdef _DMA2_Channel4 - EXT DMA_Channel_TypeDef *DMA2_Channel4; -#endif /*_DMA2_Channel4 */ - -#ifdef _DMA2_Channel5 - EXT DMA_Channel_TypeDef *DMA2_Channel5; -#endif /*_DMA2_Channel5 */ - -#ifdef _RCC - EXT RCC_TypeDef *RCC; -#endif /*_RCC */ - -#ifdef _CRC - EXT CRC_TypeDef *CRC; -#endif /*_CRC */ - -#ifdef _FLASH - EXT FLASH_TypeDef *FLASH; - EXT OB_TypeDef *OB; -#endif /*_FLASH */ - -#ifdef _FSMC - EXT FSMC_Bank1_TypeDef *FSMC_Bank1; - EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E; - EXT FSMC_Bank2_TypeDef *FSMC_Bank2; - EXT FSMC_Bank3_TypeDef *FSMC_Bank3; - EXT FSMC_Bank4_TypeDef *FSMC_Bank4; -#endif /*_FSMC */ - -#ifdef _DBGMCU - EXT DBGMCU_TypeDef *DBGMCU; -#endif /*_DBGMCU */ - -#ifdef _SysTick - EXT SysTick_TypeDef *SysTick; -#endif /*_SysTick */ - -#ifdef _NVIC - EXT NVIC_TypeDef *NVIC; - EXT SCB_TypeDef *SCB; -#endif /*_NVIC */ - -#endif /* DEBUG */ - -/* Exported constants --------------------------------------------------------*/ -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((u32)0xFFFFFFFF) /* Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((u8)0xFF) /* General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((u8)0x01) /* RESET bit */ - - - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((u16)0x0001) /* Low-Power Deepsleep */ -#define PWR_CR_PDDS ((u16)0x0002) /* Power Down Deepsleep */ -#define PWR_CR_CWUF ((u16)0x0004) /* Clear Wakeup Flag */ -#define PWR_CR_CSBF ((u16)0x0008) /* Clear Standby Flag */ -#define PWR_CR_PVDE ((u16)0x0010) /* Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((u16)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((u16)0x0020) /* Bit 0 */ -#define PWR_CR_PLS_1 ((u16)0x0040) /* Bit 1 */ -#define PWR_CR_PLS_2 ((u16)0x0080) /* Bit 2 */ - -/* PVD level configuration */ -#define PWR_CR_PLS_2V2 ((u16)0x0000) /* PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((u16)0x0020) /* PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((u16)0x0040) /* PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((u16)0x0060) /* PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((u16)0x0080) /* PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((u16)0x00A0) /* PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((u16)0x00C0) /* PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((u16)0x00E0) /* PVD level 2.9V */ - -#define PWR_CR_DBP ((u16)0x0100) /* Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((u16)0x0001) /* Wakeup Flag */ -#define PWR_CSR_SBF ((u16)0x0002) /* Standby Flag */ -#define PWR_CSR_PVDO ((u16)0x0004) /* PVD Output */ -#define PWR_CSR_EWUP ((u16)0x0100) /* Enable WKUP pin */ - - - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((u16)0xFFFF) /* Backup data */ - - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((u16)0xFFFF) /* Backup data */ - - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((u16)0xFFFF) /* Backup data */ - - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((u16)0x007F) /* Calibration value */ -#define BKP_RTCCR_CCO ((u16)0x0080) /* Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((u16)0x0100) /* Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((u16)0x0200) /* Alarm or Second Output Selection */ - - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((u8)0x01) /* TAMPER pin enable */ -#define BKP_CR_TPAL ((u8)0x02) /* TAMPER pin active level */ - - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((u16)0x0001) /* Clear Tamper event */ -#define BKP_CSR_CTI ((u16)0x0002) /* Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((u16)0x0004) /* TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((u16)0x0100) /* Tamper Event Flag */ -#define BKP_CSR_TIF ((u16)0x0200) /* Tamper Interrupt Flag */ - - - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((u32)0x00000001) /* Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((u32)0x00000002) /* Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((u32)0x000000F8) /* Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((u32)0x0000FF00) /* Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((u32)0x00010000) /* External High Speed clock enable */ -#define RCC_CR_HSERDY ((u32)0x00020000) /* External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((u32)0x00040000) /* External High Speed clock Bypass */ -#define RCC_CR_CSSON ((u32)0x00080000) /* Clock Security System enable */ -#define RCC_CR_PLLON ((u32)0x01000000) /* PLL enable */ -#define RCC_CR_PLLRDY ((u32)0x02000000) /* PLL clock ready flag */ - - -/******************* Bit definition for RCC_CFGR register *******************/ -#define RCC_CFGR_SW ((u32)0x00000003) /* SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((u32)0x00000001) /* Bit 0 */ -#define RCC_CFGR_SW_1 ((u32)0x00000002) /* Bit 1 */ - -/* SW configuration */ -#define RCC_CFGR_SW_HSI ((u32)0x00000000) /* HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((u32)0x00000001) /* HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((u32)0x00000002) /* PLL selected as system clock */ - -#define RCC_CFGR_SWS ((u32)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((u32)0x00000004) /* Bit 0 */ -#define RCC_CFGR_SWS_1 ((u32)0x00000008) /* Bit 1 */ - -/* SWS configuration */ -#define RCC_CFGR_SWS_HSI ((u32)0x00000000) /* HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((u32)0x00000004) /* HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((u32)0x00000008) /* PLL used as system clock */ - -#define RCC_CFGR_HPRE ((u32)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((u32)0x00000010) /* Bit 0 */ -#define RCC_CFGR_HPRE_1 ((u32)0x00000020) /* Bit 1 */ -#define RCC_CFGR_HPRE_2 ((u32)0x00000040) /* Bit 2 */ -#define RCC_CFGR_HPRE_3 ((u32)0x00000080) /* Bit 3 */ - -/* HPRE configuration */ -#define RCC_CFGR_HPRE_DIV1 ((u32)0x00000000) /* SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((u32)0x00000080) /* SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((u32)0x00000090) /* SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((u32)0x000000A0) /* SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((u32)0x000000B0) /* SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((u32)0x000000C0) /* SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((u32)0x000000D0) /* SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((u32)0x000000E0) /* SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((u32)0x000000F0) /* SYSCLK divided by 512 */ - -#define RCC_CFGR_PPRE1 ((u32)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((u32)0x00000100) /* Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((u32)0x00000200) /* Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((u32)0x00000400) /* Bit 2 */ - -/* PPRE1 configuration */ -#define RCC_CFGR_PPRE1_DIV1 ((u32)0x00000000) /* HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((u32)0x00000400) /* HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((u32)0x00000500) /* HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((u32)0x00000600) /* HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((u32)0x00000700) /* HCLK divided by 16 */ - -#define RCC_CFGR_PPRE2 ((u32)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((u32)0x00000800) /* Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((u32)0x00001000) /* Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((u32)0x00002000) /* Bit 2 */ - -/* PPRE2 configuration */ -#define RCC_CFGR_PPRE2_DIV1 ((u32)0x00000000) /* HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((u32)0x00002000) /* HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((u32)0x00002800) /* HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((u32)0x00003000) /* HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((u32)0x00003800) /* HCLK divided by 16 */ - -#define RCC_CFGR_ADCPRE ((u32)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((u32)0x00004000) /* Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((u32)0x00008000) /* Bit 1 */ - -/* ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE_DIV2 ((u32)0x00000000) /* PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((u32)0x00004000) /* PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((u32)0x00008000) /* PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((u32)0x0000C000) /* PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((u32)0x00010000) /* PLL entry clock source */ -#define RCC_CFGR_PLLXTPRE ((u32)0x00020000) /* HSE divider for PLL entry */ - -#define RCC_CFGR_PLLMULL ((u32)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((u32)0x00040000) /* Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((u32)0x00080000) /* Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((u32)0x00100000) /* Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((u32)0x00200000) /* Bit 3 */ - -/* PLLMUL configuration */ -#define RCC_CFGR_PLLMULL2 ((u32)0x00000000) /* PLL input clock*2 */ -#define RCC_CFGR_PLLMULL3 ((u32)0x00040000) /* PLL input clock*3 */ -#define RCC_CFGR_PLLMULL4 ((u32)0x00080000) /* PLL input clock*4 */ -#define RCC_CFGR_PLLMULL5 ((u32)0x000C0000) /* PLL input clock*5 */ -#define RCC_CFGR_PLLMULL6 ((u32)0x00100000) /* PLL input clock*6 */ -#define RCC_CFGR_PLLMULL7 ((u32)0x00140000) /* PLL input clock*7 */ -#define RCC_CFGR_PLLMULL8 ((u32)0x00180000) /* PLL input clock*8 */ -#define RCC_CFGR_PLLMULL9 ((u32)0x001C0000) /* PLL input clock*9 */ -#define RCC_CFGR_PLLMULL10 ((u32)0x00200000) /* PLL input clock10 */ -#define RCC_CFGR_PLLMULL11 ((u32)0x00240000) /* PLL input clock*11 */ -#define RCC_CFGR_PLLMULL12 ((u32)0x00280000) /* PLL input clock*12 */ -#define RCC_CFGR_PLLMULL13 ((u32)0x002C0000) /* PLL input clock*13 */ -#define RCC_CFGR_PLLMULL14 ((u32)0x00300000) /* PLL input clock*14 */ -#define RCC_CFGR_PLLMULL15 ((u32)0x00340000) /* PLL input clock*15 */ -#define RCC_CFGR_PLLMULL16 ((u32)0x00380000) /* PLL input clock*16 */ - -#define RCC_CFGR_USBPRE ((u32)0x00400000) /* USB prescaler */ - -#define RCC_CFGR_MCO ((u32)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ -#define RCC_CFGR_MCO_0 ((u32)0x01000000) /* Bit 0 */ -#define RCC_CFGR_MCO_1 ((u32)0x02000000) /* Bit 1 */ -#define RCC_CFGR_MCO_2 ((u32)0x04000000) /* Bit 2 */ - -/* MCO configuration */ -#define RCC_CFGR_MCO_NOCLOCK ((u32)0x00000000) /* No clock */ -#define RCC_CFGR_MCO_SYSCLK ((u32)0x04000000) /* System clock selected */ -#define RCC_CFGR_MCO_HSI ((u32)0x05000000) /* Internal 8 MHz RC oscillator clock selected */ -#define RCC_CFGR_MCO_HSE ((u32)0x06000000) /* External 1-25 MHz oscillator clock selected */ -#define RCC_CFGR_MCO_PLL ((u32)0x07000000) /* PLL clock divided by 2 selected*/ - - -/******************* Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((u32)0x00000001) /* LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((u32)0x00000002) /* LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((u32)0x00000004) /* HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((u32)0x00000008) /* HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((u32)0x00000010) /* PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((u32)0x00000080) /* Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((u32)0x00000100) /* LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((u32)0x00000200) /* LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((u32)0x00000400) /* HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((u32)0x00000800) /* HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((u32)0x00001000) /* PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((u32)0x00010000) /* LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((u32)0x00020000) /* LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((u32)0x00040000) /* HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((u32)0x00080000) /* HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((u32)0x00100000) /* PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((u32)0x00800000) /* Clock Security System Interrupt Clear */ - - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((u16)0x0001) /* Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((u16)0x0004) /* I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((u16)0x0008) /* IO port B reset */ -#define RCC_APB2RSTR_IOPCRST ((u16)0x0010) /* IO port C reset */ -#define RCC_APB2RSTR_IOPDRST ((u16)0x0020) /* IO port D reset */ -#define RCC_APB2RSTR_IOPERST ((u16)0x0040) /* IO port E reset */ -#define RCC_APB2RSTR_IOPFRST ((u16)0x0080) /* IO port F reset */ -#define RCC_APB2RSTR_IOPGRST ((u16)0x0100) /* IO port G reset */ -#define RCC_APB2RSTR_ADC1RST ((u16)0x0200) /* ADC 1 interface reset */ -#define RCC_APB2RSTR_ADC2RST ((u16)0x0400) /* ADC 2 interface reset */ -#define RCC_APB2RSTR_TIM1RST ((u16)0x0800) /* TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((u16)0x1000) /* SPI 1 reset */ -#define RCC_APB2RSTR_TIM8RST ((u16)0x2000) /* TIM8 Timer reset */ -#define RCC_APB2RSTR_USART1RST ((u16)0x4000) /* USART1 reset */ -#define RCC_APB2RSTR_ADC3RST ((u16)0x8000) /* ADC3 interface reset */ - - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((u32)0x00000001) /* Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((u32)0x00000002) /* Timer 3 reset */ -#define RCC_APB1RSTR_TIM4RST ((u32)0x00000004) /* Timer 4 reset */ -#define RCC_APB1RSTR_TIM5RST ((u32)0x00000008) /* Timer 5 reset */ -#define RCC_APB1RSTR_TIM6RST ((u32)0x00000010) /* Timer 6 reset */ -#define RCC_APB1RSTR_TIM7RST ((u32)0x00000020) /* Timer 7 reset */ -#define RCC_APB1RSTR_WWDGRST ((u32)0x00000800) /* Window Watchdog reset */ -#define RCC_APB1RSTR_SPI2RST ((u32)0x00004000) /* SPI 2 reset */ -#define RCC_APB1RSTR_SPI3RST ((u32)0x00008000) /* SPI 3 reset */ -#define RCC_APB1RSTR_USART2RST ((u32)0x00020000) /* USART 2 reset */ -#define RCC_APB1RSTR_USART3RST ((u32)0x00040000) /* RUSART 3 reset */ -#define RCC_APB1RSTR_UART4RST ((u32)0x00080000) /* USART 4 reset */ -#define RCC_APB1RSTR_UART5RST ((u32)0x00100000) /* USART 5 reset */ -#define RCC_APB1RSTR_I2C1RST ((u32)0x00200000) /* I2C 1 reset */ -#define RCC_APB1RSTR_I2C2RST ((u32)0x00400000) /* I2C 2 reset */ -#define RCC_APB1RSTR_USBRST ((u32)0x00800000) /* USB reset */ -#define RCC_APB1RSTR_CANRST ((u32)0x02000000) /* CAN reset */ -#define RCC_APB1RSTR_BKPRST ((u32)0x08000000) /* Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((u32)0x10000000) /* Power interface reset */ -#define RCC_APB1RSTR_DACRST ((u32)0x20000000) /* DAC interface reset */ - - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((u16)0x0001) /* DMA1 clock enable */ -#define RCC_AHBENR_DMA2EN ((u16)0x0002) /* DMA2 clock enable */ -#define RCC_AHBENR_SRAMEN ((u16)0x0004) /* SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((u16)0x0010) /* FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((u16)0x0040) /* CRC clock enable */ -#define RCC_AHBENR_FSMCEN ((u16)0x0100) /* FSMC clock enable */ -#define RCC_AHBENR_SDIOEN ((u16)0x0400) /* SDIO clock enable */ - - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((u16)0x0001) /* Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((u16)0x0004) /* I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((u16)0x0008) /* I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((u16)0x0010) /* I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((u16)0x0020) /* I/O port D clock enable */ -#define RCC_APB2ENR_IOPEEN ((u16)0x0040) /* I/O port E clock enable */ -#define RCC_APB2ENR_IOPFEN ((u16)0x0080) /* I/O port F clock enable */ -#define RCC_APB2ENR_IOPGEN ((u16)0x0100) /* I/O port G clock enable */ -#define RCC_APB2ENR_ADC1EN ((u16)0x0200) /* ADC 1 interface clock enable */ -#define RCC_APB2ENR_ADC2EN ((u16)0x0400) /* ADC 2 interface clock enable */ -#define RCC_APB2ENR_TIM1EN ((u16)0x0800) /* TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((u16)0x1000) /* SPI 1 clock enable */ -#define RCC_APB2ENR_TIM8EN ((u16)0x2000) /* TIM8 Timer clock enable */ -#define RCC_APB2ENR_USART1EN ((u16)0x4000) /* USART1 clock enable */ -#define RCC_APB2ENR_ADC3EN ((u16)0x8000) /* DMA1 clock enable */ - - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((u32)0x00000001) /* Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((u32)0x00000002) /* Timer 3 clock enable */ -#define RCC_APB1ENR_TIM4EN ((u32)0x00000004) /* Timer 4 clock enable */ -#define RCC_APB1ENR_TIM5EN ((u32)0x00000008) /* Timer 5 clock enable */ -#define RCC_APB1ENR_TIM6EN ((u32)0x00000010) /* Timer 6 clock enable */ -#define RCC_APB1ENR_TIM7EN ((u32)0x00000020) /* Timer 7 clock enable */ -#define RCC_APB1ENR_WWDGEN ((u32)0x00000800) /* Window Watchdog clock enable */ -#define RCC_APB1ENR_SPI2EN ((u32)0x00004000) /* SPI 2 clock enable */ -#define RCC_APB1ENR_SPI3EN ((u32)0x00008000) /* SPI 3 clock enable */ -#define RCC_APB1ENR_USART2EN ((u32)0x00020000) /* USART 2 clock enable */ -#define RCC_APB1ENR_USART3EN ((u32)0x00040000) /* USART 3 clock enable */ -#define RCC_APB1ENR_UART4EN ((u32)0x00080000) /* USART 4 clock enable */ -#define RCC_APB1ENR_UART5EN ((u32)0x00100000) /* USART 5 clock enable */ -#define RCC_APB1ENR_I2C1EN ((u32)0x00200000) /* I2C 1 clock enable */ -#define RCC_APB1ENR_I2C2EN ((u32)0x00400000) /* I2C 2 clock enable */ -#define RCC_APB1ENR_USBEN ((u32)0x00800000) /* USB clock enable */ -#define RCC_APB1ENR_CANEN ((u32)0x02000000) /* CAN clock enable */ -#define RCC_APB1ENR_BKPEN ((u32)0x08000000) /* Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((u32)0x10000000) /* Power interface clock enable */ -#define RCC_APB1ENR_DACEN ((u32)0x20000000) /* DAC interface clock enable */ - - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((u32)0x00000001) /* External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((u32)0x00000002) /* External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((u32)0x00000004) /* External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((u32)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((u32)0x00000100) /* Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((u32)0x00000200) /* Bit 1 */ -/* RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((u32)0x00000000) /* No clock */ -#define RCC_BDCR_RTCSEL_LSE ((u32)0x00000100) /* LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((u32)0x00000200) /* LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((u32)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((u32)0x00008000) /* RTC clock enable */ -#define RCC_BDCR_BDRST ((u32)0x00010000) /* Backup domain software reset */ - - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((u32)0x00000001) /* Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((u32)0x00000002) /* Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((u32)0x01000000) /* Remove reset flag */ -#define RCC_CSR_PINRSTF ((u32)0x04000000) /* PIN reset flag */ -#define RCC_CSR_PORRSTF ((u32)0x08000000) /* POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((u32)0x10000000) /* Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((u32)0x20000000) /* Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((u32)0x40000000) /* Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((u32)0x80000000) /* Low-Power reset flag */ - - - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function IO */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((u32)0x33333333) /* Port x mode bits */ - -#define GPIO_CRL_MODE0 ((u32)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((u32)0x00000001) /* Bit 0 */ -#define GPIO_CRL_MODE0_1 ((u32)0x00000002) /* Bit 1 */ - -#define GPIO_CRL_MODE1 ((u32)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((u32)0x00000010) /* Bit 0 */ -#define GPIO_CRL_MODE1_1 ((u32)0x00000020) /* Bit 1 */ - -#define GPIO_CRL_MODE2 ((u32)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((u32)0x00000100) /* Bit 0 */ -#define GPIO_CRL_MODE2_1 ((u32)0x00000200) /* Bit 1 */ - -#define GPIO_CRL_MODE3 ((u32)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((u32)0x00001000) /* Bit 0 */ -#define GPIO_CRL_MODE3_1 ((u32)0x00002000) /* Bit 1 */ - -#define GPIO_CRL_MODE4 ((u32)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((u32)0x00010000) /* Bit 0 */ -#define GPIO_CRL_MODE4_1 ((u32)0x00020000) /* Bit 1 */ - -#define GPIO_CRL_MODE5 ((u32)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((u32)0x00100000) /* Bit 0 */ -#define GPIO_CRL_MODE5_1 ((u32)0x00200000) /* Bit 1 */ - -#define GPIO_CRL_MODE6 ((u32)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((u32)0x01000000) /* Bit 0 */ -#define GPIO_CRL_MODE6_1 ((u32)0x02000000) /* Bit 1 */ - -#define GPIO_CRL_MODE7 ((u32)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((u32)0x10000000) /* Bit 0 */ -#define GPIO_CRL_MODE7_1 ((u32)0x20000000) /* Bit 1 */ - - -#define GPIO_CRL_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((u32)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((u32)0x00000004) /* Bit 0 */ -#define GPIO_CRL_CNF0_1 ((u32)0x00000008) /* Bit 1 */ - -#define GPIO_CRL_CNF1 ((u32)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((u32)0x00000040) /* Bit 0 */ -#define GPIO_CRL_CNF1_1 ((u32)0x00000080) /* Bit 1 */ - -#define GPIO_CRL_CNF2 ((u32)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((u32)0x00000400) /* Bit 0 */ -#define GPIO_CRL_CNF2_1 ((u32)0x00000800) /* Bit 1 */ - -#define GPIO_CRL_CNF3 ((u32)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((u32)0x00004000) /* Bit 0 */ -#define GPIO_CRL_CNF3_1 ((u32)0x00008000) /* Bit 1 */ - -#define GPIO_CRL_CNF4 ((u32)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((u32)0x00040000) /* Bit 0 */ -#define GPIO_CRL_CNF4_1 ((u32)0x00080000) /* Bit 1 */ - -#define GPIO_CRL_CNF5 ((u32)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((u32)0x00400000) /* Bit 0 */ -#define GPIO_CRL_CNF5_1 ((u32)0x00800000) /* Bit 1 */ - -#define GPIO_CRL_CNF6 ((u32)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((u32)0x04000000) /* Bit 0 */ -#define GPIO_CRL_CNF6_1 ((u32)0x08000000) /* Bit 1 */ - -#define GPIO_CRL_CNF7 ((u32)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((u32)0x40000000) /* Bit 0 */ -#define GPIO_CRL_CNF7_1 ((u32)0x80000000) /* Bit 1 */ - - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((u32)0x33333333) /* Port x mode bits */ - -#define GPIO_CRH_MODE8 ((u32)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((u32)0x00000001) /* Bit 0 */ -#define GPIO_CRH_MODE8_1 ((u32)0x00000002) /* Bit 1 */ - -#define GPIO_CRH_MODE9 ((u32)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((u32)0x00000010) /* Bit 0 */ -#define GPIO_CRH_MODE9_1 ((u32)0x00000020) /* Bit 1 */ - -#define GPIO_CRH_MODE10 ((u32)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((u32)0x00000100) /* Bit 0 */ -#define GPIO_CRH_MODE10_1 ((u32)0x00000200) /* Bit 1 */ - -#define GPIO_CRH_MODE11 ((u32)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((u32)0x00001000) /* Bit 0 */ -#define GPIO_CRH_MODE11_1 ((u32)0x00002000) /* Bit 1 */ - -#define GPIO_CRH_MODE12 ((u32)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((u32)0x00010000) /* Bit 0 */ -#define GPIO_CRH_MODE12_1 ((u32)0x00020000) /* Bit 1 */ - -#define GPIO_CRH_MODE13 ((u32)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((u32)0x00100000) /* Bit 0 */ -#define GPIO_CRH_MODE13_1 ((u32)0x00200000) /* Bit 1 */ - -#define GPIO_CRH_MODE14 ((u32)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((u32)0x01000000) /* Bit 0 */ -#define GPIO_CRH_MODE14_1 ((u32)0x02000000) /* Bit 1 */ - -#define GPIO_CRH_MODE15 ((u32)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((u32)0x10000000) /* Bit 0 */ -#define GPIO_CRH_MODE15_1 ((u32)0x20000000) /* Bit 1 */ - - -#define GPIO_CRH_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((u32)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((u32)0x00000004) /* Bit 0 */ -#define GPIO_CRH_CNF8_1 ((u32)0x00000008) /* Bit 1 */ - -#define GPIO_CRH_CNF9 ((u32)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((u32)0x00000040) /* Bit 0 */ -#define GPIO_CRH_CNF9_1 ((u32)0x00000080) /* Bit 1 */ - -#define GPIO_CRH_CNF10 ((u32)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((u32)0x00000400) /* Bit 0 */ -#define GPIO_CRH_CNF10_1 ((u32)0x00000800) /* Bit 1 */ - -#define GPIO_CRH_CNF11 ((u32)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((u32)0x00004000) /* Bit 0 */ -#define GPIO_CRH_CNF11_1 ((u32)0x00008000) /* Bit 1 */ - -#define GPIO_CRH_CNF12 ((u32)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((u32)0x00040000) /* Bit 0 */ -#define GPIO_CRH_CNF12_1 ((u32)0x00080000) /* Bit 1 */ - -#define GPIO_CRH_CNF13 ((u32)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((u32)0x00400000) /* Bit 0 */ -#define GPIO_CRH_CNF13_1 ((u32)0x00800000) /* Bit 1 */ - -#define GPIO_CRH_CNF14 ((u32)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((u32)0x04000000) /* Bit 0 */ -#define GPIO_CRH_CNF14_1 ((u32)0x08000000) /* Bit 1 */ - -#define GPIO_CRH_CNF15 ((u32)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((u32)0x40000000) /* Bit 0 */ -#define GPIO_CRH_CNF15_1 ((u32)0x80000000) /* Bit 1 */ - - -/******************* Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((u16)0x0001) /* Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((u16)0x0002) /* Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((u16)0x0004) /* Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((u16)0x0008) /* Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((u16)0x0010) /* Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((u16)0x0020) /* Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((u16)0x0040) /* Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((u16)0x0080) /* Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((u16)0x0100) /* Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((u16)0x0200) /* Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((u16)0x0400) /* Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((u16)0x0800) /* Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((u16)0x1000) /* Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((u16)0x2000) /* Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((u16)0x4000) /* Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((u16)0x8000) /* Port input data, bit 15 */ - - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((u16)0x0001) /* Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((u16)0x0002) /* Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((u16)0x0004) /* Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((u16)0x0008) /* Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((u16)0x0010) /* Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((u16)0x0020) /* Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((u16)0x0040) /* Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((u16)0x0080) /* Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((u16)0x0100) /* Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((u16)0x0200) /* Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((u16)0x0400) /* Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((u16)0x0800) /* Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((u16)0x1000) /* Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((u16)0x2000) /* Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((u16)0x4000) /* Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((u16)0x8000) /* Port output data, bit 15 */ - - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((u32)0x00000001) /* Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((u32)0x00000002) /* Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((u32)0x00000004) /* Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((u32)0x00000008) /* Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((u32)0x00000010) /* Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((u32)0x00000020) /* Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((u32)0x00000040) /* Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((u32)0x00000080) /* Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((u32)0x00000100) /* Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((u32)0x00000200) /* Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((u32)0x00000400) /* Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((u32)0x00000800) /* Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((u32)0x00001000) /* Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((u32)0x00002000) /* Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((u32)0x00004000) /* Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((u32)0x00008000) /* Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((u32)0x00010000) /* Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((u32)0x00020000) /* Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((u32)0x00040000) /* Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((u32)0x00080000) /* Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((u32)0x00100000) /* Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((u32)0x00200000) /* Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((u32)0x00400000) /* Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((u32)0x00800000) /* Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((u32)0x01000000) /* Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((u32)0x02000000) /* Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((u32)0x04000000) /* Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((u32)0x08000000) /* Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((u32)0x10000000) /* Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((u32)0x20000000) /* Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((u32)0x40000000) /* Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((u32)0x80000000) /* Port x Reset bit 15 */ - - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((u16)0x0001) /* Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((u16)0x0002) /* Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((u16)0x0004) /* Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((u16)0x0008) /* Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((u16)0x0010) /* Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((u16)0x0020) /* Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((u16)0x0040) /* Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((u16)0x0080) /* Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((u16)0x0100) /* Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((u16)0x0200) /* Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((u16)0x0400) /* Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((u16)0x0800) /* Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((u16)0x1000) /* Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((u16)0x2000) /* Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((u16)0x4000) /* Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((u16)0x8000) /* Port x Reset bit 15 */ - - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((u32)0x00000001) /* Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((u32)0x00000002) /* Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((u32)0x00000004) /* Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((u32)0x00000008) /* Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((u32)0x00000010) /* Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((u32)0x00000020) /* Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((u32)0x00000040) /* Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((u32)0x00000080) /* Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((u32)0x00000100) /* Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((u32)0x00000200) /* Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((u32)0x00000400) /* Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((u32)0x00000800) /* Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((u32)0x00001000) /* Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((u32)0x00002000) /* Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((u32)0x00004000) /* Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((u32)0x00008000) /* Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((u32)0x00010000) /* Lock key */ - - -/*----------------------------------------------------------------------------*/ - - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((u8)0x0F) /* PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((u8)0x01) /* Bit 0 */ -#define AFIO_EVCR_PIN_1 ((u8)0x02) /* Bit 1 */ -#define AFIO_EVCR_PIN_2 ((u8)0x04) /* Bit 2 */ -#define AFIO_EVCR_PIN_3 ((u8)0x08) /* Bit 3 */ - -/* PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((u8)0x00) /* Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((u8)0x01) /* Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((u8)0x02) /* Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((u8)0x03) /* Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((u8)0x04) /* Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((u8)0x05) /* Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((u8)0x06) /* Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((u8)0x07) /* Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((u8)0x08) /* Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((u8)0x09) /* Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((u8)0x0A) /* Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((u8)0x0B) /* Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((u8)0x0C) /* Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((u8)0x0D) /* Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((u8)0x0E) /* Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((u8)0x0F) /* Pin 15 selected */ - -#define AFIO_EVCR_PORT ((u8)0x70) /* PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((u8)0x10) /* Bit 0 */ -#define AFIO_EVCR_PORT_1 ((u8)0x20) /* Bit 1 */ -#define AFIO_EVCR_PORT_2 ((u8)0x40) /* Bit 2 */ - -/* PORT configuration */ -#define AFIO_EVCR_PORT_PA ((u8)0x00) /* Port A selected */ -#define AFIO_EVCR_PORT_PB ((u8)0x10) /* Port B selected */ -#define AFIO_EVCR_PORT_PC ((u8)0x20) /* Port C selected */ -#define AFIO_EVCR_PORT_PD ((u8)0x30) /* Port D selected */ -#define AFIO_EVCR_PORT_PE ((u8)0x40) /* Port E selected */ - -#define AFIO_EVCR_EVOE ((u8)0x80) /* Event Output Enable */ - - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1 _REMAP ((u32)0x00000001) /* SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((u32)0x00000002) /* I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((u32)0x00000004) /* USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((u32)0x00000008) /* USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((u32)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((u32)0x00000010) /* Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((u32)0x00000020) /* Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((u32)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((u32)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((u32)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((u32)0x00000040) /* Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((u32)0x00000080) /* Bit 1 */ - -/* TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((u32)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((u32)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((u32)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((u32)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((u32)0x00000100) /* Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((u32)0x00000200) /* Bit 1 */ - -/* TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((u32)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((u32)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((u32)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((u32)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((u32)0x00000400) /* Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((u32)0x00000800) /* Bit 1 */ - -/* TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((u32)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((u32)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((u32)0x00001000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ - -#define AFIO_MAPR_CAN_REMAP ((u32)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((u32)0x00002000) /* Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((u32)0x00004000) /* Bit 1 */ - -/* CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((u32)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((u32)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((u32)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((u32)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((u32)0x00010000) /* TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((u32)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((u32)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((u32)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((u32)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ - -#define AFIO_MAPR_SWJ_CFG ((u32)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((u32)0x01000000) /* Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((u32)0x02000000) /* Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((u32)0x04000000) /* Bit 2 */ - -/* SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG_RESET ((u32)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((u32)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((u32)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((u32)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ - - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((u16)0x000F) /* EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((u16)0x00F0) /* EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((u16)0x0F00) /* EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((u16)0xF000) /* EXTI 3 configuration */ - -/* EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((u16)0x0000) /* PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((u16)0x0001) /* PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((u16)0x0002) /* PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((u16)0x0003) /* PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((u16)0x0004) /* PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((u16)0x0005) /* PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((u16)0x0006) /* PG[0] pin */ - -/* EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((u16)0x0000) /* PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((u16)0x0010) /* PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((u16)0x0020) /* PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((u16)0x0030) /* PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((u16)0x0040) /* PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((u16)0x0050) /* PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((u16)0x0060) /* PG[1] pin */ - -/* EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((u16)0x0000) /* PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((u16)0x0100) /* PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((u16)0x0200) /* PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((u16)0x0300) /* PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((u16)0x0400) /* PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((u16)0x0500) /* PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((u16)0x0600) /* PG[2] pin */ - -/* EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((u16)0x0000) /* PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((u16)0x1000) /* PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((u16)0x2000) /* PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((u16)0x3000) /* PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((u16)0x4000) /* PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((u16)0x5000) /* PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((u16)0x6000) /* PG[3] pin */ - - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((u16)0x000F) /* EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((u16)0x00F0) /* EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((u16)0x0F00) /* EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((u16)0xF000) /* EXTI 7 configuration */ - -/* EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((u16)0x0000) /* PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((u16)0x0001) /* PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((u16)0x0002) /* PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((u16)0x0003) /* PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((u16)0x0004) /* PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((u16)0x0005) /* PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((u16)0x0006) /* PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((u16)0x0000) /* PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((u16)0x0010) /* PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((u16)0x0020) /* PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((u16)0x0030) /* PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((u16)0x0040) /* PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((u16)0x0050) /* PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((u16)0x0060) /* PG[5] pin */ - -/* EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((u16)0x0000) /* PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((u16)0x0100) /* PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((u16)0x0200) /* PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((u16)0x0300) /* PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((u16)0x0400) /* PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((u16)0x0500) /* PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((u16)0x0600) /* PG[6] pin */ - -/* EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((u16)0x0000) /* PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((u16)0x1000) /* PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((u16)0x2000) /* PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((u16)0x3000) /* PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((u16)0x4000) /* PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((u16)0x5000) /* PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((u16)0x6000) /* PG[7] pin */ - - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((u16)0x000F) /* EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((u16)0x00F0) /* EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((u16)0x0F00) /* EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((u16)0xF000) /* EXTI 11 configuration */ - -/* EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((u16)0x0000) /* PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((u16)0x0001) /* PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((u16)0x0002) /* PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((u16)0x0003) /* PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((u16)0x0004) /* PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((u16)0x0005) /* PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((u16)0x0006) /* PG[8] pin */ - -/* EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((u16)0x0000) /* PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((u16)0x0010) /* PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((u16)0x0020) /* PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((u16)0x0030) /* PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((u16)0x0040) /* PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((u16)0x0050) /* PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((u16)0x0060) /* PG[9] pin */ - -/* EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((u16)0x0000) /* PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((u16)0x0100) /* PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((u16)0x0200) /* PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((u16)0x0300) /* PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((u16)0x0400) /* PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((u16)0x0500) /* PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((u16)0x0600) /* PG[10] pin */ - -/* EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((u16)0x0000) /* PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((u16)0x1000) /* PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((u16)0x2000) /* PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((u16)0x3000) /* PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((u16)0x4000) /* PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((u16)0x5000) /* PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((u16)0x6000) /* PG[11] pin */ - - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((u16)0x000F) /* EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((u16)0x00F0) /* EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((u16)0x0F00) /* EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((u16)0xF000) /* EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((u16)0x0000) /* PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((u16)0x0001) /* PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((u16)0x0002) /* PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((u16)0x0003) /* PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((u16)0x0004) /* PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((u16)0x0005) /* PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((u16)0x0006) /* PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((u16)0x0000) /* PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((u16)0x0010) /* PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((u16)0x0020) /* PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((u16)0x0030) /* PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((u16)0x0040) /* PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((u16)0x0050) /* PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((u16)0x0060) /* PG[13] pin */ - -/* EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((u16)0x0000) /* PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((u16)0x0100) /* PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((u16)0x0200) /* PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((u16)0x0300) /* PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((u16)0x0400) /* PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((u16)0x0500) /* PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((u16)0x0600) /* PG[14] pin */ - -/* EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((u16)0x0000) /* PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((u16)0x1000) /* PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((u16)0x2000) /* PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((u16)0x3000) /* PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((u16)0x4000) /* PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((u16)0x5000) /* PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((u16)0x6000) /* PG[15] pin */ - - - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */ -#define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */ -#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */ - - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ - - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */ - - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */ - - - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((u32)0xFFFFFFFF) /* Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((u32)0x00000001) /* bit 0 */ -#define NVIC_ISER_SETENA_1 ((u32)0x00000002) /* bit 1 */ -#define NVIC_ISER_SETENA_2 ((u32)0x00000004) /* bit 2 */ -#define NVIC_ISER_SETENA_3 ((u32)0x00000008) /* bit 3 */ -#define NVIC_ISER_SETENA_4 ((u32)0x00000010) /* bit 4 */ -#define NVIC_ISER_SETENA_5 ((u32)0x00000020) /* bit 5 */ -#define NVIC_ISER_SETENA_6 ((u32)0x00000040) /* bit 6 */ -#define NVIC_ISER_SETENA_7 ((u32)0x00000080) /* bit 7 */ -#define NVIC_ISER_SETENA_8 ((u32)0x00000100) /* bit 8 */ -#define NVIC_ISER_SETENA_9 ((u32)0x00000200) /* bit 9 */ -#define NVIC_ISER_SETENA_10 ((u32)0x00000400) /* bit 10 */ -#define NVIC_ISER_SETENA_11 ((u32)0x00000800) /* bit 11 */ -#define NVIC_ISER_SETENA_12 ((u32)0x00001000) /* bit 12 */ -#define NVIC_ISER_SETENA_13 ((u32)0x00002000) /* bit 13 */ -#define NVIC_ISER_SETENA_14 ((u32)0x00004000) /* bit 14 */ -#define NVIC_ISER_SETENA_15 ((u32)0x00008000) /* bit 15 */ -#define NVIC_ISER_SETENA_16 ((u32)0x00010000) /* bit 16 */ -#define NVIC_ISER_SETENA_17 ((u32)0x00020000) /* bit 17 */ -#define NVIC_ISER_SETENA_18 ((u32)0x00040000) /* bit 18 */ -#define NVIC_ISER_SETENA_19 ((u32)0x00080000) /* bit 19 */ -#define NVIC_ISER_SETENA_20 ((u32)0x00100000) /* bit 20 */ -#define NVIC_ISER_SETENA_21 ((u32)0x00200000) /* bit 21 */ -#define NVIC_ISER_SETENA_22 ((u32)0x00400000) /* bit 22 */ -#define NVIC_ISER_SETENA_23 ((u32)0x00800000) /* bit 23 */ -#define NVIC_ISER_SETENA_24 ((u32)0x01000000) /* bit 24 */ -#define NVIC_ISER_SETENA_25 ((u32)0x02000000) /* bit 25 */ -#define NVIC_ISER_SETENA_26 ((u32)0x04000000) /* bit 26 */ -#define NVIC_ISER_SETENA_27 ((u32)0x08000000) /* bit 27 */ -#define NVIC_ISER_SETENA_28 ((u32)0x10000000) /* bit 28 */ -#define NVIC_ISER_SETENA_29 ((u32)0x20000000) /* bit 29 */ -#define NVIC_ISER_SETENA_30 ((u32)0x40000000) /* bit 30 */ -#define NVIC_ISER_SETENA_31 ((u32)0x80000000) /* bit 31 */ - - - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((u32)0xFFFFFFFF) /* Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((u32)0x00000001) /* bit 0 */ -#define NVIC_ICER_CLRENA_1 ((u32)0x00000002) /* bit 1 */ -#define NVIC_ICER_CLRENA_2 ((u32)0x00000004) /* bit 2 */ -#define NVIC_ICER_CLRENA_3 ((u32)0x00000008) /* bit 3 */ -#define NVIC_ICER_CLRENA_4 ((u32)0x00000010) /* bit 4 */ -#define NVIC_ICER_CLRENA_5 ((u32)0x00000020) /* bit 5 */ -#define NVIC_ICER_CLRENA_6 ((u32)0x00000040) /* bit 6 */ -#define NVIC_ICER_CLRENA_7 ((u32)0x00000080) /* bit 7 */ -#define NVIC_ICER_CLRENA_8 ((u32)0x00000100) /* bit 8 */ -#define NVIC_ICER_CLRENA_9 ((u32)0x00000200) /* bit 9 */ -#define NVIC_ICER_CLRENA_10 ((u32)0x00000400) /* bit 10 */ -#define NVIC_ICER_CLRENA_11 ((u32)0x00000800) /* bit 11 */ -#define NVIC_ICER_CLRENA_12 ((u32)0x00001000) /* bit 12 */ -#define NVIC_ICER_CLRENA_13 ((u32)0x00002000) /* bit 13 */ -#define NVIC_ICER_CLRENA_14 ((u32)0x00004000) /* bit 14 */ -#define NVIC_ICER_CLRENA_15 ((u32)0x00008000) /* bit 15 */ -#define NVIC_ICER_CLRENA_16 ((u32)0x00010000) /* bit 16 */ -#define NVIC_ICER_CLRENA_17 ((u32)0x00020000) /* bit 17 */ -#define NVIC_ICER_CLRENA_18 ((u32)0x00040000) /* bit 18 */ -#define NVIC_ICER_CLRENA_19 ((u32)0x00080000) /* bit 19 */ -#define NVIC_ICER_CLRENA_20 ((u32)0x00100000) /* bit 20 */ -#define NVIC_ICER_CLRENA_21 ((u32)0x00200000) /* bit 21 */ -#define NVIC_ICER_CLRENA_22 ((u32)0x00400000) /* bit 22 */ -#define NVIC_ICER_CLRENA_23 ((u32)0x00800000) /* bit 23 */ -#define NVIC_ICER_CLRENA_24 ((u32)0x01000000) /* bit 24 */ -#define NVIC_ICER_CLRENA_25 ((u32)0x02000000) /* bit 25 */ -#define NVIC_ICER_CLRENA_26 ((u32)0x04000000) /* bit 26 */ -#define NVIC_ICER_CLRENA_27 ((u32)0x08000000) /* bit 27 */ -#define NVIC_ICER_CLRENA_28 ((u32)0x10000000) /* bit 28 */ -#define NVIC_ICER_CLRENA_29 ((u32)0x20000000) /* bit 29 */ -#define NVIC_ICER_CLRENA_30 ((u32)0x40000000) /* bit 30 */ -#define NVIC_ICER_CLRENA_31 ((u32)0x80000000) /* bit 31 */ - - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((u32)0xFFFFFFFF) /* Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((u32)0x00000001) /* bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((u32)0x00000002) /* bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((u32)0x00000004) /* bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((u32)0x00000008) /* bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((u32)0x00000010) /* bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((u32)0x00000020) /* bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((u32)0x00000040) /* bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((u32)0x00000080) /* bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((u32)0x00000100) /* bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((u32)0x00000200) /* bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((u32)0x00000400) /* bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((u32)0x00000800) /* bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((u32)0x00001000) /* bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((u32)0x00002000) /* bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((u32)0x00004000) /* bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((u32)0x00008000) /* bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((u32)0x00010000) /* bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((u32)0x00020000) /* bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((u32)0x00040000) /* bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((u32)0x00080000) /* bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((u32)0x00100000) /* bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((u32)0x00200000) /* bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((u32)0x00400000) /* bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((u32)0x00800000) /* bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((u32)0x01000000) /* bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((u32)0x02000000) /* bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((u32)0x04000000) /* bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((u32)0x08000000) /* bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((u32)0x10000000) /* bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((u32)0x20000000) /* bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((u32)0x40000000) /* bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((u32)0x80000000) /* bit 31 */ - - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((u32)0xFFFFFFFF) /* Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((u32)0x00000001) /* bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((u32)0x00000002) /* bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((u32)0x00000004) /* bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((u32)0x00000008) /* bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((u32)0x00000010) /* bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((u32)0x00000020) /* bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((u32)0x00000040) /* bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((u32)0x00000080) /* bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((u32)0x00000100) /* bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((u32)0x00000200) /* bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((u32)0x00000400) /* bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((u32)0x00000800) /* bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((u32)0x00001000) /* bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((u32)0x00002000) /* bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((u32)0x00004000) /* bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((u32)0x00008000) /* bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((u32)0x00010000) /* bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((u32)0x00020000) /* bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((u32)0x00040000) /* bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((u32)0x00080000) /* bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((u32)0x00100000) /* bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((u32)0x00200000) /* bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((u32)0x00400000) /* bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((u32)0x00800000) /* bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((u32)0x01000000) /* bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((u32)0x02000000) /* bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((u32)0x04000000) /* bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((u32)0x08000000) /* bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((u32)0x10000000) /* bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((u32)0x20000000) /* bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((u32)0x40000000) /* bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((u32)0x80000000) /* bit 31 */ - - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((u32)0xFFFFFFFF) /* Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((u32)0x00000001) /* bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((u32)0x00000002) /* bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((u32)0x00000004) /* bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((u32)0x00000008) /* bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((u32)0x00000010) /* bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((u32)0x00000020) /* bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((u32)0x00000040) /* bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((u32)0x00000080) /* bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((u32)0x00000100) /* bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((u32)0x00000200) /* bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((u32)0x00000400) /* bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((u32)0x00000800) /* bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((u32)0x00001000) /* bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((u32)0x00002000) /* bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((u32)0x00004000) /* bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((u32)0x00008000) /* bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((u32)0x00010000) /* bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((u32)0x00020000) /* bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((u32)0x00040000) /* bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((u32)0x00080000) /* bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((u32)0x00100000) /* bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((u32)0x00200000) /* bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((u32)0x00400000) /* bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((u32)0x00800000) /* bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((u32)0x01000000) /* bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((u32)0x02000000) /* bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((u32)0x04000000) /* bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((u32)0x08000000) /* bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((u32)0x10000000) /* bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((u32)0x20000000) /* bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((u32)0x40000000) /* bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((u32)0x80000000) /* bit 31 */ - - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((u32)0x000000FF) /* Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((u32)0x0000FF00) /* Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((u32)0x00FF0000) /* Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((u32)0xFF000000) /* Priority of interrupt 3 */ - - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((u32)0x000000FF) /* Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((u32)0x0000FF00) /* Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((u32)0x00FF0000) /* Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((u32)0xFF000000) /* Priority of interrupt 7 */ - - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((u32)0x000000FF) /* Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((u32)0x0000FF00) /* Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((u32)0x00FF0000) /* Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((u32)0xFF000000) /* Priority of interrupt 11 */ - - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((u32)0x000000FF) /* Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((u32)0x0000FF00) /* Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((u32)0x00FF0000) /* Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((u32)0xFF000000) /* Priority of interrupt 15 */ - - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((u32)0x000000FF) /* Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((u32)0x0000FF00) /* Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((u32)0x00FF0000) /* Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((u32)0xFF000000) /* Priority of interrupt 19 */ - - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((u32)0x000000FF) /* Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((u32)0x0000FF00) /* Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((u32)0x00FF0000) /* Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((u32)0xFF000000) /* Priority of interrupt 23 */ - - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((u32)0x000000FF) /* Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((u32)0x0000FF00) /* Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((u32)0x00FF0000) /* Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((u32)0xFF000000) /* Priority of interrupt 27 */ - - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((u32)0x000000FF) /* Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((u32)0x0000FF00) /* Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((u32)0x00FF0000) /* Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((u32)0xFF000000) /* Priority of interrupt 31 */ - - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((u32)0x0000000F) /* Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((u32)0x0000FFF0) /* Number of processor within family */ -#define SCB_CPUID_Constant ((u32)0x000F0000) /* Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((u32)0x00F00000) /* Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((u32)0xFF000000) /* Implementer code. ARM is 0x41 */ - - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((u32)0x000001FF) /* Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((u32)0x00000800) /* All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((u32)0x003FF000) /* Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((u32)0x00400000) /* Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((u32)0x00800000) /* It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((u32)0x02000000) /* Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((u32)0x04000000) /* Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((u32)0x08000000) /* Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((u32)0x10000000) /* Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((u32)0x80000000) /* Set pending NMI bit */ - - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((u32)0x1FFFFF80) /* Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((u32)0x20000000) /* Table base in code(0) or RAM(1) */ - - -/****************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((u32)0x00000001) /* System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((u32)0x00000002) /* Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((u32)0x00000004) /* Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((u32)0x00000700) /* PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((u32)0x00000100) /* Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((u32)0x00000200) /* Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((u32)0x00000400) /* Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((u32)0x00000000) /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((u32)0x00000100) /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((u32)0x00000200) /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((u32)0x00000300) /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((u32)0x00000400) /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((u32)0x00000500) /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((u8)0x02) /* Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((u8)0x04) /* Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((u8)0x10) /* Wake up from WFE */ - - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((u16)0x0001) /* Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((u16)0x0002) /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((u16)0x0008) /* Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((u16)0x0010) /* Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((u16)0x0100) /* Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((u16)0x0200) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((u32)0x000000FF) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((u32)0x0000FF00) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((u32)0x00FF0000) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((u32)0xFF000000) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((u32)0x00000001) /* MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((u32)0x00000002) /* BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((u32)0x00000008) /* UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((u32)0x00000080) /* SVCall is active */ -#define SCB_SHCSR_MONITORACT ((u32)0x00000100) /* Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((u32)0x00000400) /* PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((u32)0x00000800) /* SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((u32)0x00001000) /* Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((u32)0x00002000) /* MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((u32)0x00004000) /* Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((u32)0x00008000) /* SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((u32)0x00010000) /* MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((u32)0x00020000) /* Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((u32)0x00040000) /* UsageFault enable */ - - -/******************* Bit definition for SCB_CFSR register *******************/ -/* MFSR */ -#define SCB_CFSR_IACCVIOL ((u32)0x00000001) /* Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((u32)0x00000002) /* Data access violation */ -#define SCB_CFSR_MUNSTKERR ((u32)0x00000008) /* Unstacking error */ -#define SCB_CFSR_MSTKERR ((u32)0x00000010) /* Stacking error */ -#define SCB_CFSR_MMARVALID ((u32)0x00000080) /* Memory Manage Address Register address valid flag */ -/* BFSR */ -#define SCB_CFSR_IBUSERR ((u32)0x00000100) /* Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((u32)0x00000200) /* Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((u32)0x00000400) /* Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((u32)0x00000800) /* Unstacking error */ -#define SCB_CFSR_STKERR ((u32)0x00001000) /* Stacking error */ -#define SCB_CFSR_BFARVALID ((u32)0x00008000) /* Bus Fault Address Register address valid flag */ -/* UFSR */ -#define SCB_CFSR_UNDEFINSTR ((u32)0x00010000) /* The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((u32)0x00020000) /* Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((u32)0x00040000) /* Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((u32)0x00080000) /* Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((u32)0x01000000) /* Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((u32)0x02000000) /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((u32)0x00000002) /* Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((u32)0x40000000) /* Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((u32)0x80000000) /* Fault related to debug */ - - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((u8)0x01) /* Halt request flag */ -#define SCB_DFSR_BKPT ((u8)0x02) /* BKPT flag */ -#define SCB_DFSR_DWTTRAP ((u8)0x04) /* Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((u8)0x08) /* Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((u8)0x10) /* External debug request flag */ - - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((u32)0xFFFFFFFF) /* Mem Manage fault address field */ - - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((u32)0xFFFFFFFF) /* Bus fault address field */ - - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((u32)0xFFFFFFFF) /* Implementation defined */ - - - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((u32)0x00000001) /* Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((u32)0x00000002) /* Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((u32)0x00000004) /* Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((u32)0x00000008) /* Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((u32)0x00000010) /* Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((u32)0x00000020) /* Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((u32)0x00000040) /* Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((u32)0x00000080) /* Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((u32)0x00000100) /* Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((u32)0x00000200) /* Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((u32)0x00000400) /* Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((u32)0x00000800) /* Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((u32)0x00001000) /* Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((u32)0x00002000) /* Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((u32)0x00004000) /* Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((u32)0x00008000) /* Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((u32)0x00010000) /* Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((u32)0x00020000) /* Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((u32)0x00040000) /* Interrupt Mask on line 18 */ - - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((u32)0x00000001) /* Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((u32)0x00000002) /* Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((u32)0x00000004) /* Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((u32)0x00000008) /* Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((u32)0x00000010) /* Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((u32)0x00000020) /* Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((u32)0x00000040) /* Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((u32)0x00000080) /* Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((u32)0x00000100) /* Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((u32)0x00000200) /* Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((u32)0x00000400) /* Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((u32)0x00000800) /* Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((u32)0x00001000) /* Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((u32)0x00002000) /* Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((u32)0x00004000) /* Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((u32)0x00008000) /* Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((u32)0x00010000) /* Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((u32)0x00020000) /* Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((u32)0x00040000) /* Event Mask on line 18 */ - - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((u32)0x00000001) /* Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((u32)0x00000002) /* Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((u32)0x00000004) /* Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((u32)0x00000008) /* Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((u32)0x00000010) /* Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((u32)0x00000020) /* Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((u32)0x00000040) /* Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((u32)0x00000080) /* Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((u32)0x00000100) /* Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((u32)0x00000200) /* Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((u32)0x00000400) /* Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((u32)0x00000800) /* Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((u32)0x00001000) /* Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((u32)0x00002000) /* Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((u32)0x00004000) /* Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((u32)0x00008000) /* Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((u32)0x00010000) /* Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((u32)0x00020000) /* Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((u32)0x00040000) /* Rising trigger event configuration bit of line 18 */ - - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((u32)0x00000001) /* Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((u32)0x00000002) /* Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((u32)0x00000004) /* Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((u32)0x00000008) /* Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((u32)0x00000010) /* Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((u32)0x00000020) /* Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((u32)0x00000040) /* Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((u32)0x00000080) /* Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((u32)0x00000100) /* Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((u32)0x00000200) /* Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((u32)0x00000400) /* Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((u32)0x00000800) /* Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((u32)0x00001000) /* Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((u32)0x00002000) /* Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((u32)0x00004000) /* Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((u32)0x00008000) /* Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((u32)0x00010000) /* Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((u32)0x00020000) /* Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((u32)0x00040000) /* Falling trigger event configuration bit of line 18 */ - - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((u32)0x00000001) /* Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((u32)0x00000002) /* Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((u32)0x00000004) /* Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((u32)0x00000008) /* Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((u32)0x00000010) /* Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((u32)0x00000020) /* Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((u32)0x00000040) /* Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((u32)0x00000080) /* Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((u32)0x00000100) /* Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((u32)0x00000200) /* Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((u32)0x00000400) /* Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((u32)0x00000800) /* Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((u32)0x00001000) /* Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((u32)0x00002000) /* Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((u32)0x00004000) /* Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((u32)0x00008000) /* Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((u32)0x00010000) /* Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((u32)0x00020000) /* Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((u32)0x00040000) /* Software Interrupt on line 18 */ - - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((u32)0x00000001) /* Pending bit 0 */ -#define EXTI_PR_PR1 ((u32)0x00000002) /* Pending bit 1 */ -#define EXTI_PR_PR2 ((u32)0x00000004) /* Pending bit 2 */ -#define EXTI_PR_PR3 ((u32)0x00000008) /* Pending bit 3 */ -#define EXTI_PR_PR4 ((u32)0x00000010) /* Pending bit 4 */ -#define EXTI_PR_PR5 ((u32)0x00000020) /* Pending bit 5 */ -#define EXTI_PR_PR6 ((u32)0x00000040) /* Pending bit 6 */ -#define EXTI_PR_PR7 ((u32)0x00000080) /* Pending bit 7 */ -#define EXTI_PR_PR8 ((u32)0x00000100) /* Pending bit 8 */ -#define EXTI_PR_PR9 ((u32)0x00000200) /* Pending bit 9 */ -#define EXTI_PR_PR10 ((u32)0x00000400) /* Pending bit 10 */ -#define EXTI_PR_PR11 ((u32)0x00000800) /* Pending bit 11 */ -#define EXTI_PR_PR12 ((u32)0x00001000) /* Pending bit 12 */ -#define EXTI_PR_PR13 ((u32)0x00002000) /* Pending bit 13 */ -#define EXTI_PR_PR14 ((u32)0x00004000) /* Pending bit 14 */ -#define EXTI_PR_PR15 ((u32)0x00008000) /* Pending bit 15 */ -#define EXTI_PR_PR16 ((u32)0x00010000) /* Pending bit 16 */ -#define EXTI_PR_PR17 ((u32)0x00020000) /* Pending bit 17 */ -#define EXTI_PR_PR18 ((u32)0x00040000) /* Trigger request occurred on the external interrupt line 18 */ - - - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((u32)0x00000001) /* Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((u32)0x00000010) /* Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((u32)0x00000100) /* Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((u32)0x00001000) /* Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((u32)0x00010000) /* Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((u32)0x00100000) /* Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((u32)0x01000000) /* Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error flag */ - - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((u32)0x00000001) /* Channel 1 Global interrupt clearr */ -#define DMA_IFCR_CTCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((u32)0x00000010) /* Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((u32)0x00000100) /* Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((u32)0x00001000) /* Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((u32)0x00010000) /* Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((u32)0x00100000) /* Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((u32)0x01000000) /* Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error clear */ - - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((u16)0x0001) /* Channel enable*/ -#define DMA_CCR1_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((u16)0x0010) /* Data transfer direction */ -#define DMA_CCR1_CIRC ((u16)0x0020) /* Circular mode */ -#define DMA_CCR1_PINC ((u16)0x0040) /* Peripheral increment mode */ -#define DMA_CCR1_MINC ((u16)0x0080) /* Memory increment mode */ - -#define DMA_CCR1_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((u16)0x0100) /* Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((u16)0x0200) /* Bit 1 */ - -#define DMA_CCR1_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((u16)0x0400) /* Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((u16)0x0800) /* Bit 1 */ - -#define DMA_CCR1_PL ((u16)0x3000) /* PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((u16)0x1000) /* Bit 0 */ -#define DMA_CCR1_PL_1 ((u16)0x2000) /* Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ - - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((u16)0x0001) /* Channel enable */ -#define DMA_CCR2_TCIE ((u16)0x0002) /* ransfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((u16)0x0010) /* Data transfer direction */ -#define DMA_CCR2_CIRC ((u16)0x0020) /* Circular mode */ -#define DMA_CCR2_PINC ((u16)0x0040) /* Peripheral increment mode */ -#define DMA_CCR2_MINC ((u16)0x0080) /* Memory increment mode */ - -#define DMA_CCR2_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((u16)0x0100) /* Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((u16)0x0200) /* Bit 1 */ - -#define DMA_CCR2_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((u16)0x0400) /* Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((u16)0x0800) /* Bit 1 */ - -#define DMA_CCR2_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((u16)0x1000) /* Bit 0 */ -#define DMA_CCR2_PL_1 ((u16)0x2000) /* Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ - - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((u16)0x0001) /* Channel enable */ -#define DMA_CCR3_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((u16)0x0010) /* Data transfer direction */ -#define DMA_CCR3_CIRC ((u16)0x0020) /* Circular mode */ -#define DMA_CCR3_PINC ((u16)0x0040) /* Peripheral increment mode */ -#define DMA_CCR3_MINC ((u16)0x0080) /* Memory increment mode */ - -#define DMA_CCR3_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((u16)0x0100) /* Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((u16)0x0200) /* Bit 1 */ - -#define DMA_CCR3_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((u16)0x0400) /* Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((u16)0x0800) /* Bit 1 */ - -#define DMA_CCR3_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((u16)0x1000) /* Bit 0 */ -#define DMA_CCR3_PL_1 ((u16)0x2000) /* Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ - - -/******************* Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((u16)0x0001) /* Channel enable */ -#define DMA_CCR4_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CCR4_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CCR4_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ -#define DMA_CCR4_DIR ((u16)0x0010) /* Data transfer direction */ -#define DMA_CCR4_CIRC ((u16)0x0020) /* Circular mode */ -#define DMA_CCR4_PINC ((u16)0x0040) /* Peripheral increment mode */ -#define DMA_CCR4_MINC ((u16)0x0080) /* Memory increment mode */ - -#define DMA_CCR4_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR4_PSIZE_0 ((u16)0x0100) /* Bit 0 */ -#define DMA_CCR4_PSIZE_1 ((u16)0x0200) /* Bit 1 */ - -#define DMA_CCR4_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR4_MSIZE_0 ((u16)0x0400) /* Bit 0 */ -#define DMA_CCR4_MSIZE_1 ((u16)0x0800) /* Bit 1 */ - -#define DMA_CCR4_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR4_PL_0 ((u16)0x1000) /* Bit 0 */ -#define DMA_CCR4_PL_1 ((u16)0x2000) /* Bit 1 */ - -#define DMA_CCR4_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ - - -/****************** Bit definition for DMA_CCR5 register *******************/ -#define DMA_CCR5_EN ((u16)0x0001) /* Channel enable */ -#define DMA_CCR5_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CCR5_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CCR5_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ -#define DMA_CCR5_DIR ((u16)0x0010) /* Data transfer direction */ -#define DMA_CCR5_CIRC ((u16)0x0020) /* Circular mode */ -#define DMA_CCR5_PINC ((u16)0x0040) /* Peripheral increment mode */ -#define DMA_CCR5_MINC ((u16)0x0080) /* Memory increment mode */ - -#define DMA_CCR5_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR5_PSIZE_0 ((u16)0x0100) /* Bit 0 */ -#define DMA_CCR5_PSIZE_1 ((u16)0x0200) /* Bit 1 */ - -#define DMA_CCR5_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR5_MSIZE_0 ((u16)0x0400) /* Bit 0 */ -#define DMA_CCR5_MSIZE_1 ((u16)0x0800) /* Bit 1 */ - -#define DMA_CCR5_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR5_PL_0 ((u16)0x1000) /* Bit 0 */ -#define DMA_CCR5_PL_1 ((u16)0x2000) /* Bit 1 */ - -#define DMA_CCR5_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ - - -/******************* Bit definition for DMA_CCR6 register *******************/ -#define DMA_CCR6_EN ((u16)0x0001) /* Channel enable */ -#define DMA_CCR6_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CCR6_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CCR6_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ -#define DMA_CCR6_DIR ((u16)0x0010) /* Data transfer direction */ -#define DMA_CCR6_CIRC ((u16)0x0020) /* Circular mode */ -#define DMA_CCR6_PINC ((u16)0x0040) /* Peripheral increment mode */ -#define DMA_CCR6_MINC ((u16)0x0080) /* Memory increment mode */ - -#define DMA_CCR6_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR6_PSIZE_0 ((u16)0x0100) /* Bit 0 */ -#define DMA_CCR6_PSIZE_1 ((u16)0x0200) /* Bit 1 */ - -#define DMA_CCR6_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR6_MSIZE_0 ((u16)0x0400) /* Bit 0 */ -#define DMA_CCR6_MSIZE_1 ((u16)0x0800) /* Bit 1 */ - -#define DMA_CCR6_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR6_PL_0 ((u16)0x1000) /* Bit 0 */ -#define DMA_CCR6_PL_1 ((u16)0x2000) /* Bit 1 */ - -#define DMA_CCR6_MEM2MEM ((u16)0x4000) /* Memory to memory mode */ - - -/******************* Bit definition for DMA_CCR7 register *******************/ -#define DMA_CCR7_EN ((u16)0x0001) /* Channel enable */ -#define DMA_CCR7_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */ -#define DMA_CCR7_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */ -#define DMA_CCR7_TEIE ((u16)0x0008) /* Transfer error interrupt enable */ -#define DMA_CCR7_DIR ((u16)0x0010) /* Data transfer direction */ -#define DMA_CCR7_CIRC ((u16)0x0020) /* Circular mode */ -#define DMA_CCR7_PINC ((u16)0x0040) /* Peripheral increment mode */ -#define DMA_CCR7_MINC ((u16)0x0080) /* Memory increment mode */ - -#define DMA_CCR7_PSIZE , ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR7_PSIZE_0 ((u16)0x0100) /* Bit 0 */ -#define DMA_CCR7_PSIZE_1 ((u16)0x0200) /* Bit 1 */ - -#define DMA_CCR7_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR7_MSIZE_0 ((u16)0x0400) /* Bit 0 */ -#define DMA_CCR7_MSIZE_1 ((u16)0x0800) /* Bit 1 */ - -#define DMA_CCR7_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR7_PL_0 ((u16)0x1000) /* Bit 0 */ -#define DMA_CCR7_PL_1 ((u16)0x2000) /* Bit 1 */ - -#define DMA_CCR7_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */ - - -/****************** Bit definition for DMA_CNDTR1 register ******************/ -#define DMA_CNDTR1_NDT ((u16)0xFFFF) /* Number of data to Transfer */ - - -/****************** Bit definition for DMA_CNDTR2 register ******************/ -#define DMA_CNDTR2_NDT ((u16)0xFFFF) /* Number of data to Transfer */ - - -/****************** Bit definition for DMA_CNDTR3 register ******************/ -#define DMA_CNDTR3_NDT ((u16)0xFFFF) /* Number of data to Transfer */ - - -/****************** Bit definition for DMA_CNDTR4 register ******************/ -#define DMA_CNDTR4_NDT ((u16)0xFFFF) /* Number of data to Transfer */ - - -/****************** Bit definition for DMA_CNDTR5 register ******************/ -#define DMA_CNDTR5_NDT ((u16)0xFFFF) /* Number of data to Transfer */ - - -/****************** Bit definition for DMA_CNDTR6 register ******************/ -#define DMA_CNDTR6_NDT ((u16)0xFFFF) /* Number of data to Transfer */ - - -/****************** Bit definition for DMA_CNDTR7 register ******************/ -#define DMA_CNDTR7_NDT ((u16)0xFFFF) /* Number of data to Transfer */ - - -/****************** Bit definition for DMA_CPAR1 register *******************/ -#define DMA_CPAR1_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR2 register *******************/ -#define DMA_CPAR2_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR3 register *******************/ -#define DMA_CPAR3_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR4 register *******************/ -#define DMA_CPAR4_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR5 register *******************/ -#define DMA_CPAR5_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR6 register *******************/ -#define DMA_CPAR6_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ - - -/****************** Bit definition for DMA_CPAR7 register *******************/ -#define DMA_CPAR7_PA ((u32)0xFFFFFFFF) /* Peripheral Address */ - - -/****************** Bit definition for DMA_CMAR1 register *******************/ -#define DMA_CMAR1_MA ((u32)0xFFFFFFFF) /* Memory Address */ - - -/****************** Bit definition for DMA_CMAR2 register *******************/ -#define DMA_CMAR2_MA ((u32)0xFFFFFFFF) /* Memory Address */ - - -/****************** Bit definition for DMA_CMAR3 register *******************/ -#define DMA_CMAR3_MA ((u32)0xFFFFFFFF) /* Memory Address */ - - -/****************** Bit definition for DMA_CMAR4 register *******************/ -#define DMA_CMAR4_MA ((u32)0xFFFFFFFF) /* Memory Address */ - - -/****************** Bit definition for DMA_CMAR5 register *******************/ -#define DMA_CMAR5_MA ((u32)0xFFFFFFFF) /* Memory Address */ - - -/****************** Bit definition for DMA_CMAR6 register *******************/ -#define DMA_CMAR6_MA ((u32)0xFFFFFFFF) /* Memory Address */ - - -/****************** Bit definition for DMA_CMAR7 register *******************/ -#define DMA_CMAR7_MA ((u32)0xFFFFFFFF) /* Memory Address */ - - - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((u8)0x01) /* Analog watchdog flag */ -#define ADC_SR_EOC ((u8)0x02) /* End of conversion */ -#define ADC_SR_JEOC ((u8)0x04) /* Injected channel end of conversion */ -#define ADC_SR_JSTRT ((u8)0x08) /* Injected channel Start flag */ -#define ADC_SR_STRT ((u8)0x10) /* Regular channel Start flag */ - - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((u32)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((u32)0x00000001) /* Bit 0 */ -#define ADC_CR1_AWDCH_1 ((u32)0x00000002) /* Bit 1 */ -#define ADC_CR1_AWDCH_2 ((u32)0x00000004) /* Bit 2 */ -#define ADC_CR1_AWDCH_3 ((u32)0x00000008) /* Bit 3 */ -#define ADC_CR1_AWDCH_4 ((u32)0x00000010) /* Bit 4 */ - -#define ADC_CR1_EOCIE ((u32)0x00000020) /* Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((u32)0x00000040) /* AAnalog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((u32)0x00000080) /* Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((u32)0x00000100) /* Scan mode */ -#define ADC_CR1_AWDSGL ((u32)0x00000200) /* Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((u32)0x00000400) /* Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((u32)0x00000800) /* Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((u32)0x00001000) /* Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((u32)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((u32)0x00002000) /* Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((u32)0x00004000) /* Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((u32)0x00008000) /* Bit 2 */ - -#define ADC_CR1_DUALMOD ((u32)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ -#define ADC_CR1_DUALMOD_0 ((u32)0x00010000) /* Bit 0 */ -#define ADC_CR1_DUALMOD_1 ((u32)0x00020000) /* Bit 1 */ -#define ADC_CR1_DUALMOD_2 ((u32)0x00040000) /* Bit 2 */ -#define ADC_CR1_DUALMOD_3 ((u32)0x00080000) /* Bit 3 */ - -#define ADC_CR1_JAWDEN ((u32)0x00400000) /* Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((u32)0x00800000) /* Analog watchdog enable on regular channels */ - - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((u32)0x00000001) /* A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((u32)0x00000002) /* Continuous Conversion */ -#define ADC_CR2_CAL ((u32)0x00000004) /* A/D Calibration */ -#define ADC_CR2_RSTCAL ((u32)0x00000008) /* Reset Calibration */ -#define ADC_CR2_DMA ((u32)0x00000100) /* Direct Memory access mode */ -#define ADC_CR2_ALIGN ((u32)0x00000800) /* Data Alignment */ - -#define ADC_CR2_JEXTSEL ((u32)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((u32)0x00001000) /* Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((u32)0x00002000) /* Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((u32)0x00004000) /* Bit 2 */ - -#define ADC_CR2_JEXTTRIG ((u32)0x00008000) /* External Trigger Conversion mode for injected channels */ - -#define ADC_CR2_EXTSEL ((u32)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((u32)0x00020000) /* Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((u32)0x00040000) /* Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((u32)0x00080000) /* Bit 2 */ - -#define ADC_CR2_EXTTRIG ((u32)0x00100000) /* External Trigger Conversion mode for regular channels */ -#define ADC_CR2_JSWSTART ((u32)0x00200000) /* Start Conversion of injected channels */ -#define ADC_CR2_SWSTART ((u32)0x00400000) /* Start Conversion of regular channels */ -#define ADC_CR2_TSVREFE ((u32)0x00800000) /* Temperature Sensor and VREFINT Enable */ - - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP10 ((u32)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR1_SMP10_0 ((u32)0x00000001) /* Bit 0 */ -#define ADC_SMPR1_SMP10_1 ((u32)0x00000002) /* Bit 1 */ -#define ADC_SMPR1_SMP10_2 ((u32)0x00000004) /* Bit 2 */ - -#define ADC_SMPR1_SMP11 ((u32)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR1_SMP11_0 ((u32)0x00000008) /* Bit 0 */ -#define ADC_SMPR1_SMP11_1 ((u32)0x00000010) /* Bit 1 */ -#define ADC_SMPR1_SMP11_2 ((u32)0x00000020) /* Bit 2 */ - -#define ADC_SMPR1_SMP12 ((u32)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR1_SMP12_0 ((u32)0x00000040) /* Bit 0 */ -#define ADC_SMPR1_SMP12_1 ((u32)0x00000080) /* Bit 1 */ -#define ADC_SMPR1_SMP12_2 ((u32)0x00000100) /* Bit 2 */ - -#define ADC_SMPR1_SMP13 ((u32)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR1_SMP13_0 ((u32)0x00000200) /* Bit 0 */ -#define ADC_SMPR1_SMP13_1 ((u32)0x00000400) /* Bit 1 */ -#define ADC_SMPR1_SMP13_2 ((u32)0x00000800) /* Bit 2 */ - -#define ADC_SMPR1_SMP14 ((u32)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR1_SMP14_0 ((u32)0x00001000) /* Bit 0 */ -#define ADC_SMPR1_SMP14_1 ((u32)0x00002000) /* Bit 1 */ -#define ADC_SMPR1_SMP14_2 ((u32)0x00004000) /* Bit 2 */ - -#define ADC_SMPR1_SMP15 ((u32)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ -#define ADC_SMPR1_SMP15_0 ((u32)0x00008000) /* Bit 0 */ -#define ADC_SMPR1_SMP15_1 ((u32)0x00010000) /* Bit 1 */ -#define ADC_SMPR1_SMP15_2 ((u32)0x00020000) /* Bit 2 */ - -#define ADC_SMPR1_SMP16 ((u32)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR1_SMP16_0 ((u32)0x00040000) /* Bit 0 */ -#define ADC_SMPR1_SMP16_1 ((u32)0x00080000) /* Bit 1 */ -#define ADC_SMPR1_SMP16_2 ((u32)0x00100000) /* Bit 2 */ - -#define ADC_SMPR1_SMP17 ((u32)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR1_SMP17_0 ((u32)0x00200000) /* Bit 0 */ -#define ADC_SMPR1_SMP17_1 ((u32)0x00400000) /* Bit 1 */ -#define ADC_SMPR1_SMP17_2 ((u32)0x00800000) /* Bit 2 */ - - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP0 ((u32)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR2_SMP0_0 ((u32)0x00000001) /* Bit 0 */ -#define ADC_SMPR2_SMP0_1 ((u32)0x00000002) /* Bit 1 */ -#define ADC_SMPR2_SMP0_2 ((u32)0x00000004) /* Bit 2 */ - -#define ADC_SMPR2_SMP1 ((u32)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR2_SMP1_0 ((u32)0x00000008) /* Bit 0 */ -#define ADC_SMPR2_SMP1_1 ((u32)0x00000010) /* Bit 1 */ -#define ADC_SMPR2_SMP1_2 ((u32)0x00000020) /* Bit 2 */ - -#define ADC_SMPR2_SMP2 ((u32)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR2_SMP2_0 ((u32)0x00000040) /* Bit 0 */ -#define ADC_SMPR2_SMP2_1 ((u32)0x00000080) /* Bit 1 */ -#define ADC_SMPR2_SMP2_2 ((u32)0x00000100) /* Bit 2 */ - -#define ADC_SMPR2_SMP3 ((u32)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR2_SMP3_0 ((u32)0x00000200) /* Bit 0 */ -#define ADC_SMPR2_SMP3_1 ((u32)0x00000400) /* Bit 1 */ -#define ADC_SMPR2_SMP3_2 ((u32)0x00000800) /* Bit 2 */ - -#define ADC_SMPR2_SMP4 ((u32)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR2_SMP4_0 ((u32)0x00001000) /* Bit 0 */ -#define ADC_SMPR2_SMP4_1 ((u32)0x00002000) /* Bit 1 */ -#define ADC_SMPR2_SMP4_2 ((u32)0x00004000) /* Bit 2 */ - -#define ADC_SMPR2_SMP5 ((u32)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP5_0 ((u32)0x00008000) /* Bit 0 */ -#define ADC_SMPR2_SMP5_1 ((u32)0x00010000) /* Bit 1 */ -#define ADC_SMPR2_SMP5_2 ((u32)0x00020000) /* Bit 2 */ - -#define ADC_SMPR2_SMP6 ((u32)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR2_SMP6_0 ((u32)0x00040000) /* Bit 0 */ -#define ADC_SMPR2_SMP6_1 ((u32)0x00080000) /* Bit 1 */ -#define ADC_SMPR2_SMP6_2 ((u32)0x00100000) /* Bit 2 */ - -#define ADC_SMPR2_SMP7 ((u32)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR2_SMP7_0 ((u32)0x00200000) /* Bit 0 */ -#define ADC_SMPR2_SMP7_1 ((u32)0x00400000) /* Bit 1 */ -#define ADC_SMPR2_SMP7_2 ((u32)0x00800000) /* Bit 2 */ - -#define ADC_SMPR2_SMP8 ((u32)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR2_SMP8_0 ((u32)0x01000000) /* Bit 0 */ -#define ADC_SMPR2_SMP8_1 ((u32)0x02000000) /* Bit 1 */ -#define ADC_SMPR2_SMP8_2 ((u32)0x04000000) /* Bit 2 */ - -#define ADC_SMPR2_SMP9 ((u32)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR2_SMP9_0 ((u32)0x08000000) /* Bit 0 */ -#define ADC_SMPR2_SMP9_1 ((u32)0x10000000) /* Bit 1 */ -#define ADC_SMPR2_SMP9_2 ((u32)0x20000000) /* Bit 2 */ - - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((u16)0x0FFF) /* Data offset for injected channel 1 */ - - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((u16)0x0FFF) /* Data offset for injected channel 2 */ - - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((u16)0x0FFF) /* Data offset for injected channel 3 */ - - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((u16)0x0FFF) /* Data offset for injected channel 4 */ - - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((u16)0x0FFF) /* Analog watchdog high threshold */ - - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((u16)0x0FFF) /* Analog watchdog low threshold */ - - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ13 ((u32)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR1_SQ13_0 ((u32)0x00000001) /* Bit 0 */ -#define ADC_SQR1_SQ13_1 ((u32)0x00000002) /* Bit 1 */ -#define ADC_SQR1_SQ13_2 ((u32)0x00000004) /* Bit 2 */ -#define ADC_SQR1_SQ13_3 ((u32)0x00000008) /* Bit 3 */ -#define ADC_SQR1_SQ13_4 ((u32)0x00000010) /* Bit 4 */ - -#define ADC_SQR1_SQ14 ((u32)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR1_SQ14_0 ((u32)0x00000020) /* Bit 0 */ -#define ADC_SQR1_SQ14_1 ((u32)0x00000040) /* Bit 1 */ -#define ADC_SQR1_SQ14_2 ((u32)0x00000080) /* Bit 2 */ -#define ADC_SQR1_SQ14_3 ((u32)0x00000100) /* Bit 3 */ -#define ADC_SQR1_SQ14_4 ((u32)0x00000200) /* Bit 4 */ - -#define ADC_SQR1_SQ15 ((u32)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR1_SQ15_0 ((u32)0x00000400) /* Bit 0 */ -#define ADC_SQR1_SQ15_1 ((u32)0x00000800) /* Bit 1 */ -#define ADC_SQR1_SQ15_2 ((u32)0x00001000) /* Bit 2 */ -#define ADC_SQR1_SQ15_3 ((u32)0x00002000) /* Bit 3 */ -#define ADC_SQR1_SQ15_4 ((u32)0x00004000) /* Bit 4 */ - -#define ADC_SQR1_SQ16 ((u32)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR1_SQ16_0 ((u32)0x00008000) /* Bit 0 */ -#define ADC_SQR1_SQ16_1 ((u32)0x00010000) /* Bit 1 */ -#define ADC_SQR1_SQ16_2 ((u32)0x00020000) /* Bit 2 */ -#define ADC_SQR1_SQ16_3 ((u32)0x00040000) /* Bit 3 */ -#define ADC_SQR1_SQ16_4 ((u32)0x00080000) /* Bit 4 */ - -#define ADC_SQR1_L ((u32)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((u32)0x00100000) /* Bit 0 */ -#define ADC_SQR1_L_1 ((u32)0x00200000) /* Bit 1 */ -#define ADC_SQR1_L_2 ((u32)0x00400000) /* Bit 2 */ -#define ADC_SQR1_L_3 ((u32)0x00800000) /* Bit 3 */ - - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ7 ((u32)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR2_SQ7_0 ((u32)0x00000001) /* Bit 0 */ -#define ADC_SQR2_SQ7_1 ((u32)0x00000002) /* Bit 1 */ -#define ADC_SQR2_SQ7_2 ((u32)0x00000004) /* Bit 2 */ -#define ADC_SQR2_SQ7_3 ((u32)0x00000008) /* Bit 3 */ -#define ADC_SQR2_SQ7_4 ((u32)0x00000010) /* Bit 4 */ - -#define ADC_SQR2_SQ8 ((u32)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR2_SQ8_0 ((u32)0x00000020) /* Bit 0 */ -#define ADC_SQR2_SQ8_1 ((u32)0x00000040) /* Bit 1 */ -#define ADC_SQR2_SQ8_2 ((u32)0x00000080) /* Bit 2 */ -#define ADC_SQR2_SQ8_3 ((u32)0x00000100) /* Bit 3 */ -#define ADC_SQR2_SQ8_4 ((u32)0x00000200) /* Bit 4 */ - -#define ADC_SQR2_SQ9 ((u32)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR2_SQ9_0 ((u32)0x00000400) /* Bit 0 */ -#define ADC_SQR2_SQ9_1 ((u32)0x00000800) /* Bit 1 */ -#define ADC_SQR2_SQ9_2 ((u32)0x00001000) /* Bit 2 */ -#define ADC_SQR2_SQ9_3 ((u32)0x00002000) /* Bit 3 */ -#define ADC_SQR2_SQ9_4 ((u32)0x00004000) /* Bit 4 */ - -#define ADC_SQR2_SQ10 ((u32)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR2_SQ10_0 ((u32)0x00008000) /* Bit 0 */ -#define ADC_SQR2_SQ10_1 ((u32)0x00010000) /* Bit 1 */ -#define ADC_SQR2_SQ10_2 ((u32)0x00020000) /* Bit 2 */ -#define ADC_SQR2_SQ10_3 ((u32)0x00040000) /* Bit 3 */ -#define ADC_SQR2_SQ10_4 ((u32)0x00080000) /* Bit 4 */ - -#define ADC_SQR2_SQ11 ((u32)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR2_SQ11_0 ((u32)0x00100000) /* Bit 0 */ -#define ADC_SQR2_SQ11_1 ((u32)0x00200000) /* Bit 1 */ -#define ADC_SQR2_SQ11_2 ((u32)0x00400000) /* Bit 2 */ -#define ADC_SQR2_SQ11_3 ((u32)0x00800000) /* Bit 3 */ -#define ADC_SQR2_SQ11_4 ((u32)0x01000000) /* Bit 4 */ - -#define ADC_SQR2_SQ12 ((u32)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR2_SQ12_0 ((u32)0x02000000) /* Bit 0 */ -#define ADC_SQR2_SQ12_1 ((u32)0x04000000) /* Bit 1 */ -#define ADC_SQR2_SQ12_2 ((u32)0x08000000) /* Bit 2 */ -#define ADC_SQR2_SQ12_3 ((u32)0x10000000) /* Bit 3 */ -#define ADC_SQR2_SQ12_4 ((u32)0x20000000) /* Bit 4 */ - - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ1 ((u32)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR3_SQ1_0 ((u32)0x00000001) /* Bit 0 */ -#define ADC_SQR3_SQ1_1 ((u32)0x00000002) /* Bit 1 */ -#define ADC_SQR3_SQ1_2 ((u32)0x00000004) /* Bit 2 */ -#define ADC_SQR3_SQ1_3 ((u32)0x00000008) /* Bit 3 */ -#define ADC_SQR3_SQ1_4 ((u32)0x00000010) /* Bit 4 */ - -#define ADC_SQR3_SQ2 ((u32)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR3_SQ2_0 ((u32)0x00000020) /* Bit 0 */ -#define ADC_SQR3_SQ2_1 ((u32)0x00000040) /* Bit 1 */ -#define ADC_SQR3_SQ2_2 ((u32)0x00000080) /* Bit 2 */ -#define ADC_SQR3_SQ2_3 ((u32)0x00000100) /* Bit 3 */ -#define ADC_SQR3_SQ2_4 ((u32)0x00000200) /* Bit 4 */ - -#define ADC_SQR3_SQ3 ((u32)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR3_SQ3_0 ((u32)0x00000400) /* Bit 0 */ -#define ADC_SQR3_SQ3_1 ((u32)0x00000800) /* Bit 1 */ -#define ADC_SQR3_SQ3_2 ((u32)0x00001000) /* Bit 2 */ -#define ADC_SQR3_SQ3_3 ((u32)0x00002000) /* Bit 3 */ -#define ADC_SQR3_SQ3_4 ((u32)0x00004000) /* Bit 4 */ - -#define ADC_SQR3_SQ4 ((u32)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR3_SQ4_0 ((u32)0x00008000) /* Bit 0 */ -#define ADC_SQR3_SQ4_1 ((u32)0x00010000) /* Bit 1 */ -#define ADC_SQR3_SQ4_2 ((u32)0x00020000) /* Bit 2 */ -#define ADC_SQR3_SQ4_3 ((u32)0x00040000) /* Bit 3 */ -#define ADC_SQR3_SQ4_4 ((u32)0x00080000) /* Bit 4 */ - -#define ADC_SQR3_SQ5 ((u32)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR3_SQ5_0 ((u32)0x00100000) /* Bit 0 */ -#define ADC_SQR3_SQ5_1 ((u32)0x00200000) /* Bit 1 */ -#define ADC_SQR3_SQ5_2 ((u32)0x00400000) /* Bit 2 */ -#define ADC_SQR3_SQ5_3 ((u32)0x00800000) /* Bit 3 */ -#define ADC_SQR3_SQ5_4 ((u32)0x01000000) /* Bit 4 */ - -#define ADC_SQR3_SQ6 ((u32)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR3_SQ6_0 ((u32)0x02000000) /* Bit 0 */ -#define ADC_SQR3_SQ6_1 ((u32)0x04000000) /* Bit 1 */ -#define ADC_SQR3_SQ6_2 ((u32)0x08000000) /* Bit 2 */ -#define ADC_SQR3_SQ6_3 ((u32)0x10000000) /* Bit 3 */ -#define ADC_SQR3_SQ6_4 ((u32)0x20000000) /* Bit 4 */ - - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((u32)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((u32)0x00000001) /* Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((u32)0x00000002) /* Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((u32)0x00000004) /* Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((u32)0x00000008) /* Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((u32)0x00000010) /* Bit 4 */ - -#define ADC_JSQR_JSQ2 ((u32)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((u32)0x00000020) /* Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((u32)0x00000040) /* Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((u32)0x00000080) /* Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((u32)0x00000100) /* Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((u32)0x00000200) /* Bit 4 */ - -#define ADC_JSQR_JSQ3 ((u32)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((u32)0x00000400) /* Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((u32)0x00000800) /* Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((u32)0x00001000) /* Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((u32)0x00002000) /* Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((u32)0x00004000) /* Bit 4 */ - -#define ADC_JSQR_JSQ4 ((u32)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((u32)0x00008000) /* Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((u32)0x00010000) /* Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((u32)0x00020000) /* Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((u32)0x00040000) /* Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((u32)0x00080000) /* Bit 4 */ - -#define ADC_JSQR_JL ((u32)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((u32)0x00100000) /* Bit 0 */ -#define ADC_JSQR_JL_1 ((u32)0x00200000) /* Bit 1 */ - - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((u16)0xFFFF) /* Injected data */ - - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((u16)0xFFFF) /* Injected data */ - - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((u16)0xFFFF) /* Injected data */ - - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((u16)0xFFFF) /* Injected data */ - - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((u32)0x0000FFFF) /* Regular data */ -#define ADC_DR_ADC2DATA ((u32)0xFFFF0000) /* ADC2 data */ - - - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((u32)0x00000001) /* DAC channel1 enable */ -#define DAC_CR_BOFF1 ((u32)0x00000002) /* DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 ((u32)0x00000004) /* DAC channel1 Trigger enable */ - -#define DAC_CR_TSEL1 ((u32)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ -#define DAC_CR_TSEL1_0 ((u32)0x00000008) /* Bit 0 */ -#define DAC_CR_TSEL1_1 ((u32)0x00000010) /* Bit 1 */ -#define DAC_CR_TSEL1_2 ((u32)0x00000020) /* Bit 2 */ - -#define DAC_CR_WAVE1 ((u32)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE1_0 ((u32)0x00000040) /* Bit 0 */ -#define DAC_CR_WAVE1_1 ((u32)0x00000080) /* Bit 1 */ - -#define DAC_CR_MAMP1 ((u32)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ -#define DAC_CR_MAMP1_0 ((u32)0x00000100) /* Bit 0 */ -#define DAC_CR_MAMP1_1 ((u32)0x00000200) /* Bit 1 */ -#define DAC_CR_MAMP1_2 ((u32)0x00000400) /* Bit 2 */ -#define DAC_CR_MAMP1_3 ((u32)0x00000800) /* Bit 3 */ - -#define DAC_CR_DMAEN1 ((u32)0x00001000) /* DAC channel1 DMA enable */ -#define DAC_CR_EN2 ((u32)0x00010000) /* DAC channel2 enable */ -#define DAC_CR_BOFF2 ((u32)0x00020000) /* DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 ((u32)0x00040000) /* DAC channel2 Trigger enable */ - -#define DAC_CR_TSEL2 ((u32)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ -#define DAC_CR_TSEL2_0 ((u32)0x00080000) /* Bit 0 */ -#define DAC_CR_TSEL2_1 ((u32)0x00100000) /* Bit 1 */ -#define DAC_CR_TSEL2_2 ((u32)0x00200000) /* Bit 2 */ - -#define DAC_CR_WAVE2 ((u32)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ -#define DAC_CR_WAVE2_0 ((u32)0x00400000) /* Bit 0 */ -#define DAC_CR_WAVE2_1 ((u32)0x00800000) /* Bit 1 */ - -#define DAC_CR_MAMP2 ((u32)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ -#define DAC_CR_MAMP2_0 ((u32)0x01000000) /* Bit 0 */ -#define DAC_CR_MAMP2_1 ((u32)0x02000000) /* Bit 1 */ -#define DAC_CR_MAMP2_2 ((u32)0x04000000) /* Bit 2 */ -#define DAC_CR_MAMP2_3 ((u32)0x08000000) /* Bit 3 */ - -#define DAC_CR_DMAEN2 ((u32)0x10000000) /* DAC channel2 DMA enabled */ - - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((u8)0x01) /* DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 ((u8)0x02) /* DAC channel2 software trigger */ - - -/***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((u16)0x0FFF) /* DAC channel1 12-bit Right aligned data */ - - -/***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((u16)0xFFF0) /* DAC channel1 12-bit Left aligned data */ - - -/****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((u8)0xFF) /* DAC channel1 8-bit Right aligned data */ - - -/***************** Bit definition for DAC_DHR12R2 register ******************/ -#define DAC_DHR12R2_DACC2DHR ((u16)0x0FFF) /* DAC channel2 12-bit Right aligned data */ - - -/***************** Bit definition for DAC_DHR12L2 register ******************/ -#define DAC_DHR12L2_DACC2DHR ((u16)0xFFF0) /* DAC channel2 12-bit Left aligned data */ - - -/****************** Bit definition for DAC_DHR8R2 register ******************/ -#define DAC_DHR8R2_DACC2DHR ((u8)0xFF) /* DAC channel2 8-bit Right aligned data */ - - -/***************** Bit definition for DAC_DHR12RD register ******************/ -#define DAC_DHR12RD_DACC1DHR ((u32)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ -#define DAC_DHR12RD_DACC2DHR ((u32)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ - - -/***************** Bit definition for DAC_DHR12LD register ******************/ -#define DAC_DHR12LD_DACC1DHR ((u32)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ -#define DAC_DHR12LD_DACC2DHR ((u32)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ - - -/****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((u16)0x00FF) /* DAC channel1 8-bit Right aligned data */ -#define DAC_DHR8RD_DACC2DHR ((u16)0xFF00) /* DAC channel2 8-bit Right aligned data */ - - -/******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((u16)0x0FFF) /* DAC channel1 data output */ - - -/******************* Bit definition for DAC_DOR2 register *******************/ -#define DAC_DOR2_DACC2DOR ((u16)0x0FFF) /* DAC channel2 data output */ - - - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((u16)0x0001) /* Counter enable */ -#define TIM_CR1_UDIS ((u16)0x0002) /* Update disable */ -#define TIM_CR1_URS ((u16)0x0004) /* Update request source */ -#define TIM_CR1_OPM ((u16)0x0008) /* One pulse mode */ -#define TIM_CR1_DIR ((u16)0x0010) /* Direction */ - -#define TIM_CR1_CMS ((u16)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((u16)0x0020) /* Bit 0 */ -#define TIM_CR1_CMS_1 ((u16)0x0040) /* Bit 1 */ - -#define TIM_CR1_ARPE ((u16)0x0080) /* Auto-reload preload enable */ - -#define TIM_CR1_CKD ((u16)0x0300) /* CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((u16)0x0100) /* Bit 0 */ -#define TIM_CR1_CKD_1 ((u16)0x0200) /* Bit 1 */ - - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_CCPC ((u16)0x0001) /* Capture/Compare Preloaded Control */ -#define TIM_CR2_CCUS ((u16)0x0004) /* Capture/Compare Control Update Selection */ -#define TIM_CR2_CCDS ((u16)0x0008) /* Capture/Compare DMA Selection */ - -#define TIM_CR2_MMS ((u16)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((u16)0x0010) /* Bit 0 */ -#define TIM_CR2_MMS_1 ((u16)0x0020) /* Bit 1 */ -#define TIM_CR2_MMS_2 ((u16)0x0040) /* Bit 2 */ - -#define TIM_CR2_TI1S ((u16)0x0080) /* TI1 Selection */ -#define TIM_CR2_OIS1 ((u16)0x0100) /* Output Idle state 1 (OC1 output) */ -#define TIM_CR2_OIS1N ((u16)0x0200) /* Output Idle state 1 (OC1N output) */ -#define TIM_CR2_OIS2 ((u16)0x0400) /* Output Idle state 2 (OC2 output) */ -#define TIM_CR2_OIS2N ((u16)0x0800) /* Output Idle state 2 (OC2N output) */ -#define TIM_CR2_OIS3 ((u16)0x1000) /* Output Idle state 3 (OC3 output) */ -#define TIM_CR2_OIS3N ((u16)0x2000) /* Output Idle state 3 (OC3N output) */ -#define TIM_CR2_OIS4 ((u16)0x4000) /* Output Idle state 4 (OC4 output) */ - - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((u16)0x0007) /* SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((u16)0x0001) /* Bit 0 */ -#define TIM_SMCR_SMS_1 ((u16)0x0002) /* Bit 1 */ -#define TIM_SMCR_SMS_2 ((u16)0x0004) /* Bit 2 */ - -#define TIM_SMCR_TS ((u16)0x0070) /* TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((u16)0x0010) /* Bit 0 */ -#define TIM_SMCR_TS_1 ((u16)0x0020) /* Bit 1 */ -#define TIM_SMCR_TS_2 ((u16)0x0040) /* Bit 2 */ - -#define TIM_SMCR_MSM ((u16)0x0080) /* Master/slave mode */ - -#define TIM_SMCR_ETF ((u16)0x0F00) /* ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((u16)0x0100) /* Bit 0 */ -#define TIM_SMCR_ETF_1 ((u16)0x0200) /* Bit 1 */ -#define TIM_SMCR_ETF_2 ((u16)0x0400) /* Bit 2 */ -#define TIM_SMCR_ETF_3 ((u16)0x0800) /* Bit 3 */ - -#define TIM_SMCR_ETPS ((u16)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((u16)0x1000) /* Bit 0 */ -#define TIM_SMCR_ETPS_1 ((u16)0x2000) /* Bit 1 */ - -#define TIM_SMCR_ECE ((u16)0x4000) /* External clock enable */ -#define TIM_SMCR_ETP ((u16)0x8000) /* External trigger polarity */ - - -/******************* Bit definition for TIM_DIER register *******************/ -#define TIM_DIER_UIE ((u16)0x0001) /* Update interrupt enable */ -#define TIM_DIER_CC1IE ((u16)0x0002) /* Capture/Compare 1 interrupt enable */ -#define TIM_DIER_CC2IE ((u16)0x0004) /* Capture/Compare 2 interrupt enable */ -#define TIM_DIER_CC3IE ((u16)0x0008) /* Capture/Compare 3 interrupt enable */ -#define TIM_DIER_CC4IE ((u16)0x0010) /* Capture/Compare 4 interrupt enable */ -#define TIM_DIER_COMIE ((u16)0x0020) /* COM interrupt enable */ -#define TIM_DIER_TIE ((u16)0x0040) /* Trigger interrupt enable */ -#define TIM_DIER_BIE ((u16)0x0080) /* Break interrupt enable */ -#define TIM_DIER_UDE ((u16)0x0100) /* Update DMA request enable */ -#define TIM_DIER_CC1DE ((u16)0x0200) /* Capture/Compare 1 DMA request enable */ -#define TIM_DIER_CC2DE ((u16)0x0400) /* Capture/Compare 2 DMA request enable */ -#define TIM_DIER_CC3DE ((u16)0x0800) /* Capture/Compare 3 DMA request enable */ -#define TIM_DIER_CC4DE ((u16)0x1000) /* Capture/Compare 4 DMA request enable */ -#define TIM_DIER_COMDE ((u16)0x2000) /* COM DMA request enable */ -#define TIM_DIER_TDE ((u16)0x4000) /* Trigger DMA request enable */ - - -/******************** Bit definition for TIM_SR register ********************/ -#define TIM_SR_UIF ((u16)0x0001) /* Update interrupt Flag */ -#define TIM_SR_CC1IF ((u16)0x0002) /* Capture/Compare 1 interrupt Flag */ -#define TIM_SR_CC2IF ((u16)0x0004) /* Capture/Compare 2 interrupt Flag */ -#define TIM_SR_CC3IF ((u16)0x0008) /* Capture/Compare 3 interrupt Flag */ -#define TIM_SR_CC4IF ((u16)0x0010) /* Capture/Compare 4 interrupt Flag */ -#define TIM_SR_COMIF ((u16)0x0020) /* COM interrupt Flag */ -#define TIM_SR_TIF ((u16)0x0040) /* Trigger interrupt Flag */ -#define TIM_SR_BIF ((u16)0x0080) /* Break interrupt Flag */ -#define TIM_SR_CC1OF ((u16)0x0200) /* Capture/Compare 1 Overcapture Flag */ -#define TIM_SR_CC2OF ((u16)0x0400) /* Capture/Compare 2 Overcapture Flag */ -#define TIM_SR_CC3OF ((u16)0x0800) /* Capture/Compare 3 Overcapture Flag */ -#define TIM_SR_CC4OF ((u16)0x1000) /* Capture/Compare 4 Overcapture Flag */ - - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((u8)0x01) /* Update Generation */ -#define TIM_EGR_CC1G ((u8)0x02) /* Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((u8)0x04) /* Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((u8)0x08) /* Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((u8)0x10) /* Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((u8)0x20) /* Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((u8)0x40) /* Trigger Generation */ -#define TIM_EGR_BG ((u8)0x80) /* Break Generation */ - - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((u16)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((u16)0x0001) /* Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((u16)0x0002) /* Bit 1 */ - -#define TIM_CCMR1_OC1FE ((u16)0x0004) /* Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((u16)0x0008) /* Output Compare 1 Preload enable */ - -#define TIM_CCMR1_OC1M ((u16)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((u16)0x0010) /* Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((u16)0x0020) /* Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((u16)0x0040) /* Bit 2 */ - -#define TIM_CCMR1_OC1CE ((u16)0x0080) /* Output Compare 1Clear Enable */ - -#define TIM_CCMR1_CC2S ((u16)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((u16)0x0100) /* Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((u16)0x0200) /* Bit 1 */ - -#define TIM_CCMR1_OC2FE ((u16)0x0400) /* Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((u16)0x0800) /* Output Compare 2 Preload enable */ - -#define TIM_CCMR1_OC2M ((u16)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((u16)0x1000) /* Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((u16)0x2000) /* Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((u16)0x4000) /* Bit 2 */ - -#define TIM_CCMR1_OC2CE ((u16)0x8000) /* Output Compare 2 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR1_IC1PSC ((u16)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((u16)0x0004) /* Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((u16)0x0008) /* Bit 1 */ - -#define TIM_CCMR1_IC1F ((u16)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((u16)0x0010) /* Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((u16)0x0020) /* Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((u16)0x0040) /* Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((u16)0x0080) /* Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((u16)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((u16)0x0400) /* Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((u16)0x0800) /* Bit 1 */ - -#define TIM_CCMR1_IC2F ((u16)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((u16)0x1000) /* Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((u16)0x2000) /* Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((u16)0x4000) /* Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((u16)0x8000) /* Bit 3 */ - - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((u16)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((u16)0x0001) /* Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((u16)0x0002) /* Bit 1 */ - -#define TIM_CCMR2_OC3FE ((u16)0x0004) /* Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((u16)0x0008) /* Output Compare 3 Preload enable */ - -#define TIM_CCMR2_OC3M ((u16)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((u16)0x0010) /* Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((u16)0x0020) /* Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((u16)0x0040) /* Bit 2 */ - -#define TIM_CCMR2_OC3CE ((u16)0x0080) /* Output Compare 3 Clear Enable */ - -#define TIM_CCMR2_CC4S ((u16)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((u16)0x0100) /* Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((u16)0x0200) /* Bit 1 */ - -#define TIM_CCMR2_OC4FE ((u16)0x0400) /* Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((u16)0x0800) /* Output Compare 4 Preload enable */ - -#define TIM_CCMR2_OC4M ((u16)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((u16)0x1000) /* Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((u16)0x2000) /* Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((u16)0x4000) /* Bit 2 */ - -#define TIM_CCMR2_OC4CE ((u16)0x8000) /* Output Compare 4 Clear Enable */ - -/*----------------------------------------------------------------------------*/ - -#define TIM_CCMR2_IC3PSC ((u16)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((u16)0x0004) /* Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((u16)0x0008) /* Bit 1 */ - -#define TIM_CCMR2_IC3F ((u16)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((u16)0x0010) /* Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((u16)0x0020) /* Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((u16)0x0040) /* Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((u16)0x0080) /* Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((u16)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((u16)0x0400) /* Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((u16)0x0800) /* Bit 1 */ - -#define TIM_CCMR2_IC4F ((u16)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((u16)0x1000) /* Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((u16)0x2000) /* Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((u16)0x4000) /* Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((u16)0x8000) /* Bit 3 */ - - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((u16)0x0001) /* Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((u16)0x0002) /* Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC1NE ((u16)0x0004) /* Capture/Compare 1 Complementary output enable */ -#define TIM_CCER_CC1NP ((u16)0x0008) /* Capture/Compare 1 Complementary output Polarity */ -#define TIM_CCER_CC2E ((u16)0x0010) /* Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((u16)0x0020) /* Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC2NE ((u16)0x0040) /* Capture/Compare 2 Complementary output enable */ -#define TIM_CCER_CC2NP ((u16)0x0080) /* Capture/Compare 2 Complementary output Polarity */ -#define TIM_CCER_CC3E ((u16)0x0100) /* Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((u16)0x0200) /* Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC3NE ((u16)0x0400) /* Capture/Compare 3 Complementary output enable */ -#define TIM_CCER_CC3NP ((u16)0x0800) /* Capture/Compare 3 Complementary output Polarity */ -#define TIM_CCER_CC4E ((u16)0x1000) /* Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((u16)0x2000) /* Capture/Compare 4 output Polarity */ - - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((u16)0xFFFF) /* Counter Value */ - - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((u16)0xFFFF) /* Prescaler Value */ - - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((u16)0xFFFF) /* actual auto-reload Value */ - - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((u8)0xFF) /* Repetition Counter Value */ - - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((u16)0xFFFF) /* Capture/Compare 1 Value */ - - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((u16)0xFFFF) /* Capture/Compare 2 Value */ - - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((u16)0xFFFF) /* Capture/Compare 3 Value */ - - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((u16)0xFFFF) /* Capture/Compare 4 Value */ - - -/******************* Bit definition for TIM_BDTR register *******************/ -#define TIM_BDTR_DTG ((u16)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ -#define TIM_BDTR_DTG_0 ((u16)0x0001) /* Bit 0 */ -#define TIM_BDTR_DTG_1 ((u16)0x0002) /* Bit 1 */ -#define TIM_BDTR_DTG_2 ((u16)0x0004) /* Bit 2 */ -#define TIM_BDTR_DTG_3 ((u16)0x0008) /* Bit 3 */ -#define TIM_BDTR_DTG_4 ((u16)0x0010) /* Bit 4 */ -#define TIM_BDTR_DTG_5 ((u16)0x0020) /* Bit 5 */ -#define TIM_BDTR_DTG_6 ((u16)0x0040) /* Bit 6 */ -#define TIM_BDTR_DTG_7 ((u16)0x0080) /* Bit 7 */ - -#define TIM_BDTR_LOCK ((u16)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ -#define TIM_BDTR_LOCK_0 ((u16)0x0100) /* Bit 0 */ -#define TIM_BDTR_LOCK_1 ((u16)0x0200) /* Bit 1 */ - -#define TIM_BDTR_OSSI ((u16)0x0400) /* Off-State Selection for Idle mode */ -#define TIM_BDTR_OSSR ((u16)0x0800) /* Off-State Selection for Run mode */ -#define TIM_BDTR_BKE ((u16)0x1000) /* Break enable */ -#define TIM_BDTR_BKP ((u16)0x2000) /* Break Polarity */ -#define TIM_BDTR_AOE ((u16)0x4000) /* Automatic Output enable */ -#define TIM_BDTR_MOE ((u16)0x8000) /* Main Output enable */ - - -/******************* Bit definition for TIM_DCR register ********************/ -#define TIM_DCR_DBA ((u16)0x001F) /* DBA[4:0] bits (DMA Base Address) */ -#define TIM_DCR_DBA_0 ((u16)0x0001) /* Bit 0 */ -#define TIM_DCR_DBA_1 ((u16)0x0002) /* Bit 1 */ -#define TIM_DCR_DBA_2 ((u16)0x0004) /* Bit 2 */ -#define TIM_DCR_DBA_3 ((u16)0x0008) /* Bit 3 */ -#define TIM_DCR_DBA_4 ((u16)0x0010) /* Bit 4 */ - -#define TIM_DCR_DBL ((u16)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ -#define TIM_DCR_DBL_0 ((u16)0x0100) /* Bit 0 */ -#define TIM_DCR_DBL_1 ((u16)0x0200) /* Bit 1 */ -#define TIM_DCR_DBL_2 ((u16)0x0400) /* Bit 2 */ -#define TIM_DCR_DBL_3 ((u16)0x0800) /* Bit 3 */ -#define TIM_DCR_DBL_4 ((u16)0x1000) /* Bit 4 */ - - -/******************* Bit definition for TIM_DMAR register *******************/ -#define TIM_DMAR_DMAB ((u16)0xFFFF) /* DMA register for burst accesses */ - - - -/******************************************************************************/ -/* */ -/* Real-Time Clock */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for RTC_CRH register ********************/ -#define RTC_CRH_SECIE ((u8)0x01) /* Second Interrupt Enable */ -#define RTC_CRH_ALRIE ((u8)0x02) /* Alarm Interrupt Enable */ -#define RTC_CRH_OWIE ((u8)0x04) /* OverfloW Interrupt Enable */ - - -/******************* Bit definition for RTC_CRL register ********************/ -#define RTC_CRL_SECF ((u8)0x01) /* Second Flag */ -#define RTC_CRL_ALRF ((u8)0x02) /* Alarm Flag */ -#define RTC_CRL_OWF ((u8)0x04) /* OverfloW Flag */ -#define RTC_CRL_RSF ((u8)0x08) /* Registers Synchronized Flag */ -#define RTC_CRL_CNF ((u8)0x10) /* Configuration Flag */ -#define RTC_CRL_RTOFF ((u8)0x20) /* RTC operation OFF */ - - -/******************* Bit definition for RTC_PRLH register *******************/ -#define RTC_PRLH_PRL ((u16)0x000F) /* RTC Prescaler Reload Value High */ - - -/******************* Bit definition for RTC_PRLL register *******************/ -#define RTC_PRLL_PRL ((u16)0xFFFF) /* RTC Prescaler Reload Value Low */ - - -/******************* Bit definition for RTC_DIVH register *******************/ -#define RTC_DIVH_RTC_DIV ((u16)0x000F) /* RTC Clock Divider High */ - - -/******************* Bit definition for RTC_DIVL register *******************/ -#define RTC_DIVL_RTC_DIV ((u16)0xFFFF) /* RTC Clock Divider Low */ - - -/******************* Bit definition for RTC_CNTH register *******************/ -#define RTC_CNTH_RTC_CNT ((u16)0xFFFF) /* RTC Counter High */ - - -/******************* Bit definition for RTC_CNTL register *******************/ -#define RTC_CNTL_RTC_CNT ((u16)0xFFFF) /* RTC Counter Low */ - - -/******************* Bit definition for RTC_ALRH register *******************/ -#define RTC_ALRH_RTC_ALR ((u16)0xFFFF) /* RTC Alarm High */ - - -/******************* Bit definition for RTC_ALRL register *******************/ -#define RTC_ALRL_RTC_ALR ((u16)0xFFFF) /* RTC Alarm Low */ - - - -/******************************************************************************/ -/* */ -/* Independent WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for IWDG_KR register ********************/ -#define IWDG_KR_KEY ((u16)0xFFFF) /* Key value (write only, read 0000h) */ - - -/******************* Bit definition for IWDG_PR register ********************/ -#define IWDG_PR_PR ((u8)0x07) /* PR[2:0] (Prescaler divider) */ -#define IWDG_PR_PR_0 ((u8)0x01) /* Bit 0 */ -#define IWDG_PR_PR_1 ((u8)0x02) /* Bit 1 */ -#define IWDG_PR_PR_2 ((u8)0x04) /* Bit 2 */ - - -/******************* Bit definition for IWDG_RLR register *******************/ -#define IWDG_RLR_RL ((u16)0x0FFF) /* Watchdog counter reload value */ - - -/******************* Bit definition for IWDG_SR register ********************/ -#define IWDG_SR_PVU ((u8)0x01) /* Watchdog prescaler value update */ -#define IWDG_SR_RVU ((u8)0x02) /* Watchdog counter reload value update */ - - - -/******************************************************************************/ -/* */ -/* Window WATCHDOG */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for WWDG_CR register ********************/ -#define WWDG_CR_T ((u8)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ -#define WWDG_CR_T0 ((u8)0x01) /* Bit 0 */ -#define WWDG_CR_T1 ((u8)0x02) /* Bit 1 */ -#define WWDG_CR_T2 ((u8)0x04) /* Bit 2 */ -#define WWDG_CR_T3 ((u8)0x08) /* Bit 3 */ -#define WWDG_CR_T4 ((u8)0x10) /* Bit 4 */ -#define WWDG_CR_T5 ((u8)0x20) /* Bit 5 */ -#define WWDG_CR_T6 ((u8)0x40) /* Bit 6 */ - -#define WWDG_CR_WDGA ((u8)0x80) /* Activation bit */ - - -/******************* Bit definition for WWDG_CFR register *******************/ -#define WWDG_CFR_W ((u16)0x007F) /* W[6:0] bits (7-bit window value) */ -#define WWDG_CFR_W0 ((u16)0x0001) /* Bit 0 */ -#define WWDG_CFR_W1 ((u16)0x0002) /* Bit 1 */ -#define WWDG_CFR_W2 ((u16)0x0004) /* Bit 2 */ -#define WWDG_CFR_W3 ((u16)0x0008) /* Bit 3 */ -#define WWDG_CFR_W4 ((u16)0x0010) /* Bit 4 */ -#define WWDG_CFR_W5 ((u16)0x0020) /* Bit 5 */ -#define WWDG_CFR_W6 ((u16)0x0040) /* Bit 6 */ - -#define WWDG_CFR_WDGTB ((u16)0x0180) /* WDGTB[1:0] bits (Timer Base) */ -#define WWDG_CFR_WDGTB0 ((u16)0x0080) /* Bit 0 */ -#define WWDG_CFR_WDGTB1 ((u16)0x0100) /* Bit 1 */ - -#define WWDG_CFR_EWI ((u16)0x0200) /* Early Wakeup Interrupt */ - - -/******************* Bit definition for WWDG_SR register ********************/ -#define WWDG_SR_EWIF ((u8)0x01) /* Early Wakeup Interrupt Flag */ - - - -/******************************************************************************/ -/* */ -/* Flexible Static Memory Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for FSMC_BCR1 register *******************/ -#define FSMC_BCR1_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ -#define FSMC_BCR1_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ - -#define FSMC_BCR1_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR1_MTYP_0 ((u32)0x00000004) /* Bit 0 */ -#define FSMC_BCR1_MTYP_1 ((u32)0x00000008) /* Bit 1 */ - -#define FSMC_BCR1_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR1_MWID_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BCR1_MWID_1 ((u32)0x00000020) /* Bit 1 */ - -#define FSMC_BCR1_FACCEN ((u32)0x00000040) /* Flash access enable */ -#define FSMC_BCR1_BURSTEN ((u32)0x00000100) /* Burst enable bit */ -#define FSMC_BCR1_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ -#define FSMC_BCR1_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ -#define FSMC_BCR1_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ -#define FSMC_BCR1_WREN ((u32)0x00001000) /* Write enable bit */ -#define FSMC_BCR1_WAITEN ((u32)0x00002000) /* Wait enable bit */ -#define FSMC_BCR1_EXTMOD ((u32)0x00004000) /* Extended mode enable */ -#define FSMC_BCR1_CBURSTRW ((u32)0x00080000) /* Write burst enable */ - - -/****************** Bit definition for FSMC_BCR2 register *******************/ -#define FSMC_BCR2_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ -#define FSMC_BCR2_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ - -#define FSMC_BCR2_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR2_MTYP_0 ((u32)0x00000004) /* Bit 0 */ -#define FSMC_BCR2_MTYP_1 ((u32)0x00000008) /* Bit 1 */ - -#define FSMC_BCR2_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR2_MWID_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BCR2_MWID_1 ((u32)0x00000020) /* Bit 1 */ - -#define FSMC_BCR2_FACCEN ((u32)0x00000040) /* Flash access enable */ -#define FSMC_BCR2_BURSTEN ((u32)0x00000100) /* Burst enable bit */ -#define FSMC_BCR2_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ -#define FSMC_BCR2_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ -#define FSMC_BCR2_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ -#define FSMC_BCR2_WREN ((u32)0x00001000) /* Write enable bit */ -#define FSMC_BCR2_WAITEN ((u32)0x00002000) /* Wait enable bit */ -#define FSMC_BCR2_EXTMOD ((u32)0x00004000) /* Extended mode enable */ -#define FSMC_BCR2_CBURSTRW ((u32)0x00080000) /* Write burst enable */ - - -/****************** Bit definition for FSMC_BCR3 register *******************/ -#define FSMC_BCR3_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ -#define FSMC_BCR3_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ - -#define FSMC_BCR3_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR3_MTYP_0 ((u32)0x00000004) /* Bit 0 */ -#define FSMC_BCR3_MTYP_1 ((u32)0x00000008) /* Bit 1 */ - -#define FSMC_BCR3_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR3_MWID_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BCR3_MWID_1 ((u32)0x00000020) /* Bit 1 */ - -#define FSMC_BCR3_FACCEN ((u32)0x00000040) /* Flash access enable */ -#define FSMC_BCR3_BURSTEN ((u32)0x00000100) /* Burst enable bit */ -#define FSMC_BCR3_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit. */ -#define FSMC_BCR3_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ -#define FSMC_BCR3_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ -#define FSMC_BCR3_WREN ((u32)0x00001000) /* Write enable bit */ -#define FSMC_BCR3_WAITEN ((u32)0x00002000) /* Wait enable bit */ -#define FSMC_BCR3_EXTMOD ((u32)0x00004000) /* Extended mode enable */ -#define FSMC_BCR3_CBURSTRW ((u32)0x00080000) /* Write burst enable */ - - -/****************** Bit definition for FSMC_BCR4 register *******************/ -#define FSMC_BCR4_MBKEN ((u32)0x00000001) /* Memory bank enable bit */ -#define FSMC_BCR4_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */ - -#define FSMC_BCR4_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */ -#define FSMC_BCR4_MTYP_0 ((u32)0x00000004) /* Bit 0 */ -#define FSMC_BCR4_MTYP_1 ((u32)0x00000008) /* Bit 1 */ - -#define FSMC_BCR4_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */ -#define FSMC_BCR4_MWID_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BCR4_MWID_1 ((u32)0x00000020) /* Bit 1 */ - -#define FSMC_BCR4_FACCEN ((u32)0x00000040) /* Flash access enable */ -#define FSMC_BCR4_BURSTEN ((u32)0x00000100) /* Burst enable bit */ -#define FSMC_BCR4_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */ -#define FSMC_BCR4_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */ -#define FSMC_BCR4_WAITCFG ((u32)0x00000800) /* Wait timing configuration */ -#define FSMC_BCR4_WREN ((u32)0x00001000) /* Write enable bit */ -#define FSMC_BCR4_WAITEN ((u32)0x00002000) /* Wait enable bit */ -#define FSMC_BCR4_EXTMOD ((u32)0x00004000) /* Extended mode enable */ -#define FSMC_BCR4_CBURSTRW ((u32)0x00080000) /* Write burst enable */ - - -/****************** Bit definition for FSMC_BTR1 register ******************/ -#define FSMC_BTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ -#define FSMC_BTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/****************** Bit definition for FSMC_BTR2 register *******************/ -#define FSMC_BTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ -#define FSMC_BTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/******************* Bit definition for FSMC_BTR3 register *******************/ -#define FSMC_BTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ -#define FSMC_BTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/****************** Bit definition for FSMC_BTR4 register *******************/ -#define FSMC_BTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ -#define FSMC_BTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/****************** Bit definition for FSMC_BWTR1 register ******************/ -#define FSMC_BWTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BWTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BWTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BWTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BWTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BWTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BWTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BWTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BWTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BWTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BWTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BWTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BWTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BWTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BWTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BWTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BWTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BWTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BWTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ -#define FSMC_BWTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BWTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BWTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BWTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BWTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BWTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BWTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BWTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/****************** Bit definition for FSMC_BWTR2 register ******************/ -#define FSMC_BWTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BWTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BWTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BWTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BWTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BWTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BWTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BWTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BWTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BWTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BWTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BWTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BWTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BWTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BWTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BWTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BWTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BWTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BWTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1*/ -#define FSMC_BWTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BWTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BWTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BWTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BWTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BWTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BWTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BWTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/****************** Bit definition for FSMC_BWTR3 register ******************/ -#define FSMC_BWTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BWTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BWTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BWTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BWTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BWTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BWTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BWTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BWTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BWTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BWTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BWTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BWTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BWTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BWTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BWTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BWTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BWTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BWTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ -#define FSMC_BWTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BWTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BWTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BWTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BWTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BWTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BWTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BWTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/****************** Bit definition for FSMC_BWTR4 register ******************/ -#define FSMC_BWTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */ -#define FSMC_BWTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_BWTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_BWTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_BWTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */ - -#define FSMC_BWTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */ -#define FSMC_BWTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_BWTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */ -#define FSMC_BWTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */ -#define FSMC_BWTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */ - -#define FSMC_BWTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */ -#define FSMC_BWTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_BWTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_BWTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_BWTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */ - -#define FSMC_BWTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */ -#define FSMC_BWTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_BWTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_BWTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_BWTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */ - -#define FSMC_BWTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */ -#define FSMC_BWTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */ -#define FSMC_BWTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */ -#define FSMC_BWTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */ -#define FSMC_BWTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */ - -#define FSMC_BWTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */ -#define FSMC_BWTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_BWTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_BWTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_BWTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */ - -#define FSMC_BWTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */ -#define FSMC_BWTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */ -#define FSMC_BWTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */ - - -/****************** Bit definition for FSMC_PCR2 register *******************/ -#define FSMC_PCR2_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ -#define FSMC_PCR2_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR2_PTYP ((u32)0x00000008) /* Memory type */ - -#define FSMC_PCR2_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR2_PWID_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_PCR2_PWID_1 ((u32)0x00000020) /* Bit 1 */ - -#define FSMC_PCR2_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ -#define FSMC_PCR2_ADLOW ((u32)0x00000100) /* Address low bit delivery */ - -#define FSMC_PCR2_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR2_TCLR_0 ((u32)0x00000200) /* Bit 0 */ -#define FSMC_PCR2_TCLR_1 ((u32)0x00000400) /* Bit 1 */ -#define FSMC_PCR2_TCLR_2 ((u32)0x00000800) /* Bit 2 */ -#define FSMC_PCR2_TCLR_3 ((u32)0x00001000) /* Bit 3 */ - -#define FSMC_PCR2_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR2_TAR_0 ((u32)0x00002000) /* Bit 0 */ -#define FSMC_PCR2_TAR_1 ((u32)0x00004000) /* Bit 1 */ -#define FSMC_PCR2_TAR_2 ((u32)0x00008000) /* Bit 2 */ -#define FSMC_PCR2_TAR_3 ((u32)0x00010000) /* Bit 3 */ - -#define FSMC_PCR2_ECCPS ((u32)0x000E0000) /* ECCPS[1:0] bits (ECC page size) */ -#define FSMC_PCR2_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ -#define FSMC_PCR2_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ -#define FSMC_PCR2_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ - - -/****************** Bit definition for FSMC_PCR3 register *******************/ -#define FSMC_PCR3_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ -#define FSMC_PCR3_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR3_PTYP ((u32)0x00000008) /* Memory type */ - -#define FSMC_PCR3_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR3_PWID_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_PCR3_PWID_1 ((u32)0x00000020) /* Bit 1 */ - -#define FSMC_PCR3_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ -#define FSMC_PCR3_ADLOW ((u32)0x00000100) /* Address low bit delivery */ - -#define FSMC_PCR3_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR3_TCLR_0 ((u32)0x00000200) /* Bit 0 */ -#define FSMC_PCR3_TCLR_1 ((u32)0x00000400) /* Bit 1 */ -#define FSMC_PCR3_TCLR_2 ((u32)0x00000800) /* Bit 2 */ -#define FSMC_PCR3_TCLR_3 ((u32)0x00001000) /* Bit 3 */ - -#define FSMC_PCR3_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR3_TAR_0 ((u32)0x00002000) /* Bit 0 */ -#define FSMC_PCR3_TAR_1 ((u32)0x00004000) /* Bit 1 */ -#define FSMC_PCR3_TAR_2 ((u32)0x00008000) /* Bit 2 */ -#define FSMC_PCR3_TAR_3 ((u32)0x00010000) /* Bit 3 */ - -#define FSMC_PCR3_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR3_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ -#define FSMC_PCR3_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ -#define FSMC_PCR3_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ - - -/****************** Bit definition for FSMC_PCR4 register *******************/ -#define FSMC_PCR4_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */ -#define FSMC_PCR4_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR4_PTYP ((u32)0x00000008) /* Memory type */ - -#define FSMC_PCR4_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */ -#define FSMC_PCR4_PWID_0 ((u32)0x00000010) /* Bit 0 */ -#define FSMC_PCR4_PWID_1 ((u32)0x00000020) /* Bit 1 */ - -#define FSMC_PCR4_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */ -#define FSMC_PCR4_ADLOW ((u32)0x00000100) /* Address low bit delivery */ - -#define FSMC_PCR4_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */ -#define FSMC_PCR4_TCLR_0 ((u32)0x00000200) /* Bit 0 */ -#define FSMC_PCR4_TCLR_1 ((u32)0x00000400) /* Bit 1 */ -#define FSMC_PCR4_TCLR_2 ((u32)0x00000800) /* Bit 2 */ -#define FSMC_PCR4_TCLR_3 ((u32)0x00001000) /* Bit 3 */ - -#define FSMC_PCR4_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */ -#define FSMC_PCR4_TAR_0 ((u32)0x00002000) /* Bit 0 */ -#define FSMC_PCR4_TAR_1 ((u32)0x00004000) /* Bit 1 */ -#define FSMC_PCR4_TAR_2 ((u32)0x00008000) /* Bit 2 */ -#define FSMC_PCR4_TAR_3 ((u32)0x00010000) /* Bit 3 */ - -#define FSMC_PCR4_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */ -#define FSMC_PCR4_ECCPS_0 ((u32)0x00020000) /* Bit 0 */ -#define FSMC_PCR4_ECCPS_1 ((u32)0x00040000) /* Bit 1 */ -#define FSMC_PCR4_ECCPS_2 ((u32)0x00080000) /* Bit 2 */ - - -/******************* Bit definition for FSMC_SR2 register *******************/ -#define FSMC_SR2_IRS ((u8)0x01) /* Interrupt Rising Edge status */ -#define FSMC_SR2_ILS ((u8)0x02) /* Interrupt Level status */ -#define FSMC_SR2_IFS ((u8)0x04) /* Interrupt Falling Edge status */ -#define FSMC_SR2_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR2_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ -#define FSMC_SR2_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR2_FEMPT ((u8)0x40) /* FIFO empty */ - - -/******************* Bit definition for FSMC_SR3 register *******************/ -#define FSMC_SR3_IRS ((u8)0x01) /* Interrupt Rising Edge status */ -#define FSMC_SR3_ILS ((u8)0x02) /* Interrupt Level status */ -#define FSMC_SR3_IFS ((u8)0x04) /* Interrupt Falling Edge status */ -#define FSMC_SR3_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR3_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ -#define FSMC_SR3_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR3_FEMPT ((u8)0x40) /* FIFO empty */ - - -/******************* Bit definition for FSMC_SR4 register *******************/ -#define FSMC_SR4_IRS ((u8)0x01) /* Interrupt Rising Edge status */ -#define FSMC_SR4_ILS ((u8)0x02) /* Interrupt Level status */ -#define FSMC_SR4_IFS ((u8)0x04) /* Interrupt Falling Edge status */ -#define FSMC_SR4_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR4_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */ -#define FSMC_SR4_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR4_FEMPT ((u8)0x40) /* FIFO empty */ - - -/****************** Bit definition for FSMC_PMEM2 register ******************/ -#define FSMC_PMEM2_MEMSET2 ((u32)0x000000FF) /* MEMSET2[7:0] bits (Common memory 2 setup time) */ -#define FSMC_PMEM2_MEMSET2_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_PMEM2_MEMSET2_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_PMEM2_MEMSET2_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_PMEM2_MEMSET2_3 ((u32)0x00000008) /* Bit 3 */ -#define FSMC_PMEM2_MEMSET2_4 ((u32)0x00000010) /* Bit 4 */ -#define FSMC_PMEM2_MEMSET2_5 ((u32)0x00000020) /* Bit 5 */ -#define FSMC_PMEM2_MEMSET2_6 ((u32)0x00000040) /* Bit 6 */ -#define FSMC_PMEM2_MEMSET2_7 ((u32)0x00000080) /* Bit 7 */ - -#define FSMC_PMEM2_MEMWAIT2 ((u32)0x0000FF00) /* MEMWAIT2[7:0] bits (Common memory 2 wait time) */ -#define FSMC_PMEM2_MEMWAIT2_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_PMEM2_MEMWAIT2_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_PMEM2_MEMWAIT2_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_PMEM2_MEMWAIT2_3 ((u32)0x00000800) /* Bit 3 */ -#define FSMC_PMEM2_MEMWAIT2_4 ((u32)0x00001000) /* Bit 4 */ -#define FSMC_PMEM2_MEMWAIT2_5 ((u32)0x00002000) /* Bit 5 */ -#define FSMC_PMEM2_MEMWAIT2_6 ((u32)0x00004000) /* Bit 6 */ -#define FSMC_PMEM2_MEMWAIT2_7 ((u32)0x00008000) /* Bit 7 */ - -#define FSMC_PMEM2_MEMHOLD2 ((u32)0x00FF0000) /* MEMHOLD2[7:0] bits (Common memory 2 hold time) */ -#define FSMC_PMEM2_MEMHOLD2_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_PMEM2_MEMHOLD2_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_PMEM2_MEMHOLD2_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_PMEM2_MEMHOLD2_3 ((u32)0x00080000) /* Bit 3 */ -#define FSMC_PMEM2_MEMHOLD2_4 ((u32)0x00100000) /* Bit 4 */ -#define FSMC_PMEM2_MEMHOLD2_5 ((u32)0x00200000) /* Bit 5 */ -#define FSMC_PMEM2_MEMHOLD2_6 ((u32)0x00400000) /* Bit 6 */ -#define FSMC_PMEM2_MEMHOLD2_7 ((u32)0x00800000) /* Bit 7 */ - -#define FSMC_PMEM2_MEMHIZ2 ((u32)0xFF000000) /* MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ -#define FSMC_PMEM2_MEMHIZ2_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_PMEM2_MEMHIZ2_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_PMEM2_MEMHIZ2_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_PMEM2_MEMHIZ2_3 ((u32)0x08000000) /* Bit 3 */ -#define FSMC_PMEM2_MEMHIZ2_4 ((u32)0x10000000) /* Bit 4 */ -#define FSMC_PMEM2_MEMHIZ2_5 ((u32)0x20000000) /* Bit 5 */ -#define FSMC_PMEM2_MEMHIZ2_6 ((u32)0x40000000) /* Bit 6 */ -#define FSMC_PMEM2_MEMHIZ2_7 ((u32)0x80000000) /* Bit 7 */ - - -/****************** Bit definition for FSMC_PMEM3 register ******************/ -#define FSMC_PMEM3_MEMSET3 ((u32)0x000000FF) /* MEMSET3[7:0] bits (Common memory 3 setup time) */ -#define FSMC_PMEM3_MEMSET3_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_PMEM3_MEMSET3_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_PMEM3_MEMSET3_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_PMEM3_MEMSET3_3 ((u32)0x00000008) /* Bit 3 */ -#define FSMC_PMEM3_MEMSET3_4 ((u32)0x00000010) /* Bit 4 */ -#define FSMC_PMEM3_MEMSET3_5 ((u32)0x00000020) /* Bit 5 */ -#define FSMC_PMEM3_MEMSET3_6 ((u32)0x00000040) /* Bit 6 */ -#define FSMC_PMEM3_MEMSET3_7 ((u32)0x00000080) /* Bit 7 */ - -#define FSMC_PMEM3_MEMWAIT3 ((u32)0x0000FF00) /* MEMWAIT3[7:0] bits (Common memory 3 wait time) */ -#define FSMC_PMEM3_MEMWAIT3_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_PMEM3_MEMWAIT3_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_PMEM3_MEMWAIT3_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_PMEM3_MEMWAIT3_3 ((u32)0x00000800) /* Bit 3 */ -#define FSMC_PMEM3_MEMWAIT3_4 ((u32)0x00001000) /* Bit 4 */ -#define FSMC_PMEM3_MEMWAIT3_5 ((u32)0x00002000) /* Bit 5 */ -#define FSMC_PMEM3_MEMWAIT3_6 ((u32)0x00004000) /* Bit 6 */ -#define FSMC_PMEM3_MEMWAIT3_7 ((u32)0x00008000) /* Bit 7 */ - -#define FSMC_PMEM3_MEMHOLD3 ((u32)0x00FF0000) /* MEMHOLD3[7:0] bits (Common memory 3 hold time) */ -#define FSMC_PMEM3_MEMHOLD3_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_PMEM3_MEMHOLD3_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_PMEM3_MEMHOLD3_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_PMEM3_MEMHOLD3_3 ((u32)0x00080000) /* Bit 3 */ -#define FSMC_PMEM3_MEMHOLD3_4 ((u32)0x00100000) /* Bit 4 */ -#define FSMC_PMEM3_MEMHOLD3_5 ((u32)0x00200000) /* Bit 5 */ -#define FSMC_PMEM3_MEMHOLD3_6 ((u32)0x00400000) /* Bit 6 */ -#define FSMC_PMEM3_MEMHOLD3_7 ((u32)0x00800000) /* Bit 7 */ - -#define FSMC_PMEM3_MEMHIZ3 ((u32)0xFF000000) /* MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ -#define FSMC_PMEM3_MEMHIZ3_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_PMEM3_MEMHIZ3_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_PMEM3_MEMHIZ3_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_PMEM3_MEMHIZ3_3 ((u32)0x08000000) /* Bit 3 */ -#define FSMC_PMEM3_MEMHIZ3_4 ((u32)0x10000000) /* Bit 4 */ -#define FSMC_PMEM3_MEMHIZ3_5 ((u32)0x20000000) /* Bit 5 */ -#define FSMC_PMEM3_MEMHIZ3_6 ((u32)0x40000000) /* Bit 6 */ -#define FSMC_PMEM3_MEMHIZ3_7 ((u32)0x80000000) /* Bit 7 */ - - -/****************** Bit definition for FSMC_PMEM4 register ******************/ -#define FSMC_PMEM4_MEMSET4 ((u32)0x000000FF) /* MEMSET4[7:0] bits (Common memory 4 setup time) */ -#define FSMC_PMEM4_MEMSET4_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_PMEM4_MEMSET4_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_PMEM4_MEMSET4_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_PMEM4_MEMSET4_3 ((u32)0x00000008) /* Bit 3 */ -#define FSMC_PMEM4_MEMSET4_4 ((u32)0x00000010) /* Bit 4 */ -#define FSMC_PMEM4_MEMSET4_5 ((u32)0x00000020) /* Bit 5 */ -#define FSMC_PMEM4_MEMSET4_6 ((u32)0x00000040) /* Bit 6 */ -#define FSMC_PMEM4_MEMSET4_7 ((u32)0x00000080) /* Bit 7 */ - -#define FSMC_PMEM4_MEMWAIT4 ((u32)0x0000FF00) /* MEMWAIT4[7:0] bits (Common memory 4 wait time) */ -#define FSMC_PMEM4_MEMWAIT4_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_PMEM4_MEMWAIT4_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_PMEM4_MEMWAIT4_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_PMEM4_MEMWAIT4_3 ((u32)0x00000800) /* Bit 3 */ -#define FSMC_PMEM4_MEMWAIT4_4 ((u32)0x00001000) /* Bit 4 */ -#define FSMC_PMEM4_MEMWAIT4_5 ((u32)0x00002000) /* Bit 5 */ -#define FSMC_PMEM4_MEMWAIT4_6 ((u32)0x00004000) /* Bit 6 */ -#define FSMC_PMEM4_MEMWAIT4_7 ((u32)0x00008000) /* Bit 7 */ - -#define FSMC_PMEM4_MEMHOLD4 ((u32)0x00FF0000) /* MEMHOLD4[7:0] bits (Common memory 4 hold time) */ -#define FSMC_PMEM4_MEMHOLD4_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_PMEM4_MEMHOLD4_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_PMEM4_MEMHOLD4_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_PMEM4_MEMHOLD4_3 ((u32)0x00080000) /* Bit 3 */ -#define FSMC_PMEM4_MEMHOLD4_4 ((u32)0x00100000) /* Bit 4 */ -#define FSMC_PMEM4_MEMHOLD4_5 ((u32)0x00200000) /* Bit 5 */ -#define FSMC_PMEM4_MEMHOLD4_6 ((u32)0x00400000) /* Bit 6 */ -#define FSMC_PMEM4_MEMHOLD4_7 ((u32)0x00800000) /* Bit 7 */ - -#define FSMC_PMEM4_MEMHIZ4 ((u32)0xFF000000) /* MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ -#define FSMC_PMEM4_MEMHIZ4_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_PMEM4_MEMHIZ4_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_PMEM4_MEMHIZ4_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_PMEM4_MEMHIZ4_3 ((u32)0x08000000) /* Bit 3 */ -#define FSMC_PMEM4_MEMHIZ4_4 ((u32)0x10000000) /* Bit 4 */ -#define FSMC_PMEM4_MEMHIZ4_5 ((u32)0x20000000) /* Bit 5 */ -#define FSMC_PMEM4_MEMHIZ4_6 ((u32)0x40000000) /* Bit 6 */ -#define FSMC_PMEM4_MEMHIZ4_7 ((u32)0x80000000) /* Bit 7 */ - - -/****************** Bit definition for FSMC_PATT2 register ******************/ -#define FSMC_PATT2_ATTSET2 ((u32)0x000000FF) /* ATTSET2[7:0] bits (Attribute memory 2 setup time) */ -#define FSMC_PATT2_ATTSET2_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_PATT2_ATTSET2_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_PATT2_ATTSET2_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_PATT2_ATTSET2_3 ((u32)0x00000008) /* Bit 3 */ -#define FSMC_PATT2_ATTSET2_4 ((u32)0x00000010) /* Bit 4 */ -#define FSMC_PATT2_ATTSET2_5 ((u32)0x00000020) /* Bit 5 */ -#define FSMC_PATT2_ATTSET2_6 ((u32)0x00000040) /* Bit 6 */ -#define FSMC_PATT2_ATTSET2_7 ((u32)0x00000080) /* Bit 7 */ - -#define FSMC_PATT2_ATTWAIT2 ((u32)0x0000FF00) /* ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ -#define FSMC_PATT2_ATTWAIT2_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_PATT2_ATTWAIT2_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_PATT2_ATTWAIT2_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_PATT2_ATTWAIT2_3 ((u32)0x00000800) /* Bit 3 */ -#define FSMC_PATT2_ATTWAIT2_4 ((u32)0x00001000) /* Bit 4 */ -#define FSMC_PATT2_ATTWAIT2_5 ((u32)0x00002000) /* Bit 5 */ -#define FSMC_PATT2_ATTWAIT2_6 ((u32)0x00004000) /* Bit 6 */ -#define FSMC_PATT2_ATTWAIT2_7 ((u32)0x00008000) /* Bit 7 */ - -#define FSMC_PATT2_ATTHOLD2 ((u32)0x00FF0000) /* ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ -#define FSMC_PATT2_ATTHOLD2_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_PATT2_ATTHOLD2_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_PATT2_ATTHOLD2_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_PATT2_ATTHOLD2_3 ((u32)0x00080000) /* Bit 3 */ -#define FSMC_PATT2_ATTHOLD2_4 ((u32)0x00100000) /* Bit 4 */ -#define FSMC_PATT2_ATTHOLD2_5 ((u32)0x00200000) /* Bit 5 */ -#define FSMC_PATT2_ATTHOLD2_6 ((u32)0x00400000) /* Bit 6 */ -#define FSMC_PATT2_ATTHOLD2_7 ((u32)0x00800000) /* Bit 7 */ - -#define FSMC_PATT2_ATTHIZ2 ((u32)0xFF000000) /* ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ -#define FSMC_PATT2_ATTHIZ2_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_PATT2_ATTHIZ2_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_PATT2_ATTHIZ2_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_PATT2_ATTHIZ2_3 ((u32)0x08000000) /* Bit 3 */ -#define FSMC_PATT2_ATTHIZ2_4 ((u32)0x10000000) /* Bit 4 */ -#define FSMC_PATT2_ATTHIZ2_5 ((u32)0x20000000) /* Bit 5 */ -#define FSMC_PATT2_ATTHIZ2_6 ((u32)0x40000000) /* Bit 6 */ -#define FSMC_PATT2_ATTHIZ2_7 ((u32)0x80000000) /* Bit 7 */ - - -/****************** Bit definition for FSMC_PATT3 register ******************/ -#define FSMC_PATT3_ATTSET3 ((u32)0x000000FF) /* ATTSET3[7:0] bits (Attribute memory 3 setup time) */ -#define FSMC_PATT3_ATTSET3_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_PATT3_ATTSET3_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_PATT3_ATTSET3_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_PATT3_ATTSET3_3 ((u32)0x00000008) /* Bit 3 */ -#define FSMC_PATT3_ATTSET3_4 ((u32)0x00000010) /* Bit 4 */ -#define FSMC_PATT3_ATTSET3_5 ((u32)0x00000020) /* Bit 5 */ -#define FSMC_PATT3_ATTSET3_6 ((u32)0x00000040) /* Bit 6 */ -#define FSMC_PATT3_ATTSET3_7 ((u32)0x00000080) /* Bit 7 */ - -#define FSMC_PATT3_ATTWAIT3 ((u32)0x0000FF00) /* ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ -#define FSMC_PATT3_ATTWAIT3_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_PATT3_ATTWAIT3_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_PATT3_ATTWAIT3_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_PATT3_ATTWAIT3_3 ((u32)0x00000800) /* Bit 3 */ -#define FSMC_PATT3_ATTWAIT3_4 ((u32)0x00001000) /* Bit 4 */ -#define FSMC_PATT3_ATTWAIT3_5 ((u32)0x00002000) /* Bit 5 */ -#define FSMC_PATT3_ATTWAIT3_6 ((u32)0x00004000) /* Bit 6 */ -#define FSMC_PATT3_ATTWAIT3_7 ((u32)0x00008000) /* Bit 7 */ - -#define FSMC_PATT3_ATTHOLD3 ((u32)0x00FF0000) /* ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ -#define FSMC_PATT3_ATTHOLD3_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_PATT3_ATTHOLD3_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_PATT3_ATTHOLD3_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_PATT3_ATTHOLD3_3 ((u32)0x00080000) /* Bit 3 */ -#define FSMC_PATT3_ATTHOLD3_4 ((u32)0x00100000) /* Bit 4 */ -#define FSMC_PATT3_ATTHOLD3_5 ((u32)0x00200000) /* Bit 5 */ -#define FSMC_PATT3_ATTHOLD3_6 ((u32)0x00400000) /* Bit 6 */ -#define FSMC_PATT3_ATTHOLD3_7 ((u32)0x00800000) /* Bit 7 */ - -#define FSMC_PATT3_ATTHIZ3 ((u32)0xFF000000) /* ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ -#define FSMC_PATT3_ATTHIZ3_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_PATT3_ATTHIZ3_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_PATT3_ATTHIZ3_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_PATT3_ATTHIZ3_3 ((u32)0x08000000) /* Bit 3 */ -#define FSMC_PATT3_ATTHIZ3_4 ((u32)0x10000000) /* Bit 4 */ -#define FSMC_PATT3_ATTHIZ3_5 ((u32)0x20000000) /* Bit 5 */ -#define FSMC_PATT3_ATTHIZ3_6 ((u32)0x40000000) /* Bit 6 */ -#define FSMC_PATT3_ATTHIZ3_7 ((u32)0x80000000) /* Bit 7 */ - - -/****************** Bit definition for FSMC_PATT4 register ******************/ -#define FSMC_PATT4_ATTSET4 ((u32)0x000000FF) /* ATTSET4[7:0] bits (Attribute memory 4 setup time) */ -#define FSMC_PATT4_ATTSET4_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_PATT4_ATTSET4_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_PATT4_ATTSET4_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_PATT4_ATTSET4_3 ((u32)0x00000008) /* Bit 3 */ -#define FSMC_PATT4_ATTSET4_4 ((u32)0x00000010) /* Bit 4 */ -#define FSMC_PATT4_ATTSET4_5 ((u32)0x00000020) /* Bit 5 */ -#define FSMC_PATT4_ATTSET4_6 ((u32)0x00000040) /* Bit 6 */ -#define FSMC_PATT4_ATTSET4_7 ((u32)0x00000080) /* Bit 7 */ - -#define FSMC_PATT4_ATTWAIT4 ((u32)0x0000FF00) /* ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ -#define FSMC_PATT4_ATTWAIT4_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_PATT4_ATTWAIT4_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_PATT4_ATTWAIT4_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_PATT4_ATTWAIT4_3 ((u32)0x00000800) /* Bit 3 */ -#define FSMC_PATT4_ATTWAIT4_4 ((u32)0x00001000) /* Bit 4 */ -#define FSMC_PATT4_ATTWAIT4_5 ((u32)0x00002000) /* Bit 5 */ -#define FSMC_PATT4_ATTWAIT4_6 ((u32)0x00004000) /* Bit 6 */ -#define FSMC_PATT4_ATTWAIT4_7 ((u32)0x00008000) /* Bit 7 */ - -#define FSMC_PATT4_ATTHOLD4 ((u32)0x00FF0000) /* ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ -#define FSMC_PATT4_ATTHOLD4_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_PATT4_ATTHOLD4_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_PATT4_ATTHOLD4_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_PATT4_ATTHOLD4_3 ((u32)0x00080000) /* Bit 3 */ -#define FSMC_PATT4_ATTHOLD4_4 ((u32)0x00100000) /* Bit 4 */ -#define FSMC_PATT4_ATTHOLD4_5 ((u32)0x00200000) /* Bit 5 */ -#define FSMC_PATT4_ATTHOLD4_6 ((u32)0x00400000) /* Bit 6 */ -#define FSMC_PATT4_ATTHOLD4_7 ((u32)0x00800000) /* Bit 7 */ - -#define FSMC_PATT4_ATTHIZ4 ((u32)0xFF000000) /* ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ -#define FSMC_PATT4_ATTHIZ4_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_PATT4_ATTHIZ4_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_PATT4_ATTHIZ4_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_PATT4_ATTHIZ4_3 ((u32)0x08000000) /* Bit 3 */ -#define FSMC_PATT4_ATTHIZ4_4 ((u32)0x10000000) /* Bit 4 */ -#define FSMC_PATT4_ATTHIZ4_5 ((u32)0x20000000) /* Bit 5 */ -#define FSMC_PATT4_ATTHIZ4_6 ((u32)0x40000000) /* Bit 6 */ -#define FSMC_PATT4_ATTHIZ4_7 ((u32)0x80000000) /* Bit 7 */ - - -/****************** Bit definition for FSMC_PIO4 register *******************/ -#define FSMC_PIO4_IOSET4 ((u32)0x000000FF) /* IOSET4[7:0] bits (I/O 4 setup time) */ -#define FSMC_PIO4_IOSET4_0 ((u32)0x00000001) /* Bit 0 */ -#define FSMC_PIO4_IOSET4_1 ((u32)0x00000002) /* Bit 1 */ -#define FSMC_PIO4_IOSET4_2 ((u32)0x00000004) /* Bit 2 */ -#define FSMC_PIO4_IOSET4_3 ((u32)0x00000008) /* Bit 3 */ -#define FSMC_PIO4_IOSET4_4 ((u32)0x00000010) /* Bit 4 */ -#define FSMC_PIO4_IOSET4_5 ((u32)0x00000020) /* Bit 5 */ -#define FSMC_PIO4_IOSET4_6 ((u32)0x00000040) /* Bit 6 */ -#define FSMC_PIO4_IOSET4_7 ((u32)0x00000080) /* Bit 7 */ - -#define FSMC_PIO4_IOWAIT4 ((u32)0x0000FF00) /* IOWAIT4[7:0] bits (I/O 4 wait time) */ -#define FSMC_PIO4_IOWAIT4_0 ((u32)0x00000100) /* Bit 0 */ -#define FSMC_PIO4_IOWAIT4_1 ((u32)0x00000200) /* Bit 1 */ -#define FSMC_PIO4_IOWAIT4_2 ((u32)0x00000400) /* Bit 2 */ -#define FSMC_PIO4_IOWAIT4_3 ((u32)0x00000800) /* Bit 3 */ -#define FSMC_PIO4_IOWAIT4_4 ((u32)0x00001000) /* Bit 4 */ -#define FSMC_PIO4_IOWAIT4_5 ((u32)0x00002000) /* Bit 5 */ -#define FSMC_PIO4_IOWAIT4_6 ((u32)0x00004000) /* Bit 6 */ -#define FSMC_PIO4_IOWAIT4_7 ((u32)0x00008000) /* Bit 7 */ - -#define FSMC_PIO4_IOHOLD4 ((u32)0x00FF0000) /* IOHOLD4[7:0] bits (I/O 4 hold time) */ -#define FSMC_PIO4_IOHOLD4_0 ((u32)0x00010000) /* Bit 0 */ -#define FSMC_PIO4_IOHOLD4_1 ((u32)0x00020000) /* Bit 1 */ -#define FSMC_PIO4_IOHOLD4_2 ((u32)0x00040000) /* Bit 2 */ -#define FSMC_PIO4_IOHOLD4_3 ((u32)0x00080000) /* Bit 3 */ -#define FSMC_PIO4_IOHOLD4_4 ((u32)0x00100000) /* Bit 4 */ -#define FSMC_PIO4_IOHOLD4_5 ((u32)0x00200000) /* Bit 5 */ -#define FSMC_PIO4_IOHOLD4_6 ((u32)0x00400000) /* Bit 6 */ -#define FSMC_PIO4_IOHOLD4_7 ((u32)0x00800000) /* Bit 7 */ - -#define FSMC_PIO4_IOHIZ4 ((u32)0xFF000000) /* IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ -#define FSMC_PIO4_IOHIZ4_0 ((u32)0x01000000) /* Bit 0 */ -#define FSMC_PIO4_IOHIZ4_1 ((u32)0x02000000) /* Bit 1 */ -#define FSMC_PIO4_IOHIZ4_2 ((u32)0x04000000) /* Bit 2 */ -#define FSMC_PIO4_IOHIZ4_3 ((u32)0x08000000) /* Bit 3 */ -#define FSMC_PIO4_IOHIZ4_4 ((u32)0x10000000) /* Bit 4 */ -#define FSMC_PIO4_IOHIZ4_5 ((u32)0x20000000) /* Bit 5 */ -#define FSMC_PIO4_IOHIZ4_6 ((u32)0x40000000) /* Bit 6 */ -#define FSMC_PIO4_IOHIZ4_7 ((u32)0x80000000) /* Bit 7 */ - - -/****************** Bit definition for FSMC_ECCR2 register ******************/ -#define FSMC_ECCR2_ECC2 ((u32)0xFFFFFFFF) /* ECC result */ - -/****************** Bit definition for FSMC_ECCR3 register ******************/ -#define FSMC_ECCR3_ECC3 ((u32)0xFFFFFFFF) /* ECC result */ - - - -/******************************************************************************/ -/* */ -/* SD host Interface */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for SDIO_POWER register ******************/ -#define SDIO_POWER_PWRCTRL ((u8)0x03) /* PWRCTRL[1:0] bits (Power supply control bits) */ -#define SDIO_POWER_PWRCTRL_0 ((u8)0x01) /* Bit 0 */ -#define SDIO_POWER_PWRCTRL_1 ((u8)0x02) /* Bit 1 */ - - -/****************** Bit definition for SDIO_CLKCR register ******************/ -#define SDIO_CLKCR_CLKDIV ((u16)0x00FF) /* Clock divide factor */ -#define SDIO_CLKCR_CLKEN ((u16)0x0100) /* Clock enable bit */ -#define SDIO_CLKCR_PWRSAV ((u16)0x0200) /* Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS ((u16)0x0400) /* Clock divider bypass enable bit */ - -#define SDIO_CLKCR_WIDBUS ((u16)0x1800) /* WIDBUS[1:0] bits (Wide bus mode enable bit) */ -#define SDIO_CLKCR_WIDBUS_0 ((u16)0x0800) /* Bit 0 */ -#define SDIO_CLKCR_WIDBUS_1 ((u16)0x1000) /* Bit 1 */ - -#define SDIO_CLKCR_NEGEDGE ((u16)0x2000) /* SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN ((u16)0x4000) /* HW Flow Control enable */ - - -/******************* Bit definition for SDIO_ARG register *******************/ -#define SDIO_ARG_CMDARG ((u32)0xFFFFFFFF) /* Command argument */ - - -/******************* Bit definition for SDIO_CMD register *******************/ -#define SDIO_CMD_CMDINDEX ((u16)0x003F) /* Command Index */ - -#define SDIO_CMD_WAITRESP ((u16)0x00C0) /* WAITRESP[1:0] bits (Wait for response bits) */ -#define SDIO_CMD_WAITRESP_0 ((u16)0x0040) /* Bit 0 */ -#define SDIO_CMD_WAITRESP_1 ((u16)0x0080) /* Bit 1 */ - -#define SDIO_CMD_WAITINT ((u16)0x0100) /* CPSM Waits for Interrupt Request */ -#define SDIO_CMD_WAITPEND ((u16)0x0200) /* CPSM Waits for ends of data transfer (CmdPend internal signal) */ -#define SDIO_CMD_CPSMEN ((u16)0x0400) /* Command path state machine (CPSM) Enable bit */ -#define SDIO_CMD_SDIOSUSPEND ((u16)0x0800) /* SD I/O suspend command */ -#define SDIO_CMD_ENCMDCOMPL ((u16)0x1000) /* Enable CMD completion */ -#define SDIO_CMD_NIEN ((u16)0x2000) /* Not Interrupt Enable */ -#define SDIO_CMD_CEATACMD ((u16)0x4000) /* CE-ATA command */ - - -/***************** Bit definition for SDIO_RESPCMD register *****************/ -#define SDIO_RESPCMD_RESPCMD ((u8)0x3F) /* Response command index */ - - -/****************** Bit definition for SDIO_RESP0 register ******************/ -#define SDIO_RESP0_CARDSTATUS0 ((u32)0xFFFFFFFF) /* Card Status */ - - -/****************** Bit definition for SDIO_RESP1 register ******************/ -#define SDIO_RESP1_CARDSTATUS1 ((u32)0xFFFFFFFF) /* Card Status */ - - -/****************** Bit definition for SDIO_RESP2 register ******************/ -#define SDIO_RESP2_CARDSTATUS2 ((u32)0xFFFFFFFF) /* Card Status */ - - -/****************** Bit definition for SDIO_RESP3 register ******************/ -#define SDIO_RESP3_CARDSTATUS3 ((u32)0xFFFFFFFF) /* Card Status */ - - -/****************** Bit definition for SDIO_RESP4 register ******************/ -#define SDIO_RESP4_CARDSTATUS4 ((u32)0xFFFFFFFF) /* Card Status */ - - -/****************** Bit definition for SDIO_DTIMER register *****************/ -#define SDIO_DTIMER_DATATIME ((u32)0xFFFFFFFF) /* Data timeout period. */ - - -/****************** Bit definition for SDIO_DLEN register *******************/ -#define SDIO_DLEN_DATALENGTH ((u32)0x01FFFFFF) /* Data length value */ - - -/****************** Bit definition for SDIO_DCTRL register ******************/ -#define SDIO_DCTRL_DTEN ((u16)0x0001) /* Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR ((u16)0x0002) /* Data transfer direction selection */ -#define SDIO_DCTRL_DTMODE ((u16)0x0004) /* Data transfer mode selection */ -#define SDIO_DCTRL_DMAEN ((u16)0x0008) /* DMA enabled bit */ - -#define SDIO_DCTRL_DBLOCKSIZE ((u16)0x00F0) /* DBLOCKSIZE[3:0] bits (Data block size) */ -#define SDIO_DCTRL_DBLOCKSIZE_0 ((u16)0x0010) /* Bit 0 */ -#define SDIO_DCTRL_DBLOCKSIZE_1 ((u16)0x0020) /* Bit 1 */ -#define SDIO_DCTRL_DBLOCKSIZE_2 ((u16)0x0040) /* Bit 2 */ -#define SDIO_DCTRL_DBLOCKSIZE_3 ((u16)0x0080) /* Bit 3 */ - -#define SDIO_DCTRL_RWSTART ((u16)0x0100) /* Read wait start */ -#define SDIO_DCTRL_RWSTOP ((u16)0x0200) /* Read wait stop */ -#define SDIO_DCTRL_RWMOD ((u16)0x0400) /* Read wait mode */ -#define SDIO_DCTRL_SDIOEN ((u16)0x0800) /* SD I/O enable functions */ - - -/****************** Bit definition for SDIO_DCOUNT register *****************/ -#define SDIO_DCOUNT_DATACOUNT ((u32)0x01FFFFFF) /* Data count value */ - - -/****************** Bit definition for SDIO_STA register ********************/ -#define SDIO_STA_CCRCFAIL ((u32)0x00000001) /* Command response received (CRC check failed) */ -#define SDIO_STA_DCRCFAIL ((u32)0x00000002) /* Data block sent/received (CRC check failed) */ -#define SDIO_STA_CTIMEOUT ((u32)0x00000004) /* Command response timeout */ -#define SDIO_STA_DTIMEOUT ((u32)0x00000008) /* Data timeout */ -#define SDIO_STA_TXUNDERR ((u32)0x00000010) /* Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR ((u32)0x00000020) /* Received FIFO overrun error */ -#define SDIO_STA_CMDREND ((u32)0x00000040) /* Command response received (CRC check passed) */ -#define SDIO_STA_CMDSENT ((u32)0x00000080) /* Command sent (no response required) */ -#define SDIO_STA_DATAEND ((u32)0x00000100) /* Data end (data counter, SDIDCOUNT, is zero) */ -#define SDIO_STA_STBITERR ((u32)0x00000200) /* Start bit not detected on all data signals in wide bus mode */ -#define SDIO_STA_DBCKEND ((u32)0x00000400) /* Data block sent/received (CRC check passed) */ -#define SDIO_STA_CMDACT ((u32)0x00000800) /* Command transfer in progress */ -#define SDIO_STA_TXACT ((u32)0x00001000) /* Data transmit in progress */ -#define SDIO_STA_RXACT ((u32)0x00002000) /* Data receive in progress */ -#define SDIO_STA_TXFIFOHE ((u32)0x00004000) /* Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ -#define SDIO_STA_RXFIFOHF ((u32)0x00008000) /* Receive FIFO Half Full: there are at least 8 words in the FIFO */ -#define SDIO_STA_TXFIFOF ((u32)0x00010000) /* Transmit FIFO full */ -#define SDIO_STA_RXFIFOF ((u32)0x00020000) /* Receive FIFO full */ -#define SDIO_STA_TXFIFOE ((u32)0x00040000) /* Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE ((u32)0x00080000) /* Receive FIFO empty */ -#define SDIO_STA_TXDAVL ((u32)0x00100000) /* Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL ((u32)0x00200000) /* Data available in receive FIFO */ -#define SDIO_STA_SDIOIT ((u32)0x00400000) /* SDIO interrupt received */ -#define SDIO_STA_CEATAEND ((u32)0x00800000) /* CE-ATA command completion signal received for CMD61 */ - - -/******************* Bit definition for SDIO_ICR register *******************/ -#define SDIO_ICR_CCRCFAILC ((u32)0x00000001) /* CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC ((u32)0x00000002) /* DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC ((u32)0x00000004) /* CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC ((u32)0x00000008) /* DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC ((u32)0x00000010) /* TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC ((u32)0x00000020) /* RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC ((u32)0x00000040) /* CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC ((u32)0x00000080) /* CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC ((u32)0x00000100) /* DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC ((u32)0x00000200) /* STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC ((u32)0x00000400) /* DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC ((u32)0x00400000) /* SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC ((u32)0x00800000) /* CEATAEND flag clear bit */ - - -/****************** Bit definition for SDIO_MASK register *******************/ -#define SDIO_MASK_CCRCFAILIE ((u32)0x00000001) /* Command CRC Fail Interrupt Enable */ -#define SDIO_MASK_DCRCFAILIE ((u32)0x00000002) /* Data CRC Fail Interrupt Enable */ -#define SDIO_MASK_CTIMEOUTIE ((u32)0x00000004) /* Command TimeOut Interrupt Enable */ -#define SDIO_MASK_DTIMEOUTIE ((u32)0x00000008) /* Data TimeOut Interrupt Enable */ -#define SDIO_MASK_TXUNDERRIE ((u32)0x00000010) /* Tx FIFO UnderRun Error Interrupt Enable */ -#define SDIO_MASK_RXOVERRIE ((u32)0x00000020) /* Rx FIFO OverRun Error Interrupt Enable */ -#define SDIO_MASK_CMDRENDIE ((u32)0x00000040) /* Command Response Received Interrupt Enable */ -#define SDIO_MASK_CMDSENTIE ((u32)0x00000080) /* Command Sent Interrupt Enable */ -#define SDIO_MASK_DATAENDIE ((u32)0x00000100) /* Data End Interrupt Enable */ -#define SDIO_MASK_STBITERRIE ((u32)0x00000200) /* Start Bit Error Interrupt Enable */ -#define SDIO_MASK_DBCKENDIE ((u32)0x00000400) /* Data Block End Interrupt Enable */ -#define SDIO_MASK_CMDACTIE ((u32)0x00000800) /* CCommand Acting Interrupt Enable */ -#define SDIO_MASK_TXACTIE ((u32)0x00001000) /* Data Transmit Acting Interrupt Enable */ -#define SDIO_MASK_RXACTIE ((u32)0x00002000) /* Data receive acting interrupt enabled */ -#define SDIO_MASK_TXFIFOHEIE ((u32)0x00004000) /* Tx FIFO Half Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOHFIE ((u32)0x00008000) /* Rx FIFO Half Full interrupt Enable */ -#define SDIO_MASK_TXFIFOFIE ((u32)0x00010000) /* Tx FIFO Full interrupt Enable */ -#define SDIO_MASK_RXFIFOFIE ((u32)0x00020000) /* Rx FIFO Full interrupt Enable */ -#define SDIO_MASK_TXFIFOEIE ((u32)0x00040000) /* Tx FIFO Empty interrupt Enable */ -#define SDIO_MASK_RXFIFOEIE ((u32)0x00080000) /* Rx FIFO Empty interrupt Enable */ -#define SDIO_MASK_TXDAVLIE ((u32)0x00100000) /* Data available in Tx FIFO interrupt Enable */ -#define SDIO_MASK_RXDAVLIE ((u32)0x00200000) /* Data available in Rx FIFO interrupt Enable */ -#define SDIO_MASK_SDIOITIE ((u32)0x00400000) /* SDIO Mode Interrupt Received interrupt Enable */ -#define SDIO_MASK_CEATAENDIE ((u32)0x00800000) /* CE-ATA command completion signal received Interrupt Enable */ - - -/***************** Bit definition for SDIO_FIFOCNT register *****************/ -#define SDIO_FIFOCNT_FIFOCOUNT ((u32)0x00FFFFFF) /* Remaining number of words to be written to or read from the FIFO */ - - -/****************** Bit definition for SDIO_FIFO register *******************/ -#define SDIO_FIFO_FIFODATA ((u32)0xFFFFFFFF) /* Receive and transmit FIFO data */ - - - -/******************************************************************************/ -/* */ -/* USB */ -/* */ -/******************************************************************************/ - -/* Endpoint-specific registers */ -/******************* Bit definition for USB_EP0R register *******************/ -#define USB_EP0R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP0R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP0R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP0R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP0R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP0R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP0R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP0R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP0R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP0R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP0R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP0R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP0R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP0R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP0R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP0R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/******************* Bit definition for USB_EP1R register *******************/ -#define USB_EP1R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP1R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP1R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP1R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP1R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP1R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP1R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP1R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP1R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP1R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP1R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP1R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP1R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP1R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP1R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP1R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/******************* Bit definition for USB_EP2R register *******************/ -#define USB_EP2R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP2R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP2R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP2R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP2R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP2R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP2R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP2R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP2R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP2R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP2R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP2R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP2R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP2R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP2R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP2R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/******************* Bit definition for USB_EP3R register *******************/ -#define USB_EP3R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP3R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP3R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP3R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP3R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP3R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP3R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP3R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP3R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP3R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP3R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP3R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP3R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP3R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP3R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP3R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/******************* Bit definition for USB_EP4R register *******************/ -#define USB_EP4R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP4R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP4R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP4R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP4R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP4R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP4R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP4R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP4R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP4R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP4R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP4R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP4R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP4R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP4R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP4R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/******************* Bit definition for USB_EP5R register *******************/ -#define USB_EP5R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP5R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP5R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP5R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP5R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP5R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP5R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP5R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP5R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP5R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP5R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP5R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP5R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP5R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP5R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP5R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/******************* Bit definition for USB_EP6R register *******************/ -#define USB_EP6R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP6R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP6R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP6R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP6R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP6R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP6R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP6R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP6R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP6R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP6R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP6R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP6R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP6R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP6R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP6R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/******************* Bit definition for USB_EP7R register *******************/ -#define USB_EP7R_EA ((u16)0x000F) /* Endpoint Address */ - -#define USB_EP7R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */ -#define USB_EP7R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */ -#define USB_EP7R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */ - -#define USB_EP7R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */ -#define USB_EP7R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */ -#define USB_EP7R_EP_KIND ((u16)0x0100) /* Endpoint Kind */ - -#define USB_EP7R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */ -#define USB_EP7R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */ -#define USB_EP7R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */ - -#define USB_EP7R_SETUP ((u16)0x0800) /* Setup transaction completed */ - -#define USB_EP7R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */ -#define USB_EP7R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */ -#define USB_EP7R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */ - -#define USB_EP7R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */ -#define USB_EP7R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */ - - -/* Common registers */ -/******************* Bit definition for USB_CNTR register *******************/ -#define USB_CNTR_FRES ((u16)0x0001) /* Force USB Reset */ -#define USB_CNTR_PDWN ((u16)0x0002) /* Power down */ -#define USB_CNTR_LP_MODE ((u16)0x0004) /* Low-power mode */ -#define USB_CNTR_FSUSP ((u16)0x0008) /* Force suspend */ -#define USB_CNTR_RESUME ((u16)0x0010) /* Resume request */ -#define USB_CNTR_ESOFM ((u16)0x0100) /* Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM ((u16)0x0200) /* Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM ((u16)0x0400) /* RESET Interrupt Mask */ -#define USB_CNTR_SUSPM ((u16)0x0800) /* Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM ((u16)0x1000) /* Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM ((u16)0x2000) /* Error Interrupt Mask */ -#define USB_CNTR_PMAOVRM ((u16)0x4000) /* Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM ((u16)0x8000) /* Correct Transfer Interrupt Mask */ - - -/******************* Bit definition for USB_ISTR register *******************/ -#define USB_ISTR_EP_ID ((u16)0x000F) /* Endpoint Identifier */ -#define USB_ISTR_DIR ((u16)0x0010) /* Direction of transaction */ -#define USB_ISTR_ESOF ((u16)0x0100) /* Expected Start Of Frame */ -#define USB_ISTR_SOF ((u16)0x0200) /* Start Of Frame */ -#define USB_ISTR_RESET ((u16)0x0400) /* USB RESET request */ -#define USB_ISTR_SUSP ((u16)0x0800) /* Suspend mode request */ -#define USB_ISTR_WKUP ((u16)0x1000) /* Wake up */ -#define USB_ISTR_ERR ((u16)0x2000) /* Error */ -#define USB_ISTR_PMAOVR ((u16)0x4000) /* Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR ((u16)0x8000) /* Correct Transfer */ - - -/******************* Bit definition for USB_FNR register ********************/ -#define USB_FNR_FN ((u16)0x07FF) /* Frame Number */ -#define USB_FNR_LSOF ((u16)0x1800) /* Lost SOF */ -#define USB_FNR_LCK ((u16)0x2000) /* Locked */ -#define USB_FNR_RXDM ((u16)0x4000) /* Receive Data - Line Status */ -#define USB_FNR_RXDP ((u16)0x8000) /* Receive Data + Line Status */ - - -/****************** Bit definition for USB_DADDR register *******************/ -#define USB_DADDR_ADD ((u8)0x7F) /* ADD[6:0] bits (Device Address) */ -#define USB_DADDR_ADD0 ((u8)0x01) /* Bit 0 */ -#define USB_DADDR_ADD1 ((u8)0x02) /* Bit 1 */ -#define USB_DADDR_ADD2 ((u8)0x04) /* Bit 2 */ -#define USB_DADDR_ADD3 ((u8)0x08) /* Bit 3 */ -#define USB_DADDR_ADD4 ((u8)0x10) /* Bit 4 */ -#define USB_DADDR_ADD5 ((u8)0x20) /* Bit 5 */ -#define USB_DADDR_ADD6 ((u8)0x40) /* Bit 6 */ - -#define USB_DADDR_EF ((u8)0x80) /* Enable Function */ - - -/****************** Bit definition for USB_BTABLE register ******************/ -#define USB_BTABLE_BTABLE ((u16)0xFFF8) /* Buffer Table */ - - -/* Buffer descriptor table */ -/***************** Bit definition for USB_ADDR0_TX register *****************/ -#define USB_ADDR0_TX_ADDR0_TX ((u16)0xFFFE) /* Transmission Buffer Address 0 */ - - -/***************** Bit definition for USB_ADDR1_TX register *****************/ -#define USB_ADDR1_TX_ADDR1_TX ((u16)0xFFFE) /* Transmission Buffer Address 1 */ - - -/***************** Bit definition for USB_ADDR2_TX register *****************/ -#define USB_ADDR2_TX_ADDR2_TX ((u16)0xFFFE) /* Transmission Buffer Address 2 */ - - -/***************** Bit definition for USB_ADDR3_TX register *****************/ -#define USB_ADDR3_TX_ADDR3_TX ((u16)0xFFFE) /* Transmission Buffer Address 3 */ - - -/***************** Bit definition for USB_ADDR4_TX register *****************/ -#define USB_ADDR4_TX_ADDR4_TX ((u16)0xFFFE) /* Transmission Buffer Address 4 */ - - -/***************** Bit definition for USB_ADDR5_TX register *****************/ -#define USB_ADDR5_TX_ADDR5_TX ((u16)0xFFFE) /* Transmission Buffer Address 5 */ - - -/***************** Bit definition for USB_ADDR6_TX register *****************/ -#define USB_ADDR6_TX_ADDR6_TX ((u16)0xFFFE) /* Transmission Buffer Address 6 */ - - -/***************** Bit definition for USB_ADDR7_TX register *****************/ -#define USB_ADDR7_TX_ADDR7_TX ((u16)0xFFFE) /* Transmission Buffer Address 7 */ - - -/*----------------------------------------------------------------------------*/ - - -/***************** Bit definition for USB_COUNT0_TX register ****************/ -#define USB_COUNT0_TX_COUNT0_TX ((u16)0x03FF) /* Transmission Byte Count 0 */ - - -/***************** Bit definition for USB_COUNT1_TX register ****************/ -#define USB_COUNT1_TX_COUNT1_TX ((u16)0x03FF) /* Transmission Byte Count 1 */ - - -/***************** Bit definition for USB_COUNT2_TX register ****************/ -#define USB_COUNT2_TX_COUNT2_TX ((u16)0x03FF) /* Transmission Byte Count 2 */ - - -/***************** Bit definition for USB_COUNT3_TX register ****************/ -#define USB_COUNT3_TX_COUNT3_TX ((u16)0x03FF) /* Transmission Byte Count 3 */ - - -/***************** Bit definition for USB_COUNT4_TX register ****************/ -#define USB_COUNT4_TX_COUNT4_TX ((u16)0x03FF) /* Transmission Byte Count 4 */ - -/***************** Bit definition for USB_COUNT5_TX register ****************/ -#define USB_COUNT5_TX_COUNT5_TX ((u16)0x03FF) /* Transmission Byte Count 5 */ - - -/***************** Bit definition for USB_COUNT6_TX register ****************/ -#define USB_COUNT6_TX_COUNT6_TX ((u16)0x03FF) /* Transmission Byte Count 6 */ - - -/***************** Bit definition for USB_COUNT7_TX register ****************/ -#define USB_COUNT7_TX_COUNT7_TX ((u16)0x03FF) /* Transmission Byte Count 7 */ - - -/*----------------------------------------------------------------------------*/ - - -/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ -#define USB_COUNT0_TX_0_COUNT0_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 0 (low) */ - -/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ -#define USB_COUNT0_TX_1_COUNT0_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 0 (high) */ - - - -/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ -#define USB_COUNT1_TX_0_COUNT1_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 1 (low) */ - -/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ -#define USB_COUNT1_TX_1_COUNT1_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 1 (high) */ - - - -/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ -#define USB_COUNT2_TX_0_COUNT2_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 2 (low) */ - -/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ -#define USB_COUNT2_TX_1_COUNT2_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 2 (high) */ - - - -/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ -#define USB_COUNT3_TX_0_COUNT3_TX_0 ((u16)0x000003FF) /* Transmission Byte Count 3 (low) */ - -/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ -#define USB_COUNT3_TX_1_COUNT3_TX_1 ((u16)0x03FF0000) /* Transmission Byte Count 3 (high) */ - - - -/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ -#define USB_COUNT4_TX_0_COUNT4_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 4 (low) */ - -/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ -#define USB_COUNT4_TX_1_COUNT4_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 4 (high) */ - - - -/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ -#define USB_COUNT5_TX_0_COUNT5_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 5 (low) */ - -/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ -#define USB_COUNT5_TX_1_COUNT5_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 5 (high) */ - - - -/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ -#define USB_COUNT6_TX_0_COUNT6_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 6 (low) */ - -/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ -#define USB_COUNT6_TX_1_COUNT6_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 6 (high) */ - - - -/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ -#define USB_COUNT7_TX_0_COUNT7_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 7 (low) */ - -/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ -#define USB_COUNT7_TX_1_COUNT7_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 7 (high) */ - - -/*----------------------------------------------------------------------------*/ - - -/***************** Bit definition for USB_ADDR0_RX register *****************/ -#define USB_ADDR0_RX_ADDR0_RX ((u16)0xFFFE) /* Reception Buffer Address 0 */ - - -/***************** Bit definition for USB_ADDR1_RX register *****************/ -#define USB_ADDR1_RX_ADDR1_RX ((u16)0xFFFE) /* Reception Buffer Address 1 */ - - -/***************** Bit definition for USB_ADDR2_RX register *****************/ -#define USB_ADDR2_RX_ADDR2_RX ((u16)0xFFFE) /* Reception Buffer Address 2 */ - - -/***************** Bit definition for USB_ADDR3_RX register *****************/ -#define USB_ADDR3_RX_ADDR3_RX ((u16)0xFFFE) /* Reception Buffer Address 3 */ - - -/***************** Bit definition for USB_ADDR4_RX register *****************/ -#define USB_ADDR4_RX_ADDR4_RX ((u16)0xFFFE) /* Reception Buffer Address 4 */ - - -/***************** Bit definition for USB_ADDR5_RX register *****************/ -#define USB_ADDR5_RX_ADDR5_RX ((u16)0xFFFE) /* Reception Buffer Address 5 */ - - -/***************** Bit definition for USB_ADDR6_RX register *****************/ -#define USB_ADDR6_RX_ADDR6_RX ((u16)0xFFFE) /* Reception Buffer Address 6 */ - - -/***************** Bit definition for USB_ADDR7_RX register *****************/ -#define USB_ADDR7_RX_ADDR7_RX ((u16)0xFFFE) /* Reception Buffer Address 7 */ - - -/*----------------------------------------------------------------------------*/ - - -/***************** Bit definition for USB_COUNT0_RX register ****************/ -#define USB_COUNT0_RX_COUNT0_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT0_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT0_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT0_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT0_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT0_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT0_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT0_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - - -/***************** Bit definition for USB_COUNT1_RX register ****************/ -#define USB_COUNT1_RX_COUNT1_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT1_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT1_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT1_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT1_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT1_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT1_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT1_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - - -/***************** Bit definition for USB_COUNT2_RX register ****************/ -#define USB_COUNT2_RX_COUNT2_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT2_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT2_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT2_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT2_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT2_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT2_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT2_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - - -/***************** Bit definition for USB_COUNT3_RX register ****************/ -#define USB_COUNT3_RX_COUNT3_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT3_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT3_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT3_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT3_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT3_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT3_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT3_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - - -/***************** Bit definition for USB_COUNT4_RX register ****************/ -#define USB_COUNT4_RX_COUNT4_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT4_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT4_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT4_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT4_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT4_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT4_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT4_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - - -/***************** Bit definition for USB_COUNT5_RX register ****************/ -#define USB_COUNT5_RX_COUNT5_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT5_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT5_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT5_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT5_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT5_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT5_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT5_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - -/***************** Bit definition for USB_COUNT6_RX register ****************/ -#define USB_COUNT6_RX_COUNT6_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT6_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT6_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT6_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT6_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT6_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT6_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT6_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - - -/***************** Bit definition for USB_COUNT7_RX register ****************/ -#define USB_COUNT7_RX_COUNT7_RX ((u16)0x03FF) /* Reception Byte Count */ - -#define USB_COUNT7_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */ -#define USB_COUNT7_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */ -#define USB_COUNT7_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */ -#define USB_COUNT7_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */ -#define USB_COUNT7_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */ -#define USB_COUNT7_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */ - -#define USB_COUNT7_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */ - - -/*----------------------------------------------------------------------------*/ - - -/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ -#define USB_COUNT0_RX_0_COUNT0_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT0_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ -#define USB_COUNT0_RX_1_COUNT0_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT0_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ -#define USB_COUNT1_RX_0_COUNT1_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT1_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ -#define USB_COUNT1_RX_1_COUNT1_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT1_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ -#define USB_COUNT2_RX_0_COUNT2_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT2_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ -#define USB_COUNT2_RX_1_COUNT2_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT2_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ -#define USB_COUNT3_RX_0_COUNT3_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT3_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ -#define USB_COUNT3_RX_1_COUNT3_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT3_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ -#define USB_COUNT4_RX_0_COUNT4_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT4_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ -#define USB_COUNT4_RX_1_COUNT4_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT4_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ -#define USB_COUNT5_RX_0_COUNT5_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT5_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ -#define USB_COUNT5_RX_1_COUNT5_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT5_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ -#define USB_COUNT6_RX_0_COUNT6_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT6_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ -#define USB_COUNT6_RX_1_COUNT6_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT6_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ -#define USB_COUNT7_RX_0_COUNT7_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */ - -#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */ -#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */ - -#define USB_COUNT7_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */ - -/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ -#define USB_COUNT7_RX_1_COUNT7_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */ - -#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */ -#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */ - -#define USB_COUNT7_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */ - - - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ - -/* CAN control and status registers */ -/******************* Bit definition for CAN_MCR register ********************/ -#define CAN_MCR_INRQ ((u16)0x0001) /* Initialization Request */ -#define CAN_MCR_SLEEP ((u16)0x0002) /* Sleep Mode Request */ -#define CAN_MCR_TXFP ((u16)0x0004) /* Transmit FIFO Priority */ -#define CAN_MCR_RFLM ((u16)0x0008) /* Receive FIFO Locked Mode */ -#define CAN_MCR_NART ((u16)0x0010) /* No Automatic Retransmission */ -#define CAN_MCR_AWUM ((u16)0x0020) /* Automatic Wakeup Mode */ -#define CAN_MCR_ABOM ((u16)0x0040) /* Automatic Bus-Off Management */ -#define CAN_MCR_TTCM ((u16)0x0080) /* Time Triggered Communication Mode */ -#define CAN_MCR_RESET ((u16)0x8000) /* bxCAN software master reset */ - - -/******************* Bit definition for CAN_MSR register ********************/ -#define CAN_MSR_INAK ((u16)0x0001) /* Initialization Acknowledge */ -#define CAN_MSR_SLAK ((u16)0x0002) /* Sleep Acknowledge */ -#define CAN_MSR_ERRI ((u16)0x0004) /* Error Interrupt */ -#define CAN_MSR_WKUI ((u16)0x0008) /* Wakeup Interrupt */ -#define CAN_MSR_SLAKI ((u16)0x0010) /* Sleep Acknowledge Interrupt */ -#define CAN_MSR_TXM ((u16)0x0100) /* Transmit Mode */ -#define CAN_MSR_RXM ((u16)0x0200) /* Receive Mode */ -#define CAN_MSR_SAMP ((u16)0x0400) /* Last Sample Point */ -#define CAN_MSR_RX ((u16)0x0800) /* CAN Rx Signal */ - - -/******************* Bit definition for CAN_TSR register ********************/ -#define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request Completed Mailbox0 */ -#define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of Mailbox0 */ -#define CAN_TSR_ALST0 ((u32)0x00000004) /* Arbitration Lost for Mailbox0 */ -#define CAN_TSR_TERR0 ((u32)0x00000008) /* Transmission Error of Mailbox0 */ -#define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort Request for Mailbox0 */ -#define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request Completed Mailbox1 */ -#define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of Mailbox1 */ -#define CAN_TSR_ALST1 ((u32)0x00000400) /* Arbitration Lost for Mailbox1 */ -#define CAN_TSR_TERR1 ((u32)0x00000800) /* Transmission Error of Mailbox1 */ -#define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort Request for Mailbox 1 */ -#define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request Completed Mailbox2 */ -#define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of Mailbox 2 */ -#define CAN_TSR_ALST2 ((u32)0x00040000) /* Arbitration Lost for mailbox 2 */ -#define CAN_TSR_TERR2 ((u32)0x00080000) /* Transmission Error of Mailbox 2 */ -#define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort Request for Mailbox 2 */ -#define CAN_TSR_CODE ((u32)0x03000000) /* Mailbox Code */ - -#define CAN_TSR_TME ((u32)0x1C000000) /* TME[2:0] bits */ -#define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit Mailbox 0 Empty */ -#define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit Mailbox 1 Empty */ -#define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit Mailbox 2 Empty */ - -#define CAN_TSR_LOW ((u32)0xE0000000) /* LOW[2:0] bits */ -#define CAN_TSR_LOW0 ((u32)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ -#define CAN_TSR_LOW1 ((u32)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ -#define CAN_TSR_LOW2 ((u32)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ - - -/******************* Bit definition for CAN_RF0R register *******************/ -#define CAN_RF0R_FMP0 ((u8)0x03) /* FIFO 0 Message Pending */ -#define CAN_RF0R_FULL0 ((u8)0x08) /* FIFO 0 Full */ -#define CAN_RF0R_FOVR0 ((u8)0x10) /* FIFO 0 Overrun */ -#define CAN_RF0R_RFOM0 ((u8)0x20) /* Release FIFO 0 Output Mailbox */ - - -/******************* Bit definition for CAN_RF1R register *******************/ -#define CAN_RF1R_FMP1 ((u8)0x03) /* FIFO 1 Message Pending */ -#define CAN_RF1R_FULL1 ((u8)0x08) /* FIFO 1 Full */ -#define CAN_RF1R_FOVR1 ((u8)0x10) /* FIFO 1 Overrun */ -#define CAN_RF1R_RFOM1 ((u8)0x20) /* Release FIFO 1 Output Mailbox */ - - -/******************** Bit definition for CAN_IER register *******************/ -#define CAN_IER_TMEIE ((u32)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ -#define CAN_IER_FMPIE0 ((u32)0x00000002) /* FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE0 ((u32)0x00000004) /* FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE0 ((u32)0x00000008) /* FIFO Overrun Interrupt Enable */ -#define CAN_IER_FMPIE1 ((u32)0x00000010) /* FIFO Message Pending Interrupt Enable */ -#define CAN_IER_FFIE1 ((u32)0x00000020) /* FIFO Full Interrupt Enable */ -#define CAN_IER_FOVIE1 ((u32)0x00000040) /* FIFO Overrun Interrupt Enable */ -#define CAN_IER_EWGIE ((u32)0x00000100) /* Error Warning Interrupt Enable */ -#define CAN_IER_EPVIE ((u32)0x00000200) /* Error Passive Interrupt Enable */ -#define CAN_IER_BOFIE ((u32)0x00000400) /* Bus-Off Interrupt Enable */ -#define CAN_IER_LECIE ((u32)0x00000800) /* Last Error Code Interrupt Enable */ -#define CAN_IER_ERRIE ((u32)0x00008000) /* Error Interrupt Enable */ -#define CAN_IER_WKUIE ((u32)0x00010000) /* Wakeup Interrupt Enable */ -#define CAN_IER_SLKIE ((u32)0x00020000) /* Sleep Interrupt Enable */ - - -/******************** Bit definition for CAN_ESR register *******************/ -#define CAN_ESR_EWGF ((u32)0x00000001) /* Error Warning Flag */ -#define CAN_ESR_EPVF ((u32)0x00000002) /* Error Passive Flag */ -#define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-Off Flag */ - -#define CAN_ESR_LEC ((u32)0x00000070) /* LEC[2:0] bits (Last Error Code) */ -#define CAN_ESR_LEC_0 ((u32)0x00000010) /* Bit 0 */ -#define CAN_ESR_LEC_1 ((u32)0x00000020) /* Bit 1 */ -#define CAN_ESR_LEC_2 ((u32)0x00000040) /* Bit 2 */ - -#define CAN_ESR_TEC ((u32)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ -#define CAN_ESR_REC ((u32)0xFF000000) /* Receive Error Counter */ - - -/******************* Bit definition for CAN_BTR register ********************/ -#define CAN_BTR_BRP ((u32)0x000003FF) /* Baud Rate Prescaler */ -#define CAN_BTR_TS1 ((u32)0x000F0000) /* Time Segment 1 */ -#define CAN_BTR_TS2 ((u32)0x00700000) /* Time Segment 2 */ -#define CAN_BTR_SJW ((u32)0x03000000) /* Resynchronization Jump Width */ -#define CAN_BTR_LBKM ((u32)0x40000000) /* Loop Back Mode (Debug) */ -#define CAN_BTR_SILM ((u32)0x80000000) /* Silent Mode */ - - -/* Mailbox registers */ -/****************** Bit definition for CAN_TI0R register ********************/ -#define CAN_TI0R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ -#define CAN_TI0R_IDE ((u32)0x00000004) /* Identifier Extension */ -#define CAN_TI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ -#define CAN_TI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ - - -/****************** Bit definition for CAN_TDT0R register *******************/ -#define CAN_TDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ -#define CAN_TDT0R_TGT ((u32)0x00000100) /* Transmit Global Time */ -#define CAN_TDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ - - -/****************** Bit definition for CAN_TDL0R register *******************/ -#define CAN_TDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ -#define CAN_TDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ -#define CAN_TDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ -#define CAN_TDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ - - -/****************** Bit definition for CAN_TDH0R register *******************/ -#define CAN_TDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ -#define CAN_TDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ -#define CAN_TDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ -#define CAN_TDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ - - -/******************* Bit definition for CAN_TI1R register *******************/ -#define CAN_TI1R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ -#define CAN_TI1R_IDE ((u32)0x00000004) /* Identifier Extension */ -#define CAN_TI1R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ -#define CAN_TI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ - - -/******************* Bit definition for CAN_TDT1R register ******************/ -#define CAN_TDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ -#define CAN_TDT1R_TGT ((u32)0x00000100) /* Transmit Global Time */ -#define CAN_TDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ - - -/******************* Bit definition for CAN_TDL1R register ******************/ -#define CAN_TDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ -#define CAN_TDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ -#define CAN_TDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ -#define CAN_TDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ - - -/******************* Bit definition for CAN_TDH1R register ******************/ -#define CAN_TDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ -#define CAN_TDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ -#define CAN_TDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ -#define CAN_TDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ - - -/******************* Bit definition for CAN_TI2R register *******************/ -#define CAN_TI2R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */ -#define CAN_TI2R_RTR ((u32)0x00000002) /* Remote Transmission Request */ -#define CAN_TI2R_IDE ((u32)0x00000004) /* Identifier Extension */ -#define CAN_TI2R_EXID ((u32)0x001FFFF8) /* Extended identifier */ -#define CAN_TI2R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ - - -/******************* Bit definition for CAN_TDT2R register ******************/ -#define CAN_TDT2R_DLC ((u32)0x0000000F) /* Data Length Code */ -#define CAN_TDT2R_TGT ((u32)0x00000100) /* Transmit Global Time */ -#define CAN_TDT2R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ - - -/******************* Bit definition for CAN_TDL2R register ******************/ -#define CAN_TDL2R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ -#define CAN_TDL2R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ -#define CAN_TDL2R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ -#define CAN_TDL2R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ - - -/******************* Bit definition for CAN_TDH2R register ******************/ -#define CAN_TDH2R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ -#define CAN_TDH2R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ -#define CAN_TDH2R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ -#define CAN_TDH2R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ - - -/******************* Bit definition for CAN_RI0R register *******************/ -#define CAN_RI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */ -#define CAN_RI0R_IDE ((u32)0x00000004) /* Identifier Extension */ -#define CAN_RI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */ -#define CAN_RI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ - - -/******************* Bit definition for CAN_RDT0R register ******************/ -#define CAN_RDT0R_DLC ((u32)0x0000000F) /* Data Length Code */ -#define CAN_RDT0R_FMI ((u32)0x0000FF00) /* Filter Match Index */ -#define CAN_RDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ - - -/******************* Bit definition for CAN_RDL0R register ******************/ -#define CAN_RDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ -#define CAN_RDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ -#define CAN_RDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ -#define CAN_RDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ - - -/******************* Bit definition for CAN_RDH0R register ******************/ -#define CAN_RDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ -#define CAN_RDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ -#define CAN_RDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ -#define CAN_RDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ - - -/******************* Bit definition for CAN_RI1R register *******************/ -#define CAN_RI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */ -#define CAN_RI1R_IDE ((u32)0x00000004) /* Identifier Extension */ -#define CAN_RI1R_EXID ((u32)0x001FFFF8) /* Extended identifier */ -#define CAN_RI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */ - - -/******************* Bit definition for CAN_RDT1R register ******************/ -#define CAN_RDT1R_DLC ((u32)0x0000000F) /* Data Length Code */ -#define CAN_RDT1R_FMI ((u32)0x0000FF00) /* Filter Match Index */ -#define CAN_RDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */ - - -/******************* Bit definition for CAN_RDL1R register ******************/ -#define CAN_RDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */ -#define CAN_RDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */ -#define CAN_RDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */ -#define CAN_RDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */ - - -/******************* Bit definition for CAN_RDH1R register ******************/ -#define CAN_RDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */ -#define CAN_RDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */ -#define CAN_RDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */ -#define CAN_RDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */ - -/* CAN filter registers */ -/******************* Bit definition for CAN_FMR register ********************/ -#define CAN_FMR_FINIT ((u8)0x01) /* Filter Init Mode */ - - -/******************* Bit definition for CAN_FM1R register *******************/ -#define CAN_FM1R_FBM ((u16)0x3FFF) /* Filter Mode */ -#define CAN_FM1R_FBM0 ((u16)0x0001) /* Filter Init Mode bit 0 */ -#define CAN_FM1R_FBM1 ((u16)0x0002) /* Filter Init Mode bit 1 */ -#define CAN_FM1R_FBM2 ((u16)0x0004) /* Filter Init Mode bit 2 */ -#define CAN_FM1R_FBM3 ((u16)0x0008) /* Filter Init Mode bit 3 */ -#define CAN_FM1R_FBM4 ((u16)0x0010) /* Filter Init Mode bit 4 */ -#define CAN_FM1R_FBM5 ((u16)0x0020) /* Filter Init Mode bit 5 */ -#define CAN_FM1R_FBM6 ((u16)0x0040) /* Filter Init Mode bit 6 */ -#define CAN_FM1R_FBM7 ((u16)0x0080) /* Filter Init Mode bit 7 */ -#define CAN_FM1R_FBM8 ((u16)0x0100) /* Filter Init Mode bit 8 */ -#define CAN_FM1R_FBM9 ((u16)0x0200) /* Filter Init Mode bit 9 */ -#define CAN_FM1R_FBM10 ((u16)0x0400) /* Filter Init Mode bit 10 */ -#define CAN_FM1R_FBM11 ((u16)0x0800) /* Filter Init Mode bit 11 */ -#define CAN_FM1R_FBM12 ((u16)0x1000) /* Filter Init Mode bit 12 */ -#define CAN_FM1R_FBM13 ((u16)0x2000) /* Filter Init Mode bit 13 */ - - -/******************* Bit definition for CAN_FS1R register *******************/ -#define CAN_FS1R_FSC ((u16)0x3FFF) /* Filter Scale Configuration */ -#define CAN_FS1R_FSC0 ((u16)0x0001) /* Filter Scale Configuration bit 0 */ -#define CAN_FS1R_FSC1 ((u16)0x0002) /* Filter Scale Configuration bit 1 */ -#define CAN_FS1R_FSC2 ((u16)0x0004) /* Filter Scale Configuration bit 2 */ -#define CAN_FS1R_FSC3 ((u16)0x0008) /* Filter Scale Configuration bit 3 */ -#define CAN_FS1R_FSC4 ((u16)0x0010) /* Filter Scale Configuration bit 4 */ -#define CAN_FS1R_FSC5 ((u16)0x0020) /* Filter Scale Configuration bit 5 */ -#define CAN_FS1R_FSC6 ((u16)0x0040) /* Filter Scale Configuration bit 6 */ -#define CAN_FS1R_FSC7 ((u16)0x0080) /* Filter Scale Configuration bit 7 */ -#define CAN_FS1R_FSC8 ((u16)0x0100) /* Filter Scale Configuration bit 8 */ -#define CAN_FS1R_FSC9 ((u16)0x0200) /* Filter Scale Configuration bit 9 */ -#define CAN_FS1R_FSC10 ((u16)0x0400) /* Filter Scale Configuration bit 10 */ -#define CAN_FS1R_FSC11 ((u16)0x0800) /* Filter Scale Configuration bit 11 */ -#define CAN_FS1R_FSC12 ((u16)0x1000) /* Filter Scale Configuration bit 12 */ -#define CAN_FS1R_FSC13 ((u16)0x2000) /* Filter Scale Configuration bit 13 */ - - -/****************** Bit definition for CAN_FFA1R register *******************/ -#define CAN_FFA1R_FFA ((u16)0x3FFF) /* Filter FIFO Assignment */ -#define CAN_FFA1R_FFA0 ((u16)0x0001) /* Filter FIFO Assignment for Filter 0 */ -#define CAN_FFA1R_FFA1 ((u16)0x0002) /* Filter FIFO Assignment for Filter 1 */ -#define CAN_FFA1R_FFA2 ((u16)0x0004) /* Filter FIFO Assignment for Filter 2 */ -#define CAN_FFA1R_FFA3 ((u16)0x0008) /* Filter FIFO Assignment for Filter 3 */ -#define CAN_FFA1R_FFA4 ((u16)0x0010) /* Filter FIFO Assignment for Filter 4 */ -#define CAN_FFA1R_FFA5 ((u16)0x0020) /* Filter FIFO Assignment for Filter 5 */ -#define CAN_FFA1R_FFA6 ((u16)0x0040) /* Filter FIFO Assignment for Filter 6 */ -#define CAN_FFA1R_FFA7 ((u16)0x0080) /* Filter FIFO Assignment for Filter 7 */ -#define CAN_FFA1R_FFA8 ((u16)0x0100) /* Filter FIFO Assignment for Filter 8 */ -#define CAN_FFA1R_FFA9 ((u16)0x0200) /* Filter FIFO Assignment for Filter 9 */ -#define CAN_FFA1R_FFA10 ((u16)0x0400) /* Filter FIFO Assignment for Filter 10 */ -#define CAN_FFA1R_FFA11 ((u16)0x0800) /* Filter FIFO Assignment for Filter 11 */ -#define CAN_FFA1R_FFA12 ((u16)0x1000) /* Filter FIFO Assignment for Filter 12 */ -#define CAN_FFA1R_FFA13 ((u16)0x2000) /* Filter FIFO Assignment for Filter 13 */ - - -/******************* Bit definition for CAN_FA1R register *******************/ -#define CAN_FA1R_FACT ((u16)0x3FFF) /* Filter Active */ -#define CAN_FA1R_FACT0 ((u16)0x0001) /* Filter 0 Active */ -#define CAN_FA1R_FACT1 ((u16)0x0002) /* Filter 1 Active */ -#define CAN_FA1R_FACT2 ((u16)0x0004) /* Filter 2 Active */ -#define CAN_FA1R_FACT3 ((u16)0x0008) /* Filter 3 Active */ -#define CAN_FA1R_FACT4 ((u16)0x0010) /* Filter 4 Active */ -#define CAN_FA1R_FACT5 ((u16)0x0020) /* Filter 5 Active */ -#define CAN_FA1R_FACT6 ((u16)0x0040) /* Filter 6 Active */ -#define CAN_FA1R_FACT7 ((u16)0x0080) /* Filter 7 Active */ -#define CAN_FA1R_FACT8 ((u16)0x0100) /* Filter 8 Active */ -#define CAN_FA1R_FACT9 ((u16)0x0200) /* Filter 9 Active */ -#define CAN_FA1R_FACT10 ((u16)0x0400) /* Filter 10 Active */ -#define CAN_FA1R_FACT11 ((u16)0x0800) /* Filter 11 Active */ -#define CAN_FA1R_FACT12 ((u16)0x1000) /* Filter 12 Active */ -#define CAN_FA1R_FACT13 ((u16)0x2000) /* Filter 13 Active */ - - -/******************* Bit definition for CAN_F0R1 register *******************/ -#define CAN_F0R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F0R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F0R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F0R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F0R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F0R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F0R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F0R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F0R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F0R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F0R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F0R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F0R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F0R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F0R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F0R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F0R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F0R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F0R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F0R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F0R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F0R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F0R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F0R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F0R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F0R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F0R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F0R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F0R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F0R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F0R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F0R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F1R1 register *******************/ -#define CAN_F1R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F1R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F1R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F1R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F1R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F1R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F1R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F1R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F1R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F1R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F1R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F1R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F1R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F1R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F1R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F1R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F1R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F1R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F1R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F1R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F1R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F1R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F1R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F1R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F1R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F1R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F1R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F1R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F1R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F1R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F1R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F1R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F2R1 register *******************/ -#define CAN_F2R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F2R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F2R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F2R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F2R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F2R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F2R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F2R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F2R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F2R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F2R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F2R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F2R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F2R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F2R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F2R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F2R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F2R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F2R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F2R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F2R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F2R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F2R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F2R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F2R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F2R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F2R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F2R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F2R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F2R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F2R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F2R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F3R1 register *******************/ -#define CAN_F3R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F3R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F3R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F3R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F3R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F3R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F3R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F3R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F3R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F3R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F3R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F3R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F3R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F3R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F3R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F3R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F3R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F3R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F3R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F3R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F3R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F3R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F3R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F3R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F3R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F3R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F3R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F3R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F3R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F3R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F3R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F3R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F4R1 register *******************/ -#define CAN_F4R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F4R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F4R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F4R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F4R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F4R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F4R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F4R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F4R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F4R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F4R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F4R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F4R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F4R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F4R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F4R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F4R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F4R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F4R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F4R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F4R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F4R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F4R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F4R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F4R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F4R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F4R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F4R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F4R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F4R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F4R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F4R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F5R1 register *******************/ -#define CAN_F5R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F5R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F5R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F5R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F5R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F5R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F5R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F5R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F5R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F5R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F5R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F5R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F5R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F5R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F5R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F5R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F5R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F5R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F5R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F5R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F5R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F5R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F5R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F5R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F5R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F5R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F5R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F5R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F5R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F5R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F5R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F5R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F6R1 register *******************/ -#define CAN_F6R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F6R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F6R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F6R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F6R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F6R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F6R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F6R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F6R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F6R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F6R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F6R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F6R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F6R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F6R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F6R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F6R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F6R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F6R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F6R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F6R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F6R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F6R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F6R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F6R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F6R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F6R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F6R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F6R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F6R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F6R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F6R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F7R1 register *******************/ -#define CAN_F7R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F7R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F7R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F7R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F7R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F7R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F7R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F7R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F7R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F7R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F7R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F7R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F7R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F7R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F7R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F7R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F7R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F7R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F7R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F7R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F7R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F7R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F7R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F7R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F7R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F7R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F7R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F7R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F7R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F7R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F7R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F7R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F8R1 register *******************/ -#define CAN_F8R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F8R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F8R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F8R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F8R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F8R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F8R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F8R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F8R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F8R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F8R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F8R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F8R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F8R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F8R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F8R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F8R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F8R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F8R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F8R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F8R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F8R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F8R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F8R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F8R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F8R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F8R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F8R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F8R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F8R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F8R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F8R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F9R1 register *******************/ -#define CAN_F9R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F9R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F9R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F9R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F9R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F9R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F9R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F9R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F9R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F9R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F9R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F9R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F9R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F9R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F9R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F9R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F9R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F9R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F9R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F9R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F9R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F9R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F9R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F9R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F9R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F9R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F9R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F9R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F9R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F9R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F9R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F9R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F10R1 register ******************/ -#define CAN_F10R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F10R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F10R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F10R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F10R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F10R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F10R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F10R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F10R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F10R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F10R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F10R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F10R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F10R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F10R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F10R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F10R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F10R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F10R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F10R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F10R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F10R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F10R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F10R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F10R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F10R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F10R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F10R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F10R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F10R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F10R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F10R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F11R1 register ******************/ -#define CAN_F11R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F11R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F11R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F11R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F11R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F11R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F11R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F11R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F11R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F11R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F11R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F11R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F11R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F11R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F11R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F11R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F11R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F11R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F11R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F11R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F11R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F11R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F11R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F11R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F11R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F11R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F11R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F11R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F11R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F11R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F11R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F11R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F12R1 register ******************/ -#define CAN_F12R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F12R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F12R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F12R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F12R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F12R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F12R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F12R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F12R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F12R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F12R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F12R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F12R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F12R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F12R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F12R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F12R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F12R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F12R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F12R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F12R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F12R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F12R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F12R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F12R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F12R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F12R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F12R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F12R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F12R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F12R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F12R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F13R1 register ******************/ -#define CAN_F13R1_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F13R1_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F13R1_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F13R1_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F13R1_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F13R1_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F13R1_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F13R1_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F13R1_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F13R1_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F13R1_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F13R1_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F13R1_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F13R1_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F13R1_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F13R1_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F13R1_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F13R1_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F13R1_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F13R1_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F13R1_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F13R1_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F13R1_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F13R1_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F13R1_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F13R1_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F13R1_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F13R1_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F13R1_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F13R1_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F13R1_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F13R1_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F0R2 register *******************/ -#define CAN_F0R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F0R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F0R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F0R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F0R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F0R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F0R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F0R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F0R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F0R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F0R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F0R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F0R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F0R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F0R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F0R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F0R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F0R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F0R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F0R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F0R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F0R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F0R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F0R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F0R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F0R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F0R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F0R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F0R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F0R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F0R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F0R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F1R2 register *******************/ -#define CAN_F1R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F1R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F1R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F1R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F1R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F1R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F1R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F1R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F1R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F1R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F1R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F1R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F1R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F1R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F1R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F1R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F1R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F1R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F1R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F1R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F1R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F1R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F1R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F1R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F1R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F1R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F1R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F1R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F1R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F1R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F1R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F1R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F2R2 register *******************/ -#define CAN_F2R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F2R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F2R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F2R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F2R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F2R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F2R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F2R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F2R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F2R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F2R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F2R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F2R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F2R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F2R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F2R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F2R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F2R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F2R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F2R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F2R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F2R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F2R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F2R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F2R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F2R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F2R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F2R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F2R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F2R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F2R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F2R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F3R2 register *******************/ -#define CAN_F3R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F3R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F3R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F3R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F3R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F3R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F3R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F3R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F3R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F3R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F3R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F3R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F3R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F3R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F3R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F3R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F3R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F3R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F3R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F3R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F3R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F3R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F3R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F3R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F3R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F3R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F3R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F3R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F3R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F3R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F3R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F3R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F4R2 register *******************/ -#define CAN_F4R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F4R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F4R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F4R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F4R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F4R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F4R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F4R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F4R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F4R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F4R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F4R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F4R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F4R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F4R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F4R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F4R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F4R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F4R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F4R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F4R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F4R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F4R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F4R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F4R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F4R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F4R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F4R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F4R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F4R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F4R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F4R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F5R2 register *******************/ -#define CAN_F5R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F5R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F5R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F5R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F5R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F5R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F5R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F5R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F5R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F5R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F5R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F5R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F5R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F5R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F5R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F5R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F5R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F5R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F5R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F5R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F5R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F5R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F5R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F5R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F5R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F5R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F5R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F5R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F5R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F5R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F5R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F5R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F6R2 register *******************/ -#define CAN_F6R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F6R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F6R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F6R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F6R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F6R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F6R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F6R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F6R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F6R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F6R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F6R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F6R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F6R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F6R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F6R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F6R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F6R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F6R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F6R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F6R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F6R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F6R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F6R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F6R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F6R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F6R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F6R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F6R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F6R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F6R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F6R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F7R2 register *******************/ -#define CAN_F7R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F7R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F7R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F7R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F7R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F7R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F7R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F7R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F7R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F7R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F7R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F7R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F7R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F7R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F7R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F7R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F7R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F7R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F7R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F7R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F7R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F7R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F7R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F7R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F7R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F7R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F7R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F7R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F7R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F7R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F7R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F7R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F8R2 register *******************/ -#define CAN_F8R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F8R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F8R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F8R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F8R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F8R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F8R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F8R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F8R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F8R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F8R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F8R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F8R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F8R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F8R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F8R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F8R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F8R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F8R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F8R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F8R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F8R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F8R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F8R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F8R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F8R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F8R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F8R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F8R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F8R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F8R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F8R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F9R2 register *******************/ -#define CAN_F9R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F9R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F9R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F9R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F9R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F9R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F9R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F9R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F9R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F9R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F9R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F9R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F9R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F9R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F9R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F9R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F9R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F9R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F9R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F9R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F9R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F9R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F9R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F9R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F9R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F9R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F9R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F9R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F9R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F9R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F9R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F9R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F10R2 register ******************/ -#define CAN_F10R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F10R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F10R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F10R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F10R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F10R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F10R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F10R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F10R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F10R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F10R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F10R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F10R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F10R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F10R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F10R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F10R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F10R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F10R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F10R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F10R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F10R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F10R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F10R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F10R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F10R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F10R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F10R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F10R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F10R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F10R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F10R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F11R2 register ******************/ -#define CAN_F11R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F11R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F11R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F11R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F11R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F11R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F11R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F11R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F11R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F11R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F11R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F11R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F11R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F11R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F11R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F11R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F11R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F11R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F11R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F11R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F11R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F11R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F11R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F11R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F11R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F11R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F11R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F11R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F11R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F11R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F11R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F11R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F12R2 register ******************/ -#define CAN_F12R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F12R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F12R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F12R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F12R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F12R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F12R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F12R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F12R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F12R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F12R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F12R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F12R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F12R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F12R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F12R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F12R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F12R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F12R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F12R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F12R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F12R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F12R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F12R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F12R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F12R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F12R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F12R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F12R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F12R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F12R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F12R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - -/******************* Bit definition for CAN_F13R2 register ******************/ -#define CAN_F13R2_FB0 ((u32)0x00000001) /* Filter bit 0 */ -#define CAN_F13R2_FB1 ((u32)0x00000002) /* Filter bit 1 */ -#define CAN_F13R2_FB2 ((u32)0x00000004) /* Filter bit 2 */ -#define CAN_F13R2_FB3 ((u32)0x00000008) /* Filter bit 3 */ -#define CAN_F13R2_FB4 ((u32)0x00000010) /* Filter bit 4 */ -#define CAN_F13R2_FB5 ((u32)0x00000020) /* Filter bit 5 */ -#define CAN_F13R2_FB6 ((u32)0x00000040) /* Filter bit 6 */ -#define CAN_F13R2_FB7 ((u32)0x00000080) /* Filter bit 7 */ -#define CAN_F13R2_FB8 ((u32)0x00000100) /* Filter bit 8 */ -#define CAN_F13R2_FB9 ((u32)0x00000200) /* Filter bit 9 */ -#define CAN_F13R2_FB10 ((u32)0x00000400) /* Filter bit 10 */ -#define CAN_F13R2_FB11 ((u32)0x00000800) /* Filter bit 11 */ -#define CAN_F13R2_FB12 ((u32)0x00001000) /* Filter bit 12 */ -#define CAN_F13R2_FB13 ((u32)0x00002000) /* Filter bit 13 */ -#define CAN_F13R2_FB14 ((u32)0x00004000) /* Filter bit 14 */ -#define CAN_F13R2_FB15 ((u32)0x00008000) /* Filter bit 15 */ -#define CAN_F13R2_FB16 ((u32)0x00010000) /* Filter bit 16 */ -#define CAN_F13R2_FB17 ((u32)0x00020000) /* Filter bit 17 */ -#define CAN_F13R2_FB18 ((u32)0x00040000) /* Filter bit 18 */ -#define CAN_F13R2_FB19 ((u32)0x00080000) /* Filter bit 19 */ -#define CAN_F13R2_FB20 ((u32)0x00100000) /* Filter bit 20 */ -#define CAN_F13R2_FB21 ((u32)0x00200000) /* Filter bit 21 */ -#define CAN_F13R2_FB22 ((u32)0x00400000) /* Filter bit 22 */ -#define CAN_F13R2_FB23 ((u32)0x00800000) /* Filter bit 23 */ -#define CAN_F13R2_FB24 ((u32)0x01000000) /* Filter bit 24 */ -#define CAN_F13R2_FB25 ((u32)0x02000000) /* Filter bit 25 */ -#define CAN_F13R2_FB26 ((u32)0x04000000) /* Filter bit 26 */ -#define CAN_F13R2_FB27 ((u32)0x08000000) /* Filter bit 27 */ -#define CAN_F13R2_FB28 ((u32)0x10000000) /* Filter bit 28 */ -#define CAN_F13R2_FB29 ((u32)0x20000000) /* Filter bit 29 */ -#define CAN_F13R2_FB30 ((u32)0x40000000) /* Filter bit 30 */ -#define CAN_F13R2_FB31 ((u32)0x80000000) /* Filter bit 31 */ - - - -/******************************************************************************/ -/* */ -/* Serial Peripheral Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_CPHA ((u16)0x0001) /* Clock Phase */ -#define SPI_CR1_CPOL ((u16)0x0002) /* Clock Polarity */ -#define SPI_CR1_MSTR ((u16)0x0004) /* Master Selection */ - -#define SPI_CR1_BR ((u16)0x0038) /* BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((u16)0x0008) /* Bit 0 */ -#define SPI_CR1_BR_1 ((u16)0x0010) /* Bit 1 */ -#define SPI_CR1_BR_2 ((u16)0x0020) /* Bit 2 */ - -#define SPI_CR1_SPE ((u16)0x0040) /* SPI Enable */ -#define SPI_CR1_LSBFIRST ((u16)0x0080) /* Frame Format */ -#define SPI_CR1_SSI ((u16)0x0100) /* Internal slave select */ -#define SPI_CR1_SSM ((u16)0x0200) /* Software slave management */ -#define SPI_CR1_RXONLY ((u16)0x0400) /* Receive only */ -#define SPI_CR1_DFF ((u16)0x0800) /* Data Frame Format */ -#define SPI_CR1_CRCNEXT ((u16)0x1000) /* Transmit CRC next */ -#define SPI_CR1_CRCEN ((u16)0x2000) /* Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((u16)0x4000) /* Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((u16)0x8000) /* Bidirectional data mode enable */ - - -/******************* Bit definition for SPI_CR2 register ********************/ -#define SPI_CR2_RXDMAEN ((u8)0x01) /* Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((u8)0x02) /* Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((u8)0x04) /* SS Output Enable */ -#define SPI_CR2_ERRIE ((u8)0x20) /* Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((u8)0x40) /* RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((u8)0x80) /* Tx buffer Empty Interrupt Enable */ - - -/******************** Bit definition for SPI_SR register ********************/ -#define SPI_SR_RXNE ((u8)0x01) /* Receive buffer Not Empty */ -#define SPI_SR_TXE ((u8)0x02) /* Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((u8)0x04) /* Channel side */ -#define SPI_SR_UDR ((u8)0x08) /* Underrun flag */ -#define SPI_SR_CRCERR ((u8)0x10) /* CRC Error flag */ -#define SPI_SR_MODF ((u8)0x20) /* Mode fault */ -#define SPI_SR_OVR ((u8)0x40) /* Overrun flag */ -#define SPI_SR_BSY ((u8)0x80) /* Busy flag */ - - -/******************** Bit definition for SPI_DR register ********************/ -#define SPI_DR_DR ((u16)0xFFFF) /* Data Register */ - - -/******************* Bit definition for SPI_CRCPR register ******************/ -#define SPI_CRCPR_CRCPOLY ((u16)0xFFFF) /* CRC polynomial register */ - - -/****************** Bit definition for SPI_RXCRCR register ******************/ -#define SPI_RXCRCR_RXCRC ((u16)0xFFFF) /* Rx CRC Register */ - - -/****************** Bit definition for SPI_TXCRCR register ******************/ -#define SPI_TXCRCR_TXCRC ((u16)0xFFFF) /* Tx CRC Register */ - - -/****************** Bit definition for SPI_I2SCFGR register *****************/ -#define SPI_I2SCFGR_CHLEN ((u16)0x0001) /* Channel length (number of bits per audio channel) */ - -#define SPI_I2SCFGR_DATLEN ((u16)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ -#define SPI_I2SCFGR_DATLEN_0 ((u16)0x0002) /* Bit 0 */ -#define SPI_I2SCFGR_DATLEN_1 ((u16)0x0004) /* Bit 1 */ - -#define SPI_I2SCFGR_CKPOL ((u16)0x0008) /* steady state clock polarity */ - -#define SPI_I2SCFGR_I2SSTD ((u16)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ -#define SPI_I2SCFGR_I2SSTD_0 ((u16)0x0010) /* Bit 0 */ -#define SPI_I2SCFGR_I2SSTD_1 ((u16)0x0020) /* Bit 1 */ - -#define SPI_I2SCFGR_PCMSYNC ((u16)0x0080) /* PCM frame synchronization */ - -#define SPI_I2SCFGR_I2SCFG ((u16)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ -#define SPI_I2SCFGR_I2SCFG_0 ((u16)0x0100) /* Bit 0 */ -#define SPI_I2SCFGR_I2SCFG_1 ((u16)0x0200) /* Bit 1 */ - -#define SPI_I2SCFGR_I2SE ((u16)0x0400) /* I2S Enable */ -#define SPI_I2SCFGR_I2SMOD ((u16)0x0800) /* I2S mode selection */ - - -/****************** Bit definition for SPI_I2SPR register *******************/ -#define SPI_I2SPR_I2SDIV ((u16)0x00FF) /* I2S Linear prescaler */ -#define SPI_I2SPR_ODD ((u16)0x0100) /* Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE ((u16)0x0200) /* Master Clock Output Enable */ - - - -/******************************************************************************/ -/* */ -/* Inter-integrated Circuit Interface */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for I2C_CR1 register ********************/ -#define I2C_CR1_PE ((u16)0x0001) /* Peripheral Enable */ -#define I2C_CR1_SMBUS ((u16)0x0002) /* SMBus Mode */ -#define I2C_CR1_SMBTYPE ((u16)0x0008) /* SMBus Type */ -#define I2C_CR1_ENARP ((u16)0x0010) /* ARP Enable */ -#define I2C_CR1_ENPEC ((u16)0x0020) /* PEC Enable */ -#define I2C_CR1_ENGC ((u16)0x0040) /* General Call Enable */ -#define I2C_CR1_NOSTRETCH ((u16)0x0080) /* Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START ((u16)0x0100) /* Start Generation */ -#define I2C_CR1_STOP ((u16)0x0200) /* Stop Generation */ -#define I2C_CR1_ACK ((u16)0x0400) /* Acknowledge Enable */ -#define I2C_CR1_POS ((u16)0x0800) /* Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC ((u16)0x1000) /* Packet Error Checking */ -#define I2C_CR1_ALERT ((u16)0x2000) /* SMBus Alert */ -#define I2C_CR1_SWRST ((u16)0x8000) /* Software Reset */ - - -/******************* Bit definition for I2C_CR2 register ********************/ -#define I2C_CR2_FREQ ((u16)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ -#define I2C_CR2_FREQ_0 ((u16)0x0001) /* Bit 0 */ -#define I2C_CR2_FREQ_1 ((u16)0x0002) /* Bit 1 */ -#define I2C_CR2_FREQ_2 ((u16)0x0004) /* Bit 2 */ -#define I2C_CR2_FREQ_3 ((u16)0x0008) /* Bit 3 */ -#define I2C_CR2_FREQ_4 ((u16)0x0010) /* Bit 4 */ -#define I2C_CR2_FREQ_5 ((u16)0x0020) /* Bit 5 */ - -#define I2C_CR2_ITERREN ((u16)0x0100) /* Error Interrupt Enable */ -#define I2C_CR2_ITEVTEN ((u16)0x0200) /* Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN ((u16)0x0400) /* Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN ((u16)0x0800) /* DMA Requests Enable */ -#define I2C_CR2_LAST ((u16)0x1000) /* DMA Last Transfer */ - - -/******************* Bit definition for I2C_OAR1 register *******************/ -#define I2C_OAR1_ADD1_7 ((u16)0x00FE) /* Interface Address */ -#define I2C_OAR1_ADD8_9 ((u16)0x0300) /* Interface Address */ - -#define I2C_OAR1_ADD0 ((u16)0x0001) /* Bit 0 */ -#define I2C_OAR1_ADD1 ((u16)0x0002) /* Bit 1 */ -#define I2C_OAR1_ADD2 ((u16)0x0004) /* Bit 2 */ -#define I2C_OAR1_ADD3 ((u16)0x0008) /* Bit 3 */ -#define I2C_OAR1_ADD4 ((u16)0x0010) /* Bit 4 */ -#define I2C_OAR1_ADD5 ((u16)0x0020) /* Bit 5 */ -#define I2C_OAR1_ADD6 ((u16)0x0040) /* Bit 6 */ -#define I2C_OAR1_ADD7 ((u16)0x0080) /* Bit 7 */ -#define I2C_OAR1_ADD8 ((u16)0x0100) /* Bit 8 */ -#define I2C_OAR1_ADD9 ((u16)0x0200) /* Bit 9 */ - -#define I2C_OAR1_ADDMODE ((u16)0x8000) /* Addressing Mode (Slave mode) */ - - -/******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_ENDUAL ((u8)0x01) /* Dual addressing mode enable */ -#define I2C_OAR2_ADD2 ((u8)0xFE) /* Interface address */ - - -/******************** Bit definition for I2C_DR register ********************/ -#define I2C_DR_DR ((u8)0xFF) /* 8-bit Data Register */ - - -/******************* Bit definition for I2C_SR1 register ********************/ -#define I2C_SR1_SB ((u16)0x0001) /* Start Bit (Master mode) */ -#define I2C_SR1_ADDR ((u16)0x0002) /* Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF ((u16)0x0004) /* Byte Transfer Finished */ -#define I2C_SR1_ADD10 ((u16)0x0008) /* 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF ((u16)0x0010) /* Stop detection (Slave mode) */ -#define I2C_SR1_RXNE ((u16)0x0040) /* Data Register not Empty (receivers) */ -#define I2C_SR1_TXE ((u16)0x0080) /* Data Register Empty (transmitters) */ -#define I2C_SR1_BERR ((u16)0x0100) /* Bus Error */ -#define I2C_SR1_ARLO ((u16)0x0200) /* Arbitration Lost (master mode) */ -#define I2C_SR1_AF ((u16)0x0400) /* Acknowledge Failure */ -#define I2C_SR1_OVR ((u16)0x0800) /* Overrun/Underrun */ -#define I2C_SR1_PECERR ((u16)0x1000) /* PEC Error in reception */ -#define I2C_SR1_TIMEOUT ((u16)0x4000) /* Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT ((u16)0x8000) /* SMBus Alert */ - - -/******************* Bit definition for I2C_SR2 register ********************/ -#define I2C_SR2_MSL ((u16)0x0001) /* Master/Slave */ -#define I2C_SR2_BUSY ((u16)0x0002) /* Bus Busy */ -#define I2C_SR2_TRA ((u16)0x0004) /* Transmitter/Receiver */ -#define I2C_SR2_GENCALL ((u16)0x0010) /* General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT ((u16)0x0020) /* SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST ((u16)0x0040) /* SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF ((u16)0x0080) /* Dual Flag (Slave mode) */ -#define I2C_SR2_PEC ((u16)0xFF00) /* Packet Error Checking Register */ - - -/******************* Bit definition for I2C_CCR register ********************/ -#define I2C_CCR_CCR ((u16)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_DUTY ((u16)0x4000) /* Fast Mode Duty Cycle */ -#define I2C_CCR_FS ((u16)0x8000) /* I2C Master Mode Selection */ - - -/****************** Bit definition for I2C_TRISE register *******************/ -#define I2C_TRISE_TRISE ((u8)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ - - - -/******************************************************************************/ -/* */ -/* Universal Synchronous Asynchronous Receiver Transmitter */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for USART_SR register *******************/ -#define USART_SR_PE ((u16)0x0001) /* Parity Error */ -#define USART_SR_FE ((u16)0x0002) /* Framing Error */ -#define USART_SR_NE ((u16)0x0004) /* Noise Error Flag */ -#define USART_SR_ORE ((u16)0x0008) /* OverRun Error */ -#define USART_SR_IDLE ((u16)0x0010) /* IDLE line detected */ -#define USART_SR_RXNE ((u16)0x0020) /* Read Data Register Not Empty */ -#define USART_SR_TC ((u16)0x0040) /* Transmission Complete */ -#define USART_SR_TXE ((u16)0x0080) /* Transmit Data Register Empty */ -#define USART_SR_LBD ((u16)0x0100) /* LIN Break Detection Flag */ -#define USART_SR_CTS ((u16)0x0200) /* CTS Flag */ - - -/******************* Bit definition for USART_DR register *******************/ -#define USART_DR_DR ((u16)0x01FF) /* Data value */ - - -/****************** Bit definition for USART_BRR register *******************/ -#define USART_BRR_DIV_Fraction ((u16)0x000F) /* Fraction of USARTDIV */ -#define USART_BRR_DIV_Mantissa ((u16)0xFFF0) /* Mantissa of USARTDIV */ - - -/****************** Bit definition for USART_CR1 register *******************/ -#define USART_CR1_SBK ((u16)0x0001) /* Send Break */ -#define USART_CR1_RWU ((u16)0x0002) /* Receiver wakeup */ -#define USART_CR1_RE ((u16)0x0004) /* Receiver Enable */ -#define USART_CR1_TE ((u16)0x0008) /* Transmitter Enable */ -#define USART_CR1_IDLEIE ((u16)0x0010) /* IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE ((u16)0x0020) /* RXNE Interrupt Enable */ -#define USART_CR1_TCIE ((u16)0x0040) /* Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE ((u16)0x0080) /* PE Interrupt Enable */ -#define USART_CR1_PEIE ((u16)0x0100) /* PE Interrupt Enable */ -#define USART_CR1_PS ((u16)0x0200) /* Parity Selection */ -#define USART_CR1_PCE ((u16)0x0400) /* Parity Control Enable */ -#define USART_CR1_WAKE ((u16)0x0800) /* Wakeup method */ -#define USART_CR1_M ((u16)0x1000) /* Word length */ -#define USART_CR1_UE ((u16)0x2000) /* USART Enable */ - - -/****************** Bit definition for USART_CR2 register *******************/ -#define USART_CR2_ADD ((u16)0x000F) /* Address of the USART node */ -#define USART_CR2_LBDL ((u16)0x0020) /* LIN Break Detection Length */ -#define USART_CR2_LBDIE ((u16)0x0040) /* LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL ((u16)0x0100) /* Last Bit Clock pulse */ -#define USART_CR2_CPHA ((u16)0x0200) /* Clock Phase */ -#define USART_CR2_CPOL ((u16)0x0400) /* Clock Polarity */ -#define USART_CR2_CLKEN ((u16)0x0800) /* Clock Enable */ - -#define USART_CR2_STOP ((u16)0x3000) /* STOP[1:0] bits (STOP bits) */ -#define USART_CR2_STOP_0 ((u16)0x1000) /* Bit 0 */ -#define USART_CR2_STOP_1 ((u16)0x2000) /* Bit 1 */ - -#define USART_CR2_LINEN ((u16)0x4000) /* LIN mode enable */ - - -/****************** Bit definition for USART_CR3 register *******************/ -#define USART_CR3_EIE ((u16)0x0001) /* Error Interrupt Enable */ -#define USART_CR3_IREN ((u16)0x0002) /* IrDA mode Enable */ -#define USART_CR3_IRLP ((u16)0x0004) /* IrDA Low-Power */ -#define USART_CR3_HDSEL ((u16)0x0008) /* Half-Duplex Selection */ -#define USART_CR3_NACK ((u16)0x0010) /* Smartcard NACK enable */ -#define USART_CR3_SCEN ((u16)0x0020) /* Smartcard mode enable */ -#define USART_CR3_DMAR ((u16)0x0040) /* DMA Enable Receiver */ -#define USART_CR3_DMAT ((u16)0x0080) /* DMA Enable Transmitter */ -#define USART_CR3_RTSE ((u16)0x0100) /* RTS Enable */ -#define USART_CR3_CTSE ((u16)0x0200) /* CTS Enable */ -#define USART_CR3_CTSIE ((u16)0x0400) /* CTS Interrupt Enable */ - - -/****************** Bit definition for USART_GTPR register ******************/ -#define USART_GTPR_PSC ((u16)0x00FF) /* PSC[7:0] bits (Prescaler value) */ -#define USART_GTPR_PSC_0 ((u16)0x0001) /* Bit 0 */ -#define USART_GTPR_PSC_1 ((u16)0x0002) /* Bit 1 */ -#define USART_GTPR_PSC_2 ((u16)0x0004) /* Bit 2 */ -#define USART_GTPR_PSC_3 ((u16)0x0008) /* Bit 3 */ -#define USART_GTPR_PSC_4 ((u16)0x0010) /* Bit 4 */ -#define USART_GTPR_PSC_5 ((u16)0x0020) /* Bit 5 */ -#define USART_GTPR_PSC_6 ((u16)0x0040) /* Bit 6 */ -#define USART_GTPR_PSC_7 ((u16)0x0080) /* Bit 7 */ - -#define USART_GTPR_GT ((u16)0xFF00) /* Guard time value */ - - - -/******************************************************************************/ -/* */ -/* Debug MCU */ -/* */ -/******************************************************************************/ - -/**************** Bit definition for DBGMCU_IDCODE register *****************/ -#define DBGMCU_IDCODE_DEV_ID ((u32)0x00000FFF) /* Device Identifier */ - -#define DBGMCU_IDCODE_REV_ID ((u32)0xFFFF0000) /* REV_ID[15:0] bits (Revision Identifier) */ -#define DBGMCU_IDCODE_REV_ID_0 ((u32)0x00010000) /* Bit 0 */ -#define DBGMCU_IDCODE_REV_ID_1 ((u32)0x00020000) /* Bit 1 */ -#define DBGMCU_IDCODE_REV_ID_2 ((u32)0x00040000) /* Bit 2 */ -#define DBGMCU_IDCODE_REV_ID_3 ((u32)0x00080000) /* Bit 3 */ -#define DBGMCU_IDCODE_REV_ID_4 ((u32)0x00100000) /* Bit 4 */ -#define DBGMCU_IDCODE_REV_ID_5 ((u32)0x00200000) /* Bit 5 */ -#define DBGMCU_IDCODE_REV_ID_6 ((u32)0x00400000) /* Bit 6 */ -#define DBGMCU_IDCODE_REV_ID_7 ((u32)0x00800000) /* Bit 7 */ -#define DBGMCU_IDCODE_REV_ID_8 ((u32)0x01000000) /* Bit 8 */ -#define DBGMCU_IDCODE_REV_ID_9 ((u32)0x02000000) /* Bit 9 */ -#define DBGMCU_IDCODE_REV_ID_10 ((u32)0x04000000) /* Bit 10 */ -#define DBGMCU_IDCODE_REV_ID_11 ((u32)0x08000000) /* Bit 11 */ -#define DBGMCU_IDCODE_REV_ID_12 ((u32)0x10000000) /* Bit 12 */ -#define DBGMCU_IDCODE_REV_ID_13 ((u32)0x20000000) /* Bit 13 */ -#define DBGMCU_IDCODE_REV_ID_14 ((u32)0x40000000) /* Bit 14 */ -#define DBGMCU_IDCODE_REV_ID_15 ((u32)0x80000000) /* Bit 15 */ - - -/****************** Bit definition for DBGMCU_CR register *******************/ -#define DBGMCU_CR_DBG_SLEEP ((u32)0x00000001) /* Debug Sleep Mode */ -#define DBGMCU_CR_DBG_STOP ((u32)0x00000002) /* Debug Stop Mode */ -#define DBGMCU_CR_DBG_STANDBY ((u32)0x00000004) /* Debug Standby mode */ -#define DBGMCU_CR_TRACE_IOEN ((u32)0x00000020) /* Trace Pin Assignment Control */ - -#define DBGMCU_CR_TRACE_MODE ((u32)0x000000C0) /* TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ -#define DBGMCU_CR_TRACE_MODE_0 ((u32)0x00000040) /* Bit 0 */ -#define DBGMCU_CR_TRACE_MODE_1 ((u32)0x00000080) /* Bit 1 */ - -#define DBGMCU_CR_DBG_IWDG_STOP ((u32)0x00000100) /* Debug Independent Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_WWDG_STOP ((u32)0x00000200) /* Debug Window Watchdog stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM1_STOP ((u32)0x00000400) /* TIM1 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM2_STOP ((u32)0x00000800) /* TIM2 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM3_STOP ((u32)0x00001000) /* TIM3 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM4_STOP ((u32)0x00002000) /* TIM4 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_CAN_STOP ((u32)0x00004000) /* Debug CAN stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((u32)0x00008000) /* SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((u32)0x00010000) /* SMBUS timeout mode stopped when Core is halted */ -#define DBGMCU_CR_DBG_TIM5_STOP ((u32)0x00020000) /* TIM5 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM6_STOP ((u32)0x00040000) /* TIM6 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM7_STOP ((u32)0x00080000) /* TIM7 counter stopped when core is halted */ -#define DBGMCU_CR_DBG_TIM8_STOP ((u32)0x00100000) /* TIM8 counter stopped when core is halted */ - - - -/******************************************************************************/ -/* */ -/* FLASH and Option Bytes Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((u8)0x07) /* LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((u8)0x01) /* Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((u8)0x02) /* Bit 1 */ -#define FLASH_ACR_LATENCY_2 ((u8)0x04) /* Bit 2 */ - -#define FLASH_ACR_HLFCYA ((u8)0x08) /* Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((u8)0x10) /* Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((u8)0x20) /* Prefetch Buffer Status */ - - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((u32)0xFFFFFFFF) /* FPEC Key */ - - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((u32)0xFFFFFFFF) /* Option Byte Key */ - - -/****************** Bit definition for FLASH_SR register *******************/ -#define FLASH_SR_BSY ((u8)0x01) /* Busy */ -#define FLASH_SR_PGERR ((u8)0x04) /* Programming Error */ -#define FLASH_SR_WRPRTERR ((u8)0x10) /* Write Protection Error */ -#define FLASH_SR_EOP ((u8)0x20) /* End of operation */ - - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((u16)0x0001) /* Programming */ -#define FLASH_CR_PER ((u16)0x0002) /* Page Erase */ -#define FLASH_CR_MER ((u16)0x0004) /* Mass Erase */ -#define FLASH_CR_OPTPG ((u16)0x0010) /* Option Byte Programming */ -#define FLASH_CR_OPTER ((u16)0x0020) /* Option Byte Erase */ -#define FLASH_CR_STRT ((u16)0x0040) /* Start */ -#define FLASH_CR_LOCK ((u16)0x0080) /* Lock */ -#define FLASH_CR_OPTWRE ((u16)0x0200) /* Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((u16)0x0400) /* Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((u16)0x1000) /* End of operation interrupt enable */ - - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((u32)0xFFFFFFFF) /* Flash Address */ - - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((u16)0x0001) /* Option Byte Error */ -#define FLASH_OBR_RDPRT ((u16)0x0002) /* Read protection */ - -#define FLASH_OBR_USER ((u16)0x03FC) /* User Option Bytes */ -#define FLASH_OBR_WDG_SW ((u16)0x0004) /* WDG_SW */ -#define FLASH_OBR_nRST_STOP ((u16)0x0008) /* nRST_STOP */ -#define FLASH_OBR_nRST_STDBY ((u16)0x0010) /* nRST_STDBY */ -#define FLASH_OBR_Notused ((u16)0x03E0) /* Not used */ - - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((u32)0xFFFFFFFF) /* Write Protect */ - - -/*----------------------------------------------------------------------------*/ - - -/****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP ((u32)0x000000FF) /* Read protection option byte */ -#define FLASH_RDP_nRDP ((u32)0x0000FF00) /* Read protection complemented option byte */ - - -/****************** Bit definition for FLASH_USER register ******************/ -#define FLASH_USER_USER ((u32)0x00FF0000) /* User option byte */ -#define FLASH_USER_nUSER ((u32)0xFF000000) /* User complemented option byte */ - - -/****************** Bit definition for FLASH_Data0 register *****************/ -#define FLASH_Data0_Data0 ((u32)0x000000FF) /* User data storage option byte */ -#define FLASH_Data0_nData0 ((u32)0x0000FF00) /* User data storage complemented option byte */ - - -/****************** Bit definition for FLASH_Data1 register *****************/ -#define FLASH_Data1_Data1 ((u32)0x00FF0000) /* User data storage option byte */ -#define FLASH_Data1_nData1 ((u32)0xFF000000) /* User data storage complemented option byte */ - - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0 ((u32)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ - - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define FLASH_WRP1_WRP1 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRP1_nWRP1 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ - - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define FLASH_WRP2_WRP2 ((u32)0x000000FF) /* Flash memory write protection option bytes */ -#define FLASH_WRP2_nWRP2 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */ - - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define FLASH_WRP3_WRP3 ((u32)0x00FF0000) /* Flash memory write protection option bytes */ -#define FLASH_WRP3_nWRP3 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */ - - -/* Exported macro ------------------------------------------------------------*/ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = 0x0) - -#define WRITE_REG(REG, VAL) ((REG) = VAL) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK))) - -/* Exported functions ------------------------------------------------------- */ - -#endif /* __STM32F10x_MAP_H */ - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h deleted file mode 100644 index 5a3ce7ef1..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_nvic.h +++ /dev/null @@ -1,287 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : stm32f10x_nvic.h -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : This file contains all the functions prototypes for the -* NVIC firmware library. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_NVIC_H -#define __STM32F10x_NVIC_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_map.h" - -/* Exported types ------------------------------------------------------------*/ -/* NVIC Init Structure definition */ -typedef struct -{ - u8 NVIC_IRQChannel; - u8 NVIC_IRQChannelPreemptionPriority; - u8 NVIC_IRQChannelSubPriority; - FunctionalState NVIC_IRQChannelCmd; -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* IRQ Channels --------------------------------------------------------------*/ -#define WWDG_IRQChannel ((u8)0x00) /* Window WatchDog Interrupt */ -#define PVD_IRQChannel ((u8)0x01) /* PVD through EXTI Line detection Interrupt */ -#define TAMPER_IRQChannel ((u8)0x02) /* Tamper Interrupt */ -#define RTC_IRQChannel ((u8)0x03) /* RTC global Interrupt */ -#define FLASH_IRQChannel ((u8)0x04) /* FLASH global Interrupt */ -#define RCC_IRQChannel ((u8)0x05) /* RCC global Interrupt */ -#define EXTI0_IRQChannel ((u8)0x06) /* EXTI Line0 Interrupt */ -#define EXTI1_IRQChannel ((u8)0x07) /* EXTI Line1 Interrupt */ -#define EXTI2_IRQChannel ((u8)0x08) /* EXTI Line2 Interrupt */ -#define EXTI3_IRQChannel ((u8)0x09) /* EXTI Line3 Interrupt */ -#define EXTI4_IRQChannel ((u8)0x0A) /* EXTI Line4 Interrupt */ -#define DMA1_Channel1_IRQChannel ((u8)0x0B) /* DMA1 Channel 1 global Interrupt */ -#define DMA1_Channel2_IRQChannel ((u8)0x0C) /* DMA1 Channel 2 global Interrupt */ -#define DMA1_Channel3_IRQChannel ((u8)0x0D) /* DMA1 Channel 3 global Interrupt */ -#define DMA1_Channel4_IRQChannel ((u8)0x0E) /* DMA1 Channel 4 global Interrupt */ -#define DMA1_Channel5_IRQChannel ((u8)0x0F) /* DMA1 Channel 5 global Interrupt */ -#define DMA1_Channel6_IRQChannel ((u8)0x10) /* DMA1 Channel 6 global Interrupt */ -#define DMA1_Channel7_IRQChannel ((u8)0x11) /* DMA1 Channel 7 global Interrupt */ -#define ADC1_2_IRQChannel ((u8)0x12) /* ADC1 et ADC2 global Interrupt */ -#define USB_HP_CAN_TX_IRQChannel ((u8)0x13) /* USB High Priority or CAN TX Interrupts */ -#define USB_LP_CAN_RX0_IRQChannel ((u8)0x14) /* USB Low Priority or CAN RX0 Interrupts */ -#define CAN_RX1_IRQChannel ((u8)0x15) /* CAN RX1 Interrupt */ -#define CAN_SCE_IRQChannel ((u8)0x16) /* CAN SCE Interrupt */ -#define EXTI9_5_IRQChannel ((u8)0x17) /* External Line[9:5] Interrupts */ -#define TIM1_BRK_IRQChannel ((u8)0x18) /* TIM1 Break Interrupt */ -#define TIM1_UP_IRQChannel ((u8)0x19) /* TIM1 Update Interrupt */ -#define TIM1_TRG_COM_IRQChannel ((u8)0x1A) /* TIM1 Trigger and Commutation Interrupt */ -#define TIM1_CC_IRQChannel ((u8)0x1B) /* TIM1 Capture Compare Interrupt */ -#define TIM2_IRQChannel ((u8)0x1C) /* TIM2 global Interrupt */ -#define TIM3_IRQChannel ((u8)0x1D) /* TIM3 global Interrupt */ -#define TIM4_IRQChannel ((u8)0x1E) /* TIM4 global Interrupt */ -#define I2C1_EV_IRQChannel ((u8)0x1F) /* I2C1 Event Interrupt */ -#define I2C1_ER_IRQChannel ((u8)0x20) /* I2C1 Error Interrupt */ -#define I2C2_EV_IRQChannel ((u8)0x21) /* I2C2 Event Interrupt */ -#define I2C2_ER_IRQChannel ((u8)0x22) /* I2C2 Error Interrupt */ -#define SPI1_IRQChannel ((u8)0x23) /* SPI1 global Interrupt */ -#define SPI2_IRQChannel ((u8)0x24) /* SPI2 global Interrupt */ -#define USART1_IRQChannel ((u8)0x25) /* USART1 global Interrupt */ -#define USART2_IRQChannel ((u8)0x26) /* USART2 global Interrupt */ -#define USART3_IRQChannel ((u8)0x27) /* USART3 global Interrupt */ -#define EXTI15_10_IRQChannel ((u8)0x28) /* External Line[15:10] Interrupts */ -#define RTCAlarm_IRQChannel ((u8)0x29) /* RTC Alarm through EXTI Line Interrupt */ -#define USBWakeUp_IRQChannel ((u8)0x2A) /* USB WakeUp from suspend through EXTI Line Interrupt */ -#define TIM8_BRK_IRQChannel ((u8)0x2B) /* TIM8 Break Interrupt */ -#define TIM8_UP_IRQChannel ((u8)0x2C) /* TIM8 Update Interrupt */ -#define TIM8_TRG_COM_IRQChannel ((u8)0x2D) /* TIM8 Trigger and Commutation Interrupt */ -#define TIM8_CC_IRQChannel ((u8)0x2E) /* TIM8 Capture Compare Interrupt */ -#define ADC3_IRQChannel ((u8)0x2F) /* ADC3 global Interrupt */ -#define FSMC_IRQChannel ((u8)0x30) /* FSMC global Interrupt */ -#define SDIO_IRQChannel ((u8)0x31) /* SDIO global Interrupt */ -#define TIM5_IRQChannel ((u8)0x32) /* TIM5 global Interrupt */ -#define SPI3_IRQChannel ((u8)0x33) /* SPI3 global Interrupt */ -#define UART4_IRQChannel ((u8)0x34) /* UART4 global Interrupt */ -#define UART5_IRQChannel ((u8)0x35) /* UART5 global Interrupt */ -#define TIM6_IRQChannel ((u8)0x36) /* TIM6 global Interrupt */ -#define TIM7_IRQChannel ((u8)0x37) /* TIM7 global Interrupt */ -#define DMA2_Channel1_IRQChannel ((u8)0x38) /* DMA2 Channel 1 global Interrupt */ -#define DMA2_Channel2_IRQChannel ((u8)0x39) /* DMA2 Channel 2 global Interrupt */ -#define DMA2_Channel3_IRQChannel ((u8)0x3A) /* DMA2 Channel 3 global Interrupt */ -#define DMA2_Channel4_5_IRQChannel ((u8)0x3B) /* DMA2 Channel 4 and DMA2 Channel 5 global Interrupt */ - - -#define IS_NVIC_IRQ_CHANNEL(CHANNEL) (((CHANNEL) == WWDG_IRQChannel) || \ - ((CHANNEL) == PVD_IRQChannel) || \ - ((CHANNEL) == TAMPER_IRQChannel) || \ - ((CHANNEL) == RTC_IRQChannel) || \ - ((CHANNEL) == FLASH_IRQChannel) || \ - ((CHANNEL) == RCC_IRQChannel) || \ - ((CHANNEL) == EXTI0_IRQChannel) || \ - ((CHANNEL) == EXTI1_IRQChannel) || \ - ((CHANNEL) == EXTI2_IRQChannel) || \ - ((CHANNEL) == EXTI3_IRQChannel) || \ - ((CHANNEL) == EXTI4_IRQChannel) || \ - ((CHANNEL) == DMA1_Channel1_IRQChannel) || \ - ((CHANNEL) == DMA1_Channel2_IRQChannel) || \ - ((CHANNEL) == DMA1_Channel3_IRQChannel) || \ - ((CHANNEL) == DMA1_Channel4_IRQChannel) || \ - ((CHANNEL) == DMA1_Channel5_IRQChannel) || \ - ((CHANNEL) == DMA1_Channel6_IRQChannel) || \ - ((CHANNEL) == DMA1_Channel7_IRQChannel) || \ - ((CHANNEL) == ADC1_2_IRQChannel) || \ - ((CHANNEL) == USB_HP_CAN_TX_IRQChannel) || \ - ((CHANNEL) == USB_LP_CAN_RX0_IRQChannel) || \ - ((CHANNEL) == CAN_RX1_IRQChannel) || \ - ((CHANNEL) == CAN_SCE_IRQChannel) || \ - ((CHANNEL) == EXTI9_5_IRQChannel) || \ - ((CHANNEL) == TIM1_BRK_IRQChannel) || \ - ((CHANNEL) == TIM1_UP_IRQChannel) || \ - ((CHANNEL) == TIM1_TRG_COM_IRQChannel) || \ - ((CHANNEL) == TIM1_CC_IRQChannel) || \ - ((CHANNEL) == TIM2_IRQChannel) || \ - ((CHANNEL) == TIM3_IRQChannel) || \ - ((CHANNEL) == TIM4_IRQChannel) || \ - ((CHANNEL) == I2C1_EV_IRQChannel) || \ - ((CHANNEL) == I2C1_ER_IRQChannel) || \ - ((CHANNEL) == I2C2_EV_IRQChannel) || \ - ((CHANNEL) == I2C2_ER_IRQChannel) || \ - ((CHANNEL) == SPI1_IRQChannel) || \ - ((CHANNEL) == SPI2_IRQChannel) || \ - ((CHANNEL) == USART1_IRQChannel) || \ - ((CHANNEL) == USART2_IRQChannel) || \ - ((CHANNEL) == USART3_IRQChannel) || \ - ((CHANNEL) == EXTI15_10_IRQChannel) || \ - ((CHANNEL) == RTCAlarm_IRQChannel) || \ - ((CHANNEL) == USBWakeUp_IRQChannel) || \ - ((CHANNEL) == TIM8_BRK_IRQChannel) || \ - ((CHANNEL) == TIM8_UP_IRQChannel) || \ - ((CHANNEL) == TIM8_TRG_COM_IRQChannel) || \ - ((CHANNEL) == TIM8_CC_IRQChannel) || \ - ((CHANNEL) == ADC3_IRQChannel) || \ - ((CHANNEL) == FSMC_IRQChannel) || \ - ((CHANNEL) == SDIO_IRQChannel) || \ - ((CHANNEL) == TIM5_IRQChannel) || \ - ((CHANNEL) == SPI3_IRQChannel) || \ - ((CHANNEL) == UART4_IRQChannel) || \ - ((CHANNEL) == UART5_IRQChannel) || \ - ((CHANNEL) == TIM6_IRQChannel) || \ - ((CHANNEL) == TIM7_IRQChannel) || \ - ((CHANNEL) == DMA2_Channel1_IRQChannel) || \ - ((CHANNEL) == DMA2_Channel2_IRQChannel) || \ - ((CHANNEL) == DMA2_Channel3_IRQChannel) || \ - ((CHANNEL) == DMA2_Channel4_5_IRQChannel)) - - -/* System Handlers -----------------------------------------------------------*/ -#define SystemHandler_NMI ((u32)0x00001F) /* NMI Handler */ -#define SystemHandler_HardFault ((u32)0x000000) /* Hard Fault Handler */ -#define SystemHandler_MemoryManage ((u32)0x043430) /* Memory Manage Handler */ -#define SystemHandler_BusFault ((u32)0x547931) /* Bus Fault Handler */ -#define SystemHandler_UsageFault ((u32)0x24C232) /* Usage Fault Handler */ -#define SystemHandler_SVCall ((u32)0x01FF40) /* SVCall Handler */ -#define SystemHandler_DebugMonitor ((u32)0x0A0080) /* Debug Monitor Handler */ -#define SystemHandler_PSV ((u32)0x02829C) /* PSV Handler */ -#define SystemHandler_SysTick ((u32)0x02C39A) /* SysTick Handler */ - -#define IS_CONFIG_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ - ((HANDLER) == SystemHandler_BusFault) || \ - ((HANDLER) == SystemHandler_UsageFault)) - -#define IS_PRIORITY_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ - ((HANDLER) == SystemHandler_BusFault) || \ - ((HANDLER) == SystemHandler_UsageFault) || \ - ((HANDLER) == SystemHandler_SVCall) || \ - ((HANDLER) == SystemHandler_DebugMonitor) || \ - ((HANDLER) == SystemHandler_PSV) || \ - ((HANDLER) == SystemHandler_SysTick)) - -#define IS_GET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ - ((HANDLER) == SystemHandler_BusFault) || \ - ((HANDLER) == SystemHandler_SVCall)) - -#define IS_SET_PENDING_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_NMI) || \ - ((HANDLER) == SystemHandler_PSV) || \ - ((HANDLER) == SystemHandler_SysTick)) - -#define IS_CLEAR_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_PSV) || \ - ((HANDLER) == SystemHandler_SysTick)) - -#define IS_GET_ACTIVE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ - ((HANDLER) == SystemHandler_BusFault) || \ - ((HANDLER) == SystemHandler_UsageFault) || \ - ((HANDLER) == SystemHandler_SVCall) || \ - ((HANDLER) == SystemHandler_DebugMonitor) || \ - ((HANDLER) == SystemHandler_PSV) || \ - ((HANDLER) == SystemHandler_SysTick)) - -#define IS_FAULT_SOURCE_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_HardFault) || \ - ((HANDLER) == SystemHandler_MemoryManage) || \ - ((HANDLER) == SystemHandler_BusFault) || \ - ((HANDLER) == SystemHandler_UsageFault) || \ - ((HANDLER) == SystemHandler_DebugMonitor)) - -#define IS_FAULT_ADDRESS_SYSTEM_HANDLER(HANDLER) (((HANDLER) == SystemHandler_MemoryManage) || \ - ((HANDLER) == SystemHandler_BusFault)) - - -/* Vector Table Base ---------------------------------------------------------*/ -#define NVIC_VectTab_RAM ((u32)0x20000000) -#define NVIC_VectTab_FLASH ((u32)0x08000000) - -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) - -/* System Low Power ----------------------------------------------------------*/ -#define NVIC_LP_SEVONPEND ((u8)0x10) -#define NVIC_LP_SLEEPDEEP ((u8)0x04) -#define NVIC_LP_SLEEPONEXIT ((u8)0x02) - -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) - -/* Preemption Priority Group -------------------------------------------------*/ -#define NVIC_PriorityGroup_0 ((u32)0x700) /* 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((u32)0x600) /* 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((u32)0x500) /* 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((u32)0x400) /* 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((u32)0x300) /* 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) -#define IS_NVIC_BASE_PRI(PRI) ((PRI) < 0x10) - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -void NVIC_DeInit(void); -void NVIC_SCBDeInit(void); -void NVIC_PriorityGroupConfig(u32 NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SETPRIMASK(void); -void NVIC_RESETPRIMASK(void); -void NVIC_SETFAULTMASK(void); -void NVIC_RESETFAULTMASK(void); -void NVIC_BASEPRICONFIG(u32 NewPriority); -u32 NVIC_GetBASEPRI(void); -u16 NVIC_GetCurrentPendingIRQChannel(void); -ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel); -void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel); -void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel); -u16 NVIC_GetCurrentActiveHandler(void); -ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel); -u32 NVIC_GetCPUID(void); -void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset); -void NVIC_GenerateSystemReset(void); -void NVIC_GenerateCoreReset(void); -void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState); -void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState); -void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority, - u8 SystemHandlerSubPriority); -ITStatus NVIC_GetSystemHandlerPendingBitStatus(u32 SystemHandler); -void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler); -void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler); -ITStatus NVIC_GetSystemHandlerActiveBitStatus(u32 SystemHandler); -u32 NVIC_GetFaultHandlerSources(u32 SystemHandler); -u32 NVIC_GetFaultAddress(u32 SystemHandler); - -#endif /* __STM32F10x_NVIC_H */ - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h deleted file mode 100644 index 1ca3e5261..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_type.h +++ /dev/null @@ -1,80 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : stm32f10x_type.h -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : This file contains all the common data types used for the -* STM32F10x firmware library. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_TYPE_H -#define __STM32F10x_TYPE_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef signed long const sc32; /* Read Only */ -typedef signed short const sc16; /* Read Only */ -typedef signed char const sc8; /* Read Only */ - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -typedef volatile signed long const vsc32; /* Read Only */ -typedef volatile signed short const vsc16; /* Read Only */ -typedef volatile signed char const vsc8; /* Read Only */ - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef unsigned long const uc32; /* Read Only */ -typedef unsigned short const uc16; /* Read Only */ -typedef unsigned char const uc8; /* Read Only */ - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile unsigned long const vuc32; /* Read Only */ -typedef volatile unsigned short const vuc16; /* Read Only */ -typedef volatile unsigned char const vuc8; /* Read Only */ - -typedef enum {FALSE = 0, TRUE = !FALSE} bool; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -#define U8_MAX ((u8)255) -#define S8_MAX ((s8)127) -#define S8_MIN ((s8)-128) -#define U16_MAX ((u16)65535u) -#define S16_MAX ((s16)32767) -#define S16_MIN ((s16)-32768) -#define U32_MAX ((u32)4294967295uL) -#define S32_MAX ((s32)2147483647) -#define S32_MIN ((s32)-2147483648) - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __STM32F10x_TYPE_H */ - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3 From 5ed3eb8eb99eecad0138843118e2e6d39a3189f8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 18 Jul 2009 12:19:47 +0000 Subject: Version numbers, doxygen files, and readme updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1066 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 4 +++- demos/ARMCM3-STM32F103-GCC/board.c | 11 +++++++---- demos/ARMCM3-STM32F103-GCC/board.h | 4 ++-- 3 files changed, 12 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index a6a0ecee5..fc36a80d2 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -61,7 +61,8 @@ include ../../test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ../../ports/ARMCM3/chcore.c \ +CSRC = ../../ports/ARMCM3/cmsis/core_cm3.c \ + ../../ports/ARMCM3/chcore.c \ ../../ports/ARMCM3/nvic.c \ ../../ports/ARMCM3-STM32F103/stm32_serial.c \ ../../ports/ARMCM3-STM32F103/pal_lld.c \ @@ -102,6 +103,7 @@ ASMSRC = ../../ports/ARMCM3/crt0.s \ INCDIR = $(KERNINC) $(TESTINC) \ ../../src/lib \ ../../ports/ARMCM3 \ + ../../ports/ARMCM3/cmsis \ ../../ports/ARMCM3-STM32F103 \ ./stm32lib/inc diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 25b88511f..6cdedea2e 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -24,6 +24,8 @@ #include "board.h" #include "stm32_serial.h" +#define AIRCR_VECTKEY 0x05FA0000 + /* * Digital I/O ports static configuration as defined in @p board.h. */ @@ -86,8 +88,9 @@ void hwinit1(void) { /* * NVIC/SCB initialization. + * Note: PRIGROUP 4:0 (4:4). */ - SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4). + SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1; NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL); NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK); NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV); @@ -95,9 +98,9 @@ void hwinit1(void) { /* * SysTick initialization. */ - ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1; - ST_CVR = 0; - ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS; + SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT; /* * Other subsystems initialization. diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index dcf8f8a33..c32b3d9da 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -24,10 +24,10 @@ * Tricks required to make the TRUE/FALSE declaration inside the library * compatible. */ -#ifndef __STM32F10x_MAP_H +#ifndef __STM32F10x_H #undef FALSE #undef TRUE -#include "stm32f10x_map.h" +#include #define FALSE 0 #define TRUE (!FALSE) #endif -- cgit v1.2.3 From 4849f800cf3ad6ba07ed785c5198d21917e63996 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 18 Jul 2009 12:55:22 +0000 Subject: Added ST firmware library files to the STM32 demo in order to make things easier to users. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1067 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 4 +- demos/ARMCM3-STM32F103-GCC/readme.txt | 5 +- demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h | 219 ++ .../stm32lib/inc/stm32f10x_adc.h | 479 ++++ .../stm32lib/inc/stm32f10x_bkp.h | 194 ++ .../stm32lib/inc/stm32f10x_can.h | 535 ++++ .../stm32lib/inc/stm32f10x_conf.h | 76 + .../stm32lib/inc/stm32f10x_crc.h | 93 + .../stm32lib/inc/stm32f10x_dac.h | 282 ++ .../stm32lib/inc/stm32f10x_dbgmcu.h | 109 + .../stm32lib/inc/stm32f10x_dma.h | 437 +++ .../stm32lib/inc/stm32f10x_exti.h | 183 ++ .../stm32lib/inc/stm32f10x_flash.h | 346 +++ .../stm32lib/inc/stm32f10x_fsmc.h | 716 +++++ .../stm32lib/inc/stm32f10x_gpio.h | 359 +++ .../stm32lib/inc/stm32f10x_i2c.h | 472 ++++ .../stm32lib/inc/stm32f10x_iwdg.h | 139 + .../stm32lib/inc/stm32f10x_pwr.h | 155 ++ .../stm32lib/inc/stm32f10x_rcc.h | 700 +++++ .../stm32lib/inc/stm32f10x_rtc.h | 134 + .../stm32lib/inc/stm32f10x_sdio.h | 530 ++++ .../stm32lib/inc/stm32f10x_spi.h | 490 ++++ .../stm32lib/inc/stm32f10x_tim.h | 1040 ++++++++ .../stm32lib/inc/stm32f10x_usart.h | 409 +++ .../stm32lib/inc/stm32f10x_wwdg.h | 114 + .../stm32lib/src/stm32f10x_adc.c | 1306 +++++++++ .../stm32lib/src/stm32f10x_bkp.c | 311 +++ .../stm32lib/src/stm32f10x_can.c | 990 +++++++ .../stm32lib/src/stm32f10x_crc.c | 163 ++ .../stm32lib/src/stm32f10x_dac.c | 431 +++ .../stm32lib/src/stm32f10x_dbgmcu.c | 152 ++ .../stm32lib/src/stm32f10x_dma.c | 693 +++++ .../stm32lib/src/stm32f10x_exti.c | 268 ++ .../stm32lib/src/stm32f10x_flash.c | 874 ++++++ .../stm32lib/src/stm32f10x_fsmc.c | 858 ++++++ .../stm32lib/src/stm32f10x_gpio.c | 617 +++++ .../stm32lib/src/stm32f10x_i2c.c | 1152 ++++++++ .../stm32lib/src/stm32f10x_iwdg.c | 189 ++ .../stm32lib/src/stm32f10x_pwr.c | 311 +++ .../stm32lib/src/stm32f10x_rcc.c | 1447 ++++++++++ .../stm32lib/src/stm32f10x_rtc.c | 341 +++ .../stm32lib/src/stm32f10x_sdio.c | 798 ++++++ .../stm32lib/src/stm32f10x_spi.c | 907 +++++++ .../stm32lib/src/stm32f10x_tim.c | 2799 ++++++++++++++++++++ .../stm32lib/src/stm32f10x_usart.c | 967 +++++++ .../stm32lib/src/stm32f10x_wwdg.c | 223 ++ demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk | 3 - 47 files changed, 24011 insertions(+), 9 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_flash.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_fsmc.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_gpio.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_i2c.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_iwdg.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_pwr.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rtc.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_sdio.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_spi.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_tim.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_usart.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_wwdg.h create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_adc.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_bkp.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_can.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_crc.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dac.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dbgmcu.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dma.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_exti.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_flash.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_fsmc.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_gpio.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_i2c.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_iwdg.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index fc36a80d2..3ffda1a1c 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -196,9 +196,7 @@ ULIBS = ifeq ($(USE_FWLIB),yes) include ./stm32lib/stm32lib.mk CSRC += ${STM32SRC} - # The thing generates a lot of aliasing warnings, this disables an - # optimization and the warning disappears, the code is a bit larger however. - USE_OPT += -fno-strict-aliasing + USE_OPT += -DUSE_STDPERIPH_DRIVER endif include ../../ports/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt index a3ca86747..ad3390656 100644 --- a/demos/ARMCM3-STM32F103-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -14,9 +14,8 @@ COM2 (USART2). ** Build Procedure ** -The demo was tested by using the free Codesourcery GCC-based toolchain (a -modified 4.2.3 GCC), YAGARTO 4.3.2 and an experimental WinARM build including -GCC 4.3.0. +The demo was tested by using the free Codesourcery GCC-based toolchain, +YAGARTO 4.3.2 and an experimental WinARM build including GCC 4.3.0. Just modify the TRGT line in the makefile in order to use different GCC ports. ** Notes ** diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h new file mode 100644 index 000000000..db6426244 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32f10x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h new file mode 100644 index 000000000..fd02a62cd --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h @@ -0,0 +1,479 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; +/** + * @} + */ + +/** @defgroup ADC_Exported_Constants + * @{ + */ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_mode + * @{ + */ + +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) +/** + * @} + */ + +/** @defgroup ADC_sampling_time + * @{ + */ + +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) +/** + * @} + */ + +/** @defgroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_offset + * @{ + */ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_length + * @{ + */ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @defgroup ADC_injected_rank + * @{ + */ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC_regular_rank + * @{ + */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h new file mode 100644 index 000000000..531d61f17 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the BKP firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @defgroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Constants + * @{ + */ + +/** @defgroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** + * @} + */ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin + * @{ + */ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** + * @} + */ + +/** @defgroup Data_Backup_Register + * @{ + */ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_BKP_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h new file mode 100644 index 000000000..712e34c00 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h @@ -0,0 +1,535 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter can be a value between 0 to 0xFF */ +} CanRxMsg; + +/** + * @} + */ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */ + +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#ifndef STM32F10X_CL + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#else + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ + +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ + +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ + +#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/** + * @} + */ + +/** @defgroup Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) + +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ + +#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ + +#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ + +#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\ + ((FLAG) == CAN_FLAG_BOF)) + +/** + * @} + */ + +/** @defgroup CAN_interrupts + * @{ + */ + +#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */ +#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */ +#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */ +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */ + +#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\ + ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions + * @{ + */ + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CAN_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h new file mode 100644 index 000000000..e7805cfd9 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file Project/Template/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief Library configuration file. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +/* #include "stm32f10x_adc.h" */ +/* #include "stm32f10x_bkp.h" */ +/* #include "stm32f10x_can.h" */ +/* #include "stm32f10x_crc.h" */ +/* #include "stm32f10x_dac.h" */ +/* #include "stm32f10x_dbgmcu.h" */ +/* #include "stm32f10x_dma.h" */ +#include "stm32f10x_exti.h" +/* #include "stm32f10x_flash.h" */ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_gpio.h" +/* #include "stm32f10x_i2c.h" */ +/* #include "stm32f10x_iwdg.h" */ +/* #include "stm32f10x_pwr.h" */ +#include "stm32f10x_rcc.h" +/* #include "stm32f10x_rtc.h" */ +/* #include "stm32f10x_sdio.h" */ +#include "stm32f10x_spi.h" +/* #include "stm32f10x_tim.h" */ +#include "stm32f10x_usart.h" +/* #include "stm32f10x_wwdg.h" */ +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h new file mode 100644 index 000000000..848c15ff2 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h new file mode 100644 index 000000000..6c4bc8003 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h @@ -0,0 +1,282 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in Connectivity line devices */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h new file mode 100644 index 000000000..0889683a5 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFC000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h new file mode 100644 index 000000000..9a1fe4b78 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); +void DMA_ClearFlag(uint32_t DMA_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMA_IT); +void DMA_ClearITPendingBit(uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DMA_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h new file mode 100644 index 000000000..8c011c1c8 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_flash.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_flash.h new file mode 100644 index 000000000..1c310231c --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_flash.h @@ -0,0 +1,346 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32 Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with STM32 Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ + +/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 Medium-density and Connectivity line devices: + Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG); +void FLASH_ClearFlag(uint16_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_fsmc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_fsmc.h new file mode 100644 index 000000000..1340e218a --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_fsmc.h @@ -0,0 +1,716 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don’t care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_gpio.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_gpio.h new file mode 100644 index 000000000..94f234d8d --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_gpio.h @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Remap_define + * @{ + */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ + ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS)) + +/** + * @} + */ + +/** @defgroup GPIO_Port_Sources + * @{ + */ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** + * @} + */ + +/** @defgroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ + ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) + +/** + * @} + */ +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_i2c.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_i2c.h new file mode 100644 index 000000000..4da8ed30b --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_i2c.h @@ -0,0 +1,472 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/** + * @brief EV1 + */ + +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief EV2 + */ + +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ + +/** + * @brief EV3 + */ + +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ + +/** + * @brief EV4 + */ + +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/** + * @brief EV5 + */ + +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief EV6 + */ + +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ + +/** + * @brief EV7 + */ + +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/** + * @brief EV8 + */ + +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ + +/** + * @brief EV8_2 + */ + +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + +/** + * @brief EV9 + */ + +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief EV3_2 + */ + +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_iwdg.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_iwdg.h new file mode 100644 index 000000000..d32fb0aae --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_iwdg.h @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @defgroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IWDG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_pwr.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_pwr.h new file mode 100644 index 000000000..e435ee3a6 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_pwr.h @@ -0,0 +1,155 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h new file mode 100644 index 000000000..c2a0339ca --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h @@ -0,0 +1,700 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the RCC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#ifndef STM32F10X_CL + #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) + #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +#else + #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup PLL_multiplication_factor + * @{ + */ +#ifndef STM32F10X_CL + #define RCC_PLLMul_2 ((uint32_t)0x00000000) + #define RCC_PLLMul_3 ((uint32_t)0x00040000) + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_10 ((uint32_t)0x00200000) + #define RCC_PLLMul_11 ((uint32_t)0x00240000) + #define RCC_PLLMul_12 ((uint32_t)0x00280000) + #define RCC_PLLMul_13 ((uint32_t)0x002C0000) + #define RCC_PLLMul_14 ((uint32_t)0x00300000) + #define RCC_PLLMul_15 ((uint32_t)0x00340000) + #define RCC_PLLMul_16 ((uint32_t)0x00380000) + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +#else + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) + + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_6_5)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup PREDIV1_division_factor + * @{ + */ + #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) + #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) + #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) + #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) + #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) + #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) + #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) + #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) + #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) + #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) + #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) + #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) + #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) + #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) + #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + + #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +/** + * @} + */ + + +/** @defgroup PREDIV1_clock_source + * @{ + */ +/* PREDIV1 clock source (only for STM32 connectivity line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ + ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +/** + * @} + */ + + +/** @defgroup PREDIV2_division_factor + * @{ + */ + + #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) + #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) + #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) + #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) + #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) + #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) + #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) + #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) + #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) + #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) + #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) + #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) + #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) + #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) + #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + + #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ + ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ + ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ + ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ + ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ + ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ + ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ + ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) +/** + * @} + */ + + +/** @defgroup PLL2_multiplication_factor + * @{ + */ + + #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) + #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) + #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) + #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) + #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) + #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) + #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) + #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) + #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + + #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ + ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ + ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ + ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ + ((MUL) == RCC_PLL2Mul_20)) +/** + * @} + */ + + +/** @defgroup PLL3_multiplication_factor + * @{ + */ + + #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) + #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) + #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) + #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) + #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) + #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) + #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) + #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) + #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + + #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ + ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ + ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ + ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ + ((MUL) == RCC_PLL3Mul_20)) +/** + * @} + */ + +#endif /* STM32F10X_CL */ + + +/** @defgroup System_clock_source + * @{ + */ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifndef STM32F10X_CL + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +#else + #define RCC_IT_PLL2RDY ((uint8_t)0x20) + #define RCC_IT_PLL3RDY ((uint8_t)0x40) + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) + #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) +#endif /* STM32F10X_CL */ + + +/** + * @} + */ + +#ifndef STM32F10X_CL +/** @defgroup USB_Device_clock_source + * @{ + */ + + #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) + #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +#else +/** @defgroup USB_OTG_FS_clock_source + * @{ + */ + #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) + #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) + + #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ + ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup I2S2_clock_source + * @{ + */ + #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) +/** + * @} + */ + +/** @defgroup I2S3_clock_source + * @{ + */ + #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +/** @defgroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** + * @} + */ + +/** @defgroup LSE_configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** + * @} + */ + +/** @defgroup AHB_peripheral + * @{ + */ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) + +#ifndef STM32F10X_CL + #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +#else + #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) + #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) + #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) + #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup APB2_peripheral + * @{ + */ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_peripheral + * @{ + */ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifndef STM32F10X_CL + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) +#else + #define RCC_MCO_PLL2CLK ((uint8_t)0x08) + #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) + #define RCC_MCO_XT1 ((uint8_t)0x0A) + #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ + ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ + ((MCO) == RCC_MCO_PLL3CLK)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifndef STM32F10X_CL + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#else + #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) + #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#endif /* STM32F10X_CL */ + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); + +#ifdef STM32F10X_CL + void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); + void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); + void RCC_PLL2Config(uint32_t RCC_PLL2Mul); + void RCC_PLL2Cmd(FunctionalState NewState); + void RCC_PLL3Config(uint32_t RCC_PLL3Mul); + void RCC_PLL3Cmd(FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); + +#ifndef STM32F10X_CL + void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +#else + void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +#endif /* STM32F10X_CL */ + +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); + +#ifdef STM32F10X_CL + void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); + void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +#endif /* STM32F10X_CL */ + +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +#ifdef STM32F10X_CL +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rtc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rtc.h new file mode 100644 index 000000000..8e40d0291 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rtc.h @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + +/** @defgroup RTC_interrupts_define + * @{ + */ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** + * @} + */ + +/** @defgroup RTC_interrupts_flags + * @{ + */ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions + * @{ + */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RTC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_sdio.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_sdio.h new file mode 100644 index 000000000..4c7a04a43 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_sdio.h @@ -0,0 +1,530 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_soucres + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_spi.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_spi.h new file mode 100644 index 000000000..8c006b8e2 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_spi.h @@ -0,0 +1,490 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be any combination of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be any combination of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be any combination of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be any combination of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be any combination of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be any combination of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be any combination of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be any combination of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be any combination of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be any combination of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be any combination of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be any combination of @ref I2S_MCLK_Output */ + + uint16_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be any combination of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be any combination of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_96k ((uint16_t)96000) +#define I2S_AudioFreq_48k ((uint16_t)48000) +#define I2S_AudioFreq_44k ((uint16_t)44100) +#define I2S_AudioFreq_32k ((uint16_t)32000) +#define I2S_AudioFreq_22k ((uint16_t)22050) +#define I2S_AudioFreq_16k ((uint16_t)16000) +#define I2S_AudioFreq_11k ((uint16_t)11025) +#define I2S_AudioFreq_8k ((uint16_t)8000) +#define I2S_AudioFreq_Default ((uint16_t)2) +#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \ + ((FREQ) == I2S_AudioFreq_48k) || \ + ((FREQ) == I2S_AudioFreq_44k) || \ + ((FREQ) == I2S_AudioFreq_32k) || \ + ((FREQ) == I2S_AudioFreq_22k) || \ + ((FREQ) == I2S_AudioFreq_16k) || \ + ((FREQ) == I2S_AudioFreq_11k) || \ + ((FREQ) == I2S_AudioFreq_8k) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_mangement + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_tim.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_tim.h new file mode 100644 index 000000000..323169bde --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_tim.h @@ -0,0 +1,1040 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @defgroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This sturcture is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8)) + +#define IS_TIM_18_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +#define IS_TIM_123458_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ + ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_18Bytes)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_TIM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_usart.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_usart.h new file mode 100644 index 000000000..976a06c62 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_usart.h @@ -0,0 +1,409 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/** + * @} + */ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4)) +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ + ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTS)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_USART_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_wwdg.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_wwdg.h new file mode 100644 index 000000000..39dc8e9a3 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_wwdg.h @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @defgroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_adc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_adc.c new file mode 100644 index 000000000..882455d4e --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_adc.c @@ -0,0 +1,1306 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the ADC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((uint32_t)0x00000800) +#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((uint32_t)0x00000001) +#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((uint32_t)0x00000100) +#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((uint32_t)0x0000001F) +#define SQR2_SQ_Set ((uint32_t)0x0000001F) +#define SQR1_SQ_Set ((uint32_t)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((uint32_t)0x00300000) +#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((uint32_t)0x00000007) +#define SMPR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((uint8_t)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } + else + { + if (ADCx == ADC3) + { + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. + * Note: ADC2 hasn't a DMA capability. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Resets the selected ADC calibration registers. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Resets the selected ADC calibartion registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/** + * @brief Gets the selected ADC reset calibration registers status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC reset calibration registers (SET or RESET). + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * @retval The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) DR_ADDRESS); +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_Offset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param NewState: new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx’s interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_bkp.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_bkp.c new file mode 100644 index 000000000..e4653a795 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_bkp.c @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the BKP firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @defgroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_Mask ((uint16_t)0xFF80) +#define RTCCR_Mask ((uint16_t)0xFC7F) + +/* CSR register bit mask */ +#define CSR_CTE_Set ((uint16_t)0x0001) +#define CSR_CTI_Set ((uint16_t)0x0002) + +/** + * @} + */ + + +/** @defgroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TamperPinLevel_High: Tamper pin active on high level + * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level + * @retval None + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param NewState: new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param NewState: new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** + * @brief Select the RTC output source to output on the Tamper pin. + * @param BKP_RTCOutputSource: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. + * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency + * divided by 64 on the Tamper pin. + * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on + * the Tamper pin. + * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on + * the Tamper pin. + * @retval None + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_Mask; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Sets RTC Clock Calibration value. + * @param CalibrationValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_Mask; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @param Data: data to write + * @retval None + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @retval The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @param None + * @retval The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + * @param None + * @retval None + */ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= CSR_CTE_Set; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @param None + * @retval The new state of the Tamper Pin Interrupt (SET or RESET). + */ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + * @param None + * @retval None + */ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= CSR_CTI_Set; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_can.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_can.c new file mode 100644 index 000000000..d459a1066 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_can.c @@ -0,0 +1,990 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the CAN firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @defgroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ +#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */ +#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */ +#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */ +#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */ +#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */ +#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */ +#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */ +#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */ +#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */ +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Master Status Register bits */ +#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */ +#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */ +#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */ + +/* CAN Transmit Status Register bits */ +#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */ +#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */ +#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */ +#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */ +#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */ +#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */ +#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */ +#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */ +#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */ +#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */ +#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */ +#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */ + +/* CAN Receive FIFO 0 Register bits */ +#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */ +#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */ +#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */ + +/* CAN Receive FIFO 1 Register bits */ +#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */ +#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */ +#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */ + +/* CAN Error Status Register bits */ +#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */ +#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */ +#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TimeOut ((uint32_t)0x0000FFFF) + +/* Time out for SLAK bit */ +#define SLAK_TimeOut ((uint32_t)0x0000FFFF) + +/** + * @} + */ + +/** @defgroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_FunctionPrototypes + * @{ + */ + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CANINITFAILED or CANINITOK. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CANINITFAILED; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* exit from sleep mode */ + CANx->MCR &= ~MCR_SLEEP; + + /* Request initialisation */ + CANx->MCR |= MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & MSR_INAK) != MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= MCR_TTCM; + } + else + { + CANx->MCR &= ~MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= MCR_ABOM; + } + else + { + CANx->MCR &= ~MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= MCR_AWUM; + } + else + { + CANx->MCR &= ~MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= MCR_NART; + } + else + { + CANx->MCR &= ~MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= MCR_RFLM; + } + else + { + CANx->MCR &= ~MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= MCR_TXFP; + } + else + { + CANx->MCR &= ~MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0x00; + + while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & MSR_INAK) == MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + InitStatus = CANINITOK ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * @retval None. + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which + * will be initialized. + * @retval None. + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @note This function applies only to STM32 Connectivity line devices. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None. + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + /* enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the specified CAN interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0, + * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1, + * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, + * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or + * CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITConfig(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CANx->IER &= ~CAN_IT; + } +} + +/** + * @brief Initiates the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN + * DLC and CAN datas. + * @retval The number of the mailbox that is used for transmission + * or CAN_NO_MB if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&TSR_TME0) == TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&TSR_TME1) == TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&TSR_TME2) == TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_NO_MB; + } + + if (transmit_mailbox != CAN_NO_MB) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | + TxMessage->RTR); + } + + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + /* RQCP, TXOK and TME bits */ + uint8_t state = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + switch (TransmitMailbox) + { + case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2); + state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0); + state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26); + break; + case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6); + state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8); + state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27); + break; + case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14); + state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16); + state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28); + break; + default: + state = CANTXFAILED; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CANTXPENDING; + break; + /* transmit failed */ + case (0x5): state = CANTXFAILED; + break; + /* transmit succedeed */ + case (0x7): state = CANTXOK; + break; + default: + state = CANTXFAILED; + break; + } + return state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None. + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (0): CANx->TSR |= TSR_ABRQ0; + break; + case (1): CANx->TSR |= TSR_ABRQ1; + break; + case (2): CANx->TSR |= TSR_ABRQ2; + break; + default: + break; + } +} + +/** + * @brief Releases a FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None. + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R = RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R = RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which + * contains CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_ID_STD) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + CAN_FIFORelease(CANx, FIFONumber); +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + +/** + * @brief Enters the low power mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CANSLEEPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CANSLEEPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TimeOut ; + uint8_t wakeupstatus = CANWAKEUPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* Sleep mode exited */ + wakeupstatus = CANWAKEUPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF. + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FLAG(CAN_FLAG)); + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * @retval None. + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FLAG(CAN_FLAG)); + /* Clear the selected CAN flags */ + CANx->ESR &= ~CAN_FLAG; +} + +/** + * @brief Checks whether the specified CAN interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2, + * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1, + * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, + * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK. + * @retval The new state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus pendingbitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITStatus(CAN_IT)); + switch (CAN_IT) + { + case CAN_IT_RQCP0: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0); + break; + case CAN_IT_RQCP1: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1); + break; + case CAN_IT_RQCP2: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2); + break; + case CAN_IT_FF0: + pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0); + break; + case CAN_IT_FOV0: + pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0); + break; + case CAN_IT_FF1: + pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1); + break; + case CAN_IT_FOV1: + pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1); + break; + case CAN_IT_EWG: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF); + break; + case CAN_IT_EPV: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF); + break; + case CAN_IT_BOF: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF); + break; + case CAN_IT_SLK: + pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI); + break; + case CAN_IT_WKU: + pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI); + break; + default : + pendingbitstatus = RESET; + break; + } + /* Return the CAN_IT status */ + return pendingbitstatus; +} + +/** + * @brief Clears the CAN’s interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * @retval None. + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITStatus(CAN_IT)); + switch (CAN_IT) + { + case CAN_IT_RQCP0: + CANx->TSR = TSR_RQCP0; /* rc_w1*/ + break; + case CAN_IT_RQCP1: + CANx->TSR = TSR_RQCP1; /* rc_w1*/ + break; + case CAN_IT_RQCP2: + CANx->TSR = TSR_RQCP2; /* rc_w1*/ + break; + case CAN_IT_FF0: + CANx->RF0R = RF0R_FULL0; /* rc_w1*/ + break; + case CAN_IT_FOV0: + CANx->RF0R = RF0R_FOVR0; /* rc_w1*/ + break; + case CAN_IT_FF1: + CANx->RF1R = RF1R_FULL1; /* rc_w1*/ + break; + case CAN_IT_FOV1: + CANx->RF1R = RF1R_FOVR1; /* rc_w1*/ + break; + case CAN_IT_EWG: + CANx->ESR &= ~ ESR_EWGF; /* rw */ + break; + case CAN_IT_EPV: + CANx->ESR &= ~ ESR_EPVF; /* rw */ + break; + case CAN_IT_BOF: + CANx->ESR &= ~ ESR_BOFF; /* rw */ + break; + case CAN_IT_WKU: + CANx->MSR = MSR_WKUI; /* rc_w1*/ + break; + case CAN_IT_SLK: + CANx->MSR = MSR_SLAKI; /* rc_w1*/ + break; + default : + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_crc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_crc.c new file mode 100644 index 000000000..ba665c9aa --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_crc.c @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/* CR register bit mask */ + +#define CR_RESET_Set ((uint32_t)0x00000001) + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CR_RESET_Set; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dac.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dac.c new file mode 100644 index 000000000..84f5d10d6 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dac.c @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* DAC EN mask */ +#define CR_EN_Set ((uint32_t)0x00000001) + +/* DAC DMAEN mask */ +#define CR_DMAEN_Set ((uint32_t)0x00001000) + +/* CR register Mask */ +#define CR_CLEAR_Mask ((uint32_t)0x00000FFE) + +/* DAC SWTRIG mask */ +#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_Set ((uint32_t)0x00000003) +#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_Offset ((uint32_t)0x00000008) +#define DHR12R2_Offset ((uint32_t)0x00000014) +#define DHR12RD_Offset ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_Offset ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave genration, + mask/amplitude for wave genration */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= CR_EN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(CR_EN_Set << DAC_Channel); + } +} + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= CR_DMAEN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_Set ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignement for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_Offset + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignement for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_Offset + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignement for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_Offset + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC cahnnel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dbgmcu.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dbgmcu.c new file mode 100644 index 000000000..7deea2caa --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dbgmcu.c @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dma.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dma.c new file mode 100644 index 000000000..147a88888 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dma.c @@ -0,0 +1,693 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((uint32_t)0x00000001) +#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) +#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000) +#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Calculate the used DMA */ + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + /* Calculate the used DMA */ + + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA flags */ + DMA2->IFCR = DMA_FLAG; + } + else + { + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA interrupt */ + if ((tmpreg & DMA_IT) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx’s interrupt pending bits. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA interrupt pending bits */ + DMA2->IFCR = DMA_IT; + } + else + { + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_exti.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_exti.c new file mode 100644 index 000000000..cc4ab9965 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_exti.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI’s line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI’s line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_flash.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_flash.c new file mode 100644 index 000000000..22ee18000 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_flash.c @@ -0,0 +1,874 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x00000FFF) +#define ProgramTimeout ((uint32_t)0x0000000F) + +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +static void delay(void); +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/** + * @brief Locks the FLASH Program Erase Controller. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the FCR */ + FLASH->CR |= CR_LOCK_Set; +} + +/** + * @brief Erases a specified FLASH page. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases the FLASH option bytes. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Enable the readout access */ + OB->RDP= RDP_Key; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @param FLASH_Pages: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 + * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 + * and FLASH_WRProt_Pages124to127 + * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 + * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 + * @arg FLASH_WRProt_AllPages + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @param None + * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @param None + * @retval The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Falsh write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH’s pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval None + */ +void FLASH_ClearFlag(uint16_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +} + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetStatus(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + delay(); + status = FLASH_GetStatus(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Inserts a time delay. + * @param None + * @retval None + */ +static void delay(void) +{ + __IO uint32_t i = 0; + for(i = 0xFF; i != 0; i--) + { + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_fsmc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_fsmc.c new file mode 100644 index 000000000..32ebf402e --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_fsmc.c @@ -0,0 +1,858 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for the FSMC PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC’s pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC’s interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_gpio.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_gpio.c new file mode 100644 index 000000000..fd951a3cf --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_gpio.c @@ -0,0 +1,617 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +/* --- MAPR Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * @param None + * @retval None + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param GPIO_PortSource: selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param GPIO_PinSource: specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** + * @brief Enables or disables the Event Output. + * @param NewState: new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIO_Remap: selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_Remap_SPI1 + * @arg GPIO_Remap_I2C1 + * @arg GPIO_Remap_USART1 + * @arg GPIO_Remap_USART2 + * @arg GPIO_PartialRemap_USART3 + * @arg GPIO_FullRemap_USART3 + * @arg GPIO_PartialRemap_TIM1 + * @arg GPIO_FullRemap_TIM1 + * @arg GPIO_PartialRemap1_TIM2 + * @arg GPIO_PartialRemap2_TIM2 + * @arg GPIO_FullRemap_TIM2 + * @arg GPIO_PartialRemap_TIM3 + * @arg GPIO_FullRemap_TIM3 + * @arg GPIO_Remap_TIM4 + * @arg GPIO_Remap1_CAN1 + * @arg GPIO_Remap2_CAN1 + * @arg GPIO_Remap_PD01 + * @arg GPIO_Remap_TIM5CH4_LSI + * @arg GPIO_Remap_ADC1_ETRGINJ + * @arg GPIO_Remap_ADC1_ETRGREG + * @arg GPIO_Remap_ADC2_ETRGINJ + * @arg GPIO_Remap_ADC2_ETRGREG + * @arg GPIO_Remap_ETH + * @arg GPIO_Remap_CAN2 + * @arg GPIO_Remap_SWJ_NoJTRST + * @arg GPIO_Remap_SWJ_JTAGDisable + * @arg GPIO_Remap_SWJ_Disable + * @arg GPIO_Remap_SPI3 + * @arg GPIO_Remap_TIM2ITR1_PTP_SOF + * @arg GPIO_Remap_PTP_PPS + * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected + * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. + * @param NewState: new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + tmpreg = AFIO->MAPR; + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); + } + + AFIO->MAPR = tmpreg; +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param GPIO_PinSource: specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to STM32 Connectivity line devices. + * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MediaInterface_MII: MII mode + * @arg GPIO_ETH_MediaInterface_RMII: RMII mode + * @retval None + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); + + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_i2c.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_i2c.c new file mode 100644 index 000000000..bed0e9d0f --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_i2c.c @@ -0,0 +1,1152 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the I2C firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CR1_PE_Set ((uint16_t)0x0001) +#define CR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((uint16_t)0x0100) +#define CR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((uint16_t)0x0200) +#define CR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((uint16_t)0x0400) +#define CR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((uint16_t)0x0040) +#define CR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((uint16_t)0x1000) +#define CR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((uint16_t)0x0020) +#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((uint16_t)0x0010) +#define CR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((uint16_t)0x0800) +#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((uint16_t)0x1000) +#define CR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((uint16_t)0x0001) +#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((uint16_t)0x0001) +#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | CCR_FS_Set); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/** + * @brief Specifies that the next DMA transfer is the last one. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transfered bytes. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + /* Return status */ + return lastevent; +} + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @retval An ErrorStatus enumuration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + /* Check whether the last event is equal to I2C_EVENT */ + if (lastevent == I2C_EVENT ) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL” + * Address matched flag (Slave mode)”ENDAD” + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) “ADSL” + * Address matched flag (Slave mode)”ENDAD” + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx’s interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_iwdg.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_iwdg.c new file mode 100644 index 000000000..7d6fe8235 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_iwdg.c @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the IWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @defgroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @defgroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c new file mode 100644 index 000000000..fbafe42a2 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_PDDS_Set ((uint32_t)0x00000002) +#define CR_DS_Mask ((uint32_t)0xFFFFFFFC) +#define CR_CWUF_Set ((uint32_t)0x00000004) +#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F) + +/* --------- Cortex System Control register bit mask ---------------- */ + +/* Cortex System Control register address */ +#define SCB_SysCtrl ((uint32_t)0xE000ED10) + +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V + * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V + * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V + * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V + * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_Mask; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enters STANDBY mode. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c new file mode 100644 index 000000000..d506eb9fb --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c @@ -0,0 +1,1447 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +#ifdef STM32F10X_CL + /* Alias word address of PLL2ON bit */ + #define PLL2ON_BitNumber 0x1A + #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) + + /* Alias word address of PLL3ON bit */ + #define PLL3ON_BitNumber 0x1C + #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) + +#ifndef STM32F10X_CL + #define USBPRE_BitNumber 0x16 + #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) +#else + #define OTGFSPRE_BitNumber 0x16 + #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +#ifdef STM32F10X_CL +/* --- CFGR2 Register ---*/ + + /* Alias word address of I2S2SRC bit */ + #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) + #define I2S2SRC_BitNumber 0x11 + #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) + + /* Alias word address of I2S3SRC bit */ + #define I2S3SRC_BitNumber 0x12 + #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#ifndef STM32F10X_CL + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#else + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) +#endif /* STM32F10X_CL */ + +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +#ifdef STM32F10X_CL +/* CFGR2 register bit mask */ + #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) + #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) + #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) + #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) + #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) +#endif /* STM32F10X_CL */ + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +#ifndef HSI_Value +/* Typical Value of the HSI in Hz */ + #define HSI_Value ((uint32_t)8000000) +#endif /* HSI_Value */ + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +#ifndef HSEStartUp_TimeOut +/* Time out for HSE start up */ + #define HSEStartUp_TimeOut ((uint16_t)0x0500) +#endif /* HSEStartUp_TimeOut */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifndef STM32F10X_CL + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#else + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#endif /* STM32F10X_CL */ +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} + * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the PREDIV1 division factor. + * @note + * - This function must be used only when the PLL is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock + * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + /* Set the PREDIV1 clock source and division factor */ + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Configures the PREDIV2 division factor. + * @note + * - This function must be used only when both PLL2 and PLL3 are disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV2[3:0] bits */ + tmpreg &= ~CFGR2_PREDIV2; + /* Set the PREDIV2 division factor */ + tmpreg |= RCC_PREDIV2_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Configures the PLL2 multiplication factor. + * @note + * - This function must be used only when the PLL2 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL2Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL2MUL; + /* Set the PLL2 configuration bits */ + tmpreg |= RCC_PLL2Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL2. + * @note + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * - This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; +} + + +/** + * @brief Configures the PLL3 multiplication factor. + * @note + * - This function must be used only when the PLL3 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL3Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL3MUL; + /* Set the PLL3 configuration bits */ + tmpreg |= RCC_PLL3Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL3. + * @note This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +#ifndef STM32F10X_CL +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source + * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} +#else +/** + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * This function applies only to STM32 Connectivity line devices. + * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. + * This clock is derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @retval None + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); + + *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * This parameter can be one of the following values: + * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 + * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 + * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 + * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the I2S2 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S2 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry + * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry + * @retval None + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; +} + +/** + * @brief Configures the I2S3 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S3 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry + * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry + * @retval None + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can’t be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + {/* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; + } + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; + RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @arg RCC_AHBPeriph_ETH_MAC_Tx + * @arg RCC_AHBPeriph_ETH_MAC_Rx + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FSMC + * @arg RCC_AHBPeriph_SDIO + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +#ifdef STM32F10X_CL +/** + * @brief Forces or releases AHB peripheral reset. + * @note This function applies only to STM32 Connectivity line devices. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} +#endif /* STM32F10X_CL */ + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO: specifies the clock source to output. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * @arg RCC_MCO_PLL2CLK: PLL2 clock selected + * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected + * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected + * @arg RCC_MCO_PLL3CLK: PLL3 clock selected + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC’s interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c new file mode 100644 index 000000000..0118b7a0d --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c @@ -0,0 +1,341 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the RTC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup RTC_Private_Defines + * @{ + */ + +#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */ +#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */ +#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** + * @brief Enters the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= CRL_CNF_Set; +} + +/** + * @brief Exits from the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= CRL_CNF_Reset; +} + +/** + * @brief Gets the RTC counter value. + * @param None + * @retval RTC counter value. + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t tmp = 0; + tmp = RTC->CNTL; + return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; +} + +/** + * @brief Sets the RTC counter value. + * @param CounterValue: RTC counter new value. + * @retval None + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC prescaler value. + * @param PrescalerValue: RTC prescaler new value. + * @retval None + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC alarm value. + * @param AlarmValue: RTC alarm new value. + * @retval None + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Gets the RTC divider value. + * @param None + * @retval RTC Divider value. + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** + * @brief Waits until last write operation on RTC registers has finished. + * @note This function must be called before any write to RTC registers. + * @param None + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param None + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one the following values: + * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC’s pending flags. + * @param RTC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after + * an APB reset or an APB Clock stop. + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval None + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the coressponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occured or not. + * @param RTC_IT: specifies the RTC interrupts sources to check. + * This parameter can be one of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval The new state of the RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC’s interrupt pending bits. + * @param RTC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c new file mode 100644 index 000000000..c4b32a1af --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c @@ -0,0 +1,798 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parametre can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO’s interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c new file mode 100644 index 000000000..8f67f240a --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c @@ -0,0 +1,907 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((u32)(0x00020000)) +#define I2S3_CLOCK_SRC ((u32)(0x00040000)) +#define I2S_MUL_MASK ((u32)(0x0000F000)) +#define I2S_DIV_MASK ((u32)(0x000000F0)) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if(((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLOCK_SRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLOCK_SRC; + } + + /* Check the I2S clock source configuration depending on the Device: + Only Connectivity line devices have the PLL3 VCO clock */ +#ifdef STM32F10X_CL + if((RCC->CFGR2 & tmp) != 0) + { + /* Get the configuration bits of RCC PLL3 multiplier */ + tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); + + /* Get the value of the PLL3 multiplier */ + if((tmp > 5) && (tmp < 15)) + { + /* Multplier is between 8 and 14 (value 15 is forbidden) */ + tmp += 2; + } + else + { + if (tmp == 15) + { + /* Multiplier is 20 */ + tmp = 20; + } + } + /* Get the PREDIV2 value */ + sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); + + /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ + sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); + } + else + { + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + } +#else /* STM32F10X_HD */ + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; +#endif /* STM32F10X_CL */ + + /* Compute the Real divider depending on the MCLK output state with a flaoting point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flaoting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (u16)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data : Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the transfered bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR intetrrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c new file mode 100644 index 000000000..55b417b97 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c @@ -0,0 +1,2799 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the TIM firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @defgroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define CR1_CEN_Set ((uint16_t)0x0001) +#define CR1_CEN_Reset ((uint16_t)0x03FE) +#define CR1_UDIS_Set ((uint16_t)0x0002) +#define CR1_UDIS_Reset ((uint16_t)0x03FD) +#define CR1_URS_Set ((uint16_t)0x0004) +#define CR1_URS_Reset ((uint16_t)0x03FB) +#define CR1_OPM_Reset ((uint16_t)0x03F7) +#define CR1_CounterMode_Mask ((uint16_t)0x038F) +#define CR1_ARPE_Set ((uint16_t)0x0080) +#define CR1_ARPE_Reset ((uint16_t)0x037F) +#define CR1_CKD_Mask ((uint16_t)0x00FF) +#define CR2_CCPC_Set ((uint16_t)0x0001) +#define CR2_CCPC_Reset ((uint16_t)0xFFFE) +#define CR2_CCUS_Set ((uint16_t)0x0004) +#define CR2_CCUS_Reset ((uint16_t)0xFFFB) +#define CR2_CCDS_Set ((uint16_t)0x0008) +#define CR2_CCDS_Reset ((uint16_t)0xFFF7) +#define CR2_MMS_Mask ((uint16_t)0xFF8F) +#define CR2_TI1S_Set ((uint16_t)0x0080) +#define CR2_TI1S_Reset ((uint16_t)0xFF7F) +#define CR2_OIS1_Reset ((uint16_t)0x7EFF) +#define CR2_OIS1N_Reset ((uint16_t)0x7DFF) +#define CR2_OIS2_Reset ((uint16_t)0x7BFF) +#define CR2_OIS2N_Reset ((uint16_t)0x77FF) +#define CR2_OIS3_Reset ((uint16_t)0x6FFF) +#define CR2_OIS3N_Reset ((uint16_t)0x5FFF) +#define CR2_OIS4_Reset ((uint16_t)0x3FFF) +#define SMCR_SMS_Mask ((uint16_t)0xFFF8) +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define SMCR_TS_Mask ((uint16_t)0xFF8F) +#define SMCR_MSM_Reset ((uint16_t)0xFF7F) +#define SMCR_ECE_Set ((uint16_t)0x4000) +#define CCMR_CC13S_Mask ((uint16_t)0xFFFC) +#define CCMR_CC24S_Mask ((uint16_t)0xFCFF) +#define CCMR_TI13Direct_Set ((uint16_t)0x0001) +#define CCMR_TI24Direct_Set ((uint16_t)0x0100) +#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB) +#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF) +#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7) +#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF) +#define CCMR_OC13M_Mask ((uint16_t)0xFF8F) +#define CCMR_OC24M_Mask ((uint16_t)0x8FFF) +#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F) +#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF) +#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3) +#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF) +#define CCMR_IC13F_Mask ((uint16_t)0xFF0F) +#define CCMR_IC24F_Mask ((uint16_t)0x0FFF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) +#define CCER_CC1P_Reset ((uint16_t)0xFFFD) +#define CCER_CC2P_Reset ((uint16_t)0xFFDF) +#define CCER_CC3P_Reset ((uint16_t)0xFDFF) +#define CCER_CC4P_Reset ((uint16_t)0xDFFF) +#define CCER_CC1NP_Reset ((uint16_t)0xFFF7) +#define CCER_CC2NP_Reset ((uint16_t)0xFF7F) +#define CCER_CC3NP_Reset ((uint16_t)0xF7FF) +#define CCER_CC1E_Set ((uint16_t)0x0001) +#define CCER_CC1E_Reset ((uint16_t)0xFFFE) +#define CCER_CC1NE_Reset ((uint16_t)0xFFFB) +#define CCER_CC2E_Set ((uint16_t)0x0010) +#define CCER_CC2E_Reset ((uint16_t)0xFFEF) +#define CCER_CC2NE_Reset ((uint16_t)0xFFBF) +#define CCER_CC3E_Set ((uint16_t)0x0100) +#define CCER_CC3E_Reset ((uint16_t)0xFEFF) +#define CCER_CC3NE_Reset ((uint16_t)0xFBFF) +#define CCER_CC4E_Set ((uint16_t)0x1000) +#define CCER_CC4E_Reset ((uint16_t)0xEFFF) +#define BDTR_MOE_Set ((uint16_t)0x8000) +#define BDTR_MOE_Reset ((uint16_t)0x7FFF) +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @retval None + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else + { + if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + /* Select the Counter Mode and set the clock division */ + TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; + TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision | + TIM_TimeBaseInitStruct->TIM_CounterMode; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler value immediatly */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= CCER_CC1E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC13M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC1P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC1NP_Reset; + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + /* Reset the Output N State */ + tmpccer &= CCER_CC1NE_Reset; + + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS1_Reset; + tmpcr2 &= CR2_OIS1N_Reset; + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC2E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC24M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC2P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC2NP_Reset; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + /* Reset the Output N State */ + tmpccer &= CCER_CC2NE_Reset; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS2_Reset; + tmpcr2 &= CR2_OIS2N_Reset; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC3E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC13M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC3P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= CCER_CC3NP_Reset; + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= CCER_CC3NE_Reset; + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= CR2_OIS3_Reset; + tmpcr2 &= CR2_OIS3N_Reset; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= CCER_CC4E_Reset; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= CCMR_OC24M_Mask; + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= CCER_CC4P_Reset; + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= CR2_OIS4_Reset; + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= CR1_CEN_Set; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= CR1_CEN_Reset; + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= BDTR_MOE_Set; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= BDTR_MOE_Reset; + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Configures the TIMx’s DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx’s DMA Requests. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx interrnal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= SMCR_SMS_Mask; +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @param TIM_TS_ITR0: Internal Trigger 0 + * @param TIM_TS_ITR1: Internal Trigger 1 + * @param TIM_TS_ITR2: Internal Trigger 2 + * @param TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= SMCR_SMS_Mask; + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= SMCR_TS_Mask; + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= SMCR_ECE_Set; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= CR1_CounterMode_Mask; + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= SMCR_TS_Mask; + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= SMCR_SMS_Mask; + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; + tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset; + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= CCMR_OC13M_Mask; + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= CCMR_OC24M_Mask; + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= CCMR_OC13M_Mask; + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= CCMR_OC24M_Mask; + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= CR1_ARPE_Set; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= CR1_ARPE_Reset; + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= CR2_CCUS_Set; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= CR2_CCUS_Reset; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= CR2_CCDS_Set; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= CR2_CCDS_Reset; + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= CR2_CCPC_Set; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= CR2_CCPC_Reset; + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= CCMR_OC13PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= CCMR_OC24PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= CCMR_OC13PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= CCMR_OC24PE_Reset; + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= CCMR_OC13FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= CCMR_OC24FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= CCMR_OC13FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= CCMR_OC24FE_Reset; + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1CE Bit */ + tmpccmr1 &= CCMR_OC13CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= CCMR_OC24CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= CCMR_OC13CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= CCMR_OC24CE_Reset; + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= CCER_CC1P_Reset; + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= CCER_CC1NP_Reset; + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= CCER_CC2P_Reset; + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= CCER_CC2NP_Reset; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= CCER_CC3P_Reset; + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= CCER_CC3NP_Reset; + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= CCER_CC4P_Reset; + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_Set << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_18_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_Set << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM Ouput Compare Mode. + * @note This function disables the selected channel before changing the Ouput + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This paramter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_Offset; + + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC13M_Mask; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= CCMR_OC24M_Mask; + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= CR1_UDIS_Set; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= CR1_UDIS_Reset; + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= CR1_URS_Set; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= CR1_URS_Reset; + } +} + +/** + * @brief Enables or disables the TIMx’s Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= CR2_TI1S_Set; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= CR2_TI1S_Reset; + } +} + +/** + * @brief Selects the TIMx’s One Pulse Mode. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= CR1_OPM_Reset; + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= CR2_MMS_Mask; + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= SMCR_SMS_Mask; + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= SMCR_MSM_Reset; + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= CCMR_IC13PSC_Mask; + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= CCMR_IC24PSC_Mask; + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= CCMR_IC13PSC_Mask; + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= CCMR_IC24PSC_Mask; + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= CR1_CKD_Mask; + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_123458_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @retval Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= CCER_CC1E_Reset; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= CCER_CC1P_Reset; + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= CCER_CC2E_Reset; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= CCER_CC2P_Reset; + tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= CCER_CC3E_Reset; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= CCER_CC3P_Reset; + tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= CCER_CC4E_Reset; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= CCER_CC4P_Reset; + tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c new file mode 100644 index 000000000..43fcb784e --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c @@ -0,0 +1,967 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the USART firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/** @defgroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Defines + * @{ + */ + +#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ +#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ + +#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ + +#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + /* Determine the integer part */ + integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 0x64) << 0x04; + /* Determine the fractional part */ + fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04)); + tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((uint8_t)0x0F); + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART’s DMA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3 or UART4. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @note The DMA mode is not available for UART5. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1234_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART’s LIN mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @note The guard time bits are not available for UART4 and UART5. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART’s Smart Card mode. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/** + * @brief Enables or disables the USART’s Half Duplex communication. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + +/** + * @brief Configures the USART’s IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART’s IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx’s interrupt pending bits. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c new file mode 100644 index 000000000..e2a56c45d --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.c + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief This file provides all the WWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @defgroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk index ed7ec62fb..4e2837761 100644 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk +++ b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk @@ -12,14 +12,11 @@ STM32SRC = stm32lib/src/stm32f10x_adc.c \ stm32lib/src/stm32f10x_gpio.c \ stm32lib/src/stm32f10x_i2c.c \ stm32lib/src/stm32f10x_iwdg.c \ - stm32lib/src/stm32f10x_lib.c \ - stm32lib/src/stm32f10x_nvic.c \ stm32lib/src/stm32f10x_pwr.c \ stm32lib/src/stm32f10x_rcc.c \ stm32lib/src/stm32f10x_rtc.c \ stm32lib/src/stm32f10x_sdio.c \ stm32lib/src/stm32f10x_spi.c \ - stm32lib/src/stm32f10x_systick.c \ stm32lib/src/stm32f10x_tim.c \ stm32lib/src/stm32f10x_usart.c \ stm32lib/src/stm32f10x_wwdg.c -- cgit v1.2.3 From 4e24af72219edef168d5f1ce1fc95ae18c66b3cf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 18 Jul 2009 16:30:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1068 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 9 ++++++++- demos/ARMCM3-STM32F103-GCC/board.h | 4 ++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 6cdedea2e..01831c7fd 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -34,7 +34,14 @@ static const STM32GPIOConfig config = {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, - {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH} + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, +#if !defined(STM32F10X_LD) + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +#endif +#if defined(STM32F10X_HD) + {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, + {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, +#endif }; /* diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index c32b3d9da..f9364b02b 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -111,4 +111,8 @@ #define VAL_GPIODCRH 0x88888888 #define VAL_GPIODODR 0xFFFFFFFF +#define VAL_GPIOECRL 0x88888888 +#define VAL_GPIOECRH 0x88888888 +#define VAL_GPIOEODR 0xFFFFFFFF + #endif /* _BOARD_H_ */ -- cgit v1.2.3 From 1ea7355d85e316aadfd90468b3e808bb3dc95ee9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 16 Aug 2009 13:07:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1073 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 25 ++++++++++++------------ demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 31 +++++++++++++++--------------- demos/ARM7-LPC214x-G++/Makefile | 31 +++++++++++++++--------------- demos/ARM7-LPC214x-GCC-minimal/Makefile | 28 ++++++++++++++------------- demos/ARM7-LPC214x-GCC/Makefile | 34 ++++++++++++++++----------------- demos/ARMCM3-STM32F103-GCC/Makefile | 32 +++++++++++++++---------------- demos/AVR-AT90CANx-GCC/Makefile | 14 ++++++++------ demos/AVR-ATmega128-GCC/Makefile | 14 ++++++++------ demos/MSP430-MSP430x1611-GCC/Makefile | 22 +++++++++++---------- demos/Win32-MinGW/Makefile | 14 ++++++++------ 10 files changed, 128 insertions(+), 117 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index db19978c8..4622e181f 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -43,16 +43,18 @@ PROJECT = ch LDSCRIPT= ch.ld # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/ARM7/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-AT91SAM7X/pal_lld.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ +CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ + ../../os/io/pal.c \ + ../../os/ports/GCC/ARM7/AT91SAM7X/pal_lld.c \ + ../../os/ports/GCC/ARM7/AT91SAM7X/sam7x_serial.c \ at91lib/aic.c \ board.c main.c @@ -81,14 +83,13 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s \ - ../../ports/ARM7-AT91SAM7X/vectors.s \ - ../../ports/ARM7/chcoreasm.s +ASMSRC = $(PORTASM) \ + ../../os/ports/GCC/ARM7/AT91SAM7X/vectors.s -INCDIR = $(KERNINC) $(TESTINC) \ - ../../src/lib \ - ../../ports/ARM7 \ - ../../ports/ARM7-AT91SAM7X +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/ports/GCC/ARM7/AT91SAM7X \ + ../../os/various # # Project, sources and paths @@ -176,4 +177,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM/rules.mk +include ../../os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 4b0aad5a1..0e881c364 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -43,7 +43,8 @@ PROJECT = ch LDSCRIPT= ch.ld # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/ARM7/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # List of the required uIP source files. @@ -57,14 +58,15 @@ USRC = ../../ext/uip-1.0/uip/uip_arp.c \ # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-AT91SAM7X/pal_lld.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_serial.c \ - ../../ports/ARM7-AT91SAM7X/sam7x_emac.c \ +CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ${USRC} \ - ../../src/lib/evtimer.c \ + ../../os/io/pal.c \ + ../../os/ports/GCC/ARM7/AT91SAM7X/pal_lld.c \ + ../../os/ports/GCC/ARM7/AT91SAM7X/sam7x_serial.c \ + ../../os/ports/GCC/ARM7/AT91SAM7X/sam7x_emac.c \ + ../../os/various/evtimer.c \ at91lib/aic.c \ web/webthread.c \ board.c main.c @@ -94,14 +96,13 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s \ - ../../ports/ARM7-AT91SAM7X/vectors.s \ - ../../ports/ARM7/chcoreasm.s - -INCDIR = $(KERNINC) $(TESTINC) \ - ../../src/lib \ - ../../ports/ARM7 \ - ../../ports/ARM7-AT91SAM7X \ +ASMSRC = $(PORTASM) \ + ../../os/ports/GCC/ARM7/AT91SAM7X/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/ports/GCC/ARM7/AT91SAM7X \ + ../../os/various \ ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver # @@ -190,4 +191,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM/rules.mk +include ../../os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 894a37e61..5709a5dd3 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -40,21 +40,23 @@ endif PROJECT = ch # Define linker script file here -LDSCRIPT= ch.ld +LDSCRIPT = ch.ld # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/ARM7/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/pal_lld.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ +CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../src/lib/evtimer.c \ + ../../os/io/pal.c \ + ../../os/ports/GCC//ARM7/LPC214x/vic.c \ + ../../os/ports/GCC/ARM7/LPC214x/pal_lld.c \ + ../../os/ports/GCC/ARM7/LPC214x/lpc214x_serial.c \ + ../../os/various/evtimer.c \ board.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -82,14 +84,13 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s \ - ../../ports/ARM7-LPC214x/vectors.s \ - ../../ports/ARM7/chcoreasm.s +ASMSRC = $(PORTASM) \ + ../../os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(KERNINC) $(TESTINC) \ - ../../src/lib \ - ../../ports/ARM7 \ - ../../ports/ARM7-LPC214x +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/ports/GCC/ARM7/LPC214x \ + ../../os/various # # Project, sources and paths @@ -177,4 +178,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM/rules.mk +include ../../os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index a00eb9c65..358b12597 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -40,18 +40,21 @@ endif PROJECT = ch # Define linker script file here -LDSCRIPT= ch.ld +LDSCRIPT = ch.ld # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/ARM7/port.mk +include ../../os/kernel/kernel.mk #include ../../test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/pal_lld.c \ +CSRC = ${PORTSRC} \ ${KERNSRC} \ + ${TESTSRC} \ + ../../os/io/pal.c \ + ../../os/ports/GCC//ARM7/LPC214x/vic.c \ + ../../os/ports/GCC/ARM7/LPC214x/pal_lld.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -79,14 +82,13 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s \ - ../../ports/ARM7-LPC214x/vectors.s \ - ../../ports/ARM7/chcoreasm.s +ASMSRC = $(PORTASM) \ + ../../os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(KERNINC) $(TESTINC) \ - ../../src/lib \ - ../../ports/ARM7 \ - ../../ports/ARM7-LPC214x +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/ports/GCC/ARM7/LPC214x \ + ../../os/various # # Project, sources and paths @@ -174,4 +176,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM/rules.mk +include ../../os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 2185bbe94..0b36edb4a 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -40,23 +40,24 @@ endif PROJECT = ch # Define linker script file here -LDSCRIPT= ch.ld +LDSCRIPT = ch.ld # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/ARM7/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ../../ports/ARM7/chcore.c \ - ../../ports/ARM7-LPC214x/vic.c \ - ../../ports/ARM7-LPC214x/pal_lld.c \ - ../../ports/ARM7-LPC214x/lpc214x_serial.c \ - ../../ports/ARM7-LPC214x/lpc214x_ssp.c \ +CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../src/lib/evtimer.c \ - ../../src/lib/pal.c \ + ../../os/io/pal.c \ + ../../os/ports/GCC//ARM7/LPC214x/vic.c \ + ../../os/ports/GCC/ARM7/LPC214x/pal_lld.c \ + ../../os/ports/GCC/ARM7/LPC214x/lpc214x_serial.c \ + ../../os/ports/GCC/ARM7/LPC214x/lpc214x_ssp.c \ + ../../os/various/evtimer.c \ board.c buzzer.c mmcsd.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -84,14 +85,13 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARM7/crt0.s \ - ../../ports/ARM7-LPC214x/vectors.s \ - ../../ports/ARM7/chcoreasm.s +ASMSRC = $(PORTASM) \ + ../../os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(KERNINC) $(TESTINC) \ - ../../src/lib \ - ../../ports/ARM7 \ - ../../ports/ARM7-LPC214x +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/ports/GCC/ARM7/LPC214x \ + ../../os/various # # Project, sources and paths @@ -179,4 +179,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/ARM/rules.mk +include ../../os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 3ffda1a1c..59e1fc544 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -56,20 +56,19 @@ PROJECT = ch LDSCRIPT= ch.ld # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/ARMCM3/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ../../ports/ARMCM3/cmsis/core_cm3.c \ - ../../ports/ARMCM3/chcore.c \ - ../../ports/ARMCM3/nvic.c \ - ../../ports/ARMCM3-STM32F103/stm32_serial.c \ - ../../ports/ARMCM3-STM32F103/pal_lld.c \ +CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../src/lib/pal.c \ - ../../src/lib/evtimer.c \ + ../../os/io/pal.c \ + ../../os/ports/GCC/ARMCM3/STM32F103/pal_lld.c \ + ../../os/ports/GCC/ARMCM3/STM32F103/stm32_serial.c \ + ../../os/various/evtimer.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -97,14 +96,13 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = ../../ports/ARMCM3/crt0.s \ - ../../ports/ARMCM3-STM32F103/vectors.s - -INCDIR = $(KERNINC) $(TESTINC) \ - ../../src/lib \ - ../../ports/ARMCM3 \ - ../../ports/ARMCM3/cmsis \ - ../../ports/ARMCM3-STM32F103 \ +ASMSRC = $(PORTASM) \ + ../../ports/ARMCM3-STM32F103/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/ports/GCC/ARMCM3/STM32F103 \ + ../../os/various \ ./stm32lib/inc # @@ -199,4 +197,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include ../../ports/ARM/rules.mk +include ../../os/ports/GCC/ARM/rules.mk diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index a72f1f913..7b880f6d9 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -80,15 +80,17 @@ OBJDIR = . # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/AVR/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # List C source files here. (C dependencies are automatically generated.) -SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ +SRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../os/ports/GCC/AVR/avr_serial.c \ + ../../os/various/evtimer.c \ board.c main.c @@ -123,7 +125,7 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = ../../src/include ../../src/lib ../../ports/AVR +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC)e ../../os/various # Compiler flag to set the C Standard level. diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index f291af1fb..c13d60ef9 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -80,15 +80,17 @@ OBJDIR = . # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/AVR/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # List C source files here. (C dependencies are automatically generated.) -SRC = ../../ports/AVR/chcore.c ../../ports/AVR/avr_serial.c \ - ${KERNSRC} \ - ${TESTSRC} \ - ../../src/lib/evtimer.c \ +SRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ../../os/ports/GCC/AVR/avr_serial.c \ + ../../os/various/evtimer.c \ board.c lcd.c main.c @@ -123,7 +125,7 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = ../../src/include ../../src/lib ../../ports/AVR +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC)e ../../os/various # Compiler flag to set the C Standard level. diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 8cf693eb1..e316c3fa9 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -36,30 +36,32 @@ endif PROJECT = ch # Define linker script file here -LDSCRIPT= mspgcc/msp430x1611.x +LDSCRIPT = mspgcc/msp430x1611.x # Imported source files -include ../../src/kernel.mk +include ../../os/ports/GCC/MSP430/port.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # C sources here. -CSRC = ../../ports/MSP430/chcore.c \ - ../../ports/MSP430/msp430_serial.c \ - ../../ports/MSP430/pal_lld.c \ +CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../src/lib/evtimer.c \ + ../../os/io/pal.c \ + ../../os/ports/GCC/MSP430/pal_lld.c \ + ../../os/ports/GCC/MSP430/msp430_serial.c \ + ../../os/various/evtimer.c \ board.c main.c # C++ sources here. CPPSRC = # List ASM source files here -ASMSRC = +ASMSRC = $(PORTASM) -INCDIR = $(KERNINC) $(TESTINC) \ - ../../src/lib \ - ../../ports/MSP430 +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/various # # Project, sources and paths diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index ed66e51fd..616b46015 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -47,7 +47,7 @@ DLIBS = -lws2_32 PROJECT = ch # Define linker script file here -LDSCRIPT= +LDSCRIPT = # List all user C define here, like -D_DEBUG=1 UDEFS = @@ -56,19 +56,21 @@ UDEFS = UADEFS = # Imported source files -include ../../src/kernel.mk +include ../../os/kernel/kernel.mk include ../../test/test.mk # List C source files here -SRC = chcore.c main.c ../../ports/win32/simcom.c \ - ${KERNSRC} \ - ${TESTSRC} +SRC = ${KERNSRC} \ + ${TESTSRC} \ + chcore.c \ + ../../os/ports/GCC/win32/simcom.c \ + main.c # List ASM source files here ASRC = # List all user directories here -UINCDIR = ../../src/include +UINCDIR = $(KERNINC) $(TESTINC) # List the user directory to look for the libraries here ULIBDIR = -- cgit v1.2.3 From 45a6b7dc5a1758cb2bc49b0d76effa381043d297 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 19 Aug 2009 13:11:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1082 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 3 ++- demos/ARMCM3-STM32F103-GCC/board.c | 8 ++++---- demos/ARMCM3-STM32F103-GCC/chconf.h | 10 ---------- demos/ARMCM3-STM32F103-GCC/main.c | 7 ++++++- 4 files changed, 12 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 59e1fc544..d44b016bb 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -66,8 +66,9 @@ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ + ../../os/io/serial.c \ ../../os/ports/GCC/ARMCM3/STM32F103/pal_lld.c \ - ../../os/ports/GCC/ARMCM3/STM32F103/stm32_serial.c \ + ../../os/ports/GCC/ARMCM3/STM32F103/serial_lld.c \ ../../os/various/evtimer.c \ board.c main.c diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 01831c7fd..11a47e828 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -22,14 +22,14 @@ #include #include "board.h" -#include "stm32_serial.h" +#include "serial.h" #define AIRCR_VECTKEY 0x05FA0000 /* * Digital I/O ports static configuration as defined in @p board.h. */ -static const STM32GPIOConfig config = +static const STM32GPIOConfig pal_config = { {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, @@ -83,7 +83,7 @@ void hwinit0(void) { /* * I/O ports initialization as specified in board.h. */ - palInit(&config); + palInit(&pal_config); } /* @@ -112,7 +112,7 @@ void hwinit1(void) { /* * Other subsystems initialization. */ - serial_init(0xC0, 0xC0, 0xC0); + sd_lld_init(); /* * ChibiOS/RT initialization. diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 8e6eda189..3c6353168 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index f89131d37..d1f78f7e8 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -22,7 +22,7 @@ #include #include "board.h" -#include "stm32_serial.h" +#include "serial.h" /* * Red LEDs blinker thread, times are in milliseconds. @@ -45,6 +45,11 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + /* + * Activates the communication port 2 using the driver default configuration. + */ + sdStart(&COM2, NULL); + /* * Creates the blinker thread. */ -- cgit v1.2.3 From 24fc474ac69372d242b32830c981639492bba63a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 20 Aug 2009 08:26:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1083 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 11a47e828..6c8bf8c0a 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -112,7 +112,7 @@ void hwinit1(void) { /* * Other subsystems initialization. */ - sd_lld_init(); + sdInit(); /* * ChibiOS/RT initialization. -- cgit v1.2.3 From 0b8f1183fe1f321fdd71e9d1fc5a28323f9036a7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 20 Aug 2009 12:53:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1090 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 11 ++++++----- demos/ARM7-LPC214x-GCC/board.c | 5 ++--- demos/ARM7-LPC214x-GCC/main.c | 9 +++++++-- demos/ARMCM3-STM32F103-GCC/Makefile | 6 +++--- 4 files changed, 18 insertions(+), 13 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 0b36edb4a..b34dd3b64 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -53,10 +53,11 @@ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ - ../../os/ports/GCC//ARM7/LPC214x/vic.c \ - ../../os/ports/GCC/ARM7/LPC214x/pal_lld.c \ - ../../os/ports/GCC/ARM7/LPC214x/lpc214x_serial.c \ - ../../os/ports/GCC/ARM7/LPC214x/lpc214x_ssp.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/LPC214x/pal_lld.c \ + ../../os/io/platforms/LPC214x/serial_lld.c \ + ../../os/io/platforms/LPC214x/vic.c \ + ../../os/io/platforms/LPC214x/lpc214x_ssp.c \ ../../os/various/evtimer.c \ board.c buzzer.c mmcsd.c main.c @@ -90,7 +91,7 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ - ../../os/ports/GCC/ARM7/LPC214x \ + ../../os/io/platforms/LPC214x \ ../../os/various # diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 8be258a1a..2c041b384 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -19,10 +19,9 @@ #include #include +#include -#include "lpc214x.h" #include "vic.h" -#include "lpc214x_serial.h" #include "lpc214x_ssp.h" #include "board.h" @@ -144,7 +143,7 @@ void hwinit1(void) { /* * Other subsystems. */ - serial_init(1, 2); + sdInit(); ssp_init(); InitMMC(); InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 61ad4ea77..33197c2cb 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -19,10 +19,10 @@ #include #include +#include #include #include "board.h" -#include "lpc214x_serial.h" #include "mmcsd.h" #include "buzzer.h" #include "evtimer.h" @@ -80,7 +80,7 @@ static void TimerHandler(eventid_t id) { if (!palReadPad(IOPORT_A, PA_BUTTON1)) PlaySound(1000, MS2ST(100)); if (!palReadPad(IOPORT_A, PA_BUTTON2)) { - chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); + sdWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); PlaySound(2000, MS2ST(100)); } } @@ -128,6 +128,11 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0, el1, el2; + /* + * Activates the communication port 1 using the driver default configuration. + */ + sdStart(&COM1, NULL); + /* * If a button is pressed during the reset then the blinking leds threads * are not started in order to make accurate benchmarks. diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index d44b016bb..a337a1a5b 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -67,8 +67,8 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ ../../os/io/serial.c \ - ../../os/ports/GCC/ARMCM3/STM32F103/pal_lld.c \ - ../../os/ports/GCC/ARMCM3/STM32F103/serial_lld.c \ + ../../os/io/platforms/STM32F103/pal_lld.c \ + ../../os/io/platforms/STM32F103/serial_lld.c \ ../../os/various/evtimer.c \ board.c main.c @@ -102,7 +102,7 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ - ../../os/ports/GCC/ARMCM3/STM32F103 \ + ../../os/io/platforms/STM32F103 \ ../../os/various \ ./stm32lib/inc -- cgit v1.2.3 From 9193bc2a8116ada2cd5a4deb1783fdfd7ce1629b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 20 Aug 2009 12:58:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1092 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index b34dd3b64..67b082af3 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -92,7 +92,8 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ ../../os/io/platforms/LPC214x \ - ../../os/various + ../../os/various \ + ../../os/ports/GCC/ARM7/LPC214x # # Project, sources and paths -- cgit v1.2.3 From 89cd6853e753c32903a9a6d48e3fe26be8999f97 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 21 Aug 2009 09:32:58 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1095 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 14 ++++++++------ demos/ARM7-LPC214x-G++/board.c | 6 +++--- demos/ARM7-LPC214x-G++/main.cpp | 12 ++++++++---- demos/ARM7-LPC214x-GCC-minimal/Makefile | 9 +++++---- demos/ARM7-LPC214x-GCC-minimal/board.c | 2 +- 5 files changed, 25 insertions(+), 18 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 5709a5dd3..1940c8509 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -53,15 +53,16 @@ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ - ../../os/ports/GCC//ARM7/LPC214x/vic.c \ - ../../os/ports/GCC/ARM7/LPC214x/pal_lld.c \ - ../../os/ports/GCC/ARM7/LPC214x/lpc214x_serial.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/LPC214x/pal_lld.c \ + ../../os/io/platforms/LPC214x/serial_lld.c \ + ../../os/io/platforms/LPC214x/vic.c \ ../../os/various/evtimer.c \ board.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CPPSRC = ../../src/lib/ch.cpp main.cpp +CPPSRC = ../../os/various/ch.cpp main.cpp # C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler @@ -89,8 +90,9 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ - ../../os/ports/GCC/ARM7/LPC214x \ - ../../os/various + ../../os/io/platforms/LPC214x \ + ../../os/various \ + ../../os/ports/GCC/ARM7/LPC214x # # Project, sources and paths diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index 68b060dbd..eba3f59e3 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -19,11 +19,11 @@ #include #include +#include #include "lpc214x.h" #include "vic.h" -#include "lpc214x_serial.h" -#include "lpc214x_ssp.h" +//#include "lpc214x_ssp.h" #include "board.h" //#include "mmcsd.h" @@ -144,7 +144,7 @@ void hwinit1(void) { /* * Other subsystems. */ - serial_init(1, 2); + sdInit(); // ssp_init(); // InitMMC(); // InitBuzzer(); diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 683c2675d..b217e86a2 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -19,12 +19,11 @@ #include #include - -#include +#include #include +#include -#include -#include +#include "board.h" #define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) @@ -155,6 +154,11 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0; + /* + * Activates the communication port 1 using the driver default configuration. + */ + sdStart(&COM1, NULL); + evtInit(&evt, 500); // Initializes an event timer. evtStart(&evt); // Starts the event timer. chEvtRegister(&evt.et_es, &el0, 0); // Registers a listener on the source. diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 358b12597..23b74db74 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -53,8 +53,8 @@ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ - ../../os/ports/GCC//ARM7/LPC214x/vic.c \ - ../../os/ports/GCC/ARM7/LPC214x/pal_lld.c \ + ../../os/io/platforms/LPC214x/pal_lld.c \ + ../../os/io/platforms/LPC214x/vic.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -87,8 +87,9 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ - ../../os/ports/GCC/ARM7/LPC214x \ - ../../os/various + ../../os/io/platforms/LPC214x \ + ../../os/various \ + ../../os/ports/GCC/ARM7/LPC214x # # Project, sources and paths diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index 95732cfef..bcf430ade 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -144,7 +144,7 @@ void hwinit1(void) { /* * Other subsystems. */ -// serial_init(1, 2); +// sdInit(); // ssp_init(); // InitMMC(); // InitBuzzer(); -- cgit v1.2.3 From e742f3abaa068c03b248894f09bc14fe510a08cd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 21 Aug 2009 11:08:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1098 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 10 ++++++---- demos/ARM7-AT91SAM7X-GCC/board.c | 5 ++--- demos/ARM7-AT91SAM7X-GCC/main.c | 9 +++++++-- 3 files changed, 15 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 4622e181f..34f5ff8b2 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -53,8 +53,9 @@ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ - ../../os/ports/GCC/ARM7/AT91SAM7X/pal_lld.c \ - ../../os/ports/GCC/ARM7/AT91SAM7X/sam7x_serial.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/AT91SAM7X/pal_lld.c \ + ../../os/io/platforms/AT91SAM7X/serial_lld.c \ at91lib/aic.c \ board.c main.c @@ -88,8 +89,9 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ - ../../os/ports/GCC/ARM7/AT91SAM7X \ - ../../os/various + ../../os/io/platforms/AT91SAM7X \ + ../../os/various \ + ../../os/ports/GCC/ARM7/AT91SAM7X # # Project, sources and paths diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index aac51cf0c..fb52c8f3b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -19,12 +19,11 @@ #include #include +#include #include "board.h" #include "at91lib/aic.h" -#include - /* * FIQ Handler weak symbol defined in vectors.s. */ @@ -169,7 +168,7 @@ void hwinit1(void) { /* * Serial driver initialization, RTS/CTS pins enabled for USART0 only. */ - serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + sdInit(); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 614b649cd..d1ca61cc7 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -19,10 +19,10 @@ #include #include +#include #include #include "board.h" -#include static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { @@ -42,6 +42,11 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + /* + * Activates the communication port 1 using the driver default configuration. + */ + sdStart(&COM1, NULL); + /* * Creates the blinker thread. */ @@ -53,7 +58,7 @@ int main(int argc, char **argv) { while (TRUE) { chThdSleepMilliseconds(500); if (!palReadPad(IOPORT_B, PIOB_SW1)) - chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); + sdWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); if (!palReadPad(IOPORT_B, PIOB_SW2)) TestThread(&COM1); } -- cgit v1.2.3 From 05f9e5c72131d6997f3d424be4822e486b836645 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 21 Aug 2009 11:18:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1100 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h | 2918 -------------------- demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c | 84 - demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h | 78 - .../ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h | 2918 -------------------- demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c | 84 - demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h | 78 - 7 files changed, 1 insertion(+), 6161 deletions(-) delete mode 100644 demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h delete mode 100644 demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c delete mode 100644 demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 34f5ff8b2..5a9a7a94a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -56,7 +56,7 @@ CSRC = ${PORTSRC} \ ../../os/io/serial.c \ ../../os/io/platforms/AT91SAM7X/pal_lld.c \ ../../os/io/platforms/AT91SAM7X/serial_lld.c \ - at91lib/aic.c \ + ../../os/io/platforms/AT91SAM7X/at91lib/aic.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global diff --git a/demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h b/demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h deleted file mode 100644 index 20b0e747d..000000000 --- a/demos/ARM7-AT91SAM7X-GCC/at91lib/AT91SAM7X256.h +++ /dev/null @@ -1,2918 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the disclaimer below in the documentation and/or -// other materials provided with the distribution. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 06/19/2007 (15:41:06) -// -// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// -// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// -// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; -#else -#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register -#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register -#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register -#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register -#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register -#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register -#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register -#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register - -#endif -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; -#else -#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register -#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register -#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register -#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register -#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register -#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register -#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register -#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register -#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register -#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register -#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register -#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register - -#endif -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; -#else -#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register -#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register -#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register -#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register -#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer -#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer -#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register -#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register -#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register -#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register -#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register -#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register -#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register -#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register -#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register -#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register -#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register -#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register -#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register -#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register -#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register -#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register -#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register -#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register -#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register -#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register -#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register -#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register -#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register -#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register -#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register -#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register -#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register -#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register -#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] -#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] -#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register -#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register -#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register -#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register -#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register - -#endif -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c b/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c deleted file mode 100644 index 66eebf94e..000000000 --- a/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.c +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - * ---------------------------------------------------------------------------- - * Copyright (c) 2006, Atmel Corporation - - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaiimer below. - * - * - Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the disclaimer below in the documentation and/or - * other materials provided with the distribution. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "aic.h" -#include - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures the interrupt associated with the given source, using the -/// specified mode and interrupt handler. -/// \param source Interrupt source to configure. -/// \param mode Triggering mode of the interrupt. -/// \param handler Interrupt handler function. -//------------------------------------------------------------------------------ -void AIC_ConfigureIT(unsigned int source, - unsigned int mode, - void (*handler)( void )) -{ - // Disable the interrupt first - AT91C_BASE_AIC->AIC_IDCR = 1 << source; - - // Configure mode and handler - AT91C_BASE_AIC->AIC_SMR[source] = mode; - AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; - - // Clear interrupt - AT91C_BASE_AIC->AIC_ICCR = 1 << source; -} - -//------------------------------------------------------------------------------ -/// Enables interrupts coming from the given (unique) source. -/// \param source Interrupt source to enable. -//------------------------------------------------------------------------------ -void AIC_EnableIT(unsigned int source) -{ - AT91C_BASE_AIC->AIC_IECR = 1 << source; -} - -//------------------------------------------------------------------------------ -/// Disables interrupts coming from the given (unique) source. -/// \param source Interrupt source to enable. -//------------------------------------------------------------------------------ -void AIC_DisableIT(unsigned int source) -{ - AT91C_BASE_AIC->AIC_IDCR = 1 << source; -} - diff --git a/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h b/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h deleted file mode 100644 index e8e52c78a..000000000 --- a/demos/ARM7-AT91SAM7X-GCC/at91lib/aic.h +++ /dev/null @@ -1,78 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - * ---------------------------------------------------------------------------- - * Copyright (c) 2006, Atmel Corporation - - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaiimer below. - * - * - Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the disclaimer below in the documentation and/or - * other materials provided with the distribution. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \dir -/// !Purpose -/// -/// Methods and definitions for configuring interrupts using the Advanced -/// Interrupt Controller (AIC). -/// -/// !Usage -/// -# Configure an interrupt source using AIC_ConfigureIT -/// -# Enable or disable interrupt generation of a particular source with -/// AIC_EnableIT and AIC_DisableIT. -//------------------------------------------------------------------------------ - -#ifndef AIC_H -#define AIC_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL - /// Redefinition of missing constant. - #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE -#endif - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void AIC_ConfigureIT(unsigned int source, - unsigned int mode, - void (*handler)( void )); - -extern void AIC_EnableIT(unsigned int source); - -extern void AIC_DisableIT(unsigned int source); - -#endif //#ifndef AIC_H - diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h deleted file mode 100644 index 20b0e747d..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/AT91SAM7X256.h +++ /dev/null @@ -1,2918 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// - Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the disclaimer below in the documentation and/or -// other materials provided with the distribution. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 06/19/2007 (15:41:06) -// -// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// -// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// -// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN_MB { - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB, *AT91PS_CAN_MB; -#else -#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register -#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register -#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register -#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register -#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register -#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register -#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register -#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register - -#endif -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CAN { - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN, *AT91PS_CAN; -#else -#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register -#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register -#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register -#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register -#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register -#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register -#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register -#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register -#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register -#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register -#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register -#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register - -#endif -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_EMAC { - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC, *AT91PS_EMAC; -#else -#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register -#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register -#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register -#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register -#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer -#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer -#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register -#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register -#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register -#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register -#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register -#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register -#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register -#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register -#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register -#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register -#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register -#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register -#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register -#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register -#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register -#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register -#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register -#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register -#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register -#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register -#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register -#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register -#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register -#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register -#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register -#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register -#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register -#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register -#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0] -#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32] -#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes -#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes -#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes -#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes -#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes -#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes -#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes -#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes -#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register -#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register -#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register -#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register -#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register - -#endif -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII -#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_CAN (15) // Control Area Network Controller -#define AT91C_ID_EMAC (16) // Ethernet MAC -#define AT91C_ID_ADC (17) // Analog-to-Digital Converter -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c deleted file mode 100644 index 66eebf94e..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.c +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - * ---------------------------------------------------------------------------- - * Copyright (c) 2006, Atmel Corporation - - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaiimer below. - * - * - Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the disclaimer below in the documentation and/or - * other materials provided with the distribution. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "aic.h" -#include - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures the interrupt associated with the given source, using the -/// specified mode and interrupt handler. -/// \param source Interrupt source to configure. -/// \param mode Triggering mode of the interrupt. -/// \param handler Interrupt handler function. -//------------------------------------------------------------------------------ -void AIC_ConfigureIT(unsigned int source, - unsigned int mode, - void (*handler)( void )) -{ - // Disable the interrupt first - AT91C_BASE_AIC->AIC_IDCR = 1 << source; - - // Configure mode and handler - AT91C_BASE_AIC->AIC_SMR[source] = mode; - AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; - - // Clear interrupt - AT91C_BASE_AIC->AIC_ICCR = 1 << source; -} - -//------------------------------------------------------------------------------ -/// Enables interrupts coming from the given (unique) source. -/// \param source Interrupt source to enable. -//------------------------------------------------------------------------------ -void AIC_EnableIT(unsigned int source) -{ - AT91C_BASE_AIC->AIC_IECR = 1 << source; -} - -//------------------------------------------------------------------------------ -/// Disables interrupts coming from the given (unique) source. -/// \param source Interrupt source to enable. -//------------------------------------------------------------------------------ -void AIC_DisableIT(unsigned int source) -{ - AT91C_BASE_AIC->AIC_IDCR = 1 << source; -} - diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h b/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h deleted file mode 100644 index e8e52c78a..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/at91lib/aic.h +++ /dev/null @@ -1,78 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - ROUSSET - - * ---------------------------------------------------------------------------- - * Copyright (c) 2006, Atmel Corporation - - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaiimer below. - * - * - Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the disclaimer below in the documentation and/or - * other materials provided with the distribution. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \dir -/// !Purpose -/// -/// Methods and definitions for configuring interrupts using the Advanced -/// Interrupt Controller (AIC). -/// -/// !Usage -/// -# Configure an interrupt source using AIC_ConfigureIT -/// -# Enable or disable interrupt generation of a particular source with -/// AIC_EnableIT and AIC_DisableIT. -//------------------------------------------------------------------------------ - -#ifndef AIC_H -#define AIC_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL - /// Redefinition of missing constant. - #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE -#endif - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -extern void AIC_ConfigureIT(unsigned int source, - unsigned int mode, - void (*handler)( void )); - -extern void AIC_EnableIT(unsigned int source); - -extern void AIC_DisableIT(unsigned int source); - -#endif //#ifndef AIC_H - -- cgit v1.2.3 From 9d359d8a3b3eb87a58764ac2c696bc10037c480f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 21 Aug 2009 11:31:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1101 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 12 +++++++----- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 6 +++--- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 11 ++++++++--- 3 files changed, 18 insertions(+), 11 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 0e881c364..1484fefb2 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -63,11 +63,12 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${USRC} \ ../../os/io/pal.c \ - ../../os/ports/GCC/ARM7/AT91SAM7X/pal_lld.c \ - ../../os/ports/GCC/ARM7/AT91SAM7X/sam7x_serial.c \ - ../../os/ports/GCC/ARM7/AT91SAM7X/sam7x_emac.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/AT91SAM7X/pal_lld.c \ + ../../os/io/platforms/AT91SAM7X/serial_lld.c \ + ../../os/io/platforms/AT91SAM7X/sam7x_emac.c \ + ../../os/io/platforms/AT91SAM7X/at91lib/aic.c \ ../../os/various/evtimer.c \ - at91lib/aic.c \ web/webthread.c \ board.c main.c @@ -101,8 +102,9 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ - ../../os/ports/GCC/ARM7/AT91SAM7X \ + ../../os/io/platforms/AT91SAM7X \ ../../os/various \ + ../../os/ports/GCC/ARM7/AT91SAM7X \ ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver # diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 4557d3c91..51efb3c6d 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -19,12 +19,12 @@ #include #include +#include +#include #include "board.h" #include "at91lib/aic.h" -#include -#include /* * FIQ Handler weak symbol defined in vectors.s. @@ -170,7 +170,7 @@ void hwinit1(void) { /* * Serial driver initialization, RTS/CTS pins enabled for USART0 only. */ - serial_init(AT91C_AIC_PRIOR_HIGHEST - 2, AT91C_AIC_PRIOR_HIGHEST - 2); + sdInit(); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index 0eafb2260..e18d83d71 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -20,10 +20,10 @@ #include #include #include +#include +#include #include "board.h" -#include -#include #include "web/webthread.h" @@ -47,6 +47,11 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + /* + * Activates the communication port 1 using the driver default configuration. + */ + sdStart(&COM1, NULL); + /* * Creates the blinker and web server threads. */ @@ -59,7 +64,7 @@ int main(int argc, char **argv) { while (TRUE) { chThdSleepMilliseconds(500); if (!palReadPad(IOPORT_B, PIOB_SW1)) - chFDDWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); + sdWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); if (!palReadPad(IOPORT_B, PIOB_SW2)) TestThread(&COM1); } -- cgit v1.2.3 From b19be5d31de2003c7ff52df43f095a3d498b5bf3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 21 Aug 2009 13:11:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1102 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 6 ++++-- demos/MSP430-MSP430x1611-GCC/board.c | 4 ++-- demos/MSP430-MSP430x1611-GCC/main.c | 7 ++++++- 3 files changed, 12 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index e316c3fa9..6183fccf5 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -48,8 +48,9 @@ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ - ../../os/ports/GCC/MSP430/pal_lld.c \ - ../../os/ports/GCC/MSP430/msp430_serial.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/MSP430/pal_lld.c \ + ../../os/io/platforms/MSP430/serial_lld.c \ ../../os/various/evtimer.c \ board.c main.c @@ -61,6 +62,7 @@ ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ + ../../os/io/platforms/MSP430 \ ../../os/various # diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 2d5341beb..32f7c325b 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -19,11 +19,11 @@ #include #include +#include #include #include "board.h" -#include "msp430_serial.h" /* * Digital I/O ports static configuration as defined in @p board.h. @@ -75,7 +75,7 @@ void hwinit(void) { /* * Other subsystems. */ - serial_init(); + sdInit(); } CH_IRQ_HANDLER(TIMERA0_VECTOR) { diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 2f9f6d8b9..d52f2bb07 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -19,10 +19,10 @@ #include #include +#include #include #include "board.h" -#include "msp430_serial.h" /* * Red LEDs blinker thread, times are in milliseconds. @@ -49,6 +49,11 @@ int main(int argc, char **argv) { */ hwinit(); + /* + * Activates the communication port 1 using the driver default configuration. + */ + sdStart(&COM1, NULL); + /* * The main() function becomes a thread here then the interrupts are * enabled and ChibiOS/RT goes live. -- cgit v1.2.3 From f5d6a078c744d81c0e1ceee7d6efeeba6a6c1037 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 23 Aug 2009 12:02:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1104 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index a337a1a5b..8ed5863ed 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -53,7 +53,7 @@ endif PROJECT = ch # Define linker script file here -LDSCRIPT= ch.ld +LDSCRIPT = ch.ld # Imported source files include ../../os/ports/GCC/ARMCM3/port.mk @@ -116,7 +116,7 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = cortex-m3 -TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. -- cgit v1.2.3 From 6b9e823237f11f44f70044d6cdc81751fca5b3b3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 23 Aug 2009 12:13:07 +0000 Subject: development git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1105 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 8ed5863ed..74d231e8d 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -53,7 +53,7 @@ endif PROJECT = ch # Define linker script file here -LDSCRIPT = ch.ld +LDSCRIPT= ch.ld # Imported source files include ../../os/ports/GCC/ARMCM3/port.mk @@ -71,6 +71,7 @@ CSRC = ${PORTSRC} \ ../../os/io/platforms/STM32F103/serial_lld.c \ ../../os/various/evtimer.c \ board.c main.c + # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -116,7 +117,7 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = cortex-m3 -TRGT = arm-none-eabi- +TRGT = arm-elf- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. -- cgit v1.2.3 From 46827225678cea64b9519813fb60d5a0d388676f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 26 Aug 2009 13:34:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1106 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 10 ---------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 10 ---------- demos/ARM7-LPC214x-G++/chconf.h | 10 ---------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 10 ---------- demos/ARM7-LPC214x-GCC/chconf.h | 10 ---------- demos/AVR-AT90CANx-GCC/Makefile | 8 ++++++-- demos/AVR-AT90CANx-GCC/board.c | 8 ++++---- demos/AVR-AT90CANx-GCC/chconf.h | 10 ---------- demos/AVR-AT90CANx-GCC/main.c | 9 +++++++-- demos/AVR-ATmega128-GCC/Makefile | 10 +++++++--- demos/AVR-ATmega128-GCC/board.c | 4 ++-- demos/AVR-ATmega128-GCC/chconf.h | 10 ---------- demos/AVR-ATmega128-GCC/main.c | 9 +++++++-- demos/MSP430-MSP430x1611-GCC/chconf.h | 10 ---------- 14 files changed, 33 insertions(+), 95 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index fd9c18d69..ba2e6d048 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h index 8e6eda189..3c6353168 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 8e6eda189..3c6353168 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 42baa1f3d..08663fea3 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES FALSE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX FALSE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 8e6eda189..3c6353168 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index 7b880f6d9..30ae2aad0 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -89,7 +89,8 @@ include ../../test/test.mk SRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/ports/GCC/AVR/avr_serial.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/AVR/serial_lld.c \ ../../os/various/evtimer.c \ board.c main.c @@ -125,7 +126,10 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC)e ../../os/various +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/io/platforms/AVR \ + ../../os/various # Compiler flag to set the C Standard level. diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c index 3119b82be..2fdf128a1 100644 --- a/demos/AVR-AT90CANx-GCC/board.c +++ b/demos/AVR-AT90CANx-GCC/board.c @@ -18,9 +18,9 @@ */ #include +#include #include "board.h" -#include "avr_serial.h" CH_IRQ_HANDLER(TIMER0_COMP_vect) { @@ -71,9 +71,9 @@ void hwinit(void) { /* * Timer 0 setup. */ - TCCR0A = (1 << WGM01) | (0 << WGM00) | // CTC mode. + TCCR0A = (1 << WGM01) | (0 << WGM00) | // CTC mode. (0 << COM0A1) | (0 << COM0A0) | // OC0A disabled (normal I/O). - (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. + (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; TCNT0 = 0; // Reset counter. TIFR0 = (1 << OCF0A); // Reset pending (if any). @@ -82,5 +82,5 @@ void hwinit(void) { /* * Other initializations. */ - serial_init(); + sdInit(); } diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 717a0ce09..cb7da16d3 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index aa9b99dc0..a19b1e9c5 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -18,8 +18,8 @@ */ #include +#include #include -#include #include @@ -41,7 +41,7 @@ static void TimerHandler(eventid_t id) { msg_t TestThread(void *p); if (!(PORTE & PORTE_BUTTON)) - TestThread(&SER2); + TestThread(&SD2); } int main(int argc, char **argv) { @@ -59,6 +59,11 @@ int main(int argc, char **argv) { */ chSysInit(); + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + /* * Event Timer initialization. */ diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index c13d60ef9..4af1c53db 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -89,9 +89,10 @@ include ../../test/test.mk SRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/ports/GCC/AVR/avr_serial.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/AVR/serial_lld.c \ ../../os/various/evtimer.c \ - board.c lcd.c main.c + board.c main.c # List C++ source files here. (C dependencies are automatically generated.) @@ -125,7 +126,10 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC)e ../../os/various +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/io/platforms/AVR \ + ../../os/various # Compiler flag to set the C Standard level. diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index 490dd0362..84e1565cb 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -18,9 +18,9 @@ */ #include +#include #include "board.h" -#include "avr_serial.h" CH_IRQ_HANDLER(TIMER0_COMP_vect) { @@ -82,5 +82,5 @@ void hwinit(void) { /* * Other initializations. */ - serial_init(); + sdInit(); } diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 717a0ce09..cb7da16d3 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 405770d00..dc3fd33c3 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -18,8 +18,8 @@ */ #include +#include #include -#include #include @@ -43,7 +43,7 @@ static void TimerHandler(eventid_t id) { msg_t TestThread(void *p); if (!(PINA & PORTA_BUTTON1)) - TestThread(&SER2); + TestThread(&SD2); } int main(int argc, char **argv) { @@ -61,6 +61,11 @@ int main(int argc, char **argv) { */ chSysInit(); + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + /* * This initialization requires the OS already active because it uses delay * APIs inside. diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 14e6004c9..2f018c290 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. -- cgit v1.2.3 From 6cb018ac39eb99ae0668d00cdecfa48f08dfca89 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 27 Aug 2009 15:41:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1107 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-ATmega128-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index 4af1c53db..c56520b08 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -92,7 +92,7 @@ SRC = ${PORTSRC} \ ../../os/io/serial.c \ ../../os/io/platforms/AVR/serial_lld.c \ ../../os/various/evtimer.c \ - board.c main.c + lcd.c board.c main.c # List C++ source files here. (C dependencies are automatically generated.) -- cgit v1.2.3 From 8b55cb9767ce881b7a22c5af34605ed3a261582d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 27 Aug 2009 16:42:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1109 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 14 +++++++------- demos/ARM7-AT91SAM7X-GCC/main.c | 16 ++++++++-------- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 14 +++++++------- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 16 ++++++++-------- demos/ARM7-LPC214x-G++/main.cpp | 12 ++++++------ demos/ARM7-LPC214x-GCC-minimal/main.c | 12 ++++++------ demos/ARM7-LPC214x-GCC/main.c | 28 ++++++++++++++-------------- demos/ARM7-LPC214x-GCC/mmcsd.c | 4 ++-- demos/ARMCM3-STM32F103-GCC/main.c | 12 ++++++------ demos/MSP430-MSP430x1611-GCC/main.c | 12 ++++++------ 10 files changed, 70 insertions(+), 70 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index fb52c8f3b..31e362845 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -133,25 +133,25 @@ void hwinit1(void) { /* * LCD pins setup. */ - palClearPad(IOPORT_B, PIOB_LCD_BL); - palSetPadMode(IOPORT_B, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(IOPORT2, PIOB_LCD_BL); + palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); - palSetPad(IOPORT_A, PIOA_LCD_RESET); - palSetPadMode(IOPORT_A, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT1, PIOA_LCD_RESET); + palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); /* * Joystick and buttons setup. */ - palSetGroupMode(IOPORT_A, + palSetGroupMode(IOPORT1, PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | PIOA_B4_MASK | PIOA_B5_MASK, PAL_MODE_INPUT); - palSetGroupMode(IOPORT_B, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); + palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); /* * MMC/SD slot setup. */ - palSetGroupMode(IOPORT_B, + palSetGroupMode(IOPORT2, PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, PAL_MODE_INPUT); diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index d1ca61cc7..f6c297a41 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -28,9 +28,9 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - palSetPad(IOPORT_B, PIOB_LCD_BL); + palSetPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(100); - palClearPad(IOPORT_B, PIOB_LCD_BL); + palClearPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(900); } return 0; @@ -43,9 +43,9 @@ static msg_t Thread1(void *arg) { int main(int argc, char **argv) { /* - * Activates the communication port 1 using the driver default configuration. + * Activates the serial driver 1 using the driver default configuration. */ - sdStart(&COM1, NULL); + sdStart(&SD1, NULL); /* * Creates the blinker thread. @@ -57,10 +57,10 @@ int main(int argc, char **argv) { */ while (TRUE) { chThdSleepMilliseconds(500); - if (!palReadPad(IOPORT_B, PIOB_SW1)) - sdWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT_B, PIOB_SW2)) - TestThread(&COM1); + if (!palReadPad(IOPORT2, PIOB_SW1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT2, PIOB_SW2)) + TestThread(&SD1); } return 0; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 51efb3c6d..e57f8bcdc 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -135,25 +135,25 @@ void hwinit1(void) { /* * LCD pins setup. */ - palClearPad(IOPORT_B, PIOB_LCD_BL); - palSetPadMode(IOPORT_B, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); + palClearPad(IOPORT2, PIOB_LCD_BL); + palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); - palSetPad(IOPORT_A, PIOA_LCD_RESET); - palSetPadMode(IOPORT_A, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT1, PIOA_LCD_RESET); + palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); /* * Joystick and buttons setup. */ - palSetGroupMode(IOPORT_A, + palSetGroupMode(IOPORT1, PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | PIOA_B4_MASK | PIOA_B5_MASK, PAL_MODE_INPUT); - palSetGroupMode(IOPORT_B, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); + palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); /* * MMC/SD slot setup. */ - palSetGroupMode(IOPORT_B, + palSetGroupMode(IOPORT2, PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, PAL_MODE_INPUT); diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index e18d83d71..adfba225f 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -33,9 +33,9 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - palSetPad(IOPORT_B, PIOB_LCD_BL); + palSetPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(100); - palClearPad(IOPORT_B, PIOB_LCD_BL); + palClearPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(900); } return 0; @@ -48,9 +48,9 @@ static msg_t Thread1(void *arg) { int main(int argc, char **argv) { /* - * Activates the communication port 1 using the driver default configuration. + * Activates the serial driver 2 using the driver default configuration. */ - sdStart(&COM1, NULL); + sdStart(&SD1, NULL); /* * Creates the blinker and web server threads. @@ -63,10 +63,10 @@ int main(int argc, char **argv) { */ while (TRUE) { chThdSleepMilliseconds(500); - if (!palReadPad(IOPORT_B, PIOB_SW1)) - sdWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT_B, PIOB_SW2)) - TestThread(&COM1); + if (!palReadPad(IOPORT2, PIOB_SW1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT2, PIOB_SW2)) + TestThread(&SD1); } return 0; diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index b217e86a2..b46ccd86e 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -99,10 +99,10 @@ protected: case STOP: return 0; case BITCLEAR: - palClearPort(IOPORT_A, curr->value); + palClearPort(IOPORT1, curr->value); break; case BITSET: - palSetPort(IOPORT_A, curr->value); + palSetPort(IOPORT1, curr->value); break; } curr++; @@ -124,7 +124,7 @@ class TesterThread : public EnhancedThread<128> { protected: virtual msg_t Main(void) { - return TestThread(&COM1); + return TestThread(&SD1); } public: @@ -137,7 +137,7 @@ public: */ static void TimerHandler(eventid_t id) { - if (!(palReadPort(IOPORT_A) & BOTH_BUTTONS)) { // Both buttons + if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { // Both buttons TesterThread tester; tester.Wait(); }; @@ -155,9 +155,9 @@ int main(int argc, char **argv) { struct EventListener el0; /* - * Activates the communication port 1 using the driver default configuration. + * Activates the serial driver 2 using the driver default configuration. */ - sdStart(&COM1, NULL); + sdStart(&SD1, NULL); evtInit(&evt, 500); // Initializes an event timer. evtStart(&evt); // Starts the event timer. diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 83d192b91..d303237c4 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -29,13 +29,13 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED2)); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(200); - palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); - palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED1)); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); chThdSleepMilliseconds(200); - palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); } return 0; @@ -48,9 +48,9 @@ static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { - palClearPad(IOPORT_A, PA_LEDUSB); + palClearPad(IOPORT1, PA_LEDUSB); chThdSleepMilliseconds(200); - palSetPad(IOPORT_A, PA_LEDUSB); + palSetPad(IOPORT1, PA_LEDUSB); chThdSleepMilliseconds(300); } return 0; diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 33197c2cb..a8db1b667 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -36,13 +36,13 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED2)); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(200); - palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); - palClearPort(IOPORT_A, PAL_PORT_BIT(PA_LED1)); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); chThdSleepMilliseconds(200); - palSetPort(IOPORT_A, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(800); } return 0; @@ -55,9 +55,9 @@ static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { while (TRUE) { - palClearPad(IOPORT_A, PA_LEDUSB); + palClearPad(IOPORT1, PA_LEDUSB); chThdSleepMilliseconds(200); - palSetPad(IOPORT_A, PA_LEDUSB); + palSetPad(IOPORT1, PA_LEDUSB); chThdSleepMilliseconds(300); } return 0; @@ -70,17 +70,17 @@ static WORKING_AREA(waTestThread, 128); */ static void TimerHandler(eventid_t id) { - if (!(palReadPort(IOPORT_A) & BOTH_BUTTONS)) { + if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), - NORMALPRIO, TestThread, &COM1); + NORMALPRIO, TestThread, &SD1); chThdWait(tp); PlaySound(500, MS2ST(100)); } else { - if (!palReadPad(IOPORT_A, PA_BUTTON1)) + if (!palReadPad(IOPORT1, PA_BUTTON1)) PlaySound(1000, MS2ST(100)); - if (!palReadPad(IOPORT_A, PA_BUTTON2)) { - sdWrite(&COM1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT1, PA_BUTTON2)) { + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); PlaySound(2000, MS2ST(100)); } } @@ -129,15 +129,15 @@ int main(int argc, char **argv) { struct EventListener el0, el1, el2; /* - * Activates the communication port 1 using the driver default configuration. + * Activates the serial driver 2 using the driver default configuration. */ - sdStart(&COM1, NULL); + sdStart(&SD1, NULL); /* * If a button is pressed during the reset then the blinking leds threads * are not started in order to make accurate benchmarks. */ - if ((palReadPort(IOPORT_A) & BOTH_BUTTONS) == BOTH_BUTTONS) { + if ((palReadPort(IOPORT1) & BOTH_BUTTONS) == BOTH_BUTTONS) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); } diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 98ff2a23b..aba532544 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -43,7 +43,7 @@ void InitMMC(void) { void tmrfunc(void *par) { if (cnt) { - if (!palReadPad(IOPORT_B, PB_CP1)) { + if (!palReadPad(IOPORT2, PB_CP1)) { if (!--cnt) chEvtBroadcastI(&MMCInsertEventSource); } @@ -51,7 +51,7 @@ void tmrfunc(void *par) { cnt = POLLING_INTERVAL; } else { - if (palReadPad(IOPORT_B, PB_CP1)) { + if (palReadPad(IOPORT2, PB_CP1)) { cnt = POLLING_INTERVAL; chEvtBroadcastI(&MMCRemoveEventSource); } diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index d1f78f7e8..ca2fa842b 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -31,9 +31,9 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { while (TRUE) { - palClearPad(IOPORT_C, GPIOC_LED); + palClearPad(IOPORT3, GPIOC_LED); chThdSleepMilliseconds(500); - palSetPad(IOPORT_C, GPIOC_LED); + palSetPad(IOPORT3, GPIOC_LED); chThdSleepMilliseconds(500); } return 0; @@ -46,9 +46,9 @@ static msg_t Thread1(void *arg) { int main(int argc, char **argv) { /* - * Activates the communication port 2 using the driver default configuration. + * Activates the serial driver 2 using the driver default configuration. */ - sdStart(&COM2, NULL); + sdStart(&SD2, NULL); /* * Creates the blinker thread. @@ -60,8 +60,8 @@ int main(int argc, char **argv) { * sleeping in a loop and check the button state. */ while (TRUE) { - if (palReadPad(IOPORT_A, GPIOA_BUTTON)) - TestThread(&COM2); + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD2); chThdSleepMilliseconds(500); } return 0; diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index d52f2bb07..02622e817 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -31,9 +31,9 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - palSetPad(IOPORT_F, P6_O_LED); + palSetPad(IOPORT6, P6_O_LED); chThdSleepMilliseconds(500); - palClearPad(IOPORT_F, P6_O_LED); + palClearPad(IOPORT6, P6_O_LED); chThdSleepMilliseconds(500); } return 0; @@ -50,9 +50,9 @@ int main(int argc, char **argv) { hwinit(); /* - * Activates the communication port 1 using the driver default configuration. + * Activates the serial driver 2 using the driver default configuration. */ - sdStart(&COM1, NULL); + sdStart(&SD1, NULL); /* * The main() function becomes a thread here then the interrupts are @@ -70,8 +70,8 @@ int main(int argc, char **argv) { * sleeping in a loop. */ while (TRUE) { - if (!palReadPad(IOPORT_F, P6_I_BUTTON)) - TestThread(&COM1); + if (!palReadPad(IOPORT6, P6_I_BUTTON)) + TestThread(&SD1); chThdSleepMilliseconds(500); } return 0; -- cgit v1.2.3 From 553f23ae74bee0bceb4d2b7e52e46699df2f6425 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 28 Aug 2009 15:11:16 +0000 Subject: Modified linker scripts for GCC 4.4.1. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1113 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/ch.ld | 86 +++++++++++++++++++----------------- demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld | 86 +++++++++++++++++++----------------- demos/ARM7-LPC214x-G++/ch.ld | 5 +++ demos/ARM7-LPC214x-GCC-minimal/ch.ld | 5 +++ demos/ARM7-LPC214x-GCC/ch.ld | 5 +++ demos/ARMCM3-STM32F103-GCC/ch.ld | 5 +++ 6 files changed, 110 insertions(+), 82 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 643453cd8..944a7f29d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -30,8 +30,8 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { - flash : org = 0x100000, len = 256k - ram : org = 0x200020, len = 64k - 0x20 + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 } __ram_start__ = ORIGIN(ram); @@ -42,49 +42,53 @@ SECTIONS { . = 0; - .text : + .text : ALIGN(16) SUBALIGN(16) { - _text = .; - KEEP(*(vectors)); - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash - _textdata = _etext; + _textdata = _etext; - .data : - { - _data = .; - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } } PROVIDE(end = .); diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld index 643453cd8..944a7f29d 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld @@ -30,8 +30,8 @@ __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_si MEMORY { - flash : org = 0x100000, len = 256k - ram : org = 0x200020, len = 64k - 0x20 + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 } __ram_start__ = ORIGIN(ram); @@ -42,49 +42,53 @@ SECTIONS { . = 0; - .text : + .text : ALIGN(16) SUBALIGN(16) { - _text = .; - KEEP(*(vectors)); - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash - _textdata = _etext; + _textdata = _etext; - .data : - { - _data = .; - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index a79694e7b..15d0fbe2f 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -87,6 +87,11 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram + + /DISCARD/ : + { + *(.eh_*) + } } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld index 45bde5dea..9dd4d388e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ b/demos/ARM7-LPC214x-GCC-minimal/ch.ld @@ -87,6 +87,11 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram + + /DISCARD/ : + { + *(.eh_*) + } } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index 45bde5dea..9dd4d388e 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -87,6 +87,11 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram + + /DISCARD/ : + { + *(.eh_*) + } } PROVIDE(end = .); diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index 90a0093fe..22d5546a1 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -80,6 +80,11 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram + + /DISCARD/ : + { + *(.eh_*) + } } PROVIDE(end = .); -- cgit v1.2.3 From ea88c85382def65d870706b593f095d8ba1d76bd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Aug 2009 09:09:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1139 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 74d231e8d..99d5b065d 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -67,8 +67,8 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ../../os/io/pal.c \ ../../os/io/serial.c \ - ../../os/io/platforms/STM32F103/pal_lld.c \ - ../../os/io/platforms/STM32F103/serial_lld.c \ + ../../os/io/platforms/STM32/pal_lld.c \ + ../../os/io/platforms/STM32/serial_lld.c \ ../../os/various/evtimer.c \ board.c main.c @@ -99,11 +99,11 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ../../ports/ARMCM3-STM32F103/vectors.s + ../../os/ports/GCC/ARMCM3/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ../../os/io \ - ../../os/io/platforms/STM32F103 \ + ../../os/io/platforms/STM32 \ ../../os/various \ ./stm32lib/inc -- cgit v1.2.3 From 68a37ee345f3f8f3bdcc8199a73a84a475efae7e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Aug 2009 14:14:09 +0000 Subject: New serial driver for Win32 demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1142 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 7 ++- demos/Win32-MinGW/chcore.c | 17 ++----- demos/Win32-MinGW/main.c | 108 +++++++++++++++++++++++---------------------- 3 files changed, 63 insertions(+), 69 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 616b46015..50b2a0af2 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -63,14 +63,17 @@ include ../../test/test.mk SRC = ${KERNSRC} \ ${TESTSRC} \ chcore.c \ - ../../os/ports/GCC/win32/simcom.c \ + ../../os/io/serial.c \ + ../../os/io/platforms/Win32/serial_lld.c \ main.c # List ASM source files here ASRC = # List all user directories here -UINCDIR = $(KERNINC) $(TESTINC) +UINCDIR = $(KERNINC) $(TESTINC) \ + ../../os/io \ + ../../os/io/platforms/Win32 # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 081a02753..70742d3c4 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -28,19 +28,11 @@ */ #include +#include static LARGE_INTEGER nextcnt; static LARGE_INTEGER slice; -void InitSimCom1(void); -void InitSimCom2(void); -BOOL Com1ConnInterruptSimCom(void); -BOOL Com2ConnInterruptSimCom(void); -BOOL Com1InInterruptSimCom(void); -BOOL Com2InInterruptSimCom(void); -BOOL Com1OutInterruptSimCom(void); -BOOL Com2OutInterruptSimCom(void); - /* * Simulated HW initialization. */ @@ -64,8 +56,7 @@ void InitCore(void) { QueryPerformanceCounter(&nextcnt); nextcnt.QuadPart += slice.QuadPart; - InitSimCom1(); - InitSimCom2(); + sdInit(); fflush(stdout); } @@ -75,9 +66,7 @@ void InitCore(void) { void ChkIntSources(void) { LARGE_INTEGER n; - if (Com1InInterruptSimCom() || Com2InInterruptSimCom() || - Com1OutInterruptSimCom() || Com2OutInterruptSimCom() || - Com1ConnInterruptSimCom() || Com2ConnInterruptSimCom()) { + if (sd_lld_interrupt_pending()) { if (chSchRescRequiredI()) chSchDoRescheduleI(); return; diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 68dc4eb06..bca8af11b 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -21,6 +21,7 @@ #include #include +#include static uint32_t wdguard; static WORKING_AREA(wdarea, 2048); @@ -34,8 +35,6 @@ static msg_t ConsoleThread(void *arg); msg_t TestThread(void *p); -extern FullDuplexDriver COM1, COM2; - #define cprint(msg) chMsgSend(cdtp, (msg_t)msg) /* @@ -73,13 +72,13 @@ static msg_t ConsoleThread(void *arg) { return 0; } -static void PrintLineFDD(FullDuplexDriver *sd, char *msg) { +static void PrintLineSD(SerialDriver *sd, char *msg) { while (*msg) - chFDDPut(sd, *msg++); + sdPut(sd, *msg++); } -static bool_t GetLineFDD(FullDuplexDriver *sd, char *line, int size) { +static bool_t GetLineFDD(SerialDriver *sd, char *line, int size) { char *p = line; while (TRUE) { @@ -87,27 +86,27 @@ static bool_t GetLineFDD(FullDuplexDriver *sd, char *line, int size) { if (c < 0) return TRUE; if (c == 4) { - PrintLineFDD(sd, "^D\r\n"); + PrintLineSD(sd, "^D\r\n"); return TRUE; } if (c == 8) { if (p != line) { - chFDDPut(sd, (uint8_t)c); - chFDDPut(sd, 0x20); - chFDDPut(sd, (uint8_t)c); + sdPut(sd, (uint8_t)c); + sdPut(sd, 0x20); + sdPut(sd, (uint8_t)c); p--; } continue; } if (c == '\r') { - PrintLineFDD(sd, "\r\n"); + PrintLineSD(sd, "\r\n"); *p = 0; return FALSE; } if (c < 0x20) continue; if (p < line + size - 1) { - chFDDPut(sd, (uint8_t)c); + sdPut(sd, (uint8_t)c); *p++ = (uint8_t)c; } } @@ -120,19 +119,19 @@ static bool_t GetLineFDD(FullDuplexDriver *sd, char *line, int size) { static msg_t HelloWorldThread(void *arg) { int i; short c; - FullDuplexDriver *sd = (FullDuplexDriver *)arg; + SerialDriver *sd = (SerialDriver *)arg; for (i = 0; i < 10; i++) { - PrintLineFDD(sd, "Hello World\r\n"); - c = chFDDGetTimeout(sd, 333); + PrintLineSD(sd, "Hello World\r\n"); + c = sdGetTimeout(sd, 333); switch (c) { case Q_TIMEOUT: continue; case Q_RESET: return 1; case 3: - PrintLineFDD(sd, "^C\r\n"); + PrintLineSD(sd, "^C\r\n"); return 0; default: chThdSleep(333); @@ -141,12 +140,12 @@ static msg_t HelloWorldThread(void *arg) { return 0; } -static bool_t checkend(FullDuplexDriver *sd) { +static bool_t checkend(SerialDriver *sd) { char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ if (lp) { - PrintLineFDD(sd, lp); - PrintLineFDD(sd, " ?\r\n"); + PrintLineSD(sd, lp); + PrintLineSD(sd, " ?\r\n"); return TRUE; } return FALSE; @@ -157,7 +156,7 @@ static bool_t checkend(FullDuplexDriver *sd) { * standard input and output. It recognizes few simple commands. */ static msg_t ShellThread(void *arg) { - FullDuplexDriver *sd = (FullDuplexDriver *)arg; + SerialDriver *sd = (SerialDriver *)arg; char *lp, line[64]; Thread *tp; WORKING_AREA(tarea, 2048); @@ -166,11 +165,11 @@ static msg_t ShellThread(void *arg) { chIQResetI(&sd->d2.iqueue); chOQResetI(&sd->d2.oqueue); chSysUnlock(); - PrintLineFDD(sd, "ChibiOS/RT Command Shell\r\n\n"); + PrintLineSD(sd, "ChibiOS/RT Command Shell\r\n\n"); while (TRUE) { - PrintLineFDD(sd, "ch> "); + PrintLineSD(sd, "ch> "); if (GetLineFDD(sd, line, sizeof(line))) { - PrintLineFDD(sd, "\nlogout"); + PrintLineSD(sd, "\nlogout"); break; } lp = strtok(line, " \009"); // Note: not thread safe but it is just a demo. @@ -180,24 +179,24 @@ static msg_t ShellThread(void *arg) { (stricmp(lp, "?") == 0)) { if (checkend(sd)) continue; - PrintLineFDD(sd, "Commands:\r\n"); - PrintLineFDD(sd, " help,h,? - This help\r\n"); - PrintLineFDD(sd, " exit - Logout from ChibiOS/RT\r\n"); - PrintLineFDD(sd, " time - Prints the system timer value\r\n"); - PrintLineFDD(sd, " hello - Runs the Hello World demo thread\r\n"); - PrintLineFDD(sd, " test - Runs the System Test thread\r\n"); + PrintLineSD(sd, "Commands:\r\n"); + PrintLineSD(sd, " help,h,? - This help\r\n"); + PrintLineSD(sd, " exit - Logout from ChibiOS/RT\r\n"); + PrintLineSD(sd, " time - Prints the system timer value\r\n"); + PrintLineSD(sd, " hello - Runs the Hello World demo thread\r\n"); + PrintLineSD(sd, " test - Runs the System Test thread\r\n"); } else if (stricmp(lp, "exit") == 0) { if (checkend(sd)) continue; - PrintLineFDD(sd, "\nlogout"); + PrintLineSD(sd, "\nlogout"); break; } else if (stricmp(lp, "time") == 0) { if (checkend(sd)) continue; sprintf(line, "Time: %d\r\n", chTimeNow()); - PrintLineFDD(sd, line); + PrintLineSD(sd, line); } else if (stricmp(lp, "hello") == 0) { if (checkend(sd)) @@ -216,8 +215,8 @@ static msg_t ShellThread(void *arg) { break; // Lost connection while executing the hello thread. } else { - PrintLineFDD(sd, lp); - PrintLineFDD(sd, " ?\r\n"); + PrintLineSD(sd, lp); + PrintLineSD(sd, " ?\r\n"); } } } @@ -229,23 +228,23 @@ static Thread *s1; EventListener s1tel; static void COM1Handler(eventid_t id) { - dflags_t flags; + sdflags_t flags; if (s1 && chThdTerminated(s1)) { s1 = NULL; - cprint("Init: disconnection on COM1\n"); + cprint("Init: disconnection on SD1\n"); } - flags = chFDDGetAndClearFlags(&COM1); + flags = sdGetAndClearFlags(&SD1); if ((flags & SD_CONNECTED) && (s1 == NULL)) { - cprint("Init: connection on COM1\n"); + cprint("Init: connection on SD1\n"); s1 = chThdInit(s1area, sizeof(s1area), - NORMALPRIO, ShellThread, &COM1); + NORMALPRIO, ShellThread, &SD1); chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); chThdResume(s1); } if ((flags & SD_DISCONNECTED) && (s1 != NULL)) { chSysLock(); - chIQResetI(&COM1.d2.iqueue); + chIQResetI(&SD1.d2.iqueue); chSysUnlock(); } } @@ -255,23 +254,23 @@ static Thread *s2; EventListener s2tel; static void COM2Handler(eventid_t id) { - dflags_t flags; + sdflags_t flags; if (s2 && chThdTerminated(s2)) { s2 = NULL; - cprint("Init: disconnection on COM2\n"); + cprint("Init: disconnection on SD2\n"); } - flags = chFDDGetAndClearFlags(&COM2); + flags = sdGetAndClearFlags(&SD2); if ((flags & SD_CONNECTED) && (s2 == NULL)) { - cprint("Init: connection on COM2\n"); + cprint("Init: connection on SD2\n"); s2 = chThdInit(s2area, sizeof(s1area), - NORMALPRIO, ShellThread, &COM2); + NORMALPRIO, ShellThread, &SD2); chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); chThdResume(s2); } if ((flags & SD_DISCONNECTED) && (s2 != NULL)) { chSysLock(); - chIQResetI(&COM2.d2.iqueue); + chIQResetI(&SD2.d2.iqueue); chSysUnlock(); } } @@ -290,19 +289,22 @@ int main(void) { // Startup ChibiOS/RT. chSysInit(); + sdStart(&SD1, NULL); + sdStart(&SD2, NULL); + chThdCreateStatic(wdarea, sizeof(wdarea), NORMALPRIO + 2, WatchdogThread, NULL); cdtp = chThdCreateStatic(cdarea, sizeof(cdarea), NORMALPRIO + 1, ConsoleThread, NULL); - cprint("Console service started on COM1, COM2\n"); - cprint(" - Listening for connections on COM1\n"); - chFDDGetAndClearFlags(&COM1); - chEvtRegister(&COM1.d2.sevent, &c1fel, 0); - cprint(" - Listening for connections on COM2\n"); - chFDDGetAndClearFlags(&COM2); - chEvtRegister(&COM2.d2.sevent, &c2fel, 1); + cprint("Console service started on SD1, SD2\n"); + cprint(" - Listening for connections on SD1\n"); + sdGetAndClearFlags(&SD1); + chEvtRegister(&SD1.d2.sevent, &c1fel, 0); + cprint(" - Listening for connections on SD2\n"); + sdGetAndClearFlags(&SD2); + chEvtRegister(&SD2.d2.sevent, &c2fel, 1); while (!chThdShouldTerminate()) chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); - chEvtUnregister(&COM2.d2.sevent, &c2fel); // Never invoked but this is an example... - chEvtUnregister(&COM1.d2.sevent, &c1fel); // Never invoked but this is an example... + chEvtUnregister(&SD1.d2.sevent, &c2fel); // Never invoked but this is an example... + chEvtUnregister(&SD2.d2.sevent, &c1fel); // Never invoked but this is an example... return 0; } -- cgit v1.2.3 From 07be1f54becd5106876ad7b83057aa5f750a7261 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 30 Aug 2009 16:59:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1144 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chconf.h | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 53ee70cc1..8c124180e 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -232,16 +232,6 @@ #define CH_USE_QUEUES TRUE #endif -/** - * If specified then the full duplex serial driver APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. - */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE -#endif - /** * If specified then the memory heap allocator APIs are included in the kernel. * @note The default is @p TRUE. -- cgit v1.2.3 From 6535195a339ef68e4550a9d2b831e6b640a34401 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 6 Sep 2009 13:29:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1154 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/stm32f10x.h | 7851 ++++++++++++++++++++++++++++++++ 1 file changed, 7851 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-GCC/stm32f10x.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/stm32f10x.h b/demos/ARMCM3-STM32F103-GCC/stm32f10x.h new file mode 100644 index 000000000..e1c8451a6 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/stm32f10x.h @@ -0,0 +1,7851 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.1.0 + * @date 06/19/2009 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, High + * density, Medium density and Low density devices. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + #define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - High density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_Value + #ifdef STM32F10X_CL + #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_Value */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ + | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ + | __STM32F10X_STDPERIPH_VERSION_SUB2) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + +#ifdef STM32F10X_LD + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_MD + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_HD + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_CL + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +//#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +#ifndef __cplusplus +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +#endif + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; +} AFIO_TypeDef; +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ + +#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */ +#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */ +#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */ + +#ifndef STM32F10X_LD + #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD + #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */ +#endif /* STM32F10X_HD */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#ifndef STM32F10X_LD + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_HD */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#ifdef STM32F10X_HD + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */ +#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */ +#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */ + +#ifndef STM32F10X_LD + #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD + #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */ +#endif /* STM32F10X_HD */ + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#ifndef STM32F10X_LD + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_HD */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*! Date: Sun, 13 Sep 2009 12:06:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1162 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 6183fccf5..98265abf8 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -145,4 +145,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../ports/MSP430/rules.mk +include ../../os/ports/GCC/MSP430/rules.mk -- cgit v1.2.3 From 5c75ead6a5bfb30df949f69e2fd3c90c62ac233f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 13 Sep 2009 12:25:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1163 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/chcore.c | 2 +- demos/Win32-MinGW/chcore.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/chcore.c b/demos/GNU-Linux-GCC/chcore.c index e75776e95..e7116edb4 100644 --- a/demos/GNU-Linux-GCC/chcore.c +++ b/demos/GNU-Linux-GCC/chcore.c @@ -61,7 +61,7 @@ void ChkIntSources(void) { pending = FALSE; } - if (chSchRescRequiredI()) + if (chSchIsRescRequiredExI()) chSchDoRescheduleI(); } diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 70742d3c4..95d8b9de8 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -67,7 +67,7 @@ void ChkIntSources(void) { LARGE_INTEGER n; if (sd_lld_interrupt_pending()) { - if (chSchRescRequiredI()) + if (chSchIsRescRequiredExI()) chSchDoRescheduleI(); return; } @@ -77,7 +77,7 @@ void ChkIntSources(void) { if (n.QuadPart > nextcnt.QuadPart) { nextcnt.QuadPart += slice.QuadPart; chSysTimerHandlerI(); - if (chSchRescRequiredI()) + if (chSchIsRescRequiredExI()) chSchDoRescheduleI(); } } -- cgit v1.2.3 From 9b59b00627e0e068d6e63da7f21ee54d709a46c2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Sep 2009 08:00:34 +0000 Subject: Improved makefiles. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1166 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 29 +++++++++---------- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 49 +++++++++++++++++---------------- demos/ARM7-LPC214x-G++/Makefile | 33 +++++++++++----------- demos/ARM7-LPC214x-GCC-minimal/Makefile | 25 +++++++++-------- demos/ARM7-LPC214x-GCC/Makefile | 33 +++++++++++----------- demos/ARMCM3-STM32F103-GCC/Makefile | 27 +++++++++--------- demos/AVR-AT90CANx-GCC/Makefile | 19 +++++++------ demos/AVR-ATmega128-GCC/Makefile | 19 +++++++------ demos/GNU-Linux-GCC/Makefile | 7 +++-- demos/MSP430-MSP430x1611-GCC/Makefile | 25 +++++++++-------- demos/Win32-MinGW/Makefile | 13 +++++---- 11 files changed, 145 insertions(+), 134 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 5a9a7a94a..fa6f56c8c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -43,20 +43,21 @@ PROJECT = ch LDSCRIPT= ch.ld # Imported source files -include ../../os/ports/GCC/ARM7/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/pal.c \ - ../../os/io/serial.c \ - ../../os/io/platforms/AT91SAM7X/pal_lld.c \ - ../../os/io/platforms/AT91SAM7X/serial_lld.c \ - ../../os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -85,13 +86,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ../../os/ports/GCC/ARM7/AT91SAM7X/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/AT91SAM7X \ - ../../os/various \ - ../../os/ports/GCC/ARM7/AT91SAM7X + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X \ + ${CHIBIOS}/os/various \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X # # Project, sources and paths @@ -179,4 +180,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../os/ports/GCC/ARM/rules.mk +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 1484fefb2..9538d20d5 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -43,18 +43,19 @@ PROJECT = ch LDSCRIPT= ch.ld # Imported source files -include ../../os/ports/GCC/ARM7/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # List of the required uIP source files. -USRC = ../../ext/uip-1.0/uip/uip_arp.c \ - ../../ext/uip-1.0/uip/psock.c \ - ../../ext/uip-1.0/uip/uip.c \ - ../../ext/uip-1.0/apps/webserver/httpd.c \ - ../../ext/uip-1.0/apps/webserver/http-strings.c \ - ../../ext/uip-1.0/apps/webserver/httpd-fs.c \ - ../../ext/uip-1.0/apps/webserver/httpd-cgi.c +USRC = ${CHIBIOS}/ext/uip-1.0/uip/uip_arp.c \ + ${CHIBIOS}/ext/uip-1.0/uip/psock.c \ + ${CHIBIOS}/ext/uip-1.0/uip/uip.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/http-strings.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-fs.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-cgi.c # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -62,13 +63,13 @@ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ ${USRC} \ - ../../os/io/pal.c \ - ../../os/io/serial.c \ - ../../os/io/platforms/AT91SAM7X/pal_lld.c \ - ../../os/io/platforms/AT91SAM7X/serial_lld.c \ - ../../os/io/platforms/AT91SAM7X/sam7x_emac.c \ - ../../os/io/platforms/AT91SAM7X/at91lib/aic.c \ - ../../os/various/evtimer.c \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/sam7x_emac.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/various/evtimer.c \ web/webthread.c \ board.c main.c @@ -98,14 +99,14 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ../../os/ports/GCC/ARM7/AT91SAM7X/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/AT91SAM7X \ - ../../os/various \ - ../../os/ports/GCC/ARM7/AT91SAM7X \ - ./web ../../ext/uip-1.0/uip ../../ext/uip-1.0/apps/webserver + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X \ + ${CHIBIOS}/os/various \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X \ + ./web ${CHIBIOS}/ext/uip-1.0/uip ${CHIBIOS}/ext/uip-1.0/apps/webserver # # Project, sources and paths @@ -193,4 +194,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../os/ports/GCC/ARM/rules.mk +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 1940c8509..3b0a8bee3 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -43,26 +43,27 @@ PROJECT = ch LDSCRIPT = ch.ld # Imported source files -include ../../os/ports/GCC/ARM7/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/pal.c \ - ../../os/io/serial.c \ - ../../os/io/platforms/LPC214x/pal_lld.c \ - ../../os/io/platforms/LPC214x/serial_lld.c \ - ../../os/io/platforms/LPC214x/vic.c \ - ../../os/various/evtimer.c \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/vic.c \ + ${CHIBIOS}/os/various/evtimer.c \ board.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CPPSRC = ../../os/various/ch.cpp main.cpp +CPPSRC = ${CHIBIOS}/os/various/ch.cpp main.cpp # C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler @@ -86,13 +87,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ../../os/ports/GCC/ARM7/LPC214x/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/LPC214x \ - ../../os/various \ - ../../os/ports/GCC/ARM7/LPC214x + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/LPC214x \ + ${CHIBIOS}/os/various \ + ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x # # Project, sources and paths @@ -180,4 +181,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../os/ports/GCC/ARM/rules.mk +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 23b74db74..5315948af 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -43,18 +43,19 @@ PROJECT = ch LDSCRIPT = ch.ld # Imported source files -include ../../os/ports/GCC/ARM7/port.mk -include ../../os/kernel/kernel.mk -#include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +#include ${CHIBIOS}/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/pal.c \ - ../../os/io/platforms/LPC214x/pal_lld.c \ - ../../os/io/platforms/LPC214x/vic.c \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/vic.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -83,13 +84,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ../../os/ports/GCC/ARM7/LPC214x/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/LPC214x \ - ../../os/various \ - ../../os/ports/GCC/ARM7/LPC214x + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/LPC214x \ + ${CHIBIOS}/os/various \ + ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x # # Project, sources and paths @@ -177,4 +178,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../os/ports/GCC/ARM/rules.mk +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 67b082af3..54b1e0ffd 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -43,22 +43,23 @@ PROJECT = ch LDSCRIPT = ch.ld # Imported source files -include ../../os/ports/GCC/ARM7/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/pal.c \ - ../../os/io/serial.c \ - ../../os/io/platforms/LPC214x/pal_lld.c \ - ../../os/io/platforms/LPC214x/serial_lld.c \ - ../../os/io/platforms/LPC214x/vic.c \ - ../../os/io/platforms/LPC214x/lpc214x_ssp.c \ - ../../os/various/evtimer.c \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/vic.c \ + ${CHIBIOS}/os/io/platforms/LPC214x/lpc214x_ssp.c \ + ${CHIBIOS}/os/various/evtimer.c \ board.c buzzer.c mmcsd.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -87,13 +88,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ../../os/ports/GCC/ARM7/LPC214x/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/LPC214x \ - ../../os/various \ - ../../os/ports/GCC/ARM7/LPC214x + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/LPC214x \ + ${CHIBIOS}/os/various \ + ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x # # Project, sources and paths @@ -181,4 +182,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../os/ports/GCC/ARM/rules.mk +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 99d5b065d..ca12fd05d 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -56,20 +56,21 @@ PROJECT = ch LDSCRIPT= ch.ld # Imported source files -include ../../os/ports/GCC/ARMCM3/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/pal.c \ - ../../os/io/serial.c \ - ../../os/io/platforms/STM32/pal_lld.c \ - ../../os/io/platforms/STM32/serial_lld.c \ - ../../os/various/evtimer.c \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/various/evtimer.c \ board.c main.c @@ -99,12 +100,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ../../os/ports/GCC/ARMCM3/STM32F103/vectors.s + ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/STM32 \ - ../../os/various \ + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/STM32 \ + ${CHIBIOS}/os/various \ ./stm32lib/inc # @@ -199,4 +200,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include ../../os/ports/GCC/ARM/rules.mk +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index 30ae2aad0..5754a6371 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -80,18 +80,19 @@ OBJDIR = . # Imported source files -include ../../os/ports/GCC/AVR/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/AVR/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # List C source files here. (C dependencies are automatically generated.) SRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/serial.c \ - ../../os/io/platforms/AVR/serial_lld.c \ - ../../os/various/evtimer.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/AVR/serial_lld.c \ + ${CHIBIOS}/os/various/evtimer.c \ board.c main.c @@ -127,9 +128,9 @@ DEBUG = dwarf-2 # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/AVR \ - ../../os/various + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/AVR \ + ${CHIBIOS}/os/various # Compiler flag to set the C Standard level. diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index c56520b08..dcc7f7beb 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -80,18 +80,19 @@ OBJDIR = . # Imported source files -include ../../os/ports/GCC/AVR/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/AVR/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # List C source files here. (C dependencies are automatically generated.) SRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/serial.c \ - ../../os/io/platforms/AVR/serial_lld.c \ - ../../os/various/evtimer.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/AVR/serial_lld.c \ + ${CHIBIOS}/os/various/evtimer.c \ lcd.c board.c main.c @@ -127,9 +128,9 @@ DEBUG = dwarf-2 # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/AVR \ - ../../os/various + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/AVR \ + ${CHIBIOS}/os/various # Compiler flag to set the C Standard level. diff --git a/demos/GNU-Linux-GCC/Makefile b/demos/GNU-Linux-GCC/Makefile index 5483d4448..51a8b25db 100644 --- a/demos/GNU-Linux-GCC/Makefile +++ b/demos/GNU-Linux-GCC/Makefile @@ -56,8 +56,9 @@ UDEFS = UADEFS = # Imported source files -include ../../src/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/src/kernel.mk +include ${CHIBIOS}/test/test.mk # List C source files here SRC = chcore.c main.c \ @@ -68,7 +69,7 @@ SRC = chcore.c main.c \ ASRC = # List all user directories here -UINCDIR = ../../src/include +UINCDIR = ${CHIBIOS}/src/include # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 98265abf8..dc3747875 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -39,19 +39,20 @@ PROJECT = ch LDSCRIPT = mspgcc/msp430x1611.x # Imported source files -include ../../os/ports/GCC/MSP430/port.mk -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/MSP430/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # C sources here. CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ../../os/io/pal.c \ - ../../os/io/serial.c \ - ../../os/io/platforms/MSP430/pal_lld.c \ - ../../os/io/platforms/MSP430/serial_lld.c \ - ../../os/various/evtimer.c \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/MSP430/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/MSP430/serial_lld.c \ + ${CHIBIOS}/os/various/evtimer.c \ board.c main.c # C++ sources here. @@ -61,9 +62,9 @@ CPPSRC = ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/MSP430 \ - ../../os/various + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/MSP430 \ + ${CHIBIOS}/os/various # # Project, sources and paths @@ -145,4 +146,4 @@ ULIBS = # End of user defines ############################################################################## -include ../../os/ports/GCC/MSP430/rules.mk +include ${CHIBIOS}/os/ports/GCC/MSP430/rules.mk diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 50b2a0af2..f700ce159 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -56,15 +56,16 @@ UDEFS = UADEFS = # Imported source files -include ../../os/kernel/kernel.mk -include ../../test/test.mk +CHIBIOS = ../.. +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk # List C source files here SRC = ${KERNSRC} \ ${TESTSRC} \ chcore.c \ - ../../os/io/serial.c \ - ../../os/io/platforms/Win32/serial_lld.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/Win32/serial_lld.c \ main.c # List ASM source files here @@ -72,8 +73,8 @@ ASRC = # List all user directories here UINCDIR = $(KERNINC) $(TESTINC) \ - ../../os/io \ - ../../os/io/platforms/Win32 + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/Win32 # List the user directory to look for the libraries here ULIBDIR = -- cgit v1.2.3 From e8bbaf0cbaf3213f17eba846b9beac9741e16ba4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Sep 2009 16:17:37 +0000 Subject: lwIP related work. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1173 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 191 +++ demos/ARM7-AT91SAM7X-LWIP-GCC/board.c | 180 ++ demos/ARM7-AT91SAM7X-LWIP-GCC/board.h | 78 + demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld | 98 ++ demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 379 ++++ demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h | 73 + demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h | 59 + demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 159 ++ demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h | 91 + demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk | 44 + .../lwip/netif/ethernetif.c | 333 ++++ demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h | 1801 ++++++++++++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 67 + demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt | 28 + 14 files changed, 3581 insertions(+) create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/board.c create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/board.h create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/main.c create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile new file mode 100644 index 000000000..7388fd754 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -0,0 +1,191 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk +include ./lwip/lwip.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${LWNETIFSRC} \ + ${LWCORESRC} \ + ${LWIPV4SRC} \ + ${LWAPISRC} \ + ./lwip/arch/sys_arch.c \ + ./lwip/netif/ethernetif.c \ + board.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(LWINC) \ + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X \ + ${CHIBIOS}/os/various \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X \ + ./lwip + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +TRGT = arm-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLWIP_PROVIDE_ERRNO + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c new file mode 100644 index 000000000..31e362845 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c @@ -0,0 +1,180 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include + +#include "board.h" +#include "at91lib/aic.h" + +/* + * FIQ Handler weak symbol defined in vectors.s. + */ +void FiqHandler(void); + +static CH_IRQ_HANDLER(SpuriousHandler) { + + CH_IRQ_PROLOGUE(); + + AT91C_BASE_AIC->AIC_EOICR = 0; + + CH_IRQ_EPILOGUE(); +} + +/* + * SYS IRQ handling here. + */ +static CH_IRQ_HANDLER(SYSIrqHandler) { + + CH_IRQ_PROLOGUE(); + + if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { + (void) AT91C_BASE_PITC->PITC_PIVR; + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + } + AT91C_BASE_AIC->AIC_EOICR = 0; + + CH_IRQ_EPILOGUE(); +} + +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const AT91SAM7XPIOConfig config = +{ + {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, + {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +}; + +/* + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. + */ +void hwinit0(void) { + /* + * Flash Memory: 1 wait state, about 50 cycles in a microsecond. + */ + AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; + + /* + * Watchdog disabled. + */ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + /* + * Enables the main oscillator and waits 56 slow cycles as startup time. + */ + AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) + ; + + /* + * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 + * PLLfreq = 96109714 Hz (rounded) + */ + AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (10 << 8)) | + (AT91C_CKGR_MUL & (72 << 16)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) + ; + + /* + * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) + */ + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) + ; + + /* + * PIO initialization. + */ + palInit(&config); +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { + int i; + + /* + * Default AIC setup, the device drivers will modify it as needed. + */ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; + for (i = 1; i < 31; i++) { + AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; + } + AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; + + /* + * LCD pins setup. + */ + palClearPad(IOPORT2, PIOB_LCD_BL); + palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); + + palSetPad(IOPORT1, PIOA_LCD_RESET); + palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); + + /* + * Joystick and buttons setup. + */ + palSetGroupMode(IOPORT1, + PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | + PIOA_B4_MASK | PIOA_B5_MASK, + PAL_MODE_INPUT); + palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); + + /* + * MMC/SD slot setup. + */ + palSetGroupMode(IOPORT2, + PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, + PAL_MODE_INPUT); + + /* + * PIT Initialization. + */ + AIC_ConfigureIT(AT91C_ID_SYS, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), + SYSIrqHandler); + AIC_EnableIT(AT91C_ID_SYS); + AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + + /* + * Serial driver initialization, RTS/CTS pins enabled for USART0 only. + */ + sdInit(); + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); +} diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h new file mode 100644 index 000000000..c56f50258 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "at91lib/AT91SAM7X256.h" + +#define BOARD_OLIMEX_SAM7_EX256 + +#define CLK 18432000 +#define MCK 48054857 + +/* + * Initial I/O setup. + */ +#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOA_OSR 0x00000000 /* Direction. */ +#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ + +#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOB_OSR 0x00000000 /* Direction. */ +#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ + +/* + * I/O definitions. + */ +#define PIOA_LCD_RESET 2 +#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) +#define PIOA_B1 7 +#define PIOA_B1_MASK (1 << PIOA_B1) +#define PIOA_B2 8 +#define PIOA_B2_MASK (1 << PIOA_B2) +#define PIOA_B3 9 +#define PIOA_B3_MASK (1 << PIOA_B3) +#define PIOA_B4 14 +#define PIOA_B4_MASK (1 << PIOA_B4) +#define PIOA_B5 15 +#define PIOA_B5_MASK (1 << PIOA_B5) +#define PIOA_USB_PUP 25 +#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) +#define PIOA_USB_PR 26 +#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) + +#define PIOB_PHY_PD 18 +#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) +#define PIOB_AUDIO_OUT 19 +#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) +#define PIOB_LCD_BL 20 +#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) +#define PIOB_MMC_WP 22 +#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) +#define PIOB_MMC_CP 23 +#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) +#define PIOB_SW1 24 +#define PIOB_SW1_MASK (1 << PIOB_SW1) +#define PIOB_SW2 25 +#define PIOB_SW2_MASK (1 << PIOB_SW2) +#define PIOB_PHY_IRQ 26 +#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) + +#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld b/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld new file mode 100644 index 000000000..944a7f29d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld @@ -0,0 +1,98 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h new file mode 100644 index 000000000..21ad75bde --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -0,0 +1,379 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file src/templates/chconf.h + * @brief Configuration file template. + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * Debug option, if enabled the context switch circular trace buffer is + * activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add thread custom fields here.*/ \ + void *p_timeouts; \ +}; +#endif + +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add thread initialization code here.*/ \ + currp->p_timeouts = NULL; \ +} +#endif + +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ +} +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h new file mode 100644 index 000000000..f8e120315 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + **** This file incorporates work covered by the following copyright and **** + **** permission notice: **** + + Copyright (c) 2001-2004 Swedish Institute of Computer Science. + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + OF SUCH DAMAGE. + + This file is part of the lwIP TCP/IP stack. + + Author: Adam Dunkels +*/ + +#ifndef __CC_H__ +#define __CC_H__ + +#include + +typedef uint8_t u8_t; +typedef int8_t s8_t; +typedef uint16_t u16_t; +typedef int16_t s16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +typedef uint32_t mem_ptr_t; + +#define LWIP_PLATFORM_DIAG(x) +#define LWIP_PLATFORM_ASSERT(x) { \ + chSysHalt(); \ +} + +#define BYTE_ORDER LITTLE_ENDIAN + +#endif /* __CC_H__ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h new file mode 100644 index 000000000..c6f1d1a90 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h @@ -0,0 +1,59 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + **** This file incorporates work covered by the following copyright and **** + **** permission notice: **** + + Copyright (c) 2001-2004 Swedish Institute of Computer Science. + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + OF SUCH DAMAGE. + + This file is part of the lwIP TCP/IP stack. + + Author: Adam Dunkels +*/ + +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START +#define PERF_STOP(x) + +#endif /* __PERF_H__ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c new file mode 100644 index 000000000..8248eed72 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -0,0 +1,159 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + **** This file incorporates work covered by the following copyright and **** + **** permission notice: **** + + Copyright (c) 2001-2004 Swedish Institute of Computer Science. + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + OF SUCH DAMAGE. + + This file is part of the lwIP TCP/IP stack. + + Author: Adam Dunkels +*/ + +#include + +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/sys.h" + +#include "arch/cc.h" +#include "arch/sys_arch.h" + +static unsigned cnt; + +void sys_init(void) { + + cnt = 0; +} + +sys_sem_t sys_sem_new(u8_t count) { + + sys_sem_t sem = mem_malloc(sizeof(Semaphore)); + chSemInit(sem, (cnt_t)count); + return sem; +} + +void sys_sem_free(sys_sem_t sem) { + + mem_free(sem); +} + +void sys_sem_signal(sys_sem_t sem) { + + chSemSignal(sem); +} + +u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) { + systime_t time; + + chSysLock(); + time = chTimeNow(); + chSemWaitTimeoutS(sem, (systime_t)timeout); + time = chTimeNow() - time; + chSysUnlock(); + return time; +} + +sys_mbox_t sys_mbox_new(int size) { + sys_mbox_t mbox; + + mbox = mem_malloc(sizeof(Mailbox) + sizeof(msg_t) * size); + chMBInit(mbox, (void *)(mbox + 1), size); + return mbox; +} + +void sys_mbox_free(sys_mbox_t mbox) { + + mem_free(mbox); +} + +void sys_mbox_post(sys_mbox_t mbox, void *msg) { + + chMBPost(mbox, (msg_t)msg, TIME_INFINITE); +} + +err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg) { + + if (chMBPost(mbox, (msg_t)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) + return ERR_MEM; + return ERR_OK; +} + +u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) { + + if (chMBFetchS(mbox, (msg_t *)msg, (systime_t)timeout) == RDY_TIMEOUT) + return ERR_MEM; + return ERR_OK; +} + +u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg) { + + if (chMBFetchS(mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) + return ERR_MEM; + return ERR_OK; +} + +struct sys_timeouts *sys_arch_timeouts(void) { + + return (struct sys_timeouts *)&currp->p_timeouts; +} + +sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), + void *arg, int stacksize, int prio) { + size_t wsz = THD_WA_SIZE(stacksize); + void *wsp = mem_malloc(wsz); + if (wsp == NULL) + return NULL; + return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg); +} + +sys_prot_t sys_arch_protect(void) { + + chSysLock(); + return 0; +} + +void sys_arch_unprotect(sys_prot_t pval) { + + chSysUnlock(); +} diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h new file mode 100644 index 000000000..6dd834506 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h @@ -0,0 +1,91 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + **** This file incorporates work covered by the following copyright and **** + **** permission notice: **** + + Copyright (c) 2001-2004 Swedish Institute of Computer Science. + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + OF SUCH DAMAGE. + + This file is part of the lwIP TCP/IP stack. + + Author: Adam Dunkels +*/ + +#include + +#ifndef __SYS_ARCH_H__ +#define __SYS_ARCH_H__ + +typedef Semaphore * sys_sem_t; +typedef void * sys_mbox_t; +typedef Thread * sys_thread_t; +typedef int sys_prot_t; + +#define SYS_MBOX_NULL (void *)0 +#define SYS_THREAD_NULL (Thread *)0 +#define SYS_SEM_NULL (Semaphore *)0 + +void sys_init(void); +sys_sem_t sys_sem_new(u8_t count); +void sys_sem_free(sys_sem_t sem); +void sys_sem_signal(sys_sem_t sem); +u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); + +sys_mbox_t sys_mbox_new(int size); +void sys_mbox_free(sys_mbox_t mbox); +void sys_mbox_post(sys_mbox_t mbox, void *msg); +err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg); +u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); +u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg); + +struct sys_timeouts *sys_arch_timeouts(void); + +sys_thread_t sys_thread_new(char *name, + void (* thread)(void *arg), + void *arg, + int stacksize, + int prio); + +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#endif /* __SYS_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk new file mode 100644 index 000000000..99a046b9d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwip.mk @@ -0,0 +1,44 @@ +# List of the required lwIP files. +LWNETIFSRC = \ + ${CHIBIOS}/ext/lwip/src/netif/etharp.c \ + ${CHIBIOS}/ext/lwip/src/netif/loopif.c + +LWCORESRC = \ + ${CHIBIOS}/ext/lwip/src/core/dhcp.c \ + ${CHIBIOS}/ext/lwip/src/core/dns.c \ + ${CHIBIOS}/ext/lwip/src/core/init.c \ + ${CHIBIOS}/ext/lwip/src/core/mem.c \ + ${CHIBIOS}/ext/lwip/src/core/memp.c \ + ${CHIBIOS}/ext/lwip/src/core/netif.c \ + ${CHIBIOS}/ext/lwip/src/core/pbuf.c \ + ${CHIBIOS}/ext/lwip/src/core/raw.c \ + ${CHIBIOS}/ext/lwip/src/core/stats.c \ + ${CHIBIOS}/ext/lwip/src/core/sys.c \ + ${CHIBIOS}/ext/lwip/src/core/tcp.c \ + ${CHIBIOS}/ext/lwip/src/core/tcp_in.c \ + ${CHIBIOS}/ext/lwip/src/core/tcp_out.c \ + ${CHIBIOS}/ext/lwip/src/core/udp.c + +LWIPV4SRC = \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/autoip.c \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/icmp.c \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/igmp.c \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/inet.c \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/inet_chksum.c \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/ip.c \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/ip_addr.c \ + ${CHIBIOS}/ext/lwip/src/core/ipv4/ip_frag.c + +LWAPISRC = \ + ${CHIBIOS}/ext/lwip/src/api/api_lib.c \ + ${CHIBIOS}/ext/lwip/src/api/api_msg.c \ + ${CHIBIOS}/ext/lwip/src/api/err.c \ + ${CHIBIOS}/ext/lwip/src/api/netbuf.c \ + ${CHIBIOS}/ext/lwip/src/api/netdb.c \ + ${CHIBIOS}/ext/lwip/src/api/netifapi.c \ + ${CHIBIOS}/ext/lwip/src/api/sockets.c \ + ${CHIBIOS}/ext/lwip/src/api/tcpip.c + +LWINC = \ + ${CHIBIOS}/ext/lwip/src/include \ + ${CHIBIOS}/ext/lwip/src/include/ipv4 diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c new file mode 100644 index 000000000..5716f6e58 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c @@ -0,0 +1,333 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + **** This file incorporates work covered by the following copyright and **** + **** permission notice: **** + + Copyright (c) 2001-2004 Swedish Institute of Computer Science. + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + OF SUCH DAMAGE. + + This file is part of the lwIP TCP/IP stack. + + Author: Adam Dunkels +*/ + +/** + * @file + * Ethernet Interface Skeleton + * + */ + +/* + * This file is a skeleton for developing Ethernet network interface + * drivers for lwIP. Add code to the low_level functions and do a + * search-and-replace for the word "ethernetif" to replace it with + * something that better describes your network interface. + */ + +#include "lwip/opt.h" + +#if 1 /* don't build, this is only a skeleton, see previous comment */ + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include +#include +#include "netif/etharp.h" +#include "netif/ppp_oe.h" + +/* Define those to better describe your network interface. */ +#define IFNAME0 'e' +#define IFNAME1 'n' + +/** + * Helper struct to hold private data used to operate your ethernet interface. + * Keeping the ethernet address of the MAC in this struct is not necessary + * as it is already kept in the struct netif. + * But this is only an example, anyway... + */ +struct ethernetif { + struct eth_addr *ethaddr; + /* Add whatever per-interface state that is needed here. */ +}; + +/* Forward declarations. */ +static void ethernetif_input(struct netif *netif); + +/** + * In this function, the hardware should be initialized. + * Called from ethernetif_init(). + * + * @param netif the already initialized lwip network interface structure + * for this ethernetif + */ +static void +low_level_init(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + + /* set MAC hardware address length */ + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* set MAC hardware address */ +////////// netif->hwaddr[0] = ; +////////// ... +////////// netif->hwaddr[5] = ; + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* device capabilities */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* Do whatever else is needed to initialize interface. */ +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param netif the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become availale since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ + +static err_t +low_level_output(struct netif *netif, struct pbuf *p) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *q; + +////////// initiate transfer(); + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + for(q = p; q != NULL; q = q->next) { + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ +////////// send data from(q->payload, q->len); + } + +////////// signal that packet should be sent(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.xmit); + + return ERR_OK; +} + +/** + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf * +low_level_input(struct netif *netif) +{ + struct ethernetif *ethernetif = netif->state; + struct pbuf *p, *q; + u16_t len; + + /* Obtain the size of the packet and put it into the "len" + variable. */ +////////// len = ; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* We iterate over the pbuf chain until we have read the entire + * packet into the pbuf. */ + for(q = p; q != NULL; q = q->next) { + /* Read enough bytes to fill this pbuf in the chain. The + * available data in the pbuf is given by the q->len + * variable. */ +////////// read data into(q->payload, q->len); + } +////////// acknowledge that packet has been read(); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.recv); + } else { +////////// drop packet(); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + } + + return p; +} + +/** + * This function should be called when a packet is ready to be read + * from the interface. It uses the function low_level_input() that + * should handle the actual reception of bytes from the network + * interface. Then the type of the received packet is determined and + * the appropriate input function is called. + * + * @param netif the lwip network interface structure for this ethernetif + */ +static void +ethernetif_input(struct netif *netif) +{ + struct ethernetif *ethernetif; + struct eth_hdr *ethhdr; + struct pbuf *p; + + ethernetif = netif->state; + + /* move received packet into a new pbuf */ + p = low_level_input(netif); + /* no packet could be read, silently ignore this */ + if (p == NULL) return; + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + + switch (htons(ethhdr->type)) { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: +#if PPPOE_SUPPORT + /* PPPoE packet? */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: +#endif /* PPPOE_SUPPORT */ + /* full packet send to tcpip_thread to process */ + if (netif->input(p, netif)!=ERR_OK) + { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); + pbuf_free(p); + p = NULL; + } + break; + + default: + pbuf_free(p); + p = NULL; + break; + } +} + +/** + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t +ethernetif_init(struct netif *netif) +{ + struct ethernetif *ethernetif; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + ethernetif = mem_malloc(sizeof(struct ethernetif)); + if (ethernetif == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); + return ERR_MEM; + } + +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + netif->hostname = "lwip"; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, ???); + + netif->state = ethernetif; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + netif->output = etharp_output; + netif->linkoutput = low_level_output; + + ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); + + /* initialize the hardware */ + low_level_init(netif); + + return ERR_OK; +} + +#endif /* 0 */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h new file mode 100644 index 000000000..28f7c6fd2 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h @@ -0,0 +1,1801 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 0 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 0 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of simultaneously IP packets queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT 3 +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Outgoing packets are queued during hardware address + * resolution. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 1 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 1 +#endif + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented. + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 1 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 0 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS use a local buffer if DNS_USES_STATIC_BUF=0, a static one if + DNS_USES_STATIC_BUF=1, or a dynamic one if DNS_USES_STATIC_BUF=2. + The buffer will be of size DNS_MSG_SIZE */ +#ifndef DNS_USES_STATIC_BUF +#define DNS_USES_STATIC_BUF 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND 2048 +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 128, a *very* + * conservative default.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 128 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF 256 +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN (4 * (TCP_SND_BUF/TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than or equal + * to TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable. + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT (TCP_SND_BUF/2) +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. + */ +//#define LWIP_EVENT_API + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN 14 +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 256 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (LOWPRIO) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE 0 +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 0 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO 1 +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppMain thread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppMain" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppMain thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 0 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppMain thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 0 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 0 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR and SO_REUSEPORT options. DO NOT USE! + */ +#ifndef SO_REUSE +#define SO_REUSE 0 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS 1 +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS 1 +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS 1 +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + + +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#define MAXSECRETLEN 256 /* max length of password or secret */ + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +#endif /* __LWIPOPT_H__ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c new file mode 100644 index 000000000..f6c297a41 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include +#include + +#include "board.h" + +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + while (TRUE) { + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + if (!palReadPad(IOPORT2, PIOB_SW1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT2, PIOB_SW2)) + TestThread(&SD1); + } + + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt new file mode 100644 index 000000000..986d5ec7c --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-EX256 board. + +** The Demo ** + +The demo currently just flashes the LCD background using a thread. +The button SW1 prints an "Hello World!" string on COM1, the button SW2 +activates che ChibiOS/RT test suite, output on COM1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/AT91SAM7X256/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com -- cgit v1.2.3 From a1053d5dc1e161f30debbbc12366364d5e2ec26b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Sep 2009 18:39:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1174 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 24 ++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index 8248eed72..414b434a6 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -88,8 +88,10 @@ u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) { chSysLock(); time = chTimeNow(); - chSemWaitTimeoutS(sem, (systime_t)timeout); - time = chTimeNow() - time; + if (chSemWaitTimeoutS(sem, (systime_t)timeout) != RDY_OK) + time = SYS_ARCH_TIMEOUT; + else + time = chTimeNow() - time; chSysUnlock(); return time; } @@ -120,17 +122,23 @@ err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg) { } u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) { + systime_t time; - if (chMBFetchS(mbox, (msg_t *)msg, (systime_t)timeout) == RDY_TIMEOUT) - return ERR_MEM; - return ERR_OK; + chSysLock(); + time = chTimeNow(); + if (chMBFetchS(mbox, (msg_t *)msg, (systime_t)timeout) != RDY_OK) + time = SYS_ARCH_TIMEOUT; + else + time = chTimeNow() - time; + chSysUnlock(); + return time; } u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg) { - if (chMBFetchS(mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) - return ERR_MEM; - return ERR_OK; + if (chMBFetch(mbox, (msg_t *)msg, TIME_IMMEDIATE) == RDY_TIMEOUT) + return SYS_MBOX_EMPTY; + return 0; } struct sys_timeouts *sys_arch_timeouts(void) { -- cgit v1.2.3 From 0843aa68483429a1ad69d8a1c09190ade3de2987 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Sep 2009 18:42:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1175 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index 414b434a6..ae3e1f73a 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -59,11 +59,8 @@ #include "arch/cc.h" #include "arch/sys_arch.h" -static unsigned cnt; - void sys_init(void) { - cnt = 0; } sys_sem_t sys_sem_new(u8_t count) { -- cgit v1.2.3 From c9bfcaa15ec3d03ee088ecfa5cf6cf82e718cb38 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 27 Sep 2009 18:48:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1192 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../lwip/netif/ethernetif.c | 130 +++++++++------------ demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 6 +- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 6 +- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 32 ++--- 5 files changed, 84 insertions(+), 92 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c index 5716f6e58..ccd7bd67f 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c @@ -1,61 +1,41 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ -/* - **** This file incorporates work covered by the following copyright and **** - **** permission notice: **** - - Copyright (c) 2001-2004 Swedish Institute of Computer Science. - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. The name of the author may not be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - - This file is part of the lwIP TCP/IP stack. - - Author: Adam Dunkels -*/ - /** * @file * Ethernet Interface Skeleton * */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + /* * This file is a skeleton for developing Ethernet network interface * drivers for lwIP. Add code to the low_level functions and do a @@ -65,7 +45,7 @@ #include "lwip/opt.h" -#if 1 /* don't build, this is only a skeleton, see previous comment */ +#if 0 /* don't build, this is only a skeleton, see previous comment */ #include "lwip/def.h" #include "lwip/mem.h" @@ -105,23 +85,23 @@ static void low_level_init(struct netif *netif) { struct ethernetif *ethernetif = netif->state; - + /* set MAC hardware address length */ netif->hwaddr_len = ETHARP_HWADDR_LEN; /* set MAC hardware address */ -////////// netif->hwaddr[0] = ; -////////// ... -////////// netif->hwaddr[5] = ; + netif->hwaddr[0] = ; + ... + netif->hwaddr[5] = ; /* maximum transfer unit */ netif->mtu = 1500; - + /* device capabilities */ /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; - - /* Do whatever else is needed to initialize interface. */ + + /* Do whatever else is needed to initialize interface. */ } /** @@ -146,8 +126,8 @@ low_level_output(struct netif *netif, struct pbuf *p) struct ethernetif *ethernetif = netif->state; struct pbuf *q; -////////// initiate transfer(); - + initiate transfer(); + #if ETH_PAD_SIZE pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ #endif @@ -156,15 +136,15 @@ low_level_output(struct netif *netif, struct pbuf *p) /* Send the data from the pbuf to the interface, one pbuf at a time. The size of the data in each pbuf is kept in the ->len variable. */ -////////// send data from(q->payload, q->len); + send data from(q->payload, q->len); } -////////// signal that packet should be sent(); + signal that packet should be sent(); #if ETH_PAD_SIZE pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ #endif - + LINK_STATS_INC(link.xmit); return ERR_OK; @@ -187,7 +167,7 @@ low_level_input(struct netif *netif) /* Obtain the size of the packet and put it into the "len" variable. */ -////////// len = ; + len = ; #if ETH_PAD_SIZE len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ @@ -195,7 +175,7 @@ low_level_input(struct netif *netif) /* We allocate a pbuf chain of pbufs from the pool. */ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - + if (p != NULL) { #if ETH_PAD_SIZE @@ -208,9 +188,9 @@ low_level_input(struct netif *netif) /* Read enough bytes to fill this pbuf in the chain. The * available data in the pbuf is given by the q->len * variable. */ -////////// read data into(q->payload, q->len); + read data into(q->payload, q->len); } -////////// acknowledge that packet has been read(); + acknowledge that packet has been read(); #if ETH_PAD_SIZE pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ @@ -218,12 +198,12 @@ low_level_input(struct netif *netif) LINK_STATS_INC(link.recv); } else { -////////// drop packet(); + drop packet(); LINK_STATS_INC(link.memerr); LINK_STATS_INC(link.drop); } - return p; + return p; } /** @@ -293,7 +273,7 @@ ethernetif_init(struct netif *netif) struct ethernetif *ethernetif; LWIP_ASSERT("netif != NULL", (netif != NULL)); - + ethernetif = mem_malloc(sizeof(struct ethernetif)); if (ethernetif == NULL) { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); @@ -310,7 +290,7 @@ ethernetif_init(struct netif *netif) * The last argument should be replaced with your link speed, in units * of bits per second. */ - NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, ???); + NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); netif->state = ethernetif; netif->name[0] = IFNAME0; @@ -321,9 +301,9 @@ ethernetif_init(struct netif *netif) * is available...) */ netif->output = etharp_output; netif->linkoutput = low_level_output; - + ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); - + /* initialize the hardware */ low_level_init(netif); diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 9538d20d5..bb4c21c1a 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -65,13 +65,17 @@ CSRC = ${PORTSRC} \ ${USRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/phy.c \ + ${CHIBIOS}/os/io/mac.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/sam7x_emac.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/phy_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ ${CHIBIOS}/os/various/evtimer.c \ web/webthread.c \ board.c main.c +# ${CHIBIOS}/os/io/platforms/AT91SAM7X/sam7x_emac.c \ # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index e57f8bcdc..39136b03e 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -20,7 +20,8 @@ #include #include #include -#include +#include +//#include #include "board.h" #include "at91lib/aic.h" @@ -178,7 +179,8 @@ void hwinit1(void) { /* * EMAC driver initialization. */ - emac_init(AT91C_AIC_PRIOR_HIGHEST - 3); +// emac_init(AT91C_AIC_PRIOR_HIGHEST - 3); + macInit(); /* * ChibiOS/RT initialization. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index adfba225f..e2d3e8cd8 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -28,7 +28,7 @@ #include "web/webthread.h" static WORKING_AREA(waWebThread, 512); -static WORKING_AREA(waThread1, 64); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index d064e1ef3..521a40b04 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include @@ -47,11 +47,11 @@ static const struct uip_eth_addr macaddr = { */ static void network_device_send(void) { int i; - BufDescriptorEntry *bdep; + MACTransmitDescriptor *tdp; for (i = 0; i < SEND_RETRY_MAX; i++) { - if ((bdep = EMACGetTransmitBuffer()) != NULL) { - uint8_t *bp = (uint8_t *)bdep->w1; + if ((tdp = macWaitTransmitDescriptor(&MAC1, uip_len, TIME_IMMEDIATE)) != NULL) { + uint8_t *bp = macGetTransmitBuffer(tdp); if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) memcpy(bp, &uip_buf[0], uip_len); @@ -61,7 +61,7 @@ static void network_device_send(void) { uip_appdata, uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); } - EMACTransmit(bdep, uip_len); + macReleaseTransmitDescriptor(&MAC1, tdp); return; } chThdSleep(SEND_RETRY_INTERVAL); @@ -73,10 +73,16 @@ static void network_device_send(void) { * uIP receive function wrapping the EMAC function. */ static size_t network_device_read(void) { - size_t size = UIP_CONF_BUFFER_SIZE; - if (EMACReceive(uip_buf, &size)) - return size; - return 0; + MACReceiveDescriptor *rdp; + size_t size; + uint8_t *bp; + + if ((rdp = macWaitReceiveDescriptor(&MAC1, &size, TIME_IMMEDIATE)) == NULL) + return 0; + bp = macGetReceiveBuffer(rdp); + memcpy(&uip_buf[0], bp, size); + macReleaseReceiveDescriptor(&MAC1, rdp); + return size; } void clock_init(void) {} @@ -107,7 +113,7 @@ static void PeriodicTimerHandler(eventid_t id) { static void ARPTimerHandler(eventid_t id) { uip_arp_timer(); - (void)EMACGetLinkStatus(); + (void)macPollLinkStatus(&MAC1); } /* @@ -150,7 +156,7 @@ msg_t WebThread(void *p) { /* * Event sources setup. */ - chEvtRegister(&EMACFrameReceived, &el0, FRAME_RECEIVED_ID); + chEvtRegister(macGetReceiveEventSource(&MAC1), &el0, FRAME_RECEIVED_ID); chEvtPend(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ evtInit(&evt1, MS2ST(500)); @@ -164,8 +170,8 @@ msg_t WebThread(void *p) { /* * EMAC settings. */ - EMACSetAddress(&macaddr.addr[0]); - (void)EMACGetLinkStatus(); + macSetAddress(&MAC1, &macaddr.addr[0]); + (void)macPollLinkStatus(&MAC1); /* * uIP initialization. -- cgit v1.2.3 From ea9916ae798da3689d64689b88343d26508d137e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 29 Sep 2009 19:29:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1193 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 36 +++++++++++++--------------- 2 files changed, 17 insertions(+), 21 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index bb4c21c1a..345cb3d13 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 521a40b04..986d7fb03 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -47,21 +47,18 @@ static const struct uip_eth_addr macaddr = { */ static void network_device_send(void) { int i; - MACTransmitDescriptor *tdp; + MACTransmitDescriptor td; for (i = 0; i < SEND_RETRY_MAX; i++) { - if ((tdp = macWaitTransmitDescriptor(&MAC1, uip_len, TIME_IMMEDIATE)) != NULL) { - uint8_t *bp = macGetTransmitBuffer(tdp); - + if (macWaitTransmitDescriptor(Ð1, &td, TIME_IMMEDIATE) == RDY_OK) { if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) - memcpy(bp, &uip_buf[0], uip_len); + macWriteTransmitDescriptor(&td, uip_buf, uip_len); else { - memcpy(bp, &uip_buf[0], UIP_LLH_LEN + UIP_TCPIP_HLEN); - memcpy(bp + UIP_LLH_LEN + UIP_TCPIP_HLEN, - uip_appdata, - uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); + macWriteTransmitDescriptor(&td, uip_buf, UIP_LLH_LEN + UIP_TCPIP_HLEN); + macWriteTransmitDescriptor(&td, uip_appdata, + uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); } - macReleaseTransmitDescriptor(&MAC1, tdp); + macReleaseTransmitDescriptor(&td); return; } chThdSleep(SEND_RETRY_INTERVAL); @@ -73,15 +70,14 @@ static void network_device_send(void) { * uIP receive function wrapping the EMAC function. */ static size_t network_device_read(void) { - MACReceiveDescriptor *rdp; + MACReceiveDescriptor rd; size_t size; - uint8_t *bp; - if ((rdp = macWaitReceiveDescriptor(&MAC1, &size, TIME_IMMEDIATE)) == NULL) + if (macWaitReceiveDescriptor(Ð1, &rd, TIME_IMMEDIATE) != RDY_OK) return 0; - bp = macGetReceiveBuffer(rdp); - memcpy(&uip_buf[0], bp, size); - macReleaseReceiveDescriptor(&MAC1, rdp); + size = rd.rd_size; + macReadReceiveDescriptor(&rd, uip_buf, size); + macReleaseReceiveDescriptor(&rd); return size; } @@ -113,7 +109,7 @@ static void PeriodicTimerHandler(eventid_t id) { static void ARPTimerHandler(eventid_t id) { uip_arp_timer(); - (void)macPollLinkStatus(&MAC1); + (void)macPollLinkStatus(Ð1); } /* @@ -156,7 +152,7 @@ msg_t WebThread(void *p) { /* * Event sources setup. */ - chEvtRegister(macGetReceiveEventSource(&MAC1), &el0, FRAME_RECEIVED_ID); + chEvtRegister(macGetReceiveEventSource(Ð1), &el0, FRAME_RECEIVED_ID); chEvtPend(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ evtInit(&evt1, MS2ST(500)); @@ -170,8 +166,8 @@ msg_t WebThread(void *p) { /* * EMAC settings. */ - macSetAddress(&MAC1, &macaddr.addr[0]); - (void)macPollLinkStatus(&MAC1); + macSetAddress(Ð1, &macaddr.addr[0]); + (void)macPollLinkStatus(Ð1); /* * uIP initialization. -- cgit v1.2.3 From 3a397f9f5b3920339a7316e09379bc25dd5195a0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 29 Sep 2009 20:16:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1194 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index 345cb3d13..bb4c21c1a 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From b55631f714a0469962883ac572e1910080de68fa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 30 Sep 2009 18:05:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1195 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile index bb4c21c1a..95d046fef 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile @@ -65,11 +65,11 @@ CSRC = ${PORTSRC} \ ${USRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/phy.c \ + ${CHIBIOS}/os/io/mii.c \ ${CHIBIOS}/os/io/mac.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/phy_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/mii_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ ${CHIBIOS}/os/various/evtimer.c \ -- cgit v1.2.3 From a1892b59a906042a42ef580b11736cc186994baa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 30 Sep 2009 19:41:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1197 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 1 - demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 24 +++++++++--------------- 2 files changed, 9 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index e2d3e8cd8..639af1f46 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -21,7 +21,6 @@ #include #include #include -#include #include "board.h" diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index 986d7fb03..ceb9ebcd1 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -33,8 +33,7 @@ #define IPADDR2 1 #define IPADDR3 20 -#define SEND_RETRY_MAX 10 -#define SEND_RETRY_INTERVAL 2 +#define SEND_TIMEOUT 50 static const struct uip_eth_addr macaddr = { {0xC2, 0xAF, 0x51, 0x03, 0xCF, 0x46} @@ -46,22 +45,17 @@ static const struct uip_eth_addr macaddr = { * uIP send function wrapping the EMAC functions. */ static void network_device_send(void) { - int i; MACTransmitDescriptor td; - for (i = 0; i < SEND_RETRY_MAX; i++) { - if (macWaitTransmitDescriptor(Ð1, &td, TIME_IMMEDIATE) == RDY_OK) { - if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) - macWriteTransmitDescriptor(&td, uip_buf, uip_len); - else { - macWriteTransmitDescriptor(&td, uip_buf, UIP_LLH_LEN + UIP_TCPIP_HLEN); - macWriteTransmitDescriptor(&td, uip_appdata, - uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); - } - macReleaseTransmitDescriptor(&td); - return; + if (macWaitTransmitDescriptor(Ð1, &td, MS2ST(SEND_TIMEOUT)) == RDY_OK) { + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) + macWriteTransmitDescriptor(&td, uip_buf, uip_len); + else { + macWriteTransmitDescriptor(&td, uip_buf, UIP_LLH_LEN + UIP_TCPIP_HLEN); + macWriteTransmitDescriptor(&td, uip_appdata, + uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); } - chThdSleep(SEND_RETRY_INTERVAL); + macReleaseTransmitDescriptor(&td); } /* Dropped... */ } -- cgit v1.2.3 From 9a08941c1f6996357cb8167f95965ff3d009c53d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Oct 2009 06:48:01 +0000 Subject: Fixed lockup in the experimental MAC driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1199 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c index ceb9ebcd1..12c3b8405 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c @@ -102,8 +102,8 @@ static void PeriodicTimerHandler(eventid_t id) { */ static void ARPTimerHandler(eventid_t id) { - uip_arp_timer(); (void)macPollLinkStatus(Ð1); + uip_arp_timer(); } /* -- cgit v1.2.3 From f67bb7f7d80a8c752f8792a42c674355c99ff35a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Oct 2009 07:14:57 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1200 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c index 639af1f46..0474ce008 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c @@ -55,7 +55,7 @@ int main(int argc, char **argv) { * Creates the blinker and web server threads. */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waWebThread, sizeof(waWebThread), NORMALPRIO - 1, WebThread, NULL); + chThdCreateStatic(waWebThread, sizeof(waWebThread), LOWPRIO, WebThread, NULL); /* * Normal main() thread activity. -- cgit v1.2.3 From 2857d0a365f750a9fa0a86d48f3099c97c2b4ddb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Oct 2009 09:45:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1201 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c index 39136b03e..348f4bb99 100644 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c @@ -21,7 +21,6 @@ #include #include #include -//#include #include "board.h" #include "at91lib/aic.h" @@ -179,7 +178,6 @@ void hwinit1(void) { /* * EMAC driver initialization. */ -// emac_init(AT91C_AIC_PRIOR_HIGHEST - 3); macInit(); /* -- cgit v1.2.3 From fdf3ac2d0ab45974c5671cbfb5b6da2188087862 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Oct 2009 15:58:50 +0000 Subject: LWIP related updates. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1202 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 7 +- demos/ARM7-AT91SAM7X-LWIP-GCC/board.c | 6 + demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h | 65 ++--- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h | 65 ++--- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 65 ++--- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h | 65 ++--- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 286 +++++++++++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h | 109 +++++++ .../lwip/netif/ethernetif.c | 313 --------------------- 9 files changed, 539 insertions(+), 442 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h delete mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 7388fd754..e38c35681 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -56,15 +56,20 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/mii.c \ + ${CHIBIOS}/os/io/mac.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/mii_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/various/evtimer.c \ ${LWNETIFSRC} \ ${LWCORESRC} \ ${LWIPV4SRC} \ ${LWAPISRC} \ ./lwip/arch/sys_arch.c \ - ./lwip/netif/ethernetif.c \ + ./lwip/lwipthread.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c index 31e362845..5b95524f8 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "board.h" #include "at91lib/aic.h" @@ -173,6 +174,11 @@ void hwinit1(void) { AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + /* + * EMAC driver initialization. + */ + macInit(); + /* * ChibiOS/RT initialization. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h index f8e120315..2a1175f5f 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h @@ -17,38 +17,39 @@ along with this program. If not, see . */ /* - **** This file incorporates work covered by the following copyright and **** - **** permission notice: **** - - Copyright (c) 2001-2004 Swedish Institute of Computer Science. - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. The name of the author may not be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - - This file is part of the lwIP TCP/IP stack. - - Author: Adam Dunkels -*/ + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ #ifndef __CC_H__ #define __CC_H__ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h index c6f1d1a90..d690e63e9 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h @@ -17,38 +17,39 @@ along with this program. If not, see . */ /* - **** This file incorporates work covered by the following copyright and **** - **** permission notice: **** - - Copyright (c) 2001-2004 Swedish Institute of Computer Science. - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. The name of the author may not be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - - This file is part of the lwIP TCP/IP stack. - - Author: Adam Dunkels -*/ + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ #ifndef __PERF_H__ #define __PERF_H__ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index ae3e1f73a..df3a97738 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -17,38 +17,39 @@ along with this program. If not, see . */ /* - **** This file incorporates work covered by the following copyright and **** - **** permission notice: **** - - Copyright (c) 2001-2004 Swedish Institute of Computer Science. - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. The name of the author may not be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - - This file is part of the lwIP TCP/IP stack. - - Author: Adam Dunkels -*/ + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ #include diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h index 6dd834506..2b503154c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h @@ -17,38 +17,39 @@ along with this program. If not, see . */ /* - **** This file incorporates work covered by the following copyright and **** - **** permission notice: **** - - Copyright (c) 2001-2004 Swedish Institute of Computer Science. - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. The name of the author may not be used to endorse or promote products - derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - - This file is part of the lwIP TCP/IP stack. - - Author: Adam Dunkels -*/ + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ #include diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c new file mode 100644 index 000000000..2f4869d36 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -0,0 +1,286 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/** + * @file lwipthread.c + * @brief LWIP wrapper thread code. + * @addtogroup LWIP_THREAD + * @{ + */ + +#include +#include +#include + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include +#include +#include +#include "netif/etharp.h" +#include "netif/ppp_oe.h" + +#include "lwipthread.h" + +#define PERIODIC_TIMER_ID 1 +#define FRAME_RECEIVED_ID 2 + +/* + * Initialization. + */ +static void low_level_init(struct netif *netif) { + /* set MAC hardware address length */ + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* set MAC hardware address */ + netif->hwaddr[0] = 0xC2; + netif->hwaddr[1] = 0xAF; + netif->hwaddr[2] = 0x51; + netif->hwaddr[3] = 0x03; + netif->hwaddr[4] = 0xCF; + netif->hwaddr[5] = 0x46; + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* device capabilities */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* Do whatever else is needed to initialize interface. */ + macSetAddress(Ð1, netif->hwaddr); +} + +/* + * Transmits a frame. + */ +static err_t low_level_output(struct netif *netif, struct pbuf *p) { + struct pbuf *q; + MACTransmitDescriptor td; + + if (macWaitTransmitDescriptor(Ð1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != RDY_OK) + return ERR_TIMEOUT; + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* Iterates through the pbuf chain. */ + for(q = p; q != NULL; q = q->next) { + macWriteTransmitDescriptor(&td, (uint8_t *)q->payload, (size_t)q->len); + } + macReleaseTransmitDescriptor(&td); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.xmit); + + return ERR_OK; +} + +/* + * Receives a frame. + */ +static struct pbuf *low_level_input(struct netif *netif) { + MACReceiveDescriptor rd; + struct pbuf *p, *q; + u16_t len; + + if (macWaitReceiveDescriptor(Ð1, &rd, TIME_IMMEDIATE) == RDY_OK) { + len = (u16_t)rd.rd_size; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (p != NULL) { + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* Iterates through the pbuf chain. */ + for(q = p; q != NULL; q = q->next) { + macReadReceiveDescriptor(&rd, (uint8_t *)q->payload, (size_t)q->len); + } + macReleaseReceiveDescriptor(&rd); + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.recv); + } + else { + macReleaseReceiveDescriptor(&rd); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + } + return p; + } + return NULL; +} + +/* + * Initialization. + */ +static err_t ethernetif_init(struct netif *netif) { +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + netif->hostname = "lwip"; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LWIP_LINK_SPEED); + + netif->state = NULL; + netif->name[0] = LWIP_IFNAME0; + netif->name[1] = LWIP_IFNAME1; + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + netif->output = etharp_output; + netif->linkoutput = low_level_output; + + /* initialize the hardware */ + low_level_init(netif); + + return ERR_OK; +} + +/** + * @brief LWIP handling thread. + * + * @param[in] p not used + * @return The function does not return. + */ +msg_t lwip_thread(void *p) { + EvTimer evt; + EventListener el0, el1; + struct ip_addr ip, gateway, netmask; + static struct netif thisif; + + /* Initializes the thing.*/ + sys_init(); + mem_init(); + memp_init(); + pbuf_init(); + netif_init(); + ip_init(); + tcpip_init(NULL, NULL); + + /* TCP/IP parameters.*/ + LWIP_IPADDR(&ip); + LWIP_GATEWAY(&gateway); + LWIP_NETMASK(&netmask); + netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); + + netif_set_default(&thisif); + netif_set_up(&thisif); + + /* Setup event sources.*/ + evtInit(&evt, S2ST(5)); + evtStart(&evt); + chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID); + chEvtRegisterMask(macGetReceiveEventSource(Ð1), &el1, FRAME_RECEIVED_ID); + chEvtPend(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); + + while (TRUE) { + eventmask_t mask = chEvtWaitAny(ALL_EVENTS); + if (mask & PERIODIC_TIMER_ID) + (void)macPollLinkStatus(Ð1); + if (mask & FRAME_RECEIVED_ID) { + struct pbuf *p; + while ((p = low_level_input(&thisif)) != NULL) { + struct eth_hdr *ethhdr = p->payload; + switch (htons(ethhdr->type)) { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: +#if PPPOE_SUPPORT + /* PPPoE packet? */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: +#endif /* PPPOE_SUPPORT */ + /* full packet send to tcpip_thread to process */ + if (thisif.input(p, &thisif) != ERR_OK) { + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); + pbuf_free(p); + p = NULL; + } + break; + default: + pbuf_free(p); + break; + } + } + } + } + return 0; +} + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h new file mode 100644 index 000000000..0e0fd9031 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file lwipthread.h + * @brief LWIP wrapper thread macros and structures. + * @addtogroup LWIP_THREAD + * @{ + */ + +#ifndef _LWIPTHREAD_H_ +#define _LWIPTHREAD_H_ + +/** @brief IP Address. */ +#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__) +#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 20) +#endif + +/** @brief IP Gateway. */ +#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__) +#define LWIP_GATEWAY(p) IP4_ADDR(p, 192, 168, 1, 1) +#endif + +/** @brief IP netmask. */ +#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__) +#define LWIP_NETMASK(p) IP4_ADDR(p, 255, 255, 255, 0) +#endif + +/** @brief MAC thread stack size. */ +#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define LWIP_THREAD_STACK_SIZE 256 +#endif + +/** @brief Transmission timeout. */ +#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__) +#define LWIP_SEND_TIMEOUT 50 +#endif + +/** @brief Link speed. */ +#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__) +#define LWIP_LINK_SPEED 100000000 +#endif + +/** @brief MAC Address byte 0. */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_0 0xC2 +#endif + +/** @brief MAC Address byte 1. */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_1 0xAF +#endif + +/** @brief MAC Address byte 2. */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_2 0x51 +#endif + +/** @brief MAC Address byte 3. */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_3 0x03 +#endif + +/** @brief MAC Address byte 4. */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_4 0xCF +#endif + +/** @brief MAC Address byte 5. */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_5 0x46 +#endif + +/** @brief Interface name byte 0. */ +#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__) +#define LWIP_IFNAME0 'm' +#endif + +/** @brief Interface name byte 1. */ +#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__) +#define LWIP_IFNAME1 's' +#endif + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _LWIPTHREAD_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c deleted file mode 100644 index ccd7bd67f..000000000 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/netif/ethernetif.c +++ /dev/null @@ -1,313 +0,0 @@ -/** - * @file - * Ethernet Interface Skeleton - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* - * This file is a skeleton for developing Ethernet network interface - * drivers for lwIP. Add code to the low_level functions and do a - * search-and-replace for the word "ethernetif" to replace it with - * something that better describes your network interface. - */ - -#include "lwip/opt.h" - -#if 0 /* don't build, this is only a skeleton, see previous comment */ - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include -#include -#include "netif/etharp.h" -#include "netif/ppp_oe.h" - -/* Define those to better describe your network interface. */ -#define IFNAME0 'e' -#define IFNAME1 'n' - -/** - * Helper struct to hold private data used to operate your ethernet interface. - * Keeping the ethernet address of the MAC in this struct is not necessary - * as it is already kept in the struct netif. - * But this is only an example, anyway... - */ -struct ethernetif { - struct eth_addr *ethaddr; - /* Add whatever per-interface state that is needed here. */ -}; - -/* Forward declarations. */ -static void ethernetif_input(struct netif *netif); - -/** - * In this function, the hardware should be initialized. - * Called from ethernetif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -static void -low_level_init(struct netif *netif) -{ - struct ethernetif *ethernetif = netif->state; - - /* set MAC hardware address length */ - netif->hwaddr_len = ETHARP_HWADDR_LEN; - - /* set MAC hardware address */ - netif->hwaddr[0] = ; - ... - netif->hwaddr[5] = ; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; - - /* Do whatever else is needed to initialize interface. */ -} - -/** - * This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to - * strange results. You might consider waiting for space in the DMA queue - * to become availale since the stack doesn't retry to send a packet - * dropped because of memory failure (except for the TCP timers). - */ - -static err_t -low_level_output(struct netif *netif, struct pbuf *p) -{ - struct ethernetif *ethernetif = netif->state; - struct pbuf *q; - - initiate transfer(); - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - for(q = p; q != NULL; q = q->next) { - /* Send the data from the pbuf to the interface, one pbuf at a - time. The size of the data in each pbuf is kept in the ->len - variable. */ - send data from(q->payload, q->len); - } - - signal that packet should be sent(); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - - LINK_STATS_INC(link.xmit); - - return ERR_OK; -} - -/** - * Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - * @param netif the lwip network interface structure for this ethernetif - * @return a pbuf filled with the received packet (including MAC header) - * NULL on memory error - */ -static struct pbuf * -low_level_input(struct netif *netif) -{ - struct ethernetif *ethernetif = netif->state; - struct pbuf *p, *q; - u16_t len; - - /* Obtain the size of the packet and put it into the "len" - variable. */ - len = ; - -#if ETH_PAD_SIZE - len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ -#endif - - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - - if (p != NULL) { - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - /* We iterate over the pbuf chain until we have read the entire - * packet into the pbuf. */ - for(q = p; q != NULL; q = q->next) { - /* Read enough bytes to fill this pbuf in the chain. The - * available data in the pbuf is given by the q->len - * variable. */ - read data into(q->payload, q->len); - } - acknowledge that packet has been read(); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - - LINK_STATS_INC(link.recv); - } else { - drop packet(); - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - } - - return p; -} - -/** - * This function should be called when a packet is ready to be read - * from the interface. It uses the function low_level_input() that - * should handle the actual reception of bytes from the network - * interface. Then the type of the received packet is determined and - * the appropriate input function is called. - * - * @param netif the lwip network interface structure for this ethernetif - */ -static void -ethernetif_input(struct netif *netif) -{ - struct ethernetif *ethernetif; - struct eth_hdr *ethhdr; - struct pbuf *p; - - ethernetif = netif->state; - - /* move received packet into a new pbuf */ - p = low_level_input(netif); - /* no packet could be read, silently ignore this */ - if (p == NULL) return; - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = p->payload; - - switch (htons(ethhdr->type)) { - /* IP or ARP packet? */ - case ETHTYPE_IP: - case ETHTYPE_ARP: -#if PPPOE_SUPPORT - /* PPPoE packet? */ - case ETHTYPE_PPPOEDISC: - case ETHTYPE_PPPOE: -#endif /* PPPOE_SUPPORT */ - /* full packet send to tcpip_thread to process */ - if (netif->input(p, netif)!=ERR_OK) - { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - pbuf_free(p); - p = NULL; - } - break; - - default: - pbuf_free(p); - p = NULL; - break; - } -} - -/** - * Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t -ethernetif_init(struct netif *netif) -{ - struct ethernetif *ethernetif; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - - ethernetif = mem_malloc(sizeof(struct ethernetif)); - if (ethernetif == NULL) { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); - return ERR_MEM; - } - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; -#endif /* LWIP_NETIF_HOSTNAME */ - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); - - netif->state = ethernetif; - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); - - /* initialize the hardware */ - low_level_init(netif); - - return ERR_OK; -} - -#endif /* 0 */ -- cgit v1.2.3 From cbf137ed955b30d8695d881aa8d16f1a723b89b5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Oct 2009 19:24:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1203 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 5 +++-- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 12 ++++++------ demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 5 +++++ demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h | 5 ++++- demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 11 +++++++++-- 7 files changed, 29 insertions(+), 13 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index e38c35681..80127d948 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 21ad75bde..e6a58ce12 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -339,7 +339,8 @@ #define THREAD_EXT_FIELDS \ struct { \ /* Add thread custom fields here.*/ \ - void *p_timeouts; \ + /* Space for the LWIP sys_timeouts structure.*/ \ + void *p_lwipspace[1]; \ }; #endif @@ -350,7 +351,7 @@ struct { \ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add thread initialization code here.*/ \ - currp->p_timeouts = NULL; \ + (tp)->p_lwipspace[0] = NULL; \ } #endif diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index df3a97738..329e0f8de 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -66,14 +66,14 @@ void sys_init(void) { sys_sem_t sys_sem_new(u8_t count) { - sys_sem_t sem = mem_malloc(sizeof(Semaphore)); + sys_sem_t sem = chHeapAlloc(sizeof(Semaphore)); chSemInit(sem, (cnt_t)count); return sem; } void sys_sem_free(sys_sem_t sem) { - mem_free(sem); + chHeapFree(sem); } void sys_sem_signal(sys_sem_t sem) { @@ -97,14 +97,14 @@ u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) { sys_mbox_t sys_mbox_new(int size) { sys_mbox_t mbox; - mbox = mem_malloc(sizeof(Mailbox) + sizeof(msg_t) * size); + mbox = chHeapAlloc(sizeof(Mailbox) + sizeof(msg_t) * size); chMBInit(mbox, (void *)(mbox + 1), size); return mbox; } void sys_mbox_free(sys_mbox_t mbox) { - mem_free(mbox); + chHeapFree(mbox); } void sys_mbox_post(sys_mbox_t mbox, void *msg) { @@ -141,13 +141,13 @@ u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg) { struct sys_timeouts *sys_arch_timeouts(void) { - return (struct sys_timeouts *)&currp->p_timeouts; + return (struct sys_timeouts *)currp->p_lwipspace; } sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio) { size_t wsz = THD_WA_SIZE(stacksize); - void *wsp = mem_malloc(wsz); + void *wsp = chHeapAlloc(wsz); if (wsp == NULL) return NULL; return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg); diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 2f4869d36..7b9d483c4 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -79,6 +79,11 @@ #define PERIODIC_TIMER_ID 1 #define FRAME_RECEIVED_ID 2 +/** + * Stack area for the LWIP-MAC thread. + */ +WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); + /* * Initialization. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h index 0e0fd9031..85969bede 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h @@ -44,7 +44,7 @@ /** @brief MAC thread stack size. */ #if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__) -#define LWIP_THREAD_STACK_SIZE 256 +#define LWIP_THREAD_STACK_SIZE 512 #endif /** @brief Transmission timeout. */ @@ -97,9 +97,12 @@ #define LWIP_IFNAME1 's' #endif +extern WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); + #ifdef __cplusplus extern "C" { #endif + msg_t lwip_thread(void *p); #ifdef __cplusplus } #endif diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h index 28f7c6fd2..318ee6579 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h @@ -1010,7 +1010,7 @@ * sys_thread_new() when the thread is created. */ #ifndef TCPIP_THREAD_PRIO -#define TCPIP_THREAD_PRIO (LOWPRIO) +#define TCPIP_THREAD_PRIO (LOWPRIO + 1) #endif /** diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index f6c297a41..098e764a5 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -23,15 +23,16 @@ #include #include "board.h" +#include "lwipthread.h" static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { while (TRUE) { - palSetPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(100); palClearPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(900); + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); } return 0; } @@ -52,6 +53,12 @@ int main(int argc, char **argv) { */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + /* + * Creates the LWIP threads. + */ + chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, LOWPRIO, + lwip_thread, NULL); + /* * Normal main() thread activity. */ -- cgit v1.2.3 From dd96bdcd511d158d80d2ef64b47c46fcb8219d5a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 4 Oct 2009 13:27:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1204 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h | 4 ++-- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 4 ---- demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h | 22 +++++++++++----------- 4 files changed, 14 insertions(+), 18 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index 329e0f8de..7d39c9520 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -98,7 +98,7 @@ sys_mbox_t sys_mbox_new(int size) { sys_mbox_t mbox; mbox = chHeapAlloc(sizeof(Mailbox) + sizeof(msg_t) * size); - chMBInit(mbox, (void *)(mbox + 1), size); + chMBInit(mbox, (void *)(((uint8_t *)mbox) + sizeof(Mailbox)), size); return mbox; } diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h index 2b503154c..a054ae761 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h @@ -57,11 +57,11 @@ #define __SYS_ARCH_H__ typedef Semaphore * sys_sem_t; -typedef void * sys_mbox_t; +typedef Mailbox * sys_mbox_t; typedef Thread * sys_thread_t; typedef int sys_prot_t; -#define SYS_MBOX_NULL (void *)0 +#define SYS_MBOX_NULL (Mailbox *)0 #define SYS_THREAD_NULL (Thread *)0 #define SYS_SEM_NULL (Semaphore *)0 diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 7b9d483c4..16957811e 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -274,13 +274,9 @@ msg_t lwip_thread(void *p) { /* full packet send to tcpip_thread to process */ if (thisif.input(p, &thisif) != ERR_OK) { LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - pbuf_free(p); - p = NULL; } - break; default: pbuf_free(p); - break; } } } diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h index 318ee6579..ddb3aac11 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h @@ -1019,7 +1019,7 @@ * sys_mbox_new() when tcpip_init is called. */ #ifndef TCPIP_MBOX_SIZE -#define TCPIP_MBOX_SIZE 0 +#define TCPIP_MBOX_SIZE 4 #endif /** @@ -1035,7 +1035,7 @@ * sys_thread_new() when the thread is created. */ #ifndef SLIPIF_THREAD_STACKSIZE -#define SLIPIF_THREAD_STACKSIZE 0 +#define SLIPIF_THREAD_STACKSIZE 512 #endif /** @@ -1044,7 +1044,7 @@ * sys_thread_new() when the thread is created. */ #ifndef SLIPIF_THREAD_PRIO -#define SLIPIF_THREAD_PRIO 1 +#define SLIPIF_THREAD_PRIO (LOWPRIO + 1) #endif /** @@ -1060,7 +1060,7 @@ * sys_thread_new() when the thread is created. */ #ifndef PPP_THREAD_STACKSIZE -#define PPP_THREAD_STACKSIZE 0 +#define PPP_THREAD_STACKSIZE 512 #endif /** @@ -1069,7 +1069,7 @@ * sys_thread_new() when the thread is created. */ #ifndef PPP_THREAD_PRIO -#define PPP_THREAD_PRIO 1 +#define PPP_THREAD_PRIO (LOWPRIO + 1) #endif /** @@ -1085,7 +1085,7 @@ * sys_thread_new() when the thread is created. */ #ifndef DEFAULT_THREAD_STACKSIZE -#define DEFAULT_THREAD_STACKSIZE 0 +#define DEFAULT_THREAD_STACKSIZE 512 #endif /** @@ -1094,7 +1094,7 @@ * sys_thread_new() when the thread is created. */ #ifndef DEFAULT_THREAD_PRIO -#define DEFAULT_THREAD_PRIO 1 +#define DEFAULT_THREAD_PRIO (LOWPRIO + 1) #endif /** @@ -1103,7 +1103,7 @@ * to sys_mbox_new() when the recvmbox is created. */ #ifndef DEFAULT_RAW_RECVMBOX_SIZE -#define DEFAULT_RAW_RECVMBOX_SIZE 0 +#define DEFAULT_RAW_RECVMBOX_SIZE 4 #endif /** @@ -1112,7 +1112,7 @@ * to sys_mbox_new() when the recvmbox is created. */ #ifndef DEFAULT_UDP_RECVMBOX_SIZE -#define DEFAULT_UDP_RECVMBOX_SIZE 0 +#define DEFAULT_UDP_RECVMBOX_SIZE 4 #endif /** @@ -1121,7 +1121,7 @@ * to sys_mbox_new() when the recvmbox is created. */ #ifndef DEFAULT_TCP_RECVMBOX_SIZE -#define DEFAULT_TCP_RECVMBOX_SIZE 0 +#define DEFAULT_TCP_RECVMBOX_SIZE 40 #endif /** @@ -1130,7 +1130,7 @@ * sys_mbox_new() when the acceptmbox is created. */ #ifndef DEFAULT_ACCEPTMBOX_SIZE -#define DEFAULT_ACCEPTMBOX_SIZE 0 +#define DEFAULT_ACCEPTMBOX_SIZE 4 #endif /* -- cgit v1.2.3 From b0fb2171c4b933ed56411da780a4d2111bc9f4a1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 4 Oct 2009 13:37:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1205 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 16957811e..73b670312 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -272,9 +272,9 @@ msg_t lwip_thread(void *p) { case ETHTYPE_PPPOE: #endif /* PPPOE_SUPPORT */ /* full packet send to tcpip_thread to process */ - if (thisif.input(p, &thisif) != ERR_OK) { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - } + if (thisif.input(p, &thisif) == ERR_OK) + break; + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); default: pbuf_free(p); } -- cgit v1.2.3 From 660c9df44e117f84bc51795abbfb4189cb736c82 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 4 Oct 2009 14:03:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1206 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h index ddb3aac11..17c799866 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h @@ -1001,7 +1001,7 @@ * sys_thread_new() when the thread is created. */ #ifndef TCPIP_THREAD_STACKSIZE -#define TCPIP_THREAD_STACKSIZE 256 +#define TCPIP_THREAD_STACKSIZE 1024 #endif /** @@ -1035,7 +1035,7 @@ * sys_thread_new() when the thread is created. */ #ifndef SLIPIF_THREAD_STACKSIZE -#define SLIPIF_THREAD_STACKSIZE 512 +#define SLIPIF_THREAD_STACKSIZE 1024 #endif /** @@ -1060,7 +1060,7 @@ * sys_thread_new() when the thread is created. */ #ifndef PPP_THREAD_STACKSIZE -#define PPP_THREAD_STACKSIZE 512 +#define PPP_THREAD_STACKSIZE 1024 #endif /** @@ -1085,7 +1085,7 @@ * sys_thread_new() when the thread is created. */ #ifndef DEFAULT_THREAD_STACKSIZE -#define DEFAULT_THREAD_STACKSIZE 512 +#define DEFAULT_THREAD_STACKSIZE 1024 #endif /** -- cgit v1.2.3 From b97ff7cf12656030843d8dff5a367f76f992bb08 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 10 Oct 2009 08:23:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1208 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 80127d948..e38c35681 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From 6834b95aa979dbb197ca1b9a5bced576cce4e96f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Oct 2009 10:12:22 +0000 Subject: lwIP demo added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1209 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 1 + demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 3 + demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h | 5 + demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 13 ++- demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt | 8 +- demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c | 118 ++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h | 54 +++++++++++ 7 files changed, 198 insertions(+), 4 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index e38c35681..62a8d217c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -70,6 +70,7 @@ CSRC = ${PORTSRC} \ ${LWAPISRC} \ ./lwip/arch/sys_arch.c \ ./lwip/lwipthread.c \ + ./web/web.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 73b670312..bb9f8ae5b 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -254,6 +254,9 @@ msg_t lwip_thread(void *p) { chEvtRegisterMask(macGetReceiveEventSource(Ð1), &el1, FRAME_RECEIVED_ID); chEvtPend(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); + /* Goes to the final priority after initialization.*/ + chThdSetPriority(LWIP_THREAD_PRIORITY); + while (TRUE) { eventmask_t mask = chEvtWaitAny(ALL_EVENTS); if (mask & PERIODIC_TIMER_ID) diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h index 85969bede..fe939a178 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h @@ -27,6 +27,11 @@ #ifndef _LWIPTHREAD_H_ #define _LWIPTHREAD_H_ +/** @brief MAC thread priority.*/ +#ifndef LWIP_THREAD_PRIORITY +#define LWIP_THREAD_PRIORITY LOWPRIO +#endif + /** @brief IP Address. */ #if !defined(LWIP_IPADDR) || defined(__DOXYGEN__) #define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 20) diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index 098e764a5..d7d1836da 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -23,7 +23,8 @@ #include #include "board.h" -#include "lwipthread.h" +#include "lwip\lwipthread.h" +#include "web\web.h" static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { @@ -54,11 +55,17 @@ int main(int argc, char **argv) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); /* - * Creates the LWIP threads. + * Creates the LWIP threads (it changes priority internally). */ - chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, LOWPRIO, + chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1, lwip_thread, NULL); + /* + * Creates the HTTP thread (it changes priority internally). + */ + chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1, + http_server, NULL); + /* * Normal main() thread activity. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt index 986d5ec7c..7b6460326 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt @@ -8,7 +8,9 @@ The demo runs on an Olimex SAM7-EX256 board. ** The Demo ** -The demo currently just flashes the LCD background using a thread. +The demo currently just flashes the LCD background using a thread and serves +HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP +address into web.c in order to adapt it to your network settings). The button SW1 prints an "Hello World!" string on COM1, the button SW2 activates che ChibiOS/RT test suite, output on COM1. @@ -16,6 +18,7 @@ activates che ChibiOS/RT test suite, output on COM1. The demo was built using the YAGARTO toolchain but any toolchain based on GCC and GNU userspace programs will work. +The demo requires the patcher lwIP 1.3.1 stack, see: ./ext/readme.txt ** Notes ** @@ -26,3 +29,6 @@ Also note that not all the files present in the Atmel library are distribuited with ChibiOS/RT, you can find the whole library on the Atmel web site: http://www.atmel.com + +The lwIP stack also has its own license, please read the info into the included +lwIP distribution files. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c new file mode 100644 index 000000000..88701ce3e --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * This file is a modified version of the lwIP web server demo. The original + * author is unknown because the file didn't contain any license information. + */ + +/** + * @file web.c + * @brief HTTP server wrapper thread code. + * @addtogroup WEB_THREAD + * @{ + */ + +#include + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api.h" + +#include "web.h" + +#if LWIP_NETCONN + +const static char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; +const static char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; + +static void http_server_serve(struct netconn *conn) { + struct netbuf *inbuf; + char *buf; + u16_t buflen; + + /* Read the data from the port, blocking if nothing yet there. + We assume the request (the part we care about) is in one netbuf */ + inbuf = netconn_recv(conn); + + if (netconn_err(conn) == ERR_OK) { + netbuf_data(inbuf, (void **)&buf, &buflen); + + /* Is this an HTTP GET command? (only check the first 5 chars, since + there are other formats for GET, and we're keeping it very simple )*/ + if (buflen>=5 && + buf[0]=='G' && + buf[1]=='E' && + buf[2]=='T' && + buf[3]==' ' && + buf[4]=='/' ) { + + /* Send the HTML header + * subtract 1 from the size, since we dont send the \0 in the string + * NETCONN_NOCOPY: our data is const static, so no need to copy it + */ + netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY); + + /* Send our HTML page */ + netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY); + } + } + /* Close the connection (server closes in HTTP) */ + netconn_close(conn); + + /* Delete the buffer (netconn_recv gives us ownership, + so we have to make sure to deallocate the buffer) */ + netbuf_delete(inbuf); +} + +/** + * Stack area for the http thread. + */ +WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +/** + * HTTP server thread. + */ +msg_t http_server(void *p) { + struct netconn *conn, *newconn; + + /* Create a new TCP connection handle */ + conn = netconn_new(NETCONN_TCP); + LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;); + + /* Bind to port 80 (HTTP) with default IP address */ + netconn_bind(conn, NULL, WEB_THREAD_PORT); + + /* Put the connection into LISTEN state */ + netconn_listen(conn); + + /* Goes to the final priority after initialization.*/ + chThdSetPriority(WEB_THREAD_PRIORITY); + + while(1) { + newconn = netconn_accept(conn); + http_server_serve(newconn); + netconn_delete(newconn); + } + return RDY_OK; +} + +#endif /* LWIP_NETCONN */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h new file mode 100644 index 000000000..f53cfcb44 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h @@ -0,0 +1,54 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file web.h + * @brief HTTP server wrapper thread macros and structures. + * @addtogroup WEB_THREAD + * @{ + */ + +#ifndef _WEB_H_ +#define _WEB_H_ + +#ifndef WEB_THREAD_STACK_SIZE +#define WEB_THREAD_STACK_SIZE 1024 +#endif + +#ifndef WEB_THREAD_PORT +#define WEB_THREAD_PORT 80 +#endif + +#ifndef WEB_THREAD_PRIORITY +#define WEB_THREAD_PRIORITY (LOWPRIO + 2) +#endif + +extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); + +#ifdef __cplusplus +extern "C" { +#endif + msg_t http_server(void *p); +#ifdef __cplusplus +} +#endif + +#endif /* _WEB_H_ */ + +/** @} */ -- cgit v1.2.3 From 803895890d200c84ee2914fdc1cb246e94202eeb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Oct 2009 10:16:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1210 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-WEB-GCC/Makefile | 201 -------------- demos/ARM7-AT91SAM7X-WEB-GCC/board.c | 187 ------------- demos/ARM7-AT91SAM7X-WEB-GCC/board.h | 78 ------ demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld | 98 ------- demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h | 377 -------------------------- demos/ARM7-AT91SAM7X-WEB-GCC/main.c | 72 ----- demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt | 34 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h | 9 - demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h | 42 --- demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h | 159 ----------- demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c | 179 ------------ demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h | 31 --- 12 files changed, 1467 deletions(-) delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/Makefile delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/board.c delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/board.h delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/main.c delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c delete mode 100644 demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile b/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile deleted file mode 100644 index 95d046fef..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/Makefile +++ /dev/null @@ -1,201 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk - -# List of the required uIP source files. -USRC = ${CHIBIOS}/ext/uip-1.0/uip/uip_arp.c \ - ${CHIBIOS}/ext/uip-1.0/uip/psock.c \ - ${CHIBIOS}/ext/uip-1.0/uip/uip.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/http-strings.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-fs.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-cgi.c - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${USRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/mii.c \ - ${CHIBIOS}/os/io/mac.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/mii_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ - ${CHIBIOS}/os/various/evtimer.c \ - web/webthread.c \ - board.c main.c -# ${CHIBIOS}/os/io/platforms/AT91SAM7X/sam7x_emac.c \ - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X \ - ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X \ - ./web ${CHIBIOS}/ext/uip-1.0/uip ${CHIBIOS}/ext/uip-1.0/apps/webserver - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -TRGT = arm-elf- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c b/demos/ARM7-AT91SAM7X-WEB-GCC/board.c deleted file mode 100644 index 348f4bb99..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include -#include -#include - -#include "board.h" -#include "at91lib/aic.h" - - -/* - * FIQ Handler weak symbol defined in vectors.s. - */ -void FiqHandler(void); - -static CH_IRQ_HANDLER(SpuriousHandler) { - - CH_IRQ_PROLOGUE(); - - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} - -/* - * SYS IRQ handling here. - */ -static CH_IRQ_HANDLER(SYSIrqHandler) { - - CH_IRQ_PROLOGUE(); - - if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { - (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - } - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} - -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const AT91SAM7XPIOConfig config = -{ - {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, - {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} -}; - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - /* - * Flash Memory: 1 wait state, about 50 cycles in a microsecond. - */ - AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; - - /* - * Watchdog disabled. - */ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - /* - * Enables the main oscillator and waits 56 slow cycles as startup time. - */ - AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) - ; - - /* - * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 - * PLLfreq = 96109714 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | - (AT91C_CKGR_PLLCOUNT & (10 << 8)) | - (AT91C_CKGR_MUL & (72 << 16)); - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) - ; - - /* - * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) - ; - - /* - * PIO initialization. - */ - palInit(&config); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - int i; - - /* - * Default AIC setup, the device drivers will modify it as needed. - */ - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; - for (i = 1; i < 31; i++) { - AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; - AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; - } - AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; - - /* - * LCD pins setup. - */ - palClearPad(IOPORT2, PIOB_LCD_BL); - palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); - - palSetPad(IOPORT1, PIOA_LCD_RESET); - palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); - - /* - * Joystick and buttons setup. - */ - palSetGroupMode(IOPORT1, - PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | - PIOA_B4_MASK | PIOA_B5_MASK, - PAL_MODE_INPUT); - palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); - - /* - * MMC/SD slot setup. - */ - palSetGroupMode(IOPORT2, - PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, - PAL_MODE_INPUT); - - /* - * PIT Initialization. - */ - AIC_ConfigureIT(AT91C_ID_SYS, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), - SYSIrqHandler); - AIC_EnableIT(AT91C_ID_SYS); - AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; - AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - - /* - * Serial driver initialization, RTS/CTS pins enabled for USART0 only. - */ - sdInit(); - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; - AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - - /* - * EMAC driver initialization. - */ - macInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/board.h b/demos/ARM7-AT91SAM7X-WEB-GCC/board.h deleted file mode 100644 index c56f50258..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/board.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#include "at91lib/AT91SAM7X256.h" - -#define BOARD_OLIMEX_SAM7_EX256 - -#define CLK 18432000 -#define MCK 48054857 - -/* - * Initial I/O setup. - */ -#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOA_OSR 0x00000000 /* Direction. */ -#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ - -#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOB_OSR 0x00000000 /* Direction. */ -#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ - -/* - * I/O definitions. - */ -#define PIOA_LCD_RESET 2 -#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) -#define PIOA_B1 7 -#define PIOA_B1_MASK (1 << PIOA_B1) -#define PIOA_B2 8 -#define PIOA_B2_MASK (1 << PIOA_B2) -#define PIOA_B3 9 -#define PIOA_B3_MASK (1 << PIOA_B3) -#define PIOA_B4 14 -#define PIOA_B4_MASK (1 << PIOA_B4) -#define PIOA_B5 15 -#define PIOA_B5_MASK (1 << PIOA_B5) -#define PIOA_USB_PUP 25 -#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) -#define PIOA_USB_PR 26 -#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) - -#define PIOB_PHY_PD 18 -#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) -#define PIOB_AUDIO_OUT 19 -#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) -#define PIOB_LCD_BL 20 -#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) -#define PIOB_MMC_WP 22 -#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) -#define PIOB_MMC_CP 23 -#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) -#define PIOB_SW1 24 -#define PIOB_SW1_MASK (1 << PIOB_SW1) -#define PIOB_SW2 25 -#define PIOB_SW2_MASK (1 << PIOB_SW2) -#define PIOB_PHY_IRQ 26 -#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) - -#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld b/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld deleted file mode 100644 index 944a7f29d..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/ch.ld +++ /dev/null @@ -1,98 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * AT91SAM7X256 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x100000, len = 256k - ram : org = 0x200020, len = 64k - 0x20 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash - - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram - - /DISCARD/ : - { - *(.eh_*) - } -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h deleted file mode 100644 index 3c6353168..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/chconf.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file src/templates/chconf.h - * @brief Configuration file template. - * @addtogroup Config - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. - * @note The default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. - */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * If specified then the @p chThdWait() function is included in the kernel. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * If specified then the Semaphores APIs are included in the kernel. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * If specified then the Mutexes APIs are included in the kernel. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * If specified then the Conditional Variables APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * If specified then the Conditional Variables APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * If specified then the Event flags APIs are included in the kernel. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * If specified then the Synchronous Messages APIs are included in the kernel. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * If enabled then messages are served by priority rather than in FIFO order. - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * If specified then the I/O queues APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * If specified then the memory heap allocator APIs are included in the kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * If specified then the memory pools allocator APIs are included in the - * kernel. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * If specified then the dynamic threads creation APIs are included in the - * kernel. - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * Debug option, if enabled the context switch circular trace buffer is - * activated. - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * Debug option, if enabled a runtime stack check is performed. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add thread custom fields here.*/ \ -}; -#endif - -/** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ -} -#endif - -/** - * User finalization code added to the @p chThdExit() API. - * @note It is inserted into lock zone. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ -} -#endif - -/** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c b/demos/ARM7-AT91SAM7X-WEB-GCC/main.c deleted file mode 100644 index 0474ce008..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/main.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include -#include -#include - -#include "board.h" - -#include "web/webthread.h" - -static WORKING_AREA(waWebThread, 512); -static WORKING_AREA(waThread1, 128); - -static msg_t Thread1(void *arg) { - - while (TRUE) { - palSetPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(100); - palClearPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(900); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Creates the blinker and web server threads. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waWebThread, sizeof(waWebThread), LOWPRIO, WebThread, NULL); - - /* - * Normal main() thread activity. - */ - while (TRUE) { - chThdSleepMilliseconds(500); - if (!palReadPad(IOPORT2, PIOB_SW1)) - sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); - if (!palReadPad(IOPORT2, PIOB_SW2)) - TestThread(&SD1); - } - - return 0; -} diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt b/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt deleted file mode 100644 index 129f245c2..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/readme.txt +++ /dev/null @@ -1,34 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex SAM7-EX256 board. - -** The Demo ** - -The demo currently just flashes the LCD background using a thread and serves -HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP -address into webthread.c in order to adapt it to your network settings). -The button SW1 prints an "Hello World!" string on COM1, the button SW2 -activates che ChibiOS/RT test suite, output on COM1. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. -The demo requires the patcher uIP 1.0 stack, see: ./ext/readme.txt - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright -and are licensed under a different license, see the header present in all the -source files under ./demos/AT91SAM7X256/at91lib for details. -Also note that not all the files present in the Atmel library are distribuited -with ChibiOS/RT, you can find the whole library on the Atmel web site: - - http://www.atmel.com - -The uIP stack also has its own license, please read the info into the included -uIP distribution files. diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h deleted file mode 100644 index 744cf56ef..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/cc-arch.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __CC_ARCH_H__ -#define __CC_ARCH_H__ - -#define PACK_STRUCT_FIELD(x) x __attribute__((packed)) -#define PACK_STRUCT_STRUCT __attribute__((packed)) -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_END - -#endif /* __CC_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h deleted file mode 100644 index e205f9c8d..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/clock-arch.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ - */ - -#ifndef __CLOCK_ARCH_H__ -#define __CLOCK_ARCH_H__ - -#include - -typedef systime_t clock_time_t; -#define CLOCK_CONF_SECOND CH_FREQUENCY - -#endif /* __CLOCK_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h deleted file mode 100644 index b6a17c970..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/uip-conf.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * \addtogroup uipopt - * @{ - */ - -/** - * \name Project-specific configuration options - * @{ - * - * uIP has a number of configuration options that can be overridden - * for each project. These are kept in a project-specific uip-conf.h - * file and all configuration names have the prefix UIP_CONF. - */ - -/* - * Copyright (c) 2006, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the uIP TCP/IP stack - * - * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ - */ - -/** - * \file - * An example uIP configuration file - * \author - * Adam Dunkels - */ - -#ifndef __UIP_CONF_H__ -#define __UIP_CONF_H__ - -#include - -#include /* patched */ - -/** - * 8 bit datatype - * - * This typedef defines the 8-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint8_t u8_t; - -/** - * 16 bit datatype - * - * This typedef defines the 16-bit type used throughout uIP. - * - * \hideinitializer - */ -typedef uint16_t u16_t; - -/** - * Statistics datatype - * - * This typedef defines the dataype used for keeping statistics in - * uIP. - * - * \hideinitializer - */ -typedef unsigned short uip_stats_t; - -/** - * Maximum number of TCP connections. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_CONNECTIONS 40 - -/** - * Maximum number of listening TCP ports. - * - * \hideinitializer - */ -#define UIP_CONF_MAX_LISTENPORTS 40 - -/** - * uIP buffer size. - * - * \hideinitializer - */ -#define UIP_CONF_BUFFER_SIZE 1518 - -/** - * CPU byte order. - * - * \hideinitializer - */ -#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN - -/** - * Logging on or off - * - * \hideinitializer - */ -#define UIP_CONF_LOGGING 0 - -/** - * UDP support on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP 0 - -/** - * UDP checksums on or off - * - * \hideinitializer - */ -#define UIP_CONF_UDP_CHECKSUMS 1 - -/** - * uIP statistics on or off - * - * \hideinitializer - */ -#define UIP_CONF_STATISTICS 1 - -/* Here we include the header file for the application(s) we use in - our project. */ -/*#include "smtp.h"*/ -/*#include "hello-world.h"*/ -/*#include "telnetd.h"*/ -#include "webserver.h" -/*#include "dhcpc.h"*/ -/*#include "resolv.h"*/ -/*#include "webclient.h"*/ - -#endif /* __UIP_CONF_H__ */ - -/** @} */ -/** @} */ diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c deleted file mode 100644 index 12c3b8405..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#define IPADDR0 192 -#define IPADDR1 168 -#define IPADDR2 1 -#define IPADDR3 20 - -#define SEND_TIMEOUT 50 - -static const struct uip_eth_addr macaddr = { - {0xC2, 0xAF, 0x51, 0x03, 0xCF, 0x46} -}; - -#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) - -/* - * uIP send function wrapping the EMAC functions. - */ -static void network_device_send(void) { - MACTransmitDescriptor td; - - if (macWaitTransmitDescriptor(Ð1, &td, MS2ST(SEND_TIMEOUT)) == RDY_OK) { - if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) - macWriteTransmitDescriptor(&td, uip_buf, uip_len); - else { - macWriteTransmitDescriptor(&td, uip_buf, UIP_LLH_LEN + UIP_TCPIP_HLEN); - macWriteTransmitDescriptor(&td, uip_appdata, - uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); - } - macReleaseTransmitDescriptor(&td); - } - /* Dropped... */ -} - -/* - * uIP receive function wrapping the EMAC function. - */ -static size_t network_device_read(void) { - MACReceiveDescriptor rd; - size_t size; - - if (macWaitReceiveDescriptor(Ð1, &rd, TIME_IMMEDIATE) != RDY_OK) - return 0; - size = rd.rd_size; - macReadReceiveDescriptor(&rd, uip_buf, size); - macReleaseReceiveDescriptor(&rd); - return size; -} - -void clock_init(void) {} - -clock_time_t clock_time( void ) -{ - return chTimeNow(); -} - -/* - * TCP/IP periodic timer. - */ -static void PeriodicTimerHandler(eventid_t id) { - int i; - - for (i = 0; i < UIP_CONNS; i++) { - uip_periodic(i); - if (uip_len > 0) { - uip_arp_out(); - network_device_send(); - } - } -} - -/* - * ARP periodic timer. - */ -static void ARPTimerHandler(eventid_t id) { - - (void)macPollLinkStatus(Ð1); - uip_arp_timer(); -} - -/* - * Ethernet frame received. - */ -static void FrameReceivedHandler(eventid_t id) { - - while ((uip_len = network_device_read()) > 0) { - if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { - uip_arp_ipin(); - uip_input(); - if (uip_len > 0) { - uip_arp_out(); - network_device_send(); - } - } - else if (BUF->type == HTONS(UIP_ETHTYPE_ARP)) { - uip_arp_arpin(); - if (uip_len > 0) - network_device_send(); - } - } -} - -#define FRAME_RECEIVED_ID 0 -#define PERIODIC_TIMER_ID 1 -#define ARP_TIMER_ID 2 - -static const evhandler_t evhndl[] = { - FrameReceivedHandler, - PeriodicTimerHandler, - ARPTimerHandler -}; - -msg_t WebThread(void *p) { - EvTimer evt1, evt2; - EventListener el0, el1, el2; - uip_ipaddr_t ipaddr; - - /* - * Event sources setup. - */ - chEvtRegister(macGetReceiveEventSource(Ð1), &el0, FRAME_RECEIVED_ID); - chEvtPend(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ - - evtInit(&evt1, MS2ST(500)); - evtStart(&evt1); - chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); - - evtInit(&evt2, S2ST(10)); - evtStart(&evt2); - chEvtRegister(&evt2.et_es, &el2, ARP_TIMER_ID); - - /* - * EMAC settings. - */ - macSetAddress(Ð1, &macaddr.addr[0]); - (void)macPollLinkStatus(Ð1); - - /* - * uIP initialization. - */ - uip_init(); - uip_setethaddr(macaddr); - uip_ipaddr(ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3); - uip_sethostaddr(ipaddr); - httpd_init(); - - while (TRUE) { - chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); - } - return 0; -} diff --git a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h b/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h deleted file mode 100644 index bd71b4dc4..000000000 --- a/demos/ARM7-AT91SAM7X-WEB-GCC/web/webthread.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _WEBTHREAD_H_ -#define _WEBTHREAD_H_ - -#ifdef __cplusplus -extern "C" { -#endif - msg_t WebThread(void *p); - #ifdef __cplusplus -} -#endif - -#endif /* _WEBTHREAD_H_ */ -- cgit v1.2.3 From f3237c7de5960e0c604554cbc783c8a2df8c592e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Oct 2009 10:23:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1211 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 201 ++++++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/board.c | 187 +++++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/board.h | 78 ++++++ demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld | 98 +++++++ demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 377 ++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 72 +++++ demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt | 34 +++ demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h | 9 + demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h | 42 +++ demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h | 159 +++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c | 179 ++++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h | 31 +++ 12 files changed, 1467 insertions(+) create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/Makefile create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/board.c create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/board.h create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/main.c create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile new file mode 100644 index 000000000..95d046fef --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -0,0 +1,201 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk + +# List of the required uIP source files. +USRC = ${CHIBIOS}/ext/uip-1.0/uip/uip_arp.c \ + ${CHIBIOS}/ext/uip-1.0/uip/psock.c \ + ${CHIBIOS}/ext/uip-1.0/uip/uip.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/http-strings.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-fs.c \ + ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-cgi.c + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ${USRC} \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/mii.c \ + ${CHIBIOS}/os/io/mac.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/mii_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/various/evtimer.c \ + web/webthread.c \ + board.c main.c +# ${CHIBIOS}/os/io/platforms/AT91SAM7X/sam7x_emac.c \ + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/AT91SAM7X \ + ${CHIBIOS}/os/various \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X \ + ./web ${CHIBIOS}/ext/uip-1.0/uip ${CHIBIOS}/ext/uip-1.0/apps/webserver + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +TRGT = arm-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c new file mode 100644 index 000000000..348f4bb99 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c @@ -0,0 +1,187 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include +#include + +#include "board.h" +#include "at91lib/aic.h" + + +/* + * FIQ Handler weak symbol defined in vectors.s. + */ +void FiqHandler(void); + +static CH_IRQ_HANDLER(SpuriousHandler) { + + CH_IRQ_PROLOGUE(); + + AT91C_BASE_AIC->AIC_EOICR = 0; + + CH_IRQ_EPILOGUE(); +} + +/* + * SYS IRQ handling here. + */ +static CH_IRQ_HANDLER(SYSIrqHandler) { + + CH_IRQ_PROLOGUE(); + + if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { + (void) AT91C_BASE_PITC->PITC_PIVR; + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + } + AT91C_BASE_AIC->AIC_EOICR = 0; + + CH_IRQ_EPILOGUE(); +} + +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const AT91SAM7XPIOConfig config = +{ + {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, + {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +}; + +/* + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. + */ +void hwinit0(void) { + /* + * Flash Memory: 1 wait state, about 50 cycles in a microsecond. + */ + AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; + + /* + * Watchdog disabled. + */ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + /* + * Enables the main oscillator and waits 56 slow cycles as startup time. + */ + AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) + ; + + /* + * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 + * PLLfreq = 96109714 Hz (rounded) + */ + AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (10 << 8)) | + (AT91C_CKGR_MUL & (72 << 16)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) + ; + + /* + * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) + */ + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) + ; + + /* + * PIO initialization. + */ + palInit(&config); +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { + int i; + + /* + * Default AIC setup, the device drivers will modify it as needed. + */ + AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; + for (i = 1; i < 31; i++) { + AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; + AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; + } + AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; + + /* + * LCD pins setup. + */ + palClearPad(IOPORT2, PIOB_LCD_BL); + palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); + + palSetPad(IOPORT1, PIOA_LCD_RESET); + palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); + + /* + * Joystick and buttons setup. + */ + palSetGroupMode(IOPORT1, + PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | + PIOA_B4_MASK | PIOA_B5_MASK, + PAL_MODE_INPUT); + palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); + + /* + * MMC/SD slot setup. + */ + palSetGroupMode(IOPORT2, + PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, + PAL_MODE_INPUT); + + /* + * PIT Initialization. + */ + AIC_ConfigureIT(AT91C_ID_SYS, + AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), + SYSIrqHandler); + AIC_EnableIT(AT91C_ID_SYS); + AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; + AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + + /* + * Serial driver initialization, RTS/CTS pins enabled for USART0 only. + */ + sdInit(); + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; + AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; + + /* + * EMAC driver initialization. + */ + macInit(); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); +} diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.h b/demos/ARM7-AT91SAM7X-UIP-GCC/board.h new file mode 100644 index 000000000..c56f50258 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/board.h @@ -0,0 +1,78 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "at91lib/AT91SAM7X256.h" + +#define BOARD_OLIMEX_SAM7_EX256 + +#define CLK 18432000 +#define MCK 48054857 + +/* + * Initial I/O setup. + */ +#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOA_OSR 0x00000000 /* Direction. */ +#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ + +#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ +#define VAL_PIOB_OSR 0x00000000 /* Direction. */ +#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ + +/* + * I/O definitions. + */ +#define PIOA_LCD_RESET 2 +#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) +#define PIOA_B1 7 +#define PIOA_B1_MASK (1 << PIOA_B1) +#define PIOA_B2 8 +#define PIOA_B2_MASK (1 << PIOA_B2) +#define PIOA_B3 9 +#define PIOA_B3_MASK (1 << PIOA_B3) +#define PIOA_B4 14 +#define PIOA_B4_MASK (1 << PIOA_B4) +#define PIOA_B5 15 +#define PIOA_B5_MASK (1 << PIOA_B5) +#define PIOA_USB_PUP 25 +#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) +#define PIOA_USB_PR 26 +#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) + +#define PIOB_PHY_PD 18 +#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) +#define PIOB_AUDIO_OUT 19 +#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) +#define PIOB_LCD_BL 20 +#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) +#define PIOB_MMC_WP 22 +#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) +#define PIOB_MMC_CP 23 +#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) +#define PIOB_SW1 24 +#define PIOB_SW1_MASK (1 << PIOB_SW1) +#define PIOB_SW2 25 +#define PIOB_SW2_MASK (1 << PIOB_SW2) +#define PIOB_PHY_IRQ 26 +#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) + +#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld b/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld new file mode 100644 index 000000000..944a7f29d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld @@ -0,0 +1,98 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h new file mode 100644 index 000000000..3c6353168 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -0,0 +1,377 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file src/templates/chconf.h + * @brief Configuration file template. + * @addtogroup Config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * Frequency of the system timer that drives the system ticks. This also + * defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * This constant is the number of system ticks allowed for the threads before + * preemption occurs. This option is only meaningful if the option + * @p CH_USE_ROUNDROBIN is also active. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting is to leave + * this option disabled.
+ * You can use this option if you need to merge ChibiOS/RT with external + * libraries that require nested lock/unlock operations. + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * If specified then the kernel performs the round robin scheduling algorithm + * on threads of equal priority. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) +#define CH_USE_ROUNDROBIN TRUE +#endif + +/** + * Number of RAM bytes to use as system heap. If set to zero then the whole + * available RAM is used as system heap. + * @note In order to use the whole RAM as system heap the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) +#define CH_HEAP_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * If specified then time efficient rather than space efficient code is used + * when two possible implementations exist. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * If enabled defines a CPU register to be used as storage for the global + * @p currp variable. Caching this variable in a register can greatly + * improve both space and time efficiency of the generated code. Another side + * effect is that one less register has to be saved during the context switch + * resulting in lower RAM usage and faster code. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * If specified then the @p chThdWait() function is included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * If specified then the Semaphores APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * If enabled then the threads are enqueued on semaphores by priority rather + * than FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * If specified then the Semaphores the @p chSemWaitSignal() API is included + * in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * If specified then the Mutexes APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * If specified then the Conditional Variables APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * If specified then the Event flags APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * If specified then the @p chEvtWaitXXXTimeout() functions are included in + * the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * If specified then the Synchronous Messages APIs are included in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * If enabled then messages are served by priority rather than in FIFO order. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * If specified then the Asynchronous Messages (Mailboxes) APIs are included + * in the kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * If specified then the I/O queues APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * If specified then the memory heap allocator APIs are included in the kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * If enabled enforces the use of the C-runtime @p malloc() and @p free() + * functions as backend for the system heap allocator. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * If specified then the memory pools allocator APIs are included in the + * kernel. + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * If specified then the dynamic threads creation APIs are included in the + * kernel. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * Debug option, if enabled then the checks on the API functions input + * parameters are activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * Debug option, if enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, runtime + * anomalies and port-defined checks. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * Debug option, if enabled the context switch circular trace buffer is + * activated. + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * Debug option, if enabled a runtime stack check is performed. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented at all. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * Debug option, if enabled the threads working area is filled with a byte + * pattern when a thread is created. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * Debug option, if enabled a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add thread custom fields here.*/ \ +}; +#endif + +/** + * User initialization code added to the @p chThdInit() API. + * @note It is invoked from within @p chThdInit(). + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add thread initialization code here.*/ \ +} +#endif + +/** + * User finalization code added to the @p chThdExit() API. + * @note It is inserted into lock zone. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add thread finalization code here.*/ \ +} +#endif + +/** + * Code inserted inside the idle thread loop immediately after an interrupt + * resumed execution. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c new file mode 100644 index 000000000..0474ce008 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -0,0 +1,72 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include +#include + +#include "board.h" + +#include "web/webthread.h" + +static WORKING_AREA(waWebThread, 512); +static WORKING_AREA(waThread1, 128); + +static msg_t Thread1(void *arg) { + + while (TRUE) { + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker and web server threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waWebThread, sizeof(waWebThread), LOWPRIO, WebThread, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + if (!palReadPad(IOPORT2, PIOB_SW1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT2, PIOB_SW2)) + TestThread(&SD1); + } + + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt new file mode 100644 index 000000000..129f245c2 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt @@ -0,0 +1,34 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7X256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-EX256 board. + +** The Demo ** + +The demo currently just flashes the LCD background using a thread and serves +HTTP requests at address 192.168.1.20 on port 80 (remember to change it IP +address into webthread.c in order to adapt it to your network settings). +The button SW1 prints an "Hello World!" string on COM1, the button SW2 +activates che ChibiOS/RT test suite, output on COM1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. +The demo requires the patcher uIP 1.0 stack, see: ./ext/readme.txt + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/AT91SAM7X256/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com + +The uIP stack also has its own license, please read the info into the included +uIP distribution files. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h new file mode 100644 index 000000000..744cf56ef --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/cc-arch.h @@ -0,0 +1,9 @@ +#ifndef __CC_ARCH_H__ +#define __CC_ARCH_H__ + +#define PACK_STRUCT_FIELD(x) x __attribute__((packed)) +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_END + +#endif /* __CC_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h new file mode 100644 index 000000000..e205f9c8d --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/clock-arch.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +#include + +typedef systime_t clock_time_t; +#define CLOCK_CONF_SECOND CH_FREQUENCY + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h new file mode 100644 index 000000000..b6a17c970 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/uip-conf.h @@ -0,0 +1,159 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + +#include + +#include /* patched */ + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint8_t u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef uint16_t u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 40 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 40 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1518 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 1 + +/* Here we include the header file for the application(s) we use in + our project. */ +/*#include "smtp.h"*/ +/*#include "hello-world.h"*/ +/*#include "telnetd.h"*/ +#include "webserver.h" +/*#include "dhcpc.h"*/ +/*#include "resolv.h"*/ +/*#include "webclient.h"*/ + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c new file mode 100644 index 000000000..12c3b8405 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c @@ -0,0 +1,179 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#define IPADDR0 192 +#define IPADDR1 168 +#define IPADDR2 1 +#define IPADDR3 20 + +#define SEND_TIMEOUT 50 + +static const struct uip_eth_addr macaddr = { + {0xC2, 0xAF, 0x51, 0x03, 0xCF, 0x46} +}; + +#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + +/* + * uIP send function wrapping the EMAC functions. + */ +static void network_device_send(void) { + MACTransmitDescriptor td; + + if (macWaitTransmitDescriptor(Ð1, &td, MS2ST(SEND_TIMEOUT)) == RDY_OK) { + if(uip_len <= UIP_LLH_LEN + UIP_TCPIP_HLEN) + macWriteTransmitDescriptor(&td, uip_buf, uip_len); + else { + macWriteTransmitDescriptor(&td, uip_buf, UIP_LLH_LEN + UIP_TCPIP_HLEN); + macWriteTransmitDescriptor(&td, uip_appdata, + uip_len - (UIP_LLH_LEN + UIP_TCPIP_HLEN)); + } + macReleaseTransmitDescriptor(&td); + } + /* Dropped... */ +} + +/* + * uIP receive function wrapping the EMAC function. + */ +static size_t network_device_read(void) { + MACReceiveDescriptor rd; + size_t size; + + if (macWaitReceiveDescriptor(Ð1, &rd, TIME_IMMEDIATE) != RDY_OK) + return 0; + size = rd.rd_size; + macReadReceiveDescriptor(&rd, uip_buf, size); + macReleaseReceiveDescriptor(&rd); + return size; +} + +void clock_init(void) {} + +clock_time_t clock_time( void ) +{ + return chTimeNow(); +} + +/* + * TCP/IP periodic timer. + */ +static void PeriodicTimerHandler(eventid_t id) { + int i; + + for (i = 0; i < UIP_CONNS; i++) { + uip_periodic(i); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } +} + +/* + * ARP periodic timer. + */ +static void ARPTimerHandler(eventid_t id) { + + (void)macPollLinkStatus(Ð1); + uip_arp_timer(); +} + +/* + * Ethernet frame received. + */ +static void FrameReceivedHandler(eventid_t id) { + + while ((uip_len = network_device_read()) > 0) { + if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if (uip_len > 0) { + uip_arp_out(); + network_device_send(); + } + } + else if (BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if (uip_len > 0) + network_device_send(); + } + } +} + +#define FRAME_RECEIVED_ID 0 +#define PERIODIC_TIMER_ID 1 +#define ARP_TIMER_ID 2 + +static const evhandler_t evhndl[] = { + FrameReceivedHandler, + PeriodicTimerHandler, + ARPTimerHandler +}; + +msg_t WebThread(void *p) { + EvTimer evt1, evt2; + EventListener el0, el1, el2; + uip_ipaddr_t ipaddr; + + /* + * Event sources setup. + */ + chEvtRegister(macGetReceiveEventSource(Ð1), &el0, FRAME_RECEIVED_ID); + chEvtPend(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ + + evtInit(&evt1, MS2ST(500)); + evtStart(&evt1); + chEvtRegister(&evt1.et_es, &el1, PERIODIC_TIMER_ID); + + evtInit(&evt2, S2ST(10)); + evtStart(&evt2); + chEvtRegister(&evt2.et_es, &el2, ARP_TIMER_ID); + + /* + * EMAC settings. + */ + macSetAddress(Ð1, &macaddr.addr[0]); + (void)macPollLinkStatus(Ð1); + + /* + * uIP initialization. + */ + uip_init(); + uip_setethaddr(macaddr); + uip_ipaddr(ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3); + uip_sethostaddr(ipaddr); + httpd_init(); + + while (TRUE) { + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + } + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h new file mode 100644 index 000000000..bd71b4dc4 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _WEBTHREAD_H_ +#define _WEBTHREAD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + msg_t WebThread(void *p); + #ifdef __cplusplus +} +#endif + +#endif /* _WEBTHREAD_H_ */ -- cgit v1.2.3 From f1badd1b2946417f65230bc5d1608b837391125f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Oct 2009 18:01:55 +0000 Subject: Added runtime lwip settings. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1216 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 25 ++++++++++++++++++++----- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h | 10 ++++++++++ 2 files changed, 30 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index bb9f8ae5b..d89ab25ee 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -220,7 +220,7 @@ static err_t ethernetif_init(struct netif *netif) { /** * @brief LWIP handling thread. * - * @param[in] p not used + * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL * @return The function does not return. */ msg_t lwip_thread(void *p) { @@ -238,10 +238,25 @@ msg_t lwip_thread(void *p) { ip_init(); tcpip_init(NULL, NULL); - /* TCP/IP parameters.*/ - LWIP_IPADDR(&ip); - LWIP_GATEWAY(&gateway); - LWIP_NETMASK(&netmask); + /* TCP/IP parameters, runtime or compile time.*/ + if (p) { + struct lwipthread_opts *opts = p; + if (opts->macaddress) { + unsigned i; + + for (i = 0; i < 6; i++) + thisif.hwaddr[i] = opts->macaddress[i]; + macSetAddress(Ð1, thisif.hwaddr); + } + ip.addr = opts->address; + gateway.addr = opts->gateway; + netmask.addr = opts->netmask; + } + else { + LWIP_IPADDR(&ip); + LWIP_GATEWAY(&gateway); + LWIP_NETMASK(&netmask); + } netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); netif_set_default(&thisif); diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h index fe939a178..7e001ddd1 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h @@ -102,6 +102,16 @@ #define LWIP_IFNAME1 's' #endif +/** + * @brief Runtime TCP/IP settings. + */ +struct lwipthread_opts { + uint8_t *macaddress; + uint32_t address; + uint32_t netmask; + uint32_t gateway; +}; + extern WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); #ifdef __cplusplus -- cgit v1.2.3 From 1b7bfa2fa713c75df4bbea37fc50b1d6d7b93839 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Oct 2009 18:56:06 +0000 Subject: Fixed a bug in lwip_thread(). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1217 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 12 +++++++++--- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h | 10 +++++----- 2 files changed, 14 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index d89ab25ee..6741630cb 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -92,12 +92,12 @@ static void low_level_init(struct netif *netif) { netif->hwaddr_len = ETHARP_HWADDR_LEN; /* set MAC hardware address */ - netif->hwaddr[0] = 0xC2; +/* netif->hwaddr[0] = 0xC2; netif->hwaddr[1] = 0xAF; netif->hwaddr[2] = 0x51; netif->hwaddr[3] = 0x03; netif->hwaddr[4] = 0xCF; - netif->hwaddr[5] = 0x46; + netif->hwaddr[5] = 0x46;*/ /* maximum transfer unit */ netif->mtu = 1500; @@ -246,17 +246,23 @@ msg_t lwip_thread(void *p) { for (i = 0; i < 6; i++) thisif.hwaddr[i] = opts->macaddress[i]; - macSetAddress(Ð1, thisif.hwaddr); } ip.addr = opts->address; gateway.addr = opts->gateway; netmask.addr = opts->netmask; } else { + thisif.hwaddr[0] = LWIP_ETHADDR_0; + thisif.hwaddr[1] = LWIP_ETHADDR_1; + thisif.hwaddr[2] = LWIP_ETHADDR_2; + thisif.hwaddr[3] = LWIP_ETHADDR_3; + thisif.hwaddr[4] = LWIP_ETHADDR_4; + thisif.hwaddr[5] = LWIP_ETHADDR_5; LWIP_IPADDR(&ip); LWIP_GATEWAY(&gateway); LWIP_NETMASK(&netmask); } + macSetAddress(Ð1, thisif.hwaddr); netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); netif_set_default(&thisif); diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h index 7e001ddd1..6fa4cbe7e 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h @@ -68,27 +68,27 @@ #endif /** @brief MAC Address byte 1. */ -#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__) #define LWIP_ETHADDR_1 0xAF #endif /** @brief MAC Address byte 2. */ -#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__) #define LWIP_ETHADDR_2 0x51 #endif /** @brief MAC Address byte 3. */ -#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__) #define LWIP_ETHADDR_3 0x03 #endif /** @brief MAC Address byte 4. */ -#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__) #define LWIP_ETHADDR_4 0xCF #endif /** @brief MAC Address byte 5. */ -#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__) #define LWIP_ETHADDR_5 0x46 #endif -- cgit v1.2.3 From e1eef3b01547597ce8d84759c6fc7613243ccf9a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 12 Oct 2009 17:55:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1219 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 17 +++-------------- demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h | 2 +- 2 files changed, 4 insertions(+), 15 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 6741630cb..c9752cb46 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -91,14 +91,6 @@ static void low_level_init(struct netif *netif) { /* set MAC hardware address length */ netif->hwaddr_len = ETHARP_HWADDR_LEN; - /* set MAC hardware address */ -/* netif->hwaddr[0] = 0xC2; - netif->hwaddr[1] = 0xAF; - netif->hwaddr[2] = 0x51; - netif->hwaddr[3] = 0x03; - netif->hwaddr[4] = 0xCF; - netif->hwaddr[5] = 0x46;*/ - /* maximum transfer unit */ netif->mtu = 1500; @@ -107,7 +99,6 @@ static void low_level_init(struct netif *netif) { netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; /* Do whatever else is needed to initialize interface. */ - macSetAddress(Ð1, netif->hwaddr); } /* @@ -241,12 +232,10 @@ msg_t lwip_thread(void *p) { /* TCP/IP parameters, runtime or compile time.*/ if (p) { struct lwipthread_opts *opts = p; - if (opts->macaddress) { - unsigned i; + unsigned i; - for (i = 0; i < 6; i++) - thisif.hwaddr[i] = opts->macaddress[i]; - } + for (i = 0; i < 6; i++) + thisif.hwaddr[i] = opts->macaddress[i]; ip.addr = opts->address; gateway.addr = opts->gateway; netmask.addr = opts->netmask; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h index 17c799866..298bc9585 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwipopts.h @@ -271,7 +271,7 @@ * (requires NO_SYS==0) */ #ifndef MEMP_NUM_SYS_TIMEOUT -#define MEMP_NUM_SYS_TIMEOUT 3 +#define MEMP_NUM_SYS_TIMEOUT (4 + LWIP_DHCP + LWIP_DNS) #endif /** -- cgit v1.2.3 From 2c46df1916a25b7880416aee974a518cc607717a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Oct 2009 17:45:19 +0000 Subject: New heap manager. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1221 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 255 ++++++++++++++------- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 255 ++++++++++++++------- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 6 +- 3 files changed, 345 insertions(+), 171 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index ba2e6d048..31c3c7a50 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE +#define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index e6a58ce12..b12b89b93 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE +#define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,41 +412,49 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ /* Space for the LWIP sys_timeouts structure.*/ \ void *p_lwipspace[1]; \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ (tp)->p_lwipspace[0] = NULL; \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index 7d39c9520..65b1b5314 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -66,7 +66,7 @@ void sys_init(void) { sys_sem_t sys_sem_new(u8_t count) { - sys_sem_t sem = chHeapAlloc(sizeof(Semaphore)); + sys_sem_t sem = chHeapAlloc(NULL, sizeof(Semaphore)); chSemInit(sem, (cnt_t)count); return sem; } @@ -97,7 +97,7 @@ u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) { sys_mbox_t sys_mbox_new(int size) { sys_mbox_t mbox; - mbox = chHeapAlloc(sizeof(Mailbox) + sizeof(msg_t) * size); + mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size); chMBInit(mbox, (void *)(((uint8_t *)mbox) + sizeof(Mailbox)), size); return mbox; } @@ -147,7 +147,7 @@ struct sys_timeouts *sys_arch_timeouts(void) { sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio) { size_t wsz = THD_WA_SIZE(stacksize); - void *wsp = chHeapAlloc(wsz); + void *wsp = chCoreAlloc(wsz); if (wsp == NULL) return NULL; return (sys_thread_t)chThdCreateStatic(wsp, wsz, prio, (tfunc_t)thread, arg); -- cgit v1.2.3 From b8654b471d0752cc84b0642e13ed5f4aa19fd7c1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Oct 2009 17:50:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1222 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 253 +++++++++++++++++++++++----------- demos/ARM7-LPC214x-G++/chconf.h | 253 +++++++++++++++++++++++----------- demos/ARM7-LPC214x-GCC/chconf.h | 253 +++++++++++++++++++++++----------- demos/ARMCM3-STM32F103-GCC/chconf.h | 253 +++++++++++++++++++++++----------- 4 files changed, 680 insertions(+), 332 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 3c6353168..31c3c7a50 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 3c6353168..31c3c7a50 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 3c6353168..31c3c7a50 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 3c6353168..31c3c7a50 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ -- cgit v1.2.3 From 0c0d93a91e14e60c58148f65bde4d7f45a26c67c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 16 Oct 2009 18:24:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1223 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 253 ++++++++++++++++++++---------- demos/AVR-AT90CANx-GCC/chconf.h | 253 ++++++++++++++++++++---------- demos/AVR-ATmega128-GCC/chconf.h | 253 ++++++++++++++++++++---------- demos/GNU-Linux-GCC/chconf.h | 259 ++++++++++++++++++++----------- demos/MSP430-MSP430x1611-GCC/chconf.h | 253 ++++++++++++++++++++---------- demos/Win32-MinGW/chconf.h | 267 +++++++++++++++++++++----------- 6 files changed, 1019 insertions(+), 519 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index 08663fea3..fd2e6f6ad 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN FALSE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES FALSE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE FALSE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING FALSE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index cb7da16d3..c4ebe589f 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 512 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 512 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index cb7da16d3..c4ebe589f 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 512 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 512 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/GNU-Linux-GCC/chconf.h b/demos/GNU-Linux-GCC/chconf.h index 273ba602f..dc3fcf69e 100644 --- a/demos/GNU-Linux-GCC/chconf.h +++ b/demos/GNU-Linux-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 100 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0x20000 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,19 +271,24 @@ #endif /** - * If specified then the full duplex serial driver APIs are included in the - * kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_QUEUES. */ -#if !defined(CH_USE_SERIAL_FULLDUPLEX) || defined(__DOXYGEN__) -#define CH_USE_SERIAL_FULLDUPLEX TRUE +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -253,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -272,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -286,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -295,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -305,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -314,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -343,42 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ - /* The thread termination \p EventSource.*/ \ - EventSource p_exitesource; \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ - chEvtInit(&tp->p_exitesource); \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ - chEvtBroadcastI(&currp->p_exitesource); \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ @@ -386,8 +459,6 @@ struct { \ } #endif -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) - #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 2f018c290..7452a6778 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 100 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 10 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 512 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 512 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,38 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ + /* Add threads custom fields here.*/ \ }; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ + /* Add threads initialization code here.*/ \ } #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ + /* Add threads finalization code here.*/ \ } #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 8c124180e..fda335bc7 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -18,9 +18,9 @@ */ /** - * @file src/templates/chconf.h + * @file templates/chconf.h * @brief Configuration file template. - * @addtogroup Config + * @addtogroup config * @{ */ @@ -32,29 +32,36 @@ /*===========================================================================*/ /** - * Frequency of the system timer that drives the system ticks. This also - * defines the system tick time unit. + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) #define CH_FREQUENCY 1000 #endif /** - * This constant is the number of system ticks allowed for the threads before - * preemption occurs. This option is only meaningful if the option - * @p CH_USE_ROUNDROBIN is also active. + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting is to leave - * this option disabled.
- * You can use this option if you need to merge ChibiOS/RT with external - * libraries that require nested lock/unlock operations. + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) @@ -62,23 +69,18 @@ #endif /** - * If specified then the kernel performs the round robin scheduling algorithm - * on threads of equal priority. - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_ROUNDROBIN) || defined(__DOXYGEN__) -#define CH_USE_ROUNDROBIN TRUE -#endif - -/** - * Number of RAM bytes to use as system heap. If set to zero then the whole - * available RAM is used as system heap. - * @note In order to use the whole RAM as system heap the linker script must + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_HEAP. + * @note Requires @p CH_USE_COREMEM. */ -#if !defined(CH_HEAP_SIZE) || defined(__DOXYGEN__) -#define CH_HEAP_SIZE 0x20000 +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0x20000 #endif /*===========================================================================*/ @@ -86,8 +88,10 @@ /*===========================================================================*/ /** - * If specified then time efficient rather than space efficient code is used - * when two possible implementations exist. + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ @@ -96,18 +100,20 @@ #endif /** - * If enabled defines a CPU register to be used as storage for the global - * @p currp variable. Caching this variable in a register can greatly - * improve both space and time efficiency of the generated code. Another side - * effect is that one less register has to be saved during the context switch - * resulting in lower RAM usage and faster code. + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * * @note This option is only usable with the GCC compiler and is only useful * on processors with many registers like ARM cores. * @note If this option is enabled then ALL the libraries linked to the * ChibiOS/RT code must be recompiled with the GCC option @p * -ffixed-@. * @note This option must be enabled in the Makefile, it is listed here for - * documentation. + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -118,7 +124,10 @@ /*===========================================================================*/ /** - * If specified then the @p chThdWait() function is included in the kernel. + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) @@ -126,7 +135,9 @@ #endif /** - * If specified then the Semaphores APIs are included in the kernel. + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) @@ -134,8 +145,10 @@ #endif /** - * If enabled then the threads are enqueued on semaphores by priority rather - * than FIFO order. + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -144,8 +157,10 @@ #endif /** - * If specified then the Semaphores the @p chSemWaitSignal() API is included - * in the kernel. + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -154,7 +169,9 @@ #endif /** - * If specified then the Mutexes APIs are included in the kernel. + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) @@ -162,7 +179,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_MUTEXES. */ @@ -171,7 +191,10 @@ #endif /** - * If specified then the Conditional Variables APIs are included in the kernel. + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_CONDVARS. */ @@ -180,7 +203,9 @@ #endif /** - * If specified then the Event flags APIs are included in the kernel. + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) @@ -188,8 +213,10 @@ #endif /** - * If specified then the @p chEvtWaitXXXTimeout() functions are included in - * the kernel. + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_EVENTS. */ @@ -198,7 +225,10 @@ #endif /** - * If specified then the Synchronous Messages APIs are included in the kernel. + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) @@ -206,7 +236,10 @@ #endif /** - * If enabled then messages are served by priority rather than in FIFO order. + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * * @note The default is @p FALSE. Enable this if you have special requirements. * @note Requires @p CH_USE_MESSAGES. */ @@ -215,16 +248,21 @@ #endif /** - * If specified then the Asynchronous Messages (Mailboxes) APIs are included - * in the kernel. + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * If specified then the I/O queues APIs are included in the kernel. + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_SEMAPHORES. */ @@ -233,9 +271,24 @@ #endif /** - * If specified then the memory heap allocator APIs are included in the kernel. + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES or @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) @@ -243,18 +296,24 @@ #endif /** - * If enabled enforces the use of the C-runtime @p malloc() and @p free() - * functions as backend for the system heap allocator. + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * * @note The default is @p FALSE. * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * If specified then the memory pools allocator APIs are included in the - * kernel. + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) @@ -262,8 +321,10 @@ #endif /** - * If specified then the dynamic threads creation APIs are included in the - * kernel. + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * * @note The default is @p TRUE. * @note Requires @p CH_USE_WAITEXIT. */ @@ -276,8 +337,10 @@ /*===========================================================================*/ /** - * Debug option, if enabled then the checks on the API functions input - * parameters are activated. + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) @@ -285,9 +348,11 @@ #endif /** - * Debug option, if enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, runtime - * anomalies and port-defined checks. + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) @@ -295,8 +360,10 @@ #endif /** - * Debug option, if enabled the context switch circular trace buffer is - * activated. + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) @@ -304,25 +371,37 @@ #endif /** - * Debug option, if enabled a runtime stack check is performed. + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented at all. + * may not be implemented or some ports. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * Debug option, if enabled the threads working area is filled with a byte - * pattern when a thread is created. + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * Debug option, if enabled a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -333,42 +412,46 @@ /*===========================================================================*/ /** - * User fields added to the end of the @p Thread structure. + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ struct { \ - /* Add thread custom fields here.*/ \ - /* The thread termination \p EventSource.*/ \ - EventSource p_exitesource; \ -}; + /* Add threads custom fields here.*/ \ + /* The thread termination \p EventSource.*/ \ EventSource p_exitesource; \}; #endif /** - * User initialization code added to the @p chThdInit() API. - * @note It is invoked from within @p chThdInit(). + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ - /* Add thread initialization code here.*/ \ - chEvtInit(&tp->p_exitesource); \ -} + /* Add threads initialization code here.*/ \ + chEvtInit(&tp->p_exitesource); \} #endif /** - * User finalization code added to the @p chThdExit() API. + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ - /* Add thread finalization code here.*/ \ - chEvtBroadcastI(&currp->p_exitesource); \ -} + /* Add threads finalization code here.*/ \ + chEvtBroadcastI(&currp->p_exitesource); \} #endif /** - * Code inserted inside the idle thread loop immediately after an interrupt - * resumed execution. + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) #define IDLE_LOOP_HOOK() { \ @@ -376,8 +459,6 @@ struct { \ } #endif -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) - -#endif /* _CHCONF_H_ */ +#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource)#endif /* _CHCONF_H_ */ /** @} */ -- cgit v1.2.3 From d61cb88dab424a8edcf3b2a06a0c7ea18890208a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Oct 2009 07:35:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1224 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chconf.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index fda335bc7..cef71f8c5 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -419,7 +419,9 @@ #define THREAD_EXT_FIELDS \ struct { \ /* Add threads custom fields here.*/ \ - /* The thread termination \p EventSource.*/ \ EventSource p_exitesource; \}; + /* The thread termination \p EventSource.*/ \ + EventSource p_exitesource; \ +}; #endif /** @@ -432,7 +434,8 @@ struct { \ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add threads initialization code here.*/ \ - chEvtInit(&tp->p_exitesource); \} + chEvtInit(&tp->p_exitesource); \ +} #endif /** @@ -446,7 +449,8 @@ struct { \ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add threads finalization code here.*/ \ - chEvtBroadcastI(&currp->p_exitesource); \} + chEvtBroadcastI(&currp->p_exitesource); \ +} #endif /** @@ -459,6 +463,8 @@ struct { \ } #endif -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource)#endif /* _CHCONF_H_ */ +#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) + +#endif /* _CHCONF_H_ */ /** @} */ -- cgit v1.2.3 From 26ed3732876a649fb02a83e768e4392034d65653 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Oct 2009 10:33:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1229 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 4 ++-- demos/ARM7-AT91SAM7X-GCC/main.c | 5 ++++- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 4 ++-- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 2 ++ demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 2 ++ demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 4 ++++ demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c | 6 ++++-- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 4 ++-- demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 4 ++++ demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c | 5 +++++ 10 files changed, 31 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index fa6f56c8c..65a658661 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -125,10 +125,10 @@ AOPT = TOPT = -mthumb -DTHUMB # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index f6c297a41..36ae17fae 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -25,8 +25,9 @@ #include "board.h" static WORKING_AREA(waThread1, 64); -static msg_t Thread1(void *arg) { +static msg_t Thread1(void *p) { + (void)p; while (TRUE) { palSetPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(100); @@ -41,6 +42,8 @@ static msg_t Thread1(void *arg) { * on entry. */ int main(int argc, char **argv) { + (void)argc; + (void)argv; /* * Activates the serial driver 1 using the driver default configuration. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 62a8d217c..699a8c834 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -139,10 +139,10 @@ AOPT = TOPT = -mthumb -DTHUMB # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index 65b1b5314..0a78a3653 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -146,6 +146,7 @@ struct sys_timeouts *sys_arch_timeouts(void) { sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio) { + (void)name; size_t wsz = THD_WA_SIZE(stacksize); void *wsp = chCoreAlloc(wsz); if (wsp == NULL) @@ -161,5 +162,6 @@ sys_prot_t sys_arch_protect(void) { void sys_arch_unprotect(sys_prot_t pval) { + (void)pval; chSysUnlock(); } diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index c9752cb46..36ca3fd37 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -108,6 +108,7 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p) { struct pbuf *q; MACTransmitDescriptor td; + (void)netif; if (macWaitTransmitDescriptor(Ð1, &td, MS2ST(LWIP_SEND_TIMEOUT)) != RDY_OK) return ERR_TIMEOUT; @@ -138,6 +139,7 @@ static struct pbuf *low_level_input(struct netif *netif) { struct pbuf *p, *q; u16_t len; + (void)netif; if (macWaitReceiveDescriptor(Ð1, &rd, TIME_IMMEDIATE) == RDY_OK) { len = (u16_t)rd.rd_size; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index d7d1836da..14ac139d9 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -29,6 +29,7 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { + (void)arg; while (TRUE) { palClearPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(900); @@ -44,6 +45,9 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + (void)argc; + (void)argv; + /* * Activates the serial driver 1 using the driver default configuration. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c index 88701ce3e..c64f2e47d 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c @@ -39,8 +39,8 @@ #if LWIP_NETCONN -const static char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; -const static char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; +static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n"; +static const char http_index_html[] = "Congrats!

Welcome to our lwIP HTTP server!

This is a small test page."; static void http_server_serve(struct netconn *conn) { struct netbuf *inbuf; @@ -92,6 +92,8 @@ WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); msg_t http_server(void *p) { struct netconn *conn, *newconn; + (void)p; + /* Create a new TCP connection handle */ conn = netconn_new(NETCONN_TCP); LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;); diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index 95d046fef..77695a569 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -143,10 +143,10 @@ AOPT = TOPT = -mthumb -DTHUMB # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c index 0474ce008..5b366b0b0 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -31,6 +31,7 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + (void)arg; while (TRUE) { palSetPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(100); @@ -46,6 +47,9 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + (void)argc; + (void)argv; + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c index 12c3b8405..1be4df645 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c @@ -88,6 +88,7 @@ clock_time_t clock_time( void ) static void PeriodicTimerHandler(eventid_t id) { int i; + (void)id; for (i = 0; i < UIP_CONNS; i++) { uip_periodic(i); if (uip_len > 0) { @@ -102,6 +103,7 @@ static void PeriodicTimerHandler(eventid_t id) { */ static void ARPTimerHandler(eventid_t id) { + (void)id; (void)macPollLinkStatus(Ð1); uip_arp_timer(); } @@ -111,6 +113,7 @@ static void ARPTimerHandler(eventid_t id) { */ static void FrameReceivedHandler(eventid_t id) { + (void)id; while ((uip_len = network_device_read()) > 0) { if (BUF->type == HTONS(UIP_ETHTYPE_IP)) { uip_arp_ipin(); @@ -143,6 +146,8 @@ msg_t WebThread(void *p) { EventListener el0, el1, el2; uip_ipaddr_t ipaddr; + (void)p; + /* * Event sources setup. */ -- cgit v1.2.3 From e9d7b9de5705a3b5c0b822077fbd165c86087481 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Oct 2009 11:07:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1230 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 4 ++-- demos/ARM7-LPC214x-G++/main.cpp | 4 ++++ demos/ARM7-LPC214x-GCC-minimal/Makefile | 4 ++-- demos/ARM7-LPC214x-GCC-minimal/main.c | 5 +++++ demos/ARM7-LPC214x-GCC/Makefile | 4 ++-- demos/ARM7-LPC214x-GCC/buzzer.c | 5 ++--- demos/ARM7-LPC214x-GCC/main.c | 8 ++++++++ demos/ARM7-LPC214x-GCC/mmcsd.c | 1 + demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- demos/ARMCM3-STM32F103-GCC/main.c | 4 ++++ demos/MSP430-MSP430x1611-GCC/Makefile | 4 ++-- demos/MSP430-MSP430x1611-GCC/main.c | 4 ++++ demos/Win32-MinGW/Makefile | 2 +- demos/Win32-MinGW/chcore.c | 3 ++- demos/Win32-MinGW/main.c | 6 +++++- 15 files changed, 46 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 3b0a8bee3..3bb33abfe 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -126,10 +126,10 @@ AOPT = TOPT = -mthumb -DTHUMB # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index b46ccd86e..f0268045d 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -137,6 +137,7 @@ public: */ static void TimerHandler(eventid_t id) { + (void)id; if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { // Both buttons TesterThread tester; tester.Wait(); @@ -154,6 +155,9 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0; + (void)argc; + (void)argv; + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 5315948af..21e9a0eea 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -123,10 +123,10 @@ AOPT = TOPT = -mthumb -DTHUMB # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index d303237c4..7ce5ffe95 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -28,6 +28,7 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + (void)arg; while (TRUE) { palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(200); @@ -47,6 +48,7 @@ static msg_t Thread1(void *arg) { static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { + (void)arg; while (TRUE) { palClearPad(IOPORT1, PA_LEDUSB); chThdSleepMilliseconds(200); @@ -62,6 +64,9 @@ static msg_t Thread2(void *arg) { */ int main(int argc, char **argv) { + (void)argc; + (void)argv; + /* * Creates the blinker threads. */ diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 54b1e0ffd..792ff4fbd 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -127,10 +127,10 @@ AOPT = TOPT = -mthumb -DTHUMB # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index 25be0e2d9..1d3350bb2 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -58,9 +58,8 @@ void InitBuzzer(void) { } static void stop(void *p) { - TC *tc = T1Base; - StopCounter(tc); + StopCounter((TC *)p); chEvtBroadcastI(&BuzzerSilentEventSource); } @@ -77,7 +76,7 @@ void PlaySound(int freq, systime_t duration) { tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); StartCounter(tc); - chVTSetI(&bvt, duration, stop, NULL); + chVTSetI(&bvt, duration, stop, tc); chSysUnlock(); } diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index a8db1b667..93b6fd768 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -35,6 +35,7 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + (void)arg; while (TRUE) { palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); chThdSleepMilliseconds(200); @@ -54,6 +55,7 @@ static msg_t Thread1(void *arg) { static WORKING_AREA(waThread2, 128); static msg_t Thread2(void *arg) { + (void)arg; while (TRUE) { palClearPad(IOPORT1, PA_LEDUSB); chThdSleepMilliseconds(200); @@ -70,6 +72,7 @@ static WORKING_AREA(waTestThread, 128); */ static void TimerHandler(eventid_t id) { + (void)id; if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), NORMALPRIO, TestThread, &SD1); @@ -94,6 +97,7 @@ static void InsertHandler(eventid_t id) { static uint8_t rwbuf[512]; MMCCSD data; + (void)id; PlaySoundWait(1000, MS2ST(100)); PlaySoundWait(2000, MS2ST(100)); if (mmcInit()) @@ -111,6 +115,7 @@ static void InsertHandler(eventid_t id) { */ static void RemoveHandler(eventid_t id) { + (void)id; PlaySoundWait(2000, MS2ST(100)); PlaySoundWait(1000, MS2ST(100)); } @@ -128,6 +133,9 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0, el1, el2; + (void)argc; + (void)argv; + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index aba532544..731f594a2 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -42,6 +42,7 @@ void InitMMC(void) { void tmrfunc(void *par) { + (void)par; if (cnt) { if (!palReadPad(IOPORT2, PB_CP1)) { if (!--cnt) diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index ca12fd05d..4919e567e 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -139,10 +139,10 @@ AOPT = TOPT = -mthumb -DTHUMB # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index ca2fa842b..fcc496648 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -30,6 +30,7 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + (void)arg; while (TRUE) { palClearPad(IOPORT3, GPIOC_LED); chThdSleepMilliseconds(500); @@ -45,6 +46,9 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + (void)argc; + (void)argv; + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index dc3747875..7a7a720a8 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -91,10 +91,10 @@ HEX = $(CP) -O ihex BIN = $(CP) -O binary # Define C warning options here -CWARN = -Wall -Wstrict-prototypes +CWARN = -Wall -Wextra -Wstrict-prototypes # Define C++ warning options here -CPPWARN = -Wall +CPPWARN = -Wall -Wextra # # Compiler settings diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 02622e817..3e729296b 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -30,6 +30,7 @@ static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { + (void)arg; while (TRUE) { palSetPad(IOPORT6, P6_O_LED); chThdSleepMilliseconds(500); @@ -44,6 +45,9 @@ static msg_t Thread1(void *arg) { */ int main(int argc, char **argv) { + (void)argc; + (void)argv; + /* * Hardware initialization, see board.c. */ diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index f700ce159..3552537ad 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -99,7 +99,7 @@ LIBS = $(DLIBS) $(ULIBS) LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 95d8b9de8..8dcb3b9ad 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -89,8 +89,9 @@ void ChkIntSources(void) { */ __attribute__((used)) static void __dummy(Thread *otp, Thread *ntp) { + (void)otp; (void)ntp; asm volatile (".globl @port_switch@8 \n\t" \ - "@port_switch@8: \n\t" \ + "@port_switch@8: \n\t" \ "push %ebp \n\t" \ "push %esi \n\t" \ "push %edi \n\t" \ diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index bca8af11b..6a2b5367f 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -42,10 +42,11 @@ msg_t TestThread(void *p); * areas. The system is halted if something is wrong. */ static msg_t WatchdogThread(void *arg) { + + (void)arg; wdguard = 0xA51F2E3D; cdguard = 0xA51F2E3D; while (TRUE) { - if ((wdguard != 0xA51F2E3D) || (cdguard != 0xA51F2E3D)) { printf("Halted by watchdog"); @@ -64,6 +65,7 @@ static msg_t WatchdogThread(void *arg) { */ static msg_t ConsoleThread(void *arg) { + (void)arg; while (!chThdShouldTerminate()) { printf((char *)chMsgWait()); fflush(stdout); @@ -230,6 +232,7 @@ EventListener s1tel; static void COM1Handler(eventid_t id) { sdflags_t flags; + (void)id; if (s1 && chThdTerminated(s1)) { s1 = NULL; cprint("Init: disconnection on SD1\n"); @@ -256,6 +259,7 @@ EventListener s2tel; static void COM2Handler(eventid_t id) { sdflags_t flags; + (void)id; if (s2 && chThdTerminated(s2)) { s2 = NULL; cprint("Init: disconnection on SD2\n"); -- cgit v1.2.3 From efa39b271f134bca4fe609671944cada0c409c9a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Oct 2009 11:23:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1231 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index 77695a569..9b526bda4 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -72,6 +72,7 @@ CSRC = ${PORTSRC} \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/mii_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/various/syscalls.c \ ${CHIBIOS}/os/various/evtimer.c \ web/webthread.c \ board.c main.c -- cgit v1.2.3 From eff9b996a45cb2bbf4e7bef3e08d01abb518cf65 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Oct 2009 11:55:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1233 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c index 5b366b0b0..03435d98b 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -26,7 +26,7 @@ #include "web/webthread.h" -static WORKING_AREA(waWebThread, 512); +static WORKING_AREA(waWebThread, 1024); static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { -- cgit v1.2.3 From b11fd131f4e1984f7dd0e66efda0c1b78fac4d38 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Oct 2009 19:43:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1237 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h index 6fa4cbe7e..b086ce7ef 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h @@ -58,7 +58,7 @@ #endif /** @brief Link speed. */ -#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__) +#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__) #define LWIP_LINK_SPEED 100000000 #endif -- cgit v1.2.3 From 6dfbaa34d96d3571fc28aba6179268c1df595b2f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 18 Oct 2009 07:43:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1238 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chconf.h | 2 +- demos/AVR-ATmega128-GCC/chconf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index c4ebe589f..f962e4c16 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -80,7 +80,7 @@ * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 512 +#define CH_MEMCORE_SIZE 128 #endif /*===========================================================================*/ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index c4ebe589f..f962e4c16 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -80,7 +80,7 @@ * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 512 +#define CH_MEMCORE_SIZE 128 #endif /*===========================================================================*/ -- cgit v1.2.3 From fb68f0d51775b7e0bafa82fa67573e652babb6a6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Oct 2009 10:09:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1251 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 ++ demos/ARMCM3-STM32F103-GCC/board.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 4919e567e..8f3e902ed 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -68,8 +68,10 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/spi.c \ ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/various/evtimer.c \ board.c main.c diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index f9364b02b..ac936f2a1 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -24,13 +24,11 @@ * Tricks required to make the TRUE/FALSE declaration inside the library * compatible. */ -#ifndef __STM32F10x_H #undef FALSE #undef TRUE #include #define FALSE 0 #define TRUE (!FALSE) -#endif /* * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. -- cgit v1.2.3 From 43f9fd4180030081daae9122bd57a521ec9c58e1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 30 Oct 2009 15:45:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1258 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 3 ++- demos/ARM7-AT91SAM7X-LWIP-GCC/board.c | 3 ++- demos/ARM7-AT91SAM7X-UIP-GCC/board.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 31e362845..3faae501a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -25,7 +25,7 @@ #include "at91lib/aic.h" /* - * FIQ Handler weak symbol defined in vectors.s. + * FIQ Handler weak symbol defined in vectors.s. */ void FiqHandler(void); @@ -123,6 +123,7 @@ void hwinit1(void) { * Default AIC setup, the device drivers will modify it as needed. */ AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; for (i = 1; i < 31; i++) { AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c index 5b95524f8..e988aaa86 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c @@ -26,7 +26,7 @@ #include "at91lib/aic.h" /* - * FIQ Handler weak symbol defined in vectors.s. + * FIQ Handler weak symbol defined in vectors.s. */ void FiqHandler(void); @@ -124,6 +124,7 @@ void hwinit1(void) { * Default AIC setup, the device drivers will modify it as needed. */ AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; for (i = 1; i < 31; i++) { AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c index 348f4bb99..9dbd5f0e4 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c @@ -27,7 +27,7 @@ /* - * FIQ Handler weak symbol defined in vectors.s. + * FIQ Handler weak symbol defined in vectors.s. */ void FiqHandler(void); @@ -125,6 +125,7 @@ void hwinit1(void) { * Default AIC setup, the device drivers will modify it as needed. */ AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; for (i = 1; i < 31; i++) { AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; -- cgit v1.2.3 From a95d728fc36f0d96c08a78b6af543a440217d3a4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 31 Oct 2009 15:22:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1259 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 1 + demos/ARMCM3-STM32F103-GCC/board.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 8f3e902ed..2e65c9c16 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -72,6 +72,7 @@ CSRC = ${PORTSRC} \ ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ ${CHIBIOS}/os/various/evtimer.c \ board.c main.c diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 6c8bf8c0a..050c2be62 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -19,10 +19,12 @@ #include #include +#include +#include +#include #include #include "board.h" -#include "serial.h" #define AIRCR_VECTKEY 0x05FA0000 @@ -112,7 +114,9 @@ void hwinit1(void) { /* * Other subsystems initialization. */ + dmaInit(); sdInit(); + spiInit(); /* * ChibiOS/RT initialization. -- cgit v1.2.3 From 639d957e5eacffffb849b976552b39a2b66433aa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 1 Nov 2009 19:18:09 +0000 Subject: Bug 2890382. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1263 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/main.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index fcc496648..943509849 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -19,15 +19,16 @@ #include #include +#include +#include #include #include "board.h" -#include "serial.h" /* * Red LEDs blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread1, 128); +static WORKING_AREA(waThread1, 512); static msg_t Thread1(void *arg) { (void)arg; @@ -40,6 +41,10 @@ static msg_t Thread1(void *arg) { return 0; } +static SPIConfig spicfg = { + 16, IOPORT1, 4, 0 +}; + /* * Entry point, note, the main() function is already a thread in the system * on entry. @@ -59,6 +64,11 @@ int main(int argc, char **argv) { */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + palSetPadMode(IOPORT1, 4, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT1, 4); + spiStart(&SPID1, &spicfg); + spiStop(&SPID1); + /* * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop and check the button state. -- cgit v1.2.3 From 493c21948bdca96c6632a5afcd8c4e63f8151910 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 2 Nov 2009 21:45:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1266 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/main.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 943509849..d3889251a 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -45,6 +45,9 @@ static SPIConfig spicfg = { 16, IOPORT1, 4, 0 }; +static uint8_t txbuf[8] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF}; +static uint8_t rxbuf[8]; + /* * Entry point, note, the main() function is already a thread in the system * on entry. @@ -67,6 +70,9 @@ int main(int argc, char **argv) { palSetPadMode(IOPORT1, 4, PAL_MODE_OUTPUT_PUSHPULL); palSetPad(IOPORT1, 4); spiStart(&SPID1, &spicfg); + spiSelect(&SPID1); + spiExchange(&SPID1, 8, txbuf, rxbuf); + spiUnselect(&SPID1); spiStop(&SPID1); /* -- cgit v1.2.3 From 0bd69a2cb10011aa34897d747df6a959121a1e4e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 7 Nov 2009 08:59:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1271 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/main.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index d3889251a..116a0aaf1 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -41,13 +41,6 @@ static msg_t Thread1(void *arg) { return 0; } -static SPIConfig spicfg = { - 16, IOPORT1, 4, 0 -}; - -static uint8_t txbuf[8] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF}; -static uint8_t rxbuf[8]; - /* * Entry point, note, the main() function is already a thread in the system * on entry. @@ -67,14 +60,6 @@ int main(int argc, char **argv) { */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - palSetPadMode(IOPORT1, 4, PAL_MODE_OUTPUT_PUSHPULL); - palSetPad(IOPORT1, 4); - spiStart(&SPID1, &spicfg); - spiSelect(&SPID1); - spiExchange(&SPID1, 8, txbuf, rxbuf); - spiUnselect(&SPID1); - spiStop(&SPID1); - /* * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop and check the button state. -- cgit v1.2.3 From 09c69c89337a9e00f8b13cd170bebba3f57a2028 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 13 Nov 2009 21:09:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1284 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 2e65c9c16..9129cd687 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -38,7 +38,7 @@ endif # Enable this if you really want to use the STM FWLib. ifeq ($(USE_FWLIB),) - USE_FWLIB = no + USE_FWLIB = yes endif # @@ -69,13 +69,13 @@ CSRC = ${PORTSRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ ${CHIBIOS}/os/io/spi.c \ + ${CHIBIOS}/os/io/mmc_spi.c \ ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ ${CHIBIOS}/os/various/evtimer.c \ - board.c main.c - + board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -108,8 +108,7 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ${CHIBIOS}/os/io \ ${CHIBIOS}/os/io/platforms/STM32 \ - ${CHIBIOS}/os/various \ - ./stm32lib/inc + ${CHIBIOS}/os/various # # Project, sources and paths @@ -198,8 +197,9 @@ ULIBS = ############################################################################## ifeq ($(USE_FWLIB),yes) - include ./stm32lib/stm32lib.mk + include ${CHIBIOS}/ext/stm32lib/stm32lib.mk CSRC += ${STM32SRC} + INCDIR += ${STM32INC} USE_OPT += -DUSE_STDPERIPH_DRIVER endif -- cgit v1.2.3 From e340ae2337ea5d4073fca8dcba8c3215984578d7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 13 Nov 2009 21:15:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1285 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/board.c | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 9129cd687..decfbb466 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -38,7 +38,7 @@ endif # Enable this if you really want to use the STM FWLib. ifeq ($(USE_FWLIB),) - USE_FWLIB = yes + USE_FWLIB = no endif # diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 050c2be62..dac529780 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -20,8 +20,6 @@ #include #include #include -#include -#include #include #include "board.h" @@ -114,9 +112,7 @@ void hwinit1(void) { /* * Other subsystems initialization. */ - dmaInit(); sdInit(); - spiInit(); /* * ChibiOS/RT initialization. -- cgit v1.2.3 From f217c7a99c4a1ded3f9c53a121433cc66d3c2063 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 13 Nov 2009 21:16:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1286 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h | 219 -- .../stm32lib/inc/stm32f10x_adc.h | 479 ---- .../stm32lib/inc/stm32f10x_bkp.h | 194 -- .../stm32lib/inc/stm32f10x_can.h | 535 ---- .../stm32lib/inc/stm32f10x_conf.h | 76 - .../stm32lib/inc/stm32f10x_crc.h | 93 - .../stm32lib/inc/stm32f10x_dac.h | 282 -- .../stm32lib/inc/stm32f10x_dbgmcu.h | 109 - .../stm32lib/inc/stm32f10x_dma.h | 437 --- .../stm32lib/inc/stm32f10x_exti.h | 183 -- .../stm32lib/inc/stm32f10x_flash.h | 346 --- .../stm32lib/inc/stm32f10x_fsmc.h | 716 ----- .../stm32lib/inc/stm32f10x_gpio.h | 359 --- .../stm32lib/inc/stm32f10x_i2c.h | 472 ---- .../stm32lib/inc/stm32f10x_iwdg.h | 139 - .../stm32lib/inc/stm32f10x_pwr.h | 155 -- .../stm32lib/inc/stm32f10x_rcc.h | 700 ----- .../stm32lib/inc/stm32f10x_rtc.h | 134 - .../stm32lib/inc/stm32f10x_sdio.h | 530 ---- .../stm32lib/inc/stm32f10x_spi.h | 490 ---- .../stm32lib/inc/stm32f10x_tim.h | 1040 -------- .../stm32lib/inc/stm32f10x_usart.h | 409 --- .../stm32lib/inc/stm32f10x_wwdg.h | 114 - .../stm32lib/src/stm32f10x_adc.c | 1306 --------- .../stm32lib/src/stm32f10x_bkp.c | 311 --- .../stm32lib/src/stm32f10x_can.c | 990 ------- .../stm32lib/src/stm32f10x_crc.c | 163 -- .../stm32lib/src/stm32f10x_dac.c | 431 --- .../stm32lib/src/stm32f10x_dbgmcu.c | 152 -- .../stm32lib/src/stm32f10x_dma.c | 693 ----- .../stm32lib/src/stm32f10x_exti.c | 268 -- .../stm32lib/src/stm32f10x_flash.c | 874 ------ .../stm32lib/src/stm32f10x_fsmc.c | 858 ------ .../stm32lib/src/stm32f10x_gpio.c | 617 ----- .../stm32lib/src/stm32f10x_i2c.c | 1152 -------- .../stm32lib/src/stm32f10x_iwdg.c | 189 -- .../stm32lib/src/stm32f10x_pwr.c | 311 --- .../stm32lib/src/stm32f10x_rcc.c | 1447 ---------- .../stm32lib/src/stm32f10x_rtc.c | 341 --- .../stm32lib/src/stm32f10x_sdio.c | 798 ------ .../stm32lib/src/stm32f10x_spi.c | 907 ------- .../stm32lib/src/stm32f10x_tim.c | 2799 -------------------- .../stm32lib/src/stm32f10x_usart.c | 967 ------- .../stm32lib/src/stm32f10x_wwdg.c | 223 -- demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk | 22 - 45 files changed, 24030 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h delete mode 100644 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demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h deleted file mode 100644 index db6426244..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/misc.h +++ /dev/null @@ -1,219 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/** @defgroup MISC_Exported_Types - * @{ - */ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, please - refer to stm32f10x.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup NVIC_Priority_Table - * @{ - */ - -/** -@code - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endcode -*/ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) - -/** - * @} - */ - -/** @defgroup SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Functions - * @{ - */ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h deleted file mode 100644 index fd02a62cd..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_adc.h +++ /dev/null @@ -1,479 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_ADC_H -#define __STM32F10x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; -/** - * @} - */ - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_mode - * @{ - */ - -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_Mode_RegInjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ - ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ - ((MODE) == ADC_Mode_InjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult) || \ - ((MODE) == ADC_Mode_FastInterl) || \ - ((MODE) == ADC_Mode_SlowInterl) || \ - ((MODE) == ADC_Mode_AlterTrig)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_None) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) -/** - * @} - */ - -/** @defgroup ADC_sampling_time - * @{ - */ - -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ - ((TIME) == ADC_SampleTime_7Cycles5) || \ - ((TIME) == ADC_SampleTime_13Cycles5) || \ - ((TIME) == ADC_SampleTime_28Cycles5) || \ - ((TIME) == ADC_SampleTime_41Cycles5) || \ - ((TIME) == ADC_SampleTime_55Cycles5) || \ - ((TIME) == ADC_SampleTime_71Cycles5) || \ - ((TIME) == ADC_SampleTime_239Cycles5)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) -/** - * @} - */ - -/** @defgroup ADC_injected_channel_selection - * @{ - */ - -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_injected_rank - * @{ - */ - -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) - -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - -/** @defgroup ADC_regular_rank - * @{ - */ - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) - -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -void ADC_DeInit(ADC_TypeDef* ADCx); -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h deleted file mode 100644 index 531d61f17..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_bkp.h +++ /dev/null @@ -1,194 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the BKP firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_BKP_H -#define __STM32F10x_BKP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup BKP - * @{ - */ - -/** @defgroup BKP_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Constants - * @{ - */ - -/** @defgroup Tamper_Pin_active_level - * @{ - */ - -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) -#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ - ((LEVEL) == BKP_TamperPinLevel_Low)) -/** - * @} - */ - -/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin - * @{ - */ - -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) -#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ - ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ - ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ - ((SOURCE) == BKP_RTCOutputSource_Second)) -/** - * @} - */ - -/** @defgroup Data_Backup_Register - * @{ - */ - -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ - ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ - ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ - ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ - ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ - ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ - ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ - ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ - ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ - ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ - ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ - ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ - ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ - ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) - -#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Functions - * @{ - */ - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_BKP_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h deleted file mode 100644 index 712e34c00..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_can.h +++ /dev/null @@ -1,535 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CAN_H -#define __STM32F10x_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Exported_Types - * @{ - */ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ - -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware - is allowed to lengthen or shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ - -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter can be a value between 0 to 0xFF */ -} CanRxMsg; - -/** - * @} - */ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */ - -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ - -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ - -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ - -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) - -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#ifndef STM32F10X_CL - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) -#else - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ - -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ - -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) - -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ - -#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/** - * @} - */ - -/** @defgroup Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ - -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) - -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ - -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) - -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ - -#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */ -#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ - -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ - -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ - -#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ - -#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ - -#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\ - ((FLAG) == CAN_FLAG_BOF)) - -/** - * @} - */ - -/** @defgroup CAN_interrupts - * @{ - */ - -#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */ -#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */ -#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */ - -#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\ - ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions - * @{ - */ - -void CAN_DeInit(CAN_TypeDef* CANx); -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CAN_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h deleted file mode 100644 index e7805cfd9..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_conf.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - ****************************************************************************** - * @file Project/Template/stm32f10x_conf.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief Library configuration file. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CONF_H -#define __STM32F10x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Uncomment the line below to enable peripheral header file inclusion */ -/* #include "stm32f10x_adc.h" */ -/* #include "stm32f10x_bkp.h" */ -/* #include "stm32f10x_can.h" */ -/* #include "stm32f10x_crc.h" */ -/* #include "stm32f10x_dac.h" */ -/* #include "stm32f10x_dbgmcu.h" */ -/* #include "stm32f10x_dma.h" */ -#include "stm32f10x_exti.h" -/* #include "stm32f10x_flash.h" */ -#include "stm32f10x_fsmc.h" -#include "stm32f10x_gpio.h" -/* #include "stm32f10x_i2c.h" */ -/* #include "stm32f10x_iwdg.h" */ -/* #include "stm32f10x_pwr.h" */ -#include "stm32f10x_rcc.h" -/* #include "stm32f10x_rtc.h" */ -/* #include "stm32f10x_sdio.h" */ -#include "stm32f10x_spi.h" -/* #include "stm32f10x_tim.h" */ -#include "stm32f10x_usart.h" -/* #include "stm32f10x_wwdg.h" */ -#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F10x_CONF_H */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h deleted file mode 100644 index 848c15ff2..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_crc.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CRC_H -#define __STM32F10x_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions - * @{ - */ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CRC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h deleted file mode 100644 index 6c4bc8003..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dac.h +++ /dev/null @@ -1,282 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DAC_H -#define __STM32F10x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Exported_Types - * @{ - */ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in High-density devices*/ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in Connectivity line devices */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions - * @{ - */ - -void DAC_DeInit(void); -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DAC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h deleted file mode 100644 index 0889683a5..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dbgmcu.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the DBGMCU - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DBGMCU_H -#define __STM32F10x_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/** @defgroup DBGMCU_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) - -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFC000F8) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Functions - * @{ - */ - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_DBGMCU_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h deleted file mode 100644 index 9a1fe4b78..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_dma.h +++ /dev/null @@ -1,437 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DMA_H -#define __STM32F10x_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Exported_Types - * @{ - */ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7) || \ - ((PERIPH) == DMA2_Channel1) || \ - ((PERIPH) == DMA2_Channel2) || \ - ((PERIPH) == DMA2_Channel3) || \ - ((PERIPH) == DMA2_Channel4) || \ - ((PERIPH) == DMA2_Channel5)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ - ((DIR) == DMA_DIR_PeripheralSRC)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ - ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ - ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ - ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ - ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ - ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ - ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ - ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ - ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ - ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ - ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ - ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ - ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ - ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ - ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ - ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ - ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ - ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ - ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ - ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ - ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) -/** - * @} - */ - -/** @defgroup DMA_Buffer_Size - * @{ - */ - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions - * @{ - */ - -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); -void DMA_ClearFlag(uint32_t DMA_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMA_IT); -void DMA_ClearITPendingBit(uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DMA_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h deleted file mode 100644 index 8c011c1c8..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_exti.h +++ /dev/null @@ -1,183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_EXTI_H -#define __STM32F10x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/** @defgroup EXTI_Exported_Types - * @{ - */ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_flash.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_flash.h deleted file mode 100644 index 1c310231c..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_flash.h +++ /dev/null @@ -1,346 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FLASH_H -#define __STM32F10x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @defgroup FLASH_Exported_Types - * @{ - */ - -/** - * @brief FLASH Status - */ - -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ - -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup Half_Cycle_Enable_Disable - * @{ - */ - -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ -#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ - ((STATE) == FLASH_HalfCycleAccess_Disable)) -/** - * @} - */ - -/** @defgroup Prefetch_Buffer_Enable_Disable - * @{ - */ - -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ -#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ - ((STATE) == FLASH_PrefetchBuffer_Disable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - -/* Values to be used with STM32 Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ - -/* Values to be used with STM32 Medium-density devices */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ - -/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ -#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 0 to 1 */ -#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 2 to 3 */ -#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 4 to 5 */ -#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 6 to 7 */ -#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 8 to 9 */ -#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 10 to 11 */ -#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 12 to 13 */ -#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 14 to 15 */ -#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 16 to 17 */ -#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 18 to 19 */ -#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 20 to 21 */ -#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 22 to 23 */ -#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 24 to 25 */ -#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 26 to 27 */ -#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 28 to 29 */ -#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 30 to 31 */ -#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 32 to 33 */ -#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 34 to 35 */ -#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 36 to 37 */ -#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 38 to 39 */ -#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 40 to 41 */ -#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 42 to 43 */ -#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 44 to 45 */ -#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 46 to 47 */ -#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 48 to 49 */ -#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 50 to 51 */ -#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 52 to 53 */ -#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 54 to 55 */ -#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 56 to 57 */ -#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 58 to 59 */ -#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 Medium-density and Connectivity line devices: - Write protection of page 60 to 61 */ -#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ -#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - -#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ - -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ - -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions - * @{ - */ - -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG); -void FLASH_ClearFlag(uint16_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_FLASH_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_fsmc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_fsmc.h deleted file mode 100644 index 1340e218a..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_fsmc.h +++ /dev/null @@ -1,716 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FSMC_H -#define __STM32F10x_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/** @defgroup FSMC_Exported_Types - * @{ - */ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ - -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note: It is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The value of this parameter depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don’t care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ - -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) - -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ - -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) - -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ - -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ - -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ - -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ - -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ - -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ - -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) - -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ - -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ - -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ - -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ - -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ - -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) - -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ - -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ - -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) - -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ - -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ - -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Functions - * @{ - */ - -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_PCCARDDeInit(void); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_PCCARDCmd(FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_gpio.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_gpio.h deleted file mode 100644 index 94f234d8d..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_gpio.h +++ /dev/null @@ -1,359 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_GPIO_H -#define __STM32F10x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** @defgroup GPIO_Exported_Types - * @{ - */ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG)) - -/** - * @brief Output Maximum frequency selection - */ - -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)) - -/** - * @brief Configuration Mode enumeration - */ - -typedef enum -{ GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ - ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ - ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ - ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) - -/** - * @brief GPIO Init structure definition - */ - -typedef struct -{ - uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - - -/** - * @brief Bit_SET and Bit_RESET enumeration - */ - -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ - -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Remap_define - * @{ - */ - -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ -#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected - to TIM2 Internal Trigger 1 for calibration - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ - ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ - ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ - ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ - ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ - ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ - ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ - ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ - ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ - ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ - ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ - ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ - ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS)) - -/** - * @} - */ - -/** @defgroup GPIO_Port_Sources - * @{ - */ - -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) -#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE)) - -#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOG)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ - -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) - -/** - * @} - */ - -/** @defgroup Ethernet_Media_Interface - * @{ - */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - -#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ - ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) - -/** - * @} - */ -/** - * @} - */ - -/** @defgroup GPIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_i2c.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_i2c.h deleted file mode 100644 index 4da8ed30b..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_i2c.h +++ /dev/null @@ -1,472 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_I2C_H -#define __STM32F10x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/** - * @} - */ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - * @brief EV1 - */ - -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief EV2 - */ - -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ - -/** - * @brief EV3 - */ - -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ - -/** - * @brief EV4 - */ - -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/** - * @brief EV5 - */ - -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief EV6 - */ - -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ - -/** - * @brief EV7 - */ - -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/** - * @brief EV8 - */ - -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ - -/** - * @brief EV8_2 - */ - -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - -/** - * @brief EV9 - */ - -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief EV3_2 - */ - -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ - -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_I2C_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_iwdg.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_iwdg.h deleted file mode 100644 index d32fb0aae..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_iwdg.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_IWDG_H -#define __STM32F10x_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/** @defgroup IWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions - * @{ - */ - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_IWDG_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_pwr.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_pwr.h deleted file mode 100644 index e435ee3a6..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_pwr.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_PWR_H -#define __STM32F10x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/** @defgroup PWR_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ - ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ - ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ - ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) -/** - * @} - */ - -/** @defgroup Regulator_state_is_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_PWR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h deleted file mode 100644 index c2a0339ca..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rcc.h +++ /dev/null @@ -1,700 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the RCC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RCC_H -#define __STM32F10x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @defgroup RCC_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/** - * @} - */ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup PLL_entry_clock_source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) - -#ifndef STM32F10X_CL - #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) - #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div2)) -#else - #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup PLL_multiplication_factor - * @{ - */ -#ifndef STM32F10X_CL - #define RCC_PLLMul_2 ((uint32_t)0x00000000) - #define RCC_PLLMul_3 ((uint32_t)0x00040000) - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_10 ((uint32_t)0x00200000) - #define RCC_PLLMul_11 ((uint32_t)0x00240000) - #define RCC_PLLMul_12 ((uint32_t)0x00280000) - #define RCC_PLLMul_13 ((uint32_t)0x002C0000) - #define RCC_PLLMul_14 ((uint32_t)0x00300000) - #define RCC_PLLMul_15 ((uint32_t)0x00340000) - #define RCC_PLLMul_16 ((uint32_t)0x00380000) - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) - -#else - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) - - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_6_5)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -#ifdef STM32F10X_CL -/** @defgroup PREDIV1_division_factor - * @{ - */ - #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) - #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) - #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) - #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) - #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) - #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) - #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) - #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) - #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) - #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) - #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) - #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) - #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) - #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) - #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) - - #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -/** - * @} - */ - - -/** @defgroup PREDIV1_clock_source - * @{ - */ -/* PREDIV1 clock source (only for STM32 connectivity line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ - ((SOURCE) == RCC_PREDIV1_Source_PLL2)) -/** - * @} - */ - - -/** @defgroup PREDIV2_division_factor - * @{ - */ - - #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) - #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) - #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) - #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) - #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) - #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) - #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) - #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) - #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) - #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) - #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) - #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) - #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) - #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) - #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) - - #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ - ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ - ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ - ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ - ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ - ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ - ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ - ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) -/** - * @} - */ - - -/** @defgroup PLL2_multiplication_factor - * @{ - */ - - #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) - #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) - #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) - #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) - #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) - #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) - #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) - #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) - #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) - - #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ - ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ - ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ - ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ - ((MUL) == RCC_PLL2Mul_20)) -/** - * @} - */ - - -/** @defgroup PLL3_multiplication_factor - * @{ - */ - - #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) - #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) - #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) - #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) - #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) - #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) - #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) - #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) - #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) - - #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ - ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ - ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ - ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ - ((MUL) == RCC_PLL3Mul_20)) -/** - * @} - */ - -#endif /* STM32F10X_CL */ - - -/** @defgroup System_clock_source - * @{ - */ - -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup AHB_clock_source - * @{ - */ - -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup APB1_APB2_clock_source - * @{ - */ - -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#ifndef STM32F10X_CL - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) - #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) -#else - #define RCC_IT_PLL2RDY ((uint8_t)0x20) - #define RCC_IT_PLL3RDY ((uint8_t)0x40) - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) - #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) -#endif /* STM32F10X_CL */ - - -/** - * @} - */ - -#ifndef STM32F10X_CL -/** @defgroup USB_Device_clock_source - * @{ - */ - - #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) - #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - - #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) -#else -/** @defgroup USB_OTG_FS_clock_source - * @{ - */ - #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) - #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) - - #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ - ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -#ifdef STM32F10X_CL -/** @defgroup I2S2_clock_source - * @{ - */ - #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) -/** - * @} - */ - -/** @defgroup I2S3_clock_source - * @{ - */ - #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -/** @defgroup ADC_clock_source - * @{ - */ - -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ - ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) -/** - * @} - */ - -/** @defgroup LSE_configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RTC_clock_source - * @{ - */ - -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) -/** - * @} - */ - -/** @defgroup AHB_peripheral - * @{ - */ - -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) - -#ifndef STM32F10X_CL - #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) - #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) -#else - #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) - #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) - #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) - #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) - - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) - #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup APB2_peripheral - * @{ - */ - -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) -#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup APB1_peripheral - * @{ - */ - -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup Clock_source_to_output_on_MCO_pin - * @{ - */ - -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -#ifndef STM32F10X_CL - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2)) -#else - #define RCC_MCO_PLL2CLK ((uint8_t)0x08) - #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) - #define RCC_MCO_XT1 ((uint8_t)0x0A) - #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) - - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ - ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ - ((MCO) == RCC_MCO_PLL3CLK)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ - -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#ifndef STM32F10X_CL - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#else - #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) - #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#endif /* STM32F10X_CL */ - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions - * @{ - */ - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); - -#ifdef STM32F10X_CL - void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); - void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); - void RCC_PLL2Config(uint32_t RCC_PLL2Mul); - void RCC_PLL2Cmd(FunctionalState NewState); - void RCC_PLL3Config(uint32_t RCC_PLL3Mul); - void RCC_PLL3Cmd(FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); - -#ifndef STM32F10X_CL - void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -#else - void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); -#endif /* STM32F10X_CL */ - -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); - -#ifdef STM32F10X_CL - void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); - void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); -#endif /* STM32F10X_CL */ - -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -#ifdef STM32F10X_CL -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RCC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rtc.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rtc.h deleted file mode 100644 index 8e40d0291..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_rtc.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RTC_H -#define __STM32F10x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - -/** @defgroup RTC_interrupts_define - * @{ - */ - -#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ -#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ - ((IT) == RTC_IT_SEC)) -/** - * @} - */ - -/** @defgroup RTC_interrupts_flags - * @{ - */ - -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ -#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ - ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ - ((FLAG) == RTC_FLAG_SEC)) -#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions - * @{ - */ - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RTC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_sdio.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_sdio.h deleted file mode 100644 index 4c7a04a43..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_sdio.h +++ /dev/null @@ -1,530 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SDIO_H -#define __STM32F10x_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/** @defgroup SDIO_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_soucres - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Functions - * @{ - */ - -void SDIO_DeInit(void); -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -void SDIO_DMACmd(FunctionalState NewState); -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_SDIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_spi.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_spi.h deleted file mode 100644 index 8c006b8e2..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_spi.h +++ /dev/null @@ -1,490 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the SPI firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SPI_H -#define __STM32F10x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Exported_Types - * @{ - */ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be any combination of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be any combination of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be any combination of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be any combination of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be any combination of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be any combination of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be any combination of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be any combination of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be any combination of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be any combination of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be any combination of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be any combination of @ref I2S_MCLK_Output */ - - uint16_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be any combination of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be any combination of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/** - * @} - */ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx) || \ - ((MODE) == I2S_Mode_MasterRx) ) -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_96k ((uint16_t)96000) -#define I2S_AudioFreq_48k ((uint16_t)48000) -#define I2S_AudioFreq_44k ((uint16_t)44100) -#define I2S_AudioFreq_32k ((uint16_t)32000) -#define I2S_AudioFreq_22k ((uint16_t)22050) -#define I2S_AudioFreq_16k ((uint16_t)16000) -#define I2S_AudioFreq_11k ((uint16_t)11025) -#define I2S_AudioFreq_8k ((uint16_t)8000) -#define I2S_AudioFreq_Default ((uint16_t)2) -#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \ - ((FREQ) == I2S_AudioFreq_48k) || \ - ((FREQ) == I2S_AudioFreq_44k) || \ - ((FREQ) == I2S_AudioFreq_32k) || \ - ((FREQ) == I2S_AudioFreq_22k) || \ - ((FREQ) == I2S_AudioFreq_16k) || \ - ((FREQ) == I2S_AudioFreq_11k) || \ - ((FREQ) == I2S_AudioFreq_8k) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_mangement - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ - ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions - * @{ - */ - -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_SPI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_tim.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_tim.h deleted file mode 100644 index 323169bde..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_tim.h +++ /dev/null @@ -1,1040 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_TIM_H -#define __STM32F10x_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/** @defgroup TIM_Exported_Types - * @{ - */ - -/** - * @brief TIM Time Base Init structure definition - * @note This sturcture is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This sturcture is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) - -#define IS_TIM_18_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) - -#define IS_TIM_123458_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_state - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_state - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_state - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ - ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_18Bytes)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) -#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Ouput_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Ouput_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Ouput_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - - -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions - * @{ - */ - -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_TIM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_usart.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_usart.h deleted file mode 100644 index 976a06c62..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_usart.h +++ /dev/null @@ -1,409 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_USART_H -#define __STM32F10x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Exported_Types - * @{ - */ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/** - * @} - */ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4)) -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) -#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ - ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ - || ((USART_FLAG) != USART_FLAG_CTS)) -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions - * @{ - */ - -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); -void USART_SendBreak(USART_TypeDef* USARTx); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_USART_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_wwdg.h b/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_wwdg.h deleted file mode 100644 index 39dc8e9a3..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/inc/stm32f10x_wwdg.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_WWDG_H -#define __STM32F10x_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/** @defgroup WWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions - * @{ - */ - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_adc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_adc.c deleted file mode 100644 index 882455d4e..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_adc.c +++ /dev/null @@ -1,1306 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the ADC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_adc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_Set ((uint32_t)0x00000800) -#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_Set ((uint32_t)0x00000400) -#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CR2_ADON_Set ((uint32_t)0x00000001) -#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_Set ((uint32_t)0x00000100) -#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_Set ((uint32_t)0x0000001F) -#define SQR2_SQ_Set ((uint32_t)0x0000001F) -#define SQR1_SQ_Set ((uint32_t)0x0000001F) - -/* SQR1 register Mask */ -#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_Set ((uint32_t)0x00300000) -#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_Set ((uint32_t)0x00000007) -#define SMPR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_Offset ((uint8_t)0x28) - -/* ADC1 DR register base address */ -#define DR_ADDRESS ((uint32_t)0x4001244C) - -/** - * @} - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if (ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if (ADCx == ADC2) - { - /* Enable ADC2 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - /* Release ADC2 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } - else - { - if (ADCx == ADC3) - { - /* Enable ADC3 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); - /* Release ADC3 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); - } - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - /* Clear DUALMOD and SCAN bits */ - tmpreg1 &= CR1_CLEAR_Mask; - /* Configure ADCx: Dual mode and scan conversion mode */ - /* Set DUALMOD bits according to ADC_Mode value */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - /* Clear CONT, ALIGN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_Mask; - /* Configure ADCx: external trigger event and continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= SQR1_CLEAR_Mask; - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfChannel value */ - tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - /* Initialize the ADC_NbrOfChannel member */ - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= CR2_ADON_Set; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= CR2_ADON_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. - * Note: ADC2 hasn't a DMA capability. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= CR2_DMA_Set; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= CR2_DMA_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Resets the selected ADC calibration registers. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_ResetCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Resets the selected ADC calibartion registers */ - ADCx->CR2 |= CR2_RSTCAL_Set; -} - -/** - * @brief Gets the selected ADC reset calibration registers status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC reset calibration registers (SET or RESET). - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of RSTCAL bit */ - if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) - { - /* RSTCAL bit is set */ - bitstatus = SET; - } - else - { - /* RSTCAL bit is reset */ - bitstatus = RESET; - } - /* Return the RSTCAL bit status */ - return bitstatus; -} - -/** - * @brief Starts the selected ADC calibration process. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_StartCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC calibration process */ - ADCx->CR2 |= CR2_CAL_Set; -} - -/** - * @brief Gets the selected ADC calibration status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC calibration (SET or RESET). - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of CAL bit */ - if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) - { - /* CAL bit is set: calibration on going */ - bitstatus = SET; - } - else - { - /* CAL bit is reset: end of calibration */ - bitstatus = RESET; - } - /* Return the CAL bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC software start conversion . - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event and start the selected - ADC conversion */ - ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event and stop the selected - ADC conversion */ - ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the SWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_Reset; - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= CR1_DISCEN_Set; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= CR1_DISCEN_Reset; - } -} - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables or disables the ADCx conversion through external trigger. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event */ - ADCx->CR2 |= CR2_EXTTRIG_Set; - } - else - { - /* Disable the selected ADC conversion on external event */ - ADCx->CR2 &= CR2_EXTTRIG_Reset; - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * @retval The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - /* Return the dual mode conversion value */ - return (*(__IO uint32_t *) DR_ADDRESS); -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= CR1_JAUTO_Set; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= CR1_JAUTO_Reset; - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= CR1_JDISCEN_Set; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= CR1_JDISCEN_Reset; - } -} - -/** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 - * capture compare4 event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not - * by external trigger (for ADC1, ADC2 and ADC3) - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_Reset; - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of - * injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC external event selection for injected group */ - ADCx->CR2 |= CR2_JEXTTRIG_Set; - } - else - { - /* Disable the selected ADC external event selection for injected group */ - ADCx->CR2 &= CR2_JEXTTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion for injected group on external event and start the selected - ADC injected conversion */ - ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event for injected group and stop the selected - ADC injected conversion */ - ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Clear the old injected sequnence lenght JL bits */ - tmpreg1 &= JSQR_JL_Reset; - /* Set the injected sequnence lenght JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_Offset; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - tmpreg &= CR1_AWDMode_Reset; - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_Reset; - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Enables or disables the temperature sensor and Vrefint channel. - * @param NewState: new state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC1->CR2 |= CR2_TSVREFE_Set; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC1->CR2 &= CR2_TSVREFE_Reset; - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx’s interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_bkp.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_bkp.c deleted file mode 100644 index e4653a795..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_bkp.c +++ /dev/null @@ -1,311 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the BKP firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_bkp.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup BKP - * @brief BKP driver modules - * @{ - */ - -/** @defgroup BKP_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Defines - * @{ - */ - -/* ------------ BKP registers bit address in the alias region --------------- */ -#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) - -/* --- CR Register ----*/ - -/* Alias word address of TPAL bit */ -#define CR_OFFSET (BKP_OFFSET + 0x30) -#define TPAL_BitNumber 0x01 -#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) - -/* Alias word address of TPE bit */ -#define TPE_BitNumber 0x00 -#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TPIE bit */ -#define CSR_OFFSET (BKP_OFFSET + 0x34) -#define TPIE_BitNumber 0x02 -#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) - -/* Alias word address of TIF bit */ -#define TIF_BitNumber 0x09 -#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) - -/* Alias word address of TEF bit */ -#define TEF_BitNumber 0x08 -#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) - -/* ---------------------- BKP registers bit mask ------------------------ */ - -/* RTCCR register bit mask */ -#define RTCCR_CAL_Mask ((uint16_t)0xFF80) -#define RTCCR_Mask ((uint16_t)0xFC7F) - -/* CSR register bit mask */ -#define CSR_CTE_Set ((uint16_t)0x0001) -#define CSR_CTI_Set ((uint16_t)0x0002) - -/** - * @} - */ - - -/** @defgroup BKP_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * @param None - * @retval None - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/** - * @brief Configures the Tamper Pin active level. - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * This parameter can be one of the following values: - * @arg BKP_TamperPinLevel_High: Tamper pin active on high level - * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level - * @retval None - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - /* Check the parameters */ - assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); - *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; -} - -/** - * @brief Enables or disables the Tamper Pin activation. - * @param NewState: new state of the Tamper Pin activation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Tamper Pin Interrupt. - * @param NewState: new state of the Tamper Pin Interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; -} - -/** - * @brief Select the RTC output source to output on the Tamper pin. - * @param BKP_RTCOutputSource: specifies the RTC output source. - * This parameter can be one of the following values: - * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. - * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency - * divided by 64 on the Tamper pin. - * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on - * the Tamper pin. - * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on - * the Tamper pin. - * @retval None - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); - tmpreg = BKP->RTCCR; - /* Clear CCO, ASOE and ASOS bits */ - tmpreg &= RTCCR_Mask; - - /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ - tmpreg |= BKP_RTCOutputSource; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Sets RTC Clock Calibration value. - * @param CalibrationValue: specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x7F. - * @retval None - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); - tmpreg = BKP->RTCCR; - /* Clear CAL[6:0] bits */ - tmpreg &= RTCCR_CAL_Mask; - /* Set CAL[6:0] bits according to CalibrationValue value */ - tmpreg |= CalibrationValue; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Writes user data to the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @param Data: data to write - * @retval None - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Reads data from the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @retval The content of the specified Data Backup Register - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Checks whether the Tamper Pin Event flag is set or not. - * @param None - * @retval The new state of the Tamper Pin Event flag (SET or RESET). - */ -FlagStatus BKP_GetFlagStatus(void) -{ - return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); -} - -/** - * @brief Clears Tamper Pin Event pending flag. - * @param None - * @retval None - */ -void BKP_ClearFlag(void) -{ - /* Set CTE bit to clear Tamper Pin Event flag */ - BKP->CSR |= CSR_CTE_Set; -} - -/** - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * @param None - * @retval The new state of the Tamper Pin Interrupt (SET or RESET). - */ -ITStatus BKP_GetITStatus(void) -{ - return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); -} - -/** - * @brief Clears Tamper Pin Interrupt pending bit. - * @param None - * @retval None - */ -void BKP_ClearITPendingBit(void) -{ - /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ - BKP->CSR |= CSR_CTI_Set; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_can.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_can.c deleted file mode 100644 index d459a1066..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_can.c +++ /dev/null @@ -1,990 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the CAN firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_can.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ - -/** @defgroup CAN_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Defines - * @{ - */ - -/* CAN Master Control Register bits */ -#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */ -#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */ -#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */ -#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */ -#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */ -#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */ -#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */ -#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */ -#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Master Status Register bits */ -#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */ -#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */ -#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */ - -/* CAN Transmit Status Register bits */ -#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */ -#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */ -#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */ -#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */ -#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */ -#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */ -#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */ -#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */ -#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */ -#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */ -#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */ -#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */ - -/* CAN Receive FIFO 0 Register bits */ -#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */ -#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */ -#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */ - -/* CAN Receive FIFO 1 Register bits */ -#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */ -#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */ -#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */ - -/* CAN Error Status Register bits */ -#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */ -#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */ -#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TimeOut ((uint32_t)0x0000FFFF) - -/* Time out for SLAK bit */ -#define SLAK_TimeOut ((uint32_t)0x0000FFFF) - -/** - * @} - */ - -/** @defgroup CAN_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_FunctionPrototypes - * @{ - */ - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** - * @} - */ - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CANINITFAILED or CANINITOK. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CANINITFAILED; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* exit from sleep mode */ - CANx->MCR &= ~MCR_SLEEP; - - /* Request initialisation */ - CANx->MCR |= MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & MSR_INAK) != MSR_INAK) - { - InitStatus = CANINITFAILED; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= MCR_TTCM; - } - else - { - CANx->MCR &= ~MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= MCR_ABOM; - } - else - { - CANx->MCR &= ~MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= MCR_AWUM; - } - else - { - CANx->MCR &= ~MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= MCR_NART; - } - else - { - CANx->MCR &= ~MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= MCR_RFLM; - } - else - { - CANx->MCR &= ~MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= MCR_TXFP; - } - else - { - CANx->MCR &= ~MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0x00; - - while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & MSR_INAK) == MSR_INAK) - { - InitStatus = CANINITFAILED; - } - else - { - InitStatus = CANINITOK ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration information. - * @retval None. - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which - * will be initialized. - * @retval None. - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @note This function applies only to STM32 Connectivity line devices. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None. - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - /* enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the specified CAN interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0, - * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1, - * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, - * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or - * CAN_IT_SLK. - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_ITConfig(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CAN interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CAN interrupt */ - CANx->IER &= ~CAN_IT; - } -} - -/** - * @brief Initiates the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN - * DLC and CAN datas. - * @retval The number of the mailbox that is used for transmission - * or CAN_NO_MB if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&TSR_TME0) == TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&TSR_TME1) == TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&TSR_TME2) == TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_NO_MB; - } - - if (transmit_mailbox != CAN_NO_MB) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | - TxMessage->RTR); - } - - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - /* RQCP, TXOK and TME bits */ - uint8_t state = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - switch (TransmitMailbox) - { - case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2); - state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0); - state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26); - break; - case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6); - state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8); - state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27); - break; - case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14); - state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16); - state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28); - break; - default: - state = CANTXFAILED; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CANTXPENDING; - break; - /* transmit failed */ - case (0x5): state = CANTXFAILED; - break; - /* transmit succedeed */ - case (0x7): state = CANTXOK; - break; - default: - state = CANTXFAILED; - break; - } - return state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None. - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (0): CANx->TSR |= TSR_ABRQ0; - break; - case (1): CANx->TSR |= TSR_ABRQ1; - break; - case (2): CANx->TSR |= TSR_ABRQ2; - break; - default: - break; - } -} - -/** - * @brief Releases a FIFO. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None. - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R = RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R = RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending messages. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} - -/** - * @brief Receives a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive message which - * contains CAN Id, CAN DLC, CAN datas and FMI number. - * @retval None. - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_ID_STD) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - CAN_FIFORelease(CANx, FIFONumber); -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - -/** - * @brief Enters the low power mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CANSLEEPFAILED; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CANSLEEPOK; - } - /* At this step, sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes the CAN up. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TimeOut ; - uint8_t wakeupstatus = CANWAKEUPFAILED; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* Sleep mode exited */ - wakeupstatus = CANWAKEUPOK; - } - /* At this step, sleep mode status */ - return (uint8_t)wakeupstatus; -} - -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF. - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FLAG(CAN_FLAG)); - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * @retval None. - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FLAG(CAN_FLAG)); - /* Clear the selected CAN flags */ - CANx->ESR &= ~CAN_FLAG; -} - -/** - * @brief Checks whether the specified CAN interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2, - * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1, - * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, - * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK. - * @retval The new state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus pendingbitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_ITStatus(CAN_IT)); - switch (CAN_IT) - { - case CAN_IT_RQCP0: - pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0); - break; - case CAN_IT_RQCP1: - pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1); - break; - case CAN_IT_RQCP2: - pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2); - break; - case CAN_IT_FF0: - pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0); - break; - case CAN_IT_FOV0: - pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0); - break; - case CAN_IT_FF1: - pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1); - break; - case CAN_IT_FOV1: - pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1); - break; - case CAN_IT_EWG: - pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF); - break; - case CAN_IT_EPV: - pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF); - break; - case CAN_IT_BOF: - pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF); - break; - case CAN_IT_SLK: - pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI); - break; - case CAN_IT_WKU: - pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI); - break; - default : - pendingbitstatus = RESET; - break; - } - /* Return the CAN_IT status */ - return pendingbitstatus; -} - -/** - * @brief Clears the CAN’s interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * @retval None. - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_ITStatus(CAN_IT)); - switch (CAN_IT) - { - case CAN_IT_RQCP0: - CANx->TSR = TSR_RQCP0; /* rc_w1*/ - break; - case CAN_IT_RQCP1: - CANx->TSR = TSR_RQCP1; /* rc_w1*/ - break; - case CAN_IT_RQCP2: - CANx->TSR = TSR_RQCP2; /* rc_w1*/ - break; - case CAN_IT_FF0: - CANx->RF0R = RF0R_FULL0; /* rc_w1*/ - break; - case CAN_IT_FOV0: - CANx->RF0R = RF0R_FOVR0; /* rc_w1*/ - break; - case CAN_IT_FF1: - CANx->RF1R = RF1R_FULL1; /* rc_w1*/ - break; - case CAN_IT_FOV1: - CANx->RF1R = RF1R_FOVR1; /* rc_w1*/ - break; - case CAN_IT_EWG: - CANx->ESR &= ~ ESR_EWGF; /* rw */ - break; - case CAN_IT_EPV: - CANx->ESR &= ~ ESR_EPVF; /* rw */ - break; - case CAN_IT_BOF: - CANx->ESR &= ~ ESR_BOFF; /* rw */ - break; - case CAN_IT_WKU: - CANx->MSR = MSR_WKUI; /* rc_w1*/ - break; - case CAN_IT_SLK: - CANx->MSR = MSR_SLAKI; /* rc_w1*/ - break; - default : - break; - } -} - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_crc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_crc.c deleted file mode 100644 index ba665c9aa..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_crc.c +++ /dev/null @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_crc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/** @defgroup CRC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Defines - * @{ - */ - -/* CR register bit mask */ - -#define CR_RESET_Set ((uint32_t)0x00000001) - -/** - * @} - */ - -/** @defgroup CRC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CR_RESET_Set; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dac.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dac.c deleted file mode 100644 index 84f5d10d6..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dac.c +++ /dev/null @@ -1,431 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the DAC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dac.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/** @defgroup DAC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Defines - * @{ - */ - -/* DAC EN mask */ -#define CR_EN_Set ((uint32_t)0x00000001) - -/* DAC DMAEN mask */ -#define CR_DMAEN_Set ((uint32_t)0x00001000) - -/* CR register Mask */ -#define CR_CLEAR_Mask ((uint32_t)0x00000FFE) - -/* DAC SWTRIG mask */ -#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_Set ((uint32_t)0x00000003) -#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_Offset ((uint32_t)0x00000008) -#define DHR12R2_Offset ((uint32_t)0x00000014) -#define DHR12RD_Offset ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_Offset ((uint32_t)0x0000002C) -/** - * @} - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave genration, - mask/amplitude for wave genration */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= CR_EN_Set << DAC_Channel; - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= ~(CR_EN_Set << DAC_Channel); - } -} - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= CR_DMAEN_Set << DAC_Channel; - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_Set ; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignement for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_Offset + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignement for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_Offset + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel - * DAC. - * @param DAC_Align: Specifies the data alignement for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_Offset + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC cahnnel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dbgmcu.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dbgmcu.c deleted file mode 100644 index 7deea2caa..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dbgmcu.c +++ /dev/null @@ -1,152 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dbgmcu.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/** @defgroup DBGMCU_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Defines - * @{ - */ - -#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF) -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); -} - -/** - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * @param DBGMCU_Periph: specifies the peripheral and low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dma.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dma.c deleted file mode 100644 index 147a88888..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_dma.c +++ /dev/null @@ -1,693 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the DMA firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dma.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/** @defgroup DMA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup DMA_Private_Defines - * @{ - */ - -/* DMA ENABLE mask */ -#define CCR_ENABLE_Set ((uint32_t)0x00000001) -#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) -#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) -#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) -#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) -#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) -#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000) -#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F) -#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0) -#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00) -#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000) -#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/** - * @} - */ - -/** @defgroup DMA_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= CCR_ENABLE_Reset; - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_Channel4_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_Channel5_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_Channel6_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_Channel7_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel1) - { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->IFCR |= DMA2_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel2) - { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->IFCR |= DMA2_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel3) - { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->IFCR |= DMA2_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel4) - { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->IFCR |= DMA2_Channel4_IT_Mask; - } - else - { - if (DMAy_Channelx == DMA2_Channel5) - { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->IFCR |= DMA2_Channel5_IT_Mask; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_Mask; - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= CCR_ENABLE_Set; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= CCR_ENABLE_Reset; - } -} - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Calculate the used DMA */ - if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval None - */ -void DMA_ClearFlag(uint32_t DMA_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - /* Calculate the used DMA */ - - if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMA flags */ - DMA2->IFCR = DMA_FLAG; - } - else - { - /* Clear the selected DMA flags */ - DMA1->IFCR = DMA_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Calculate the used DMA */ - if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMA interrupt */ - if ((tmpreg & DMA_IT) != (uint32_t)RESET) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx’s interrupt pending bits. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMA_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Calculate the used DMA */ - if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMA interrupt pending bits */ - DMA2->IFCR = DMA_IT; - } - else - { - /* Clear the selected DMA interrupt pending bits */ - DMA1->IFCR = DMA_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_exti.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_exti.c deleted file mode 100644 index cc4ab9965..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_exti.c +++ /dev/null @@ -1,268 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the EXTI firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_exti.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/** @defgroup EXTI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Defines - * @{ - */ - -#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x000FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LineNone; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt. - * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI’s line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI’s line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_flash.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_flash.c deleted file mode 100644 index 22ee18000..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_flash.c +++ /dev/null @@ -1,874 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the FLASH firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_flash.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/** @defgroup FLASH_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Defines - * @{ - */ - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) -#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) -#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) - -/* Flash Access Control Register bits */ -#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0x00001FFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0x00001FFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0x00001FFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0x00001FDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x00000FFF) -#define ProgramTimeout ((uint32_t)0x0000000F) - -/** - * @} - */ - -/** @defgroup FLASH_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_FunctionPrototypes - * @{ - */ - -static void delay(void); -/** - * @} - */ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Half cycle flash access. - * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. - * This parameter can be one of the following values: - * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable - * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable - * @retval None - */ -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) -{ - /* Check the parameters */ - assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); - - /* Enable or disable the Half cycle access */ - FLASH->ACR &= ACR_HLFCYA_Mask; - FLASH->ACR |= FLASH_HalfCycleAccess; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. - * This parameter can be one of the following values: - * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable - * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable - * @retval None - */ -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); - - /* Enable or disable the Prefetch Buffer */ - FLASH->ACR &= ACR_PRFTBE_Mask; - FLASH->ACR |= FLASH_PrefetchBuffer; -} - -/** - * @brief Unlocks the FLASH Program Erase Controller. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/** - * @brief Locks the FLASH Program Erase Controller. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the Lock Bit to lock the FPEC and the FCR */ - FLASH->CR |= CR_LOCK_Set; -} - -/** - * @brief Erases a specified FLASH page. - * @param Page_Address: The page address to be erased. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Page_Address)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases the FLASH option bytes. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* if the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - /* Enable the readout access */ - OB->RDP= RDP_Key; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @param FLASH_Pages: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 - * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 - * and FLASH_WRProt_Pages124to127 - * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 - * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 - * @arg FLASH_WRProt_AllPages - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note If the user has already programmed the other option bytes before calling - * this function, he must re-program them since this function erases all option bytes. - * @param Newstate: new state of the ReadOut Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDP = 0x00; - } - else - { - OB->RDP = RDP_Key; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - /* Return the User Option Byte */ - return (uint32_t)(FLASH->OBR >> 2); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * @param None - * @retval The FLASH Write Protection Option Bytes Register value - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - /* Return the Falsh write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERROR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @param NewState: new state of the specified Flash interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH’s pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @retval None - */ -void FLASH_ClearFlag(uint16_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -/** - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * @param Timeout: FLASH progamming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetStatus(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - delay(); - status = FLASH_GetStatus(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @brief Inserts a time delay. - * @param None - * @retval None - */ -static void delay(void) -{ - __IO uint32_t i = 0; - for(i = 0xFF; i != 0; i--) - { - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_fsmc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_fsmc.c deleted file mode 100644 index 32ebf402e..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_fsmc.c +++ /dev/null @@ -1,858 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the FSMC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_fsmc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/** @defgroup FSMC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup FSMC_Private_Defines - * @{ - */ - -/* --------------------- FSMC registers bit mask ---------------------------- */ - -/* FSMC BCRx Mask */ -#define BCR_MBKEN_Set ((uint32_t)0x00000001) -#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_Set ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_Set ((uint32_t)0x00000004) -#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_Set ((uint32_t)0x00000040) -#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) -#define PCR_MemoryType_NAND ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FSMC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for - * the FSMC NOR/SRAM specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; - } - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MemoryType_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified - * parameters in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef - * structure that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; - } -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; - } - } -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; - } -} - -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC’s pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC’s interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_gpio.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_gpio.c deleted file mode 100644 index fd951a3cf..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_gpio.c +++ /dev/null @@ -1,617 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the GPIO firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_gpio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/** @defgroup GPIO_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------------*/ -#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) - -/* --- EVENTCR Register -----*/ - -/* Alias word address of EVOE bit */ -#define EVCR_OFFSET (AFIO_OFFSET + 0x00) -#define EVOE_BitNumber ((uint8_t)0x07) -#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) - - -/* --- MAPR Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define MAPR_OFFSET (AFIO_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((u8)0x17) -#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - - -#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup GPIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); - } - else - { - if (GPIOx == GPIOG) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); - } - } -} - -/** - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * @param None - * @retval None - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - -/*---------------------------- GPIO Mode Configuration -----------------------*/ - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - /* Check the parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - /* Output mode */ - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } -/*---------------------------- GPIO CRL Configuration ------------------------*/ - /* Configure the eight low port pins */ - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CRL; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding low control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << pinpos); - } - else - { - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CRL = tmpreg; - } -/*---------------------------- GPIO CRH Configuration ------------------------*/ - /* Configure the eight high port pins */ - if (GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CRH; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - /* Get the port pins position */ - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding high control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CRH = tmpreg; - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @brief Selects the GPIO pin used as Event output. - * @param GPIO_PortSource: selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * @param GPIO_PinSource: specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmpreg = AFIO->EVCR; - /* Clear the PORT[6:4] and PIN[3:0] bits */ - tmpreg &= EVCR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->EVCR = tmpreg; -} - -/** - * @brief Enables or disables the Event Output. - * @param NewState: new state of the Event output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; -} - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIO_Remap: selects the pin to remap. - * This parameter can be one of the following values: - * @arg GPIO_Remap_SPI1 - * @arg GPIO_Remap_I2C1 - * @arg GPIO_Remap_USART1 - * @arg GPIO_Remap_USART2 - * @arg GPIO_PartialRemap_USART3 - * @arg GPIO_FullRemap_USART3 - * @arg GPIO_PartialRemap_TIM1 - * @arg GPIO_FullRemap_TIM1 - * @arg GPIO_PartialRemap1_TIM2 - * @arg GPIO_PartialRemap2_TIM2 - * @arg GPIO_FullRemap_TIM2 - * @arg GPIO_PartialRemap_TIM3 - * @arg GPIO_FullRemap_TIM3 - * @arg GPIO_Remap_TIM4 - * @arg GPIO_Remap1_CAN1 - * @arg GPIO_Remap2_CAN1 - * @arg GPIO_Remap_PD01 - * @arg GPIO_Remap_TIM5CH4_LSI - * @arg GPIO_Remap_ADC1_ETRGINJ - * @arg GPIO_Remap_ADC1_ETRGREG - * @arg GPIO_Remap_ADC2_ETRGINJ - * @arg GPIO_Remap_ADC2_ETRGREG - * @arg GPIO_Remap_ETH - * @arg GPIO_Remap_CAN2 - * @arg GPIO_Remap_SWJ_NoJTRST - * @arg GPIO_Remap_SWJ_JTAGDisable - * @arg GPIO_Remap_SWJ_Disable - * @arg GPIO_Remap_SPI3 - * @arg GPIO_Remap_TIM2ITR1_PTP_SOF - * @arg GPIO_Remap_PTP_PPS - * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected - * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. - * @param NewState: new state of the port pin remapping. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_REMAP(GPIO_Remap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmpreg = AFIO->MAPR; - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->MAPR &= DBGAFR_SWJCFG_MASK; - } - else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - - if (NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); - } - - AFIO->MAPR = tmpreg; -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * @param GPIO_PinSource: specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/** - * @brief Selects the Ethernet media interface. - * @note This function applies only to STM32 Connectivity line devices. - * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg GPIO_ETH_MediaInterface_MII: MII mode - * @arg GPIO_ETH_MediaInterface_RMII: RMII mode - * @retval None - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); - - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_i2c.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_i2c.c deleted file mode 100644 index bed0e9d0f..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_i2c.c +++ /dev/null @@ -1,1152 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the I2C firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_i2c.h" -#include "stm32f10x_rcc.h" - - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/** @defgroup I2C_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Defines - * @{ - */ - -/* I2C SPE mask */ -#define CR1_PE_Set ((uint16_t)0x0001) -#define CR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CR1_START_Set ((uint16_t)0x0100) -#define CR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CR1_STOP_Set ((uint16_t)0x0200) -#define CR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CR1_ACK_Set ((uint16_t)0x0400) -#define CR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CR1_ENGC_Set ((uint16_t)0x0040) -#define CR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CR1_SWRST_Set ((uint16_t)0x8000) -#define CR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CR1_PEC_Set ((uint16_t)0x1000) -#define CR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CR1_ENPEC_Set ((uint16_t)0x0020) -#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CR1_ENARP_Set ((uint16_t)0x0010) -#define CR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CR2_DMAEN_Set ((uint16_t)0x0800) -#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CR2_LAST_Set ((uint16_t)0x1000) -#define CR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OAR1_ADD0_Set ((uint16_t)0x0001) -#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OAR2_ENDUAL_Set ((uint16_t)0x0001) -#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OAR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CCR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CCR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/** - * @} - */ - -/** @defgroup I2C_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the I2Cx peripheral registers to their default reset values. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_DeInit(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - if (I2Cx == I2C1) - { - /* Enable I2C1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - /* Enable I2C2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - /* Release I2C2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/** - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * @retval None - */ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - RCC_ClocksTypeDef rcc_clocks; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= CR2_FREQ_Reset; - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= CR1_PE_Reset; - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & CCR_CCR_Set) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | CCR_FS_Set); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= CR1_PE_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= CR2_DMAEN_Set; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= CR2_DMAEN_Reset; - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= CR2_LAST_Set; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= CR2_LAST_Reset; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= CR1_START_Set; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= CR1_START_Reset; - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= CR1_STOP_Set; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= CR1_STOP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= CR1_ACK_Set; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= CR1_ACK_Reset; - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= OAR2_ADD2_Reset; - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= OAR2_ENDUAL_Set; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= OAR2_ENDUAL_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= CR1_ENGC_Set; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= CR1_ENGC_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a - * Transmitter or a Receiver. This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= OAR1_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= OAR1_ADD0_Reset; - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= CR1_SWRST_Set; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= CR1_SWRST_Reset; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= CR1_PEC_Set; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= CR1_PEC_Reset; - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transfered bytes. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= CR1_ENPEC_Set; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= CR1_ENPEC_Reset; - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= CR1_ENARP_Set; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= CR1_ENARP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= CR1_NOSTRETCH_Set; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= CR1_NOSTRETCH_Reset; - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - /* Return status */ - return lastevent; -} - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2 - * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 - * @arg I2C_EVENT_MASTER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 - * @retval An ErrorStatus enumuration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - /* Check whether the last event is equal to I2C_EVENT */ - if (lastevent == I2C_EVENT ) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL” - * Address matched flag (Slave mode)”ENDAD” - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) “ADSL” - * Address matched flag (Slave mode)”ENDAD” - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_Mask; - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx’s interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_iwdg.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_iwdg.c deleted file mode 100644 index 7d6fe8235..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_iwdg.c +++ /dev/null @@ -1,189 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the IWDG firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_iwdg.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/** @defgroup IWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Defines - * @{ - */ - -/* ---------------------- IWDG registers bit mask ----------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_Reload ((uint16_t)0xAAAA) -#define KR_KEY_Enable ((uint16_t)0xCCCC) - -/** - * @} - */ - -/** @defgroup IWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_Reload; -} - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_Enable; -} - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c deleted file mode 100644 index fbafe42a2..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_pwr.c +++ /dev/null @@ -1,311 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the PWR firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_pwr.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/** @defgroup PWR_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Defines - * @{ - */ - -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_PDDS_Set ((uint32_t)0x00000002) -#define CR_DS_Mask ((uint32_t)0xFFFFFFFC) -#define CR_CWUF_Set ((uint32_t)0x00000004) -#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F) - -/* --------- Cortex System Control register bit mask ---------------- */ - -/* Cortex System Control register address */ -#define SCB_SysCtrl ((uint32_t)0xE000ED10) - -/* SLEEPDEEP bit mask */ -#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) -/** - * @} - */ - -/** @defgroup PWR_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the RTC and backup registers. - * @param NewState: new state of the access to the RTC and backup registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V - * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V - * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V - * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V - * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - tmpreg = PWR->CR; - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_Mask; - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @brief Enters STOP mode. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_Mask; - /* Set LPDS bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - /* Store the new value */ - PWR->CR = tmpreg; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } -} - -/** - * @brief Enters STANDBY mode. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wake-up flag */ - PWR->CR |= CR_CWUF_Set; - /* Select STANDBY mode */ - PWR->CR |= CR_PDDS_Set; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_PVDO: PVD Output - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c deleted file mode 100644 index d506eb9fb..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rcc.c +++ /dev/null @@ -1,1447 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the RCC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/** @defgroup RCC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -#ifdef STM32F10X_CL - /* Alias word address of PLL2ON bit */ - #define PLL2ON_BitNumber 0x1A - #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) - - /* Alias word address of PLL3ON bit */ - #define PLL3ON_BitNumber 0x1C - #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CFGR Register ---*/ - -/* Alias word address of USBPRE bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x04) - -#ifndef STM32F10X_CL - #define USBPRE_BitNumber 0x16 - #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) -#else - #define OTGFSPRE_BitNumber 0x16 - #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* --- BDCR Register ---*/ - -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x20) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x24) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -#ifdef STM32F10X_CL -/* --- CFGR2 Register ---*/ - - /* Alias word address of I2S2SRC bit */ - #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) - #define I2S2SRC_BitNumber 0x11 - #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) - - /* Alias word address of I2S3SRC bit */ - #define I2S3SRC_BitNumber 0x12 - #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* ---------------------- RCC registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CR_HSEBYP_Set ((uint32_t)0x00040000) -#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CR_HSEON_Set ((uint32_t)0x00010000) -#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR register bit mask */ -#ifndef STM32F10X_CL - #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) -#else - #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) -#endif /* STM32F10X_CL */ - -#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* CSR register bit mask */ -#define CSR_RMVF_Set ((uint32_t)0x01000000) - -#ifdef STM32F10X_CL -/* CFGR2 register bit mask */ - #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) - #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) - #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) - #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) - #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) -#endif /* STM32F10X_CL */ - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -#ifndef HSI_Value -/* Typical Value of the HSI in Hz */ - #define HSI_Value ((uint32_t)8000000) -#endif /* HSI_Value */ - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR register byte 4 (Bits[31:24]) base address */ -#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -#ifndef HSEStartUp_TimeOut -/* Time out for HSE start up */ - #define HSEStartUp_TimeOut ((uint16_t)0x0500) -#endif /* HSEStartUp_TimeOut */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Variables - * @{ - */ - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/** - * @} - */ - -/** @defgroup RCC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifndef STM32F10X_CL - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#else - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#endif /* STM32F10X_CL */ -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note HSE can not be stopped if it is used directly or through the PLL as system clock. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: HSE oscillator OFF - * @arg RCC_HSE_ON: HSE oscillator ON - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - /* Reset HSEON bit */ - RCC->CR &= CR_HSEON_Reset; - /* Reset HSEBYP bit */ - RCC->CR &= CR_HSEBYP_Reset; - /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ - switch(RCC_HSE) - { - case RCC_HSE_ON: - /* Set HSEON bit */ - RCC->CR |= CR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - /* Set HSEBYP and HSEON bits */ - RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; - break; - - default: - break; - } -} - -/** - * @brief Waits for HSE start-up. - * @param None - * @retval An ErrorStatus enumuration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - tmpreg = RCC->CR; - /* Clear HSITRIM[4:0] bits */ - tmpreg &= CR_HSITRIM_Mask; - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note HSI can not be stopped if it is used directly or through the PLL as system clock. - * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PLLSource: specifies the PLL entry clock source. - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry - * @param RCC_PLLMul: specifies the PLL multiplication factor. - * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} - * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - tmpreg = RCC->CFGR; - /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - tmpreg &= CFGR_PLL_Mask; - /* Set the PLL configuration bits */ - tmpreg |= RCC_PLLSource | RCC_PLLMul; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the PLL. - * @note The PLL can not be disabled if it is used as system clock. - * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#ifdef STM32F10X_CL -/** - * @brief Configures the PREDIV1 division factor. - * @note - * - This function must be used only when the PLL is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. - * This parameter can be one of the following values: - * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock - * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - /* Set the PREDIV1 clock source and division factor */ - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Configures the PREDIV2 division factor. - * @note - * - This function must be used only when both PLL2 and PLL3 are disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV2[3:0] bits */ - tmpreg &= ~CFGR2_PREDIV2; - /* Set the PREDIV2 division factor */ - tmpreg |= RCC_PREDIV2_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Configures the PLL2 multiplication factor. - * @note - * - This function must be used only when the PLL2 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL2Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL2MUL; - /* Set the PLL2 configuration bits */ - tmpreg |= RCC_PLL2Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL2. - * @note - * - The PLL2 can not be disabled if it is used indirectly as system clock - * (i.e. it is used as PLL clock entry that is used as System clock). - * - This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; -} - - -/** - * @brief Configures the PLL3 multiplication factor. - * @note - * - This function must be used only when the PLL3 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. - * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL3Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL3MUL; - /* Set the PLL3 configuration bits */ - tmpreg |= RCC_PLL3Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL3. - * @note This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the system clock (SYSCLK). - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - tmpreg = RCC->CFGR; - /* Clear SW[1:0] bits */ - tmpreg &= CFGR_SW_Mask; - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can - * be one of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - tmpreg = RCC->CFGR; - /* Clear HPRE[3:0] bits */ - tmpreg &= CFGR_HPRE_Reset_Mask; - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE1[2:0] bits */ - tmpreg &= CFGR_PPRE1_Reset_Mask; - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE2[2:0] bits */ - tmpreg &= CFGR_PPRE2_Reset_Mask; - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -#ifndef STM32F10X_CL -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source - * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - - *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; -} -#else -/** - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * This function applies only to STM32 Connectivity line devices. - * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. - * This clock is derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @retval None - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); - - *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the ADC clock (ADCCLK). - * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * This parameter can be one of the following values: - * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 - * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 - * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 - * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); - tmpreg = RCC->CFGR; - /* Clear ADCPRE[1:0] bits */ - tmpreg &= CFGR_ADCPRE_Reset_Mask; - /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ - tmpreg |= RCC_PCLK2; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -#ifdef STM32F10X_CL -/** - * @brief Configures the I2S2 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S2 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry - * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry - * @retval None - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; -} - -/** - * @brief Configures the I2S3 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S3 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry - * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry - * @retval None - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: LSE oscillator OFF - * @arg RCC_LSE_ON: LSE oscillator ON - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch(RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note Once the RTC clock is selected it can’t be changed unless the Backup domain is reset. - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Returns the frequencies of different on chip clocks. - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & CFGR_SWS_Mask; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_Value; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_Value; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & CFGR_PLLMull_Mask; - pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; - } - else - {/* HSE selected as PLL clock entry */ - if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; - } - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; - RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_Value; - break; - } - - /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get ADCCLK prescaler */ - tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - /* ADCCLK clock frequency */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @arg RCC_AHBPeriph_ETH_MAC_Tx - * @arg RCC_AHBPeriph_ETH_MAC_Rx - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FSMC - * @arg RCC_AHBPeriph_SDIO - * - * @note SRAM and FLITF clock can be disabled only during sleep mode. - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -#ifdef STM32F10X_CL -/** - * @brief Forces or releases AHB peripheral reset. - * @note This function applies only to STM32 Connectivity line devices. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} -#endif /* STM32F10X_CL */ - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @param NewState: new state of the Clock Security System.. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO pin. - * @param RCC_MCO: specifies the clock source to output. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * @arg RCC_MCO_PLL2CLK: PLL2 clock selected - * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected - * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected - * @arg RCC_MCO_PLL3CLK: PLL3 clock selected - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCO)); - - /* Perform Byte access to MCO bits to select the MCO source */ - *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready - * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_Mask; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= CSR_RMVF_Set; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC’s interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c deleted file mode 100644 index 0118b7a0d..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_rtc.c +++ /dev/null @@ -1,341 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the RTC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rtc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/** @defgroup RTC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup RTC_Private_Defines - * @{ - */ - -#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */ -#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */ -#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ -#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RTC->CRH |= RTC_IT; - } - else - { - RTC->CRH &= (uint16_t)~RTC_IT; - } -} - -/** - * @brief Enters the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_EnterConfigMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= CRL_CNF_Set; -} - -/** - * @brief Exits from the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_ExitConfigMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= CRL_CNF_Reset; -} - -/** - * @brief Gets the RTC counter value. - * @param None - * @retval RTC counter value. - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t tmp = 0; - tmp = RTC->CNTL; - return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; -} - -/** - * @brief Sets the RTC counter value. - * @param CounterValue: RTC counter new value. - * @retval None - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - /* Set RTC COUNTER MSB word */ - RTC->CNTH = CounterValue >> 16; - /* Set RTC COUNTER LSB word */ - RTC->CNTL = (CounterValue & RTC_LSB_Mask); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC prescaler value. - * @param PrescalerValue: RTC prescaler new value. - * @retval None - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - /* Check the parameters */ - assert_param(IS_RTC_PRESCALER(PrescalerValue)); - - RTC_EnterConfigMode(); - /* Set RTC PRESCALER MSB word */ - RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16; - /* Set RTC PRESCALER LSB word */ - RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC alarm value. - * @param AlarmValue: RTC alarm new value. - * @retval None - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - /* Set the ALARM MSB word */ - RTC->ALRH = AlarmValue >> 16; - /* Set the ALARM LSB word */ - RTC->ALRL = (AlarmValue & RTC_LSB_Mask); - RTC_ExitConfigMode(); -} - -/** - * @brief Gets the RTC divider value. - * @param None - * @retval RTC Divider value. - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/** - * @brief Waits until last write operation on RTC registers has finished. - * @note This function must be called before any write to RTC registers. - * @param None - * @retval None - */ -void RTC_WaitForLastTask(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) - * are synchronized with RTC APB clock. - * @note This function must be called before any read operation after an APB reset - * or an APB clock stop. - * @param None - * @retval None - */ -void RTC_WaitForSynchro(void) -{ - /* Clear RSF flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; - /* Loop until RSF flag is set */ - while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one the following values: - * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC’s pending flags. - * @param RTC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after - * an APB reset or an APB Clock stop. - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval None - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the coressponding RTC flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG; -} - -/** - * @brief Checks whether the specified RTC interrupt has occured or not. - * @param RTC_IT: specifies the RTC interrupts sources to check. - * This parameter can be one of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval The new state of the RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - bitstatus = (ITStatus)(RTC->CRL & RTC_IT); - if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC’s interrupt pending bits. - * @param RTC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - - /* Clear the coressponding RTC pending bit */ - RTC->CRL &= (uint16_t)~RTC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c deleted file mode 100644 index c4b32a1af..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_sdio.c +++ /dev/null @@ -1,798 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the SDIO firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_sdio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/** @defgroup SDIO_Private_TypesDefinitions - * @{ - */ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ - -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ - -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ - -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ - -/* --- CLKCR Register ---*/ - -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ - -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ - -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ - -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/** - * @} - */ - -/** @defgroup SDIO_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCR = 0x00000000; - SDIO->ARG = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTIMER = 0x00000000; - SDIO->DLEN = 0x00000000; - SDIO->DCTRL = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->MASK = 0x00000000; -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF - * @arg SDIO_PowerState_ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER &= PWR_PWRCTRL_MASK; - SDIO->POWER |= SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can - * be one of the following: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that - * contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parametre can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO’s interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c deleted file mode 100644 index 8f67f240a..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_spi.c +++ /dev/null @@ -1,907 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the SPI firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_spi.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/** @defgroup SPI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup SPI_Private_Defines - * @{ - */ - -/* SPI SPE mask */ -#define CR1_SPE_Set ((uint16_t)0x0040) -#define CR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CR1_CRCEN_Set ((uint16_t)0x2000) -#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CR2_SSOE_Set ((uint16_t)0x0004) -#define CR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((u32)(0x00020000)) -#define I2S3_CLOCK_SRC ((u32)(0x00040000)) -#define I2S_MUL_MASK ((u32)(0x0000F000)) -#define I2S_DIV_MASK ((u32)(0x000000F0)) - -/** - * @} - */ - -/** @defgroup SPI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= SPI_Mode_Select; - -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral - * (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @note - * The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) */ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get the I2S clock source mask depending on the peripheral number */ - if(((uint32_t)SPIx) == SPI2_BASE) - { - /* The mask is relative to I2S2 */ - tmp = I2S2_CLOCK_SRC; - } - else - { - /* The mask is relative to I2S3 */ - tmp = I2S3_CLOCK_SRC; - } - - /* Check the I2S clock source configuration depending on the Device: - Only Connectivity line devices have the PLL3 VCO clock */ -#ifdef STM32F10X_CL - if((RCC->CFGR2 & tmp) != 0) - { - /* Get the configuration bits of RCC PLL3 multiplier */ - tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); - - /* Get the value of the PLL3 multiplier */ - if((tmp > 5) && (tmp < 15)) - { - /* Multplier is between 8 and 14 (value 15 is forbidden) */ - tmp += 2; - } - else - { - if (tmp == 15) - { - /* Multiplier is 20 */ - tmp = 20; - } - } - /* Get the PREDIV2 value */ - sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); - - /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ - sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); - } - else - { - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; - } -#else /* STM32F10X_HD */ - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; -#endif /* STM32F10X_CL */ - - /* Compute the Real divider depending on the MCLK output state with a flaoting point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flaoting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (u16)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= CR1_SPE_Set; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= CR1_SPE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - /* Disable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI/I2S interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI/I2S interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI/I2S DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI/I2S DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param Data : Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= CR2_SSOE_Set; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= CR2_SSOE_Reset; - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= CR1_CRCNext_Set; -} - -/** - * @brief Enables or disables the CRC value calculation of the transfered bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= CR1_CRCEN_Set; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= CR1_CRCEN_Reset; - } -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Checks whether the specified SPI/I2S flag is set or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - /* Check the status of the specified SPI/I2S flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI/I2S IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI/I2S interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR intetrrupt pending bit. - * @note - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c deleted file mode 100644 index 55b417b97..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_tim.c +++ /dev/null @@ -1,2799 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the TIM firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_tim.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/** @defgroup TIM_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Defines - * @{ - */ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define CR1_CEN_Set ((uint16_t)0x0001) -#define CR1_CEN_Reset ((uint16_t)0x03FE) -#define CR1_UDIS_Set ((uint16_t)0x0002) -#define CR1_UDIS_Reset ((uint16_t)0x03FD) -#define CR1_URS_Set ((uint16_t)0x0004) -#define CR1_URS_Reset ((uint16_t)0x03FB) -#define CR1_OPM_Reset ((uint16_t)0x03F7) -#define CR1_CounterMode_Mask ((uint16_t)0x038F) -#define CR1_ARPE_Set ((uint16_t)0x0080) -#define CR1_ARPE_Reset ((uint16_t)0x037F) -#define CR1_CKD_Mask ((uint16_t)0x00FF) -#define CR2_CCPC_Set ((uint16_t)0x0001) -#define CR2_CCPC_Reset ((uint16_t)0xFFFE) -#define CR2_CCUS_Set ((uint16_t)0x0004) -#define CR2_CCUS_Reset ((uint16_t)0xFFFB) -#define CR2_CCDS_Set ((uint16_t)0x0008) -#define CR2_CCDS_Reset ((uint16_t)0xFFF7) -#define CR2_MMS_Mask ((uint16_t)0xFF8F) -#define CR2_TI1S_Set ((uint16_t)0x0080) -#define CR2_TI1S_Reset ((uint16_t)0xFF7F) -#define CR2_OIS1_Reset ((uint16_t)0x7EFF) -#define CR2_OIS1N_Reset ((uint16_t)0x7DFF) -#define CR2_OIS2_Reset ((uint16_t)0x7BFF) -#define CR2_OIS2N_Reset ((uint16_t)0x77FF) -#define CR2_OIS3_Reset ((uint16_t)0x6FFF) -#define CR2_OIS3N_Reset ((uint16_t)0x5FFF) -#define CR2_OIS4_Reset ((uint16_t)0x3FFF) -#define SMCR_SMS_Mask ((uint16_t)0xFFF8) -#define SMCR_ETR_Mask ((uint16_t)0x00FF) -#define SMCR_TS_Mask ((uint16_t)0xFF8F) -#define SMCR_MSM_Reset ((uint16_t)0xFF7F) -#define SMCR_ECE_Set ((uint16_t)0x4000) -#define CCMR_CC13S_Mask ((uint16_t)0xFFFC) -#define CCMR_CC24S_Mask ((uint16_t)0xFCFF) -#define CCMR_TI13Direct_Set ((uint16_t)0x0001) -#define CCMR_TI24Direct_Set ((uint16_t)0x0100) -#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB) -#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF) -#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7) -#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF) -#define CCMR_OC13M_Mask ((uint16_t)0xFF8F) -#define CCMR_OC24M_Mask ((uint16_t)0x8FFF) -#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F) -#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF) -#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3) -#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF) -#define CCMR_IC13F_Mask ((uint16_t)0xFF0F) -#define CCMR_IC24F_Mask ((uint16_t)0x0FFF) -#define CCMR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) -#define CCER_CC1P_Reset ((uint16_t)0xFFFD) -#define CCER_CC2P_Reset ((uint16_t)0xFFDF) -#define CCER_CC3P_Reset ((uint16_t)0xFDFF) -#define CCER_CC4P_Reset ((uint16_t)0xDFFF) -#define CCER_CC1NP_Reset ((uint16_t)0xFFF7) -#define CCER_CC2NP_Reset ((uint16_t)0xFF7F) -#define CCER_CC3NP_Reset ((uint16_t)0xF7FF) -#define CCER_CC1E_Set ((uint16_t)0x0001) -#define CCER_CC1E_Reset ((uint16_t)0xFFFE) -#define CCER_CC1NE_Reset ((uint16_t)0xFFFB) -#define CCER_CC2E_Set ((uint16_t)0x0010) -#define CCER_CC2E_Reset ((uint16_t)0xFFEF) -#define CCER_CC2NE_Reset ((uint16_t)0xFFBF) -#define CCER_CC3E_Set ((uint16_t)0x0100) -#define CCER_CC3E_Reset ((uint16_t)0xFEFF) -#define CCER_CC3NE_Reset ((uint16_t)0xFBFF) -#define CCER_CC4E_Set ((uint16_t)0x1000) -#define CCER_CC4E_Reset ((uint16_t)0xEFFF) -#define BDTR_MOE_Set ((uint16_t)0x8000) -#define BDTR_MOE_Reset ((uint16_t)0x7FFF) -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @retval None - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else - { - if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - /* Select the Counter Mode and set the clock division */ - TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; - TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision | - TIM_TimeBaseInitStruct->TIM_CounterMode; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= CCER_CC1E_Reset; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= CCMR_OC13M_Mask; - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= CCER_CC1P_Reset; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= CCER_CC1NP_Reset; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= CCER_CC1NE_Reset; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= CR2_OIS1_Reset; - tmpcr2 &= CR2_OIS1N_Reset; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= CCER_CC2E_Reset; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= CCMR_OC24M_Mask; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= CCER_CC2P_Reset; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= CCER_CC2NP_Reset; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= CCER_CC2NE_Reset; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= CR2_OIS2_Reset; - tmpcr2 &= CR2_OIS2N_Reset; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= CCER_CC3E_Reset; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= CCMR_OC13M_Mask; - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= CCER_CC3P_Reset; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= CCER_CC3NP_Reset; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= CCER_CC3NE_Reset; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= CR2_OIS3_Reset; - tmpcr2 &= CR2_OIS3N_Reset; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= CCER_CC4E_Reset; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= CCMR_OC24M_Mask; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= CCER_CC4P_Reset; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Ouput Compare IDLE State */ - tmpcr2 &= CR2_OIS4_Reset; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= CR1_CEN_Set; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= CR1_CEN_Reset; - } -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= BDTR_MOE_Set; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= BDTR_MOE_Reset; - } -} - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can only generate an update interrupt. - * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note - * - TIM6 and TIM7 can only generate an update event. - * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Configures the TIMx’s DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, - * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, - * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, - * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, - * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, - * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, - * TIM_DMABase_DCR. - * @param TIM_DMABurstLength: DMA Burst length. - * This parameter can be one value between: - * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx’s DMA Requests. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Configures the TIMx interrnal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= SMCR_SMS_Mask; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @param TIM_TS_ITR0: Internal Trigger 0 - * @param TIM_TS_ITR1: Internal Trigger 1 - * @param TIM_TS_ITR2: Internal Trigger 2 - * @param TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter : specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= SMCR_SMS_Mask; - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= SMCR_TS_Mask; - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= SMCR_ECE_Set; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_Mask; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= CR1_CounterMode_Mask; - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= SMCR_TS_Mask; - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= SMCR_SMS_Mask; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask; - tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset; - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= CCMR_OC13M_Mask; - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= CCMR_OC24M_Mask; - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= CCMR_OC13M_Mask; - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= CCMR_OC24M_Mask; - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= CR1_ARPE_Set; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= CR1_ARPE_Reset; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= CR2_CCUS_Set; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= CR2_CCUS_Reset; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= CR2_CCDS_Set; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= CR2_CCDS_Reset; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= CR2_CCPC_Set; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= CR2_CCPC_Reset; - } -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= CCMR_OC13PE_Reset; - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= CCMR_OC24PE_Reset; - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= CCMR_OC13PE_Reset; - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= CCMR_OC24PE_Reset; - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= CCMR_OC13FE_Reset; - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= CCMR_OC24FE_Reset; - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= CCMR_OC13FE_Reset; - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= CCMR_OC24FE_Reset; - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1CE Bit */ - tmpccmr1 &= CCMR_OC13CE_Reset; - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= CCMR_OC24CE_Reset; - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= CCMR_OC13CE_Reset; - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= CCMR_OC24CE_Reset; - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= CCER_CC1P_Reset; - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1NP Bit */ - tmpccer &= CCER_CC1NP_Reset; - tmpccer |= TIM_OCNPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= CCER_CC2P_Reset; - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2NP Bit */ - tmpccer &= CCER_CC2NP_Reset; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= CCER_CC3P_Reset; - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3NP Bit */ - tmpccer &= CCER_CC3NP_Reset; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= CCER_CC4P_Reset; - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_Set << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_18_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_Set << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/** - * @brief Selects the TIM Ouput Compare Mode. - * @note This function disables the selected channel before changing the Ouput - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This paramter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_Offset; - - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_Mask; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_Mask; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= CR1_UDIS_Set; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= CR1_UDIS_Reset; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= CR1_URS_Set; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= CR1_URS_Reset; - } -} - -/** - * @brief Enables or disables the TIMx’s Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= CR2_TI1S_Set; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= CR2_TI1S_Reset; - } -} - -/** - * @brief Selects the TIMx’s One Pulse Mode. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - /* Reset the OPM Bit */ - TIMx->CR1 &= CR1_OPM_Reset; - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This paramter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - /* Reset the MMS Bits */ - TIMx->CR2 &= CR2_MMS_Mask; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - /* Reset the SMS Bits */ - TIMx->SMCR &= SMCR_SMS_Mask; - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - /* Reset the MSM Bit */ - TIMx->SMCR &= SMCR_MSM_Reset; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= CCMR_IC13PSC_Mask; - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= CCMR_IC24PSC_Mask; - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= CCMR_IC13PSC_Mask; - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= CCMR_IC24PSC_Mask; - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - /* Reset the CKD Bits */ - TIMx->CR1 &= CR1_CKD_Mask; - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_123458_PERIPH(TIMx)); - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @retval Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 8 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= CCER_CC1E_Reset; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= CCER_CC1P_Reset; - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= CCER_CC2E_Reset; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= CCER_CC2P_Reset; - tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= CCER_CC3E_Reset; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask; - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= CCER_CC3P_Reset; - tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= CCER_CC4E_Reset; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask; - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= CCER_CC4P_Reset; - tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c deleted file mode 100644 index 43fcb784e..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_usart.c +++ /dev/null @@ -1,967 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the USART firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_usart.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/** @defgroup USART_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Defines - * @{ - */ - -#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ -#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ - -#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ - -#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ -#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ -#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ -#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ -#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ - -#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ -#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ - -#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ -#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ -#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ - -#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ -#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ - -#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ -#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ - -#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ -#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ - -#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ -#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ - -#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ -#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ -#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ -#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ - -/** - * @} - */ - -/** @defgroup USART_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else - { - if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - /* The hardware flow control is available only for USART1, USART2 and USART3 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= CR2_STOP_CLEAR_Mask; - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= CR3_CLEAR_Mask; - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - if (usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - /* Determine the integer part */ - integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate))); - tmpreg = (integerdivider / 0x64) << 0x04; - /* Determine the fractional part */ - fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04)); - tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((uint8_t)0x0F); - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= CR2_CLOCK_CLEAR_Mask; - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= CR1_UE_Set; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= CR1_UE_Reset; - } -} - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables or disables the USART’s DMA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3 or UART4. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @note The DMA mode is not available for UART5. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1234_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @brief Sets the address of the USART node. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= CR2_Address_Mask; - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= CR1_WAKE_Mask; - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= CR1_RWU_Set; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= CR1_RWU_Reset; - } -} - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= CR2_LBDL_Mask; - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART’s LIN mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= CR2_LINEN_Set; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= CR2_LINEN_Reset; - } -} - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @brief Transmits break characters. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= CR1_SBK_Set; -} - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @note The guard time bits are not available for UART4 and UART5. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= GTPR_LSB_Mask; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= GTPR_MSB_Mask; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART’s Smart Card mode. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= CR3_SCEN_Set; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= CR3_SCEN_Reset; - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= CR3_NACK_Set; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= CR3_NACK_Reset; - } -} - -/** - * @brief Enables or disables the USART’s Half Duplex communication. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= CR3_HDSEL_Set; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= CR3_HDSEL_Reset; - } -} - -/** - * @brief Configures the USART’s IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= CR3_IRLP_Mask; - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART’s IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= CR3_IREN_Set; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= CR3_IREN_Reset; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx’s interrupt pending bits. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c b/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c deleted file mode 100644 index e2a56c45d..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/src/stm32f10x_wwdg.c +++ /dev/null @@ -1,223 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.c - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief This file provides all the WWDG firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_wwdg.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/** @defgroup WWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Defines - * @{ - */ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) - -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_WDGA_Set ((uint32_t)0x00000080) - -/* CFR register bit mask */ -#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/** - * @} - */ - -/** @defgroup WWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_Mask; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_Mask; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_Mask; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_Mask; -} - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = CR_WDGA_Set | Counter; -} - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->SR); -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk b/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk deleted file mode 100644 index 4e2837761..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32lib/stm32lib.mk +++ /dev/null @@ -1,22 +0,0 @@ -# STM32 FWLib files. -STM32SRC = stm32lib/src/stm32f10x_adc.c \ - stm32lib/src/stm32f10x_bkp.c \ - stm32lib/src/stm32f10x_can.c \ - stm32lib/src/stm32f10x_crc.c \ - stm32lib/src/stm32f10x_dac.c \ - stm32lib/src/stm32f10x_dbgmcu.c \ - stm32lib/src/stm32f10x_dma.c \ - stm32lib/src/stm32f10x_exti.c \ - stm32lib/src/stm32f10x_flash.c \ - stm32lib/src/stm32f10x_fsmc.c \ - stm32lib/src/stm32f10x_gpio.c \ - stm32lib/src/stm32f10x_i2c.c \ - stm32lib/src/stm32f10x_iwdg.c \ - stm32lib/src/stm32f10x_pwr.c \ - stm32lib/src/stm32f10x_rcc.c \ - stm32lib/src/stm32f10x_rtc.c \ - stm32lib/src/stm32f10x_sdio.c \ - stm32lib/src/stm32f10x_spi.c \ - stm32lib/src/stm32f10x_tim.c \ - stm32lib/src/stm32f10x_usart.c \ - stm32lib/src/stm32f10x_wwdg.c -- cgit v1.2.3 From 173d332a864e00ad795285b113dde975594714fb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Nov 2009 07:56:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1287 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/stm32f10x.h | 7851 -------------------------------- 1 file changed, 7851 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-GCC/stm32f10x.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/stm32f10x.h b/demos/ARMCM3-STM32F103-GCC/stm32f10x.h deleted file mode 100644 index e1c8451a6..000000000 --- a/demos/ARMCM3-STM32F103-GCC/stm32f10x.h +++ /dev/null @@ -1,7851 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.1.0 - * @date 06/19/2009 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, High - * density, Medium density and Low density devices. - ****************************************************************************** - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2009 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - #define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - High density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_Value - #ifdef STM32F10X_CL - #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_Value */ - - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ - | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ - | __STM32F10X_STDPERIPH_VERSION_SUB2) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - -#ifdef STM32F10X_LD - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_MD - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_HD - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_CL - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -//#include "system_stm32f10x.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -#ifndef __cplusplus -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -#endif - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; -} AFIO_TypeDef; -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ - -#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */ -#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */ -#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */ - -#ifndef STM32F10X_LD - #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_HD - #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */ -#endif /* STM32F10X_HD */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#ifndef STM32F10X_LD - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_HD */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#ifdef STM32F10X_HD - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */ -#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */ -#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */ - -#ifndef STM32F10X_LD - #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_HD - #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */ -#endif /* STM32F10X_HD */ - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#ifndef STM32F10X_LD - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_HD */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*! Date: Sat, 14 Nov 2009 14:57:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1291 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 206 ++++++++++++ demos/ARMCM3-STM32F103-FATFS-GCC/board.c | 127 ++++++++ demos/ARMCM3-STM32F103-FATFS-GCC/board.h | 119 +++++++ demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld | 94 ++++++ demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 464 ++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 163 ++++++++++ demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt | 28 ++ demos/ARMCM3-STM32F103-GCC/readme.txt | 10 +- 8 files changed, 1205 insertions(+), 6 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/Makefile create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/board.c create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/board.h create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/main.c create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile new file mode 100644 index 000000000..85a8880f1 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -0,0 +1,206 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ${CHIBIOS}/os/io/pal.c \ + ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/spi.c \ + ${CHIBIOS}/os/io/mmc_spi.c \ + ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ + ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ + ${CHIBIOS}/os/various/evtimer.c \ + board.c main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + ${CHIBIOS}/os/io \ + ${CHIBIOS}/os/io/platforms/STM32 \ + ${CHIBIOS}/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +TRGT = arm-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include ${CHIBIOS}/ext/stm32lib/stm32lib.mk + CSRC += ${STM32SRC} + INCDIR += ${STM32INC} + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c new file mode 100644 index 000000000..bc384a544 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c @@ -0,0 +1,127 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" + +#define AIRCR_VECTKEY 0x05FA0000 + +/* + * Digital I/O ports static configuration as defined in @p board.h. + */ +static const STM32GPIOConfig pal_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, +#if !defined(STM32F10X_LD) + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +#endif +#if defined(STM32F10X_HD) + {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, + {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, +#endif +}; + +/* + * Early initialization code. + * This initialization is performed just after reset before BSS and DATA + * segments initialization. + */ +void hwinit0(void) { + + /* + * Clocks and PLL initialization. + */ + // HSI setup. + RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION; + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; // Waits until HSI stable, it should already be. + // HSE setup. + RCC->CR |= RCC_CR_HSEON; + while (!(RCC->CR & RCC_CR_HSERDY)) + ; // Waits until HSE stable. + // PLL setup. + RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; // Waits until PLL stable. + // Clock sources. + RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 | + RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 | + RCC_CFGR_MCO_NOCLOCK | USBPREBITS; + + /* + * Flash setup and final clock selection. + */ + FLASH->ACR = FLASHBITS; // Flash wait states depending on clock. + RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock. + while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL) + ; + + /* + * I/O ports initialization as specified in board.h. + */ + palInit(&pal_config); +} + +/* + * Late initialization code. + * This initialization is performed after BSS and DATA segments initialization + * and before invoking the main() function. + */ +void hwinit1(void) { + + /* + * NVIC/SCB initialization. + * Note: PRIGROUP 4:0 (4:4). + */ + SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1; + NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL); + NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK); + NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV); + + /* + * SysTick initialization. + */ + SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT; + + /* + * Other subsystems initialization. + */ + dmaInit(); + sdInit(); + spiInit(); + mmcInit(); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); +} diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h new file mode 100644 index 000000000..0f53e5b0e --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h @@ -0,0 +1,119 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Tricks required to make the TRUE/FALSE declaration inside the library + * compatible. + */ +#undef FALSE +#undef TRUE +#include +#define FALSE 0 +#define TRUE (!FALSE) + +/* + * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. + */ +//#define SYSCLK_48 + +/* + * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. + */ +#define LSECLK 32768 +#define HSECLK 8000000 +#define HSICLK 8000000 +#define PLLPRE 1 +#ifdef SYSCLK_48 + #define PLLMUL 6 +#else + #define PLLMUL 9 +#endif +#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) +#define SYSCLK PLLCLK +#define APB1CLK (SYSCLK / 2) +#define APB2CLK (SYSCLK / 2) +#define AHB1CLK (SYSCLK / 1) + +/* + * Values derived from the clock settings. + */ +#define PLLPREBITS ((PLLPRE - 1) << 17) +#define PLLMULBITS ((PLLMUL - 2) << 18) +#ifdef SYSCLK_48 + #define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS + #define FLASHBITS 0x00000011 +#else + #define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS + #define FLASHBITS 0x00000012 +#endif + +/* + * Extra definitions for RCC_CR register (missing from the ST header file). + */ +#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3) + +/* + * Extra definitions for RCC_CFGR register (missing from the ST header file). + */ +#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16) +#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16) +#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22) +#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22) + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_SPI1NSS 4 + +#define GPIOB_SPI2NSS 12 + +#define GPIOC_MMCWP 6 +#define GPIOC_MMCCP 7 +#define GPIOC_CANCNTL 10 +#define GPIOC_DISC 11 +#define GPIOC_LED 12 + +/* + * All inputs with pullups unless otherwise specified. + */ +#define VAL_GPIOACRL 0x88888884 // PA0:FI +#define VAL_GPIOACRH 0x88888888 +#define VAL_GPIOAODR 0xFFFFFFFF + +#define VAL_GPIOBCRL 0x88883888 // PB3:PP +#define VAL_GPIOBCRH 0x88888888 +#define VAL_GPIOBODR 0xFFFFFFFF + +#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI +#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP +#define VAL_GPIOCODR 0xFFFFFFFF + +#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI +#define VAL_GPIODCRH 0x88888888 +#define VAL_GPIODODR 0xFFFFFFFF + +#define VAL_GPIOECRL 0x88888888 +#define VAL_GPIOECRH 0x88888888 +#define VAL_GPIOEODR 0xFFFFFFFF + +#endif /* _BOARD_H_ */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld b/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld new file mode 100644 index 000000000..9d18539f8 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103 memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 20k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)); + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h new file mode 100644 index 000000000..31c3c7a50 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -0,0 +1,464 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @addtogroup config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented or some ports. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c new file mode 100644 index 000000000..914eea1e2 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -0,0 +1,163 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" + +/* + * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). + */ +static SPIConfig hs_spicfg = { + IOPORT2, GPIOB_SPI2NSS, 0 +}; + +/* + * Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first). + */ +static SPIConfig ls_spicfg = { + IOPORT2, GPIOB_SPI2NSS, SPI_CR1_BR_2 | SPI_CR1_BR_1 +}; + +/* + * MMC driver instance. + */ +static MMCDriver MMCD1; + +/* + * MMC configuration (empty). + */ +static const MMCConfig mmc_cfg = {}; + +/* + * Card insertion verification. + */ +static bool_t mmc_is_inserted(void) { + + return (bool_t)palReadPad(IOPORT3, GPIOC_MMCCP); +} + +/* + * Card protection verification. + */ +static bool_t mmc_is_protected(void) { + + return (bool_t)palReadPad(IOPORT3, GPIOC_MMCWP); +} + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 512); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Executed as event handler at 500mS intervals. + */ +static void TimerHandler(eventid_t id) { + + (void)id; + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD2); +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + + (void)id; + mmcConnect(&MMCD1); +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + static const evhandler_t evhndl[] = { + TimerHandler, + InsertHandler, + RemoveHandler + }; + static EvTimer evt; + struct EventListener el0, el1, el2; + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Initializes the MMC driver to work with SPI2. + */ + palSetPadMode(IOPORT2, GPIOB_SPI2NSS, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT2, GPIOB_SPI2NSS); + mmcObjectInit(&MMCD1, &SPID2, + &ls_spicfg, &hs_spicfg, + mmc_is_protected, mmc_is_inserted); + mmcStart(&MMCD1, &mmc_cfg); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + +// spiStop(&SPID1); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listed for events. + */ + evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + chEvtRegister(&MMCD1.mmc_inserted_event, &el1, 1); + chEvtRegister(&MMCD1.mmc_removed_event, &el2, 2); + while (TRUE) + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + return 0; +} diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt new file mode 100644 index 000000000..09f544035 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** +***************************************************************************** + +** TARGET ** + +The demo will on an Olimex STM32-P103 board. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +COM2 (USART2). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain, +YAGARTO and an experimental WinARM build including GCC 4.3.0. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt index ad3390656..353dd2658 100644 --- a/demos/ARMCM3-STM32F103-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -14,17 +14,15 @@ COM2 (USART2). ** Build Procedure ** -The demo was tested by using the free Codesourcery GCC-based toolchain, -YAGARTO 4.3.2 and an experimental WinARM build including GCC 4.3.0. +The demo has been tested by using the free Codesourcery GCC-based toolchain, +YAGARTO and an experimental WinARM build including GCC 4.3.0. Just modify the TRGT line in the makefile in order to use different GCC ports. ** Notes ** Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license, see the header -present in all the source files under ./demos/ARMCM3-STM32F103/stm32lib for -details. -Also note that not all the files present in the ST library are distribuited +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited with ChibiOS/RT, you can find the whole library on the ST web site: http://www.st.com -- cgit v1.2.3 From 07755f046116952984c5611724092d174cb5f54f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Nov 2009 17:28:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1294 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 5 ++++- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 85a8880f1..afb044c49 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -60,12 +60,14 @@ CHIBIOS = ../.. include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk +include ${CHIBIOS}/ext/fatfs/fatfs.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ + ${FATFSSRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ ${CHIBIOS}/os/io/spi.c \ @@ -108,7 +110,8 @@ ASMSRC = $(PORTASM) \ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ${CHIBIOS}/os/io \ ${CHIBIOS}/os/io/platforms/STM32 \ - ${CHIBIOS}/os/various + ${CHIBIOS}/os/various \ + $(FATFSINC) # # Project, sources and paths diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 914eea1e2..a41d666f8 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -44,7 +44,7 @@ static SPIConfig ls_spicfg = { /* * MMC driver instance. */ -static MMCDriver MMCD1; +MMCDriver MMCD1; /* * MMC configuration (empty). -- cgit v1.2.3 From 99b688bc5e1ef930459d2523883539b1948ff5cd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Nov 2009 19:17:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1296 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index a41d666f8..e01977ac0 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -25,6 +25,8 @@ #include #include +#include + #include "board.h" /* @@ -67,6 +69,11 @@ static bool_t mmc_is_protected(void) { return (bool_t)palReadPad(IOPORT3, GPIOC_MMCWP); } +/** + * @brief FS object. + */ +FATFS MMC_FS; + /* * Red LEDs blinker thread, times are in milliseconds. */ @@ -97,9 +104,19 @@ static void TimerHandler(eventid_t id) { * MMC card insertion event. */ static void InsertHandler(eventid_t id) { + FRESULT err; (void)id; - mmcConnect(&MMCD1); + /* + * On insertion MMC initialization and FS mount. + */ + if (mmcConnect(&MMCD1)) + return; + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + mmcDisconnect(&MMCD1); + return; + } } /* @@ -146,8 +163,6 @@ int main(int argc, char **argv) { */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); -// spiStop(&SPID1); - /* * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop and listed for events. -- cgit v1.2.3 From 9963e8f14e99c8ad7083002a0e5242d2aa13bd59 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Nov 2009 19:40:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1297 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index e01977ac0..ef06c6614 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -105,6 +105,8 @@ static void TimerHandler(eventid_t id) { */ static void InsertHandler(eventid_t id) { FRESULT err; + uint32_t clusters; + FATFS *fsp; (void)id; /* @@ -117,6 +119,11 @@ static void InsertHandler(eventid_t id) { mmcDisconnect(&MMCD1); return; } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + mmcDisconnect(&MMCD1); + return; + } } /* -- cgit v1.2.3 From 55252f65b2a444692ff1b2673b32ec1cf2b205c0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Nov 2009 19:57:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1298 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index ef06c6614..5fd6737a6 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -58,7 +58,7 @@ static const MMCConfig mmc_cfg = {}; */ static bool_t mmc_is_inserted(void) { - return (bool_t)palReadPad(IOPORT3, GPIOC_MMCCP); + return palReadPad(IOPORT3, GPIOC_MMCCP); } /* @@ -66,7 +66,7 @@ static bool_t mmc_is_inserted(void) { */ static bool_t mmc_is_protected(void) { - return (bool_t)palReadPad(IOPORT3, GPIOC_MMCWP); + return !palReadPad(IOPORT3, GPIOC_MMCWP); } /** -- cgit v1.2.3 From 84cf9ce9ffa3d538b367f74c8206b8ef894d466f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 15 Nov 2009 08:52:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1299 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 3 +- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 132 ++++++++++++++++++---------- demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt | 9 +- 3 files changed, 96 insertions(+), 48 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index afb044c49..b84adf3a5 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -77,6 +77,7 @@ CSRC = ${PORTSRC} \ ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ ${CHIBIOS}/os/various/evtimer.c \ + ${CHIBIOS}/os/various/syscalls.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -158,7 +159,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = +DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 5fd6737a6..2ddf02b3f 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -27,52 +27,41 @@ #include -#include "board.h" +#include +#include -/* - * Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first). - */ -static SPIConfig hs_spicfg = { - IOPORT2, GPIOB_SPI2NSS, 0 -}; +#include "board.h" -/* - * Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first). +/** + * @brief FS object. */ -static SPIConfig ls_spicfg = { - IOPORT2, GPIOB_SPI2NSS, SPI_CR1_BR_2 | SPI_CR1_BR_1 -}; +FATFS MMC_FS; -/* - * MMC driver instance. +/** + * MMC driver instance. */ MMCDriver MMCD1; -/* - * MMC configuration (empty). - */ -static const MMCConfig mmc_cfg = {}; +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; -/* - * Card insertion verification. - */ -static bool_t mmc_is_inserted(void) { +/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig hs_spicfg = {IOPORT2, GPIOB_SPI2NSS, 0}; - return palReadPad(IOPORT3, GPIOC_MMCCP); -} +/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).*/ +static SPIConfig ls_spicfg = {IOPORT2, GPIOB_SPI2NSS, SPI_CR1_BR_2 | SPI_CR1_BR_1}; -/* - * Card protection verification. - */ -static bool_t mmc_is_protected(void) { +/* MMC configuration (empty).*/ +static const MMCConfig mmc_cfg = {}; - return !palReadPad(IOPORT3, GPIOC_MMCWP); -} +/* Card insertion verification.*/ +static bool_t mmc_is_inserted(void) {return palReadPad(IOPORT3, GPIOC_MMCCP);} -/** - * @brief FS object. - */ -FATFS MMC_FS; +/* Card protection verification.*/ +static bool_t mmc_is_protected(void) {return !palReadPad(IOPORT3, GPIOC_MMCWP);} + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; /* * Red LEDs blinker thread, times are in milliseconds. @@ -90,14 +79,65 @@ static msg_t Thread1(void *arg) { return 0; } +static FRESULT scan_files(char *path) +{ + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + siprintf(&path[i], "/%s", fn); + res = scan_files(path); + if (res != FR_OK) + break; + path[i] = 0; + } + else { + iprintf("%s/%s\r\n", path, fn); + } + } + } + return res; +} + /* * Executed as event handler at 500mS intervals. */ static void TimerHandler(eventid_t id) { (void)id; - if (palReadPad(IOPORT1, GPIOA_BUTTON)) - TestThread(&SD2); + if (palReadPad(IOPORT1, GPIOA_BUTTON)) { + if (fs_ready) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + iprintf("FS: f_getfree() failed\r\n"); + return; + } + iprintf("FS: %lu free clusters, %u sectors per cluster, %lu bytes free\r\n", + clusters, MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); + fbuff[0] = 0; + scan_files((char *)fbuff); + } + else + TestThread(&SD2); + } } /* @@ -105,25 +145,27 @@ static void TimerHandler(eventid_t id) { */ static void InsertHandler(eventid_t id) { FRESULT err; - uint32_t clusters; - FATFS *fsp; (void)id; + iprintf("MMC: inserted\r\n"); /* * On insertion MMC initialization and FS mount. */ - if (mmcConnect(&MMCD1)) - return; - err = f_mount(0, &MMC_FS); - if (err != FR_OK) { - mmcDisconnect(&MMCD1); + iprintf("MMC: initialization "); + if (mmcConnect(&MMCD1)) { + iprintf("failed\r\n"); return; } - err = f_getfree("/", &clusters, &fsp); + iprintf("ok\r\n"); + iprintf("FS: mount "); + err = f_mount(0, &MMC_FS); if (err != FR_OK) { + iprintf("failed\r\n"); mmcDisconnect(&MMCD1); return; } + fs_ready = TRUE; + iprintf("ok\r\n"); } /* @@ -132,6 +174,8 @@ static void InsertHandler(eventid_t id) { static void RemoveHandler(eventid_t id) { (void)id; + iprintf("MMC: removed\r\n"); + fs_ready = FALSE; } /* diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt index 09f544035..65f40a89a 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt @@ -8,9 +8,12 @@ The demo will on an Olimex STM32-P103 board. ** The Demo ** -The demo flashes the board LED using a thread, by pressing the button located -on the board the test procedure is activated with output on the serial port -COM2 (USART2). +This demo shows how to integrate the FatFs file system and use the SPI and MMC +drivers. +The demo flashes the board LED using a thread and monitors the MMC slot for +a card insertion. By pressing the button located on the board while a card is +inserted a directory dump on the serial port is performed, if a card is not +inserted then the test procedure is activated. ** Build Procedure ** -- cgit v1.2.3 From 7328a246ef2191998bc49bd4f22c8af3d44a16af Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 15 Nov 2009 10:51:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1303 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index b84adf3a5..58a37266f 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From aa2f5af6f01de0e2083c2c92bc4ae2fedeac847d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 16 Nov 2009 16:39:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1309 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index decfbb466..c2b7f61ca 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -68,10 +68,12 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ + ${CHIBIOS}/os/io/adc.c \ ${CHIBIOS}/os/io/spi.c \ ${CHIBIOS}/os/io/mmc_spi.c \ ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/STM32/adc_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ ${CHIBIOS}/os/various/evtimer.c \ -- cgit v1.2.3 From ea7ffbbbc0d052c5fe36014b9f18b47961c9e614 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 17 Nov 2009 19:06:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1312 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 5 ----- 1 file changed, 5 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index c2b7f61ca..53c9a26e3 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -68,13 +68,8 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/adc.c \ - ${CHIBIOS}/os/io/spi.c \ - ${CHIBIOS}/os/io/mmc_spi.c \ ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/STM32/adc_lld.c \ - ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ ${CHIBIOS}/os/various/evtimer.c \ board.c main.c -- cgit v1.2.3 From 1dd5442c8c6c3b7d77133825abf147501de36093 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 17 Nov 2009 22:09:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1313 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 2 +- demos/ARMCM3-STM32F103-GCC/board.h | 3 +++ demos/ARMCM3-STM32F103-GCC/main.c | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 2ddf02b3f..d46678a3b 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -66,7 +66,7 @@ uint8_t fbuff[1024]; /* * Red LEDs blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread1, 512); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { (void)arg; diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index ac936f2a1..0f53e5b0e 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -83,6 +83,9 @@ * IO pins assignments. */ #define GPIOA_BUTTON 0 +#define GPIOA_SPI1NSS 4 + +#define GPIOB_SPI2NSS 12 #define GPIOC_MMCWP 6 #define GPIOC_MMCCP 7 diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 116a0aaf1..46d947696 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -28,7 +28,7 @@ /* * Red LEDs blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread1, 512); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { (void)arg; -- cgit v1.2.3 From 780110bd2cbfd2adae472c5fcd7e014289559204 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 26 Nov 2009 21:03:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1327 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 4 +++- demos/ARM7-AT91SAM7X-GCC/board.h | 9 ++++++++- demos/ARM7-AT91SAM7X-LWIP-GCC/board.c | 4 +++- demos/ARM7-AT91SAM7X-LWIP-GCC/board.h | 9 ++++++++- demos/ARM7-AT91SAM7X-UIP-GCC/board.c | 4 +++- demos/ARM7-AT91SAM7X-UIP-GCC/board.h | 9 ++++++++- 6 files changed, 33 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 3faae501a..920ed7402 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -59,10 +59,12 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { /* * Digital I/O ports static configuration as defined in @p board.h. */ -static const AT91SAM7XPIOConfig config = +static const AT91SAM7PIOConfig config = { {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, +#if defined(SAM7X128) || defined(SAM7X256) || defined(SAM7X512) {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +#endif }; /* diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h index c56f50258..2cb285429 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -20,7 +20,14 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include "at91lib/AT91SAM7X256.h" +/* + * Select your platform by modifying the following line. + */ +#if !defined(SAM7_PLATFORM) +#define SAM7_PLATFORM SAM7X256 +#endif + +#include "at91sam7.h" #define BOARD_OLIMEX_SAM7_EX256 diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c index e988aaa86..7f129abaa 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c @@ -60,10 +60,12 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { /* * Digital I/O ports static configuration as defined in @p board.h. */ -static const AT91SAM7XPIOConfig config = +static const AT91SAM7PIOConfig config = { {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, +#if defined(SAM7X128) || defined(SAM7X256) || defined(SAM7X512) {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +#endif }; /* diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h index c56f50258..c0b428561 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h @@ -20,7 +20,14 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include "at91lib/AT91SAM7X256.h" +/* + * Select your platform by modifying the following line. + */ +#if !defined(SAM7_PLATFORM) +#define SAM7_PLATFORM SAM7X256 +#endif + +#include "at91sam7.h" #define BOARD_OLIMEX_SAM7_EX256 diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c index 9dbd5f0e4..9d0ed6e22 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c @@ -61,10 +61,12 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { /* * Digital I/O ports static configuration as defined in @p board.h. */ -static const AT91SAM7XPIOConfig config = +static const AT91SAM7PIOConfig config = { {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, +#if defined(SAM7X128) || defined(SAM7X256) || defined(SAM7X512) {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} +#endif }; /* diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.h b/demos/ARM7-AT91SAM7X-UIP-GCC/board.h index c56f50258..c0b428561 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/board.h @@ -20,7 +20,14 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include "at91lib/AT91SAM7X256.h" +/* + * Select your platform by modifying the following line. + */ +#if !defined(SAM7_PLATFORM) +#define SAM7_PLATFORM SAM7X256 +#endif + +#include "at91sam7.h" #define BOARD_OLIMEX_SAM7_EX256 -- cgit v1.2.3 From 845216dae25a5ec7b9e3e5fdf2441b619cbe4b53 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 26 Nov 2009 21:36:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1331 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 12 ++++++------ demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 16 ++++++++-------- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 18 +++++++++--------- 3 files changed, 23 insertions(+), 23 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 65a658661..aa4adb2ac 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -55,9 +55,9 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${CHIBIOS}/os/io/pal.c \ ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/at91lib/aic.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -86,13 +86,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X \ + ${CHIBIOS}/os/io/platforms/AT91SAM7 \ ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 # # Project, sources and paths diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 699a8c834..404fb07e0 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -58,11 +58,11 @@ CSRC = ${PORTSRC} \ ${CHIBIOS}/os/io/serial.c \ ${CHIBIOS}/os/io/mii.c \ ${CHIBIOS}/os/io/mac.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/mii_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/mii_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/mac_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/at91lib/aic.c \ ${CHIBIOS}/os/various/evtimer.c \ ${LWNETIFSRC} \ ${LWCORESRC} \ @@ -99,13 +99,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(LWINC) \ ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X \ + ${CHIBIOS}/os/io/platforms/AT91SAM7 \ ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 \ ./lwip # diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index 9b526bda4..dcd6cecd5 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -67,16 +67,16 @@ CSRC = ${PORTSRC} \ ${CHIBIOS}/os/io/serial.c \ ${CHIBIOS}/os/io/mii.c \ ${CHIBIOS}/os/io/mac.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/mii_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/mac_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X/at91lib/aic.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/pal_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/serial_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/mii_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/mac_lld.c \ + ${CHIBIOS}/os/io/platforms/AT91SAM7/at91lib/aic.c \ ${CHIBIOS}/os/various/syscalls.c \ ${CHIBIOS}/os/various/evtimer.c \ web/webthread.c \ board.c main.c -# ${CHIBIOS}/os/io/platforms/AT91SAM7X/sam7x_emac.c \ +# ${CHIBIOS}/os/io/platforms/AT91SAM7/sam7x_emac.c \ # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -104,13 +104,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X/vectors.s + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AT91SAM7X \ + ${CHIBIOS}/os/io/platforms/AT91SAM7 \ ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7X \ + ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 \ ./web ${CHIBIOS}/ext/uip-1.0/uip ${CHIBIOS}/ext/uip-1.0/apps/webserver # -- cgit v1.2.3 From 78550c25e593d553cc8c468749259366a5fff4e3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 28 Nov 2009 15:05:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1335 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 14 +++--- demos/ARMCM3-STM32F103-GCC/board.c | 79 +++----------------------------- demos/ARMCM3-STM32F103-GCC/halconf.h | 88 ++++++++++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/main.c | 10 ++-- 4 files changed, 103 insertions(+), 88 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/halconf.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 53c9a26e3..87293f6f8 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -57,6 +57,8 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/STM32/platform.mk include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -66,12 +68,10 @@ include ${CHIBIOS}/test/test.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${CHIBIOS}/os/various/evtimer.c \ + ${CHIBIOS}/os/various/syscalls.c \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -102,9 +102,7 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/STM32 \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various # diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index dac529780..58be4d77f 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -17,32 +17,8 @@ along with this program. If not, see . */ -#include -#include -#include -#include - -#include "board.h" - -#define AIRCR_VECTKEY 0x05FA0000 - -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const STM32GPIOConfig pal_config = -{ - {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, - {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, - {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, - {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, -#if !defined(STM32F10X_LD) - {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, -#endif -#if defined(STM32F10X_HD) - {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, - {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, -#endif -}; +#include "ch.h" +#include "hal.h" /* * Early initialization code. @@ -51,39 +27,7 @@ static const STM32GPIOConfig pal_config = */ void hwinit0(void) { - /* - * Clocks and PLL initialization. - */ - // HSI setup. - RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION; - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; // Waits until HSI stable, it should already be. - // HSE setup. - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; // Waits until HSE stable. - // PLL setup. - RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; // Waits until PLL stable. - // Clock sources. - RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 | - RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 | - RCC_CFGR_MCO_NOCLOCK | USBPREBITS; - - /* - * Flash setup and final clock selection. - */ - FLASH->ACR = FLASHBITS; // Flash wait states depending on clock. - RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock. - while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL) - ; - - /* - * I/O ports initialization as specified in board.h. - */ - palInit(&pal_config); + stm32_clock_init(); } /* @@ -95,24 +39,13 @@ void hwinit1(void) { /* * NVIC/SCB initialization. - * Note: PRIGROUP 4:0 (4:4). - */ - SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1; - NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL); - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK); - NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV); - - /* - * SysTick initialization. */ - SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT; + stm32_nvic_init(); /* - * Other subsystems initialization. + * HAL initialization. */ - sdInit(); + halInit(); /* * ChibiOS/RT initialization. diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h new file mode 100644 index 000000000..648a113e7 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MII subsystem. + */ +#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) +#define CH_HAL_USE_MII FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 46d947696..2e62d944d 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -17,13 +17,9 @@ along with this program. If not, see . */ -#include -#include -#include -#include -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" +#include "test.h" /* * Red LEDs blinker thread, times are in milliseconds. -- cgit v1.2.3 From a1e543399593523ac2c9e09df258d5603b6da671 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 28 Nov 2009 15:45:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1336 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 22 +++----- demos/ARMCM3-STM32F103-FATFS-GCC/board.c | 85 +++---------------------------- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 17 +++---- 3 files changed, 20 insertions(+), 104 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 58a37266f..042a82793 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -57,6 +57,8 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/STM32/platform.mk include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -67,15 +69,9 @@ include ${CHIBIOS}/ext/fatfs/fatfs.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${FATFSSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/spi.c \ - ${CHIBIOS}/os/io/mmc_spi.c \ - ${CHIBIOS}/os/io/platforms/STM32/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/STM32/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/STM32/spi_lld.c \ - ${CHIBIOS}/os/io/platforms/STM32/stm32_dma.c \ ${CHIBIOS}/os/various/evtimer.c \ ${CHIBIOS}/os/various/syscalls.c \ board.c main.c @@ -108,11 +104,9 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/STM32 \ - ${CHIBIOS}/os/various \ - $(FATFSINC) +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ + $(FATFSINC) \ + ${CHIBIOS}/os/various # # Project, sources and paths @@ -159,7 +153,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 +DDEFS = # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c index bc384a544..58be4d77f 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c @@ -17,35 +17,8 @@ along with this program. If not, see . */ -#include -#include -#include -#include -#include -#include -#include - -#include "board.h" - -#define AIRCR_VECTKEY 0x05FA0000 - -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const STM32GPIOConfig pal_config = -{ - {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, - {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, - {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, - {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, -#if !defined(STM32F10X_LD) - {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, -#endif -#if defined(STM32F10X_HD) - {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, - {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, -#endif -}; +#include "ch.h" +#include "hal.h" /* * Early initialization code. @@ -54,39 +27,7 @@ static const STM32GPIOConfig pal_config = */ void hwinit0(void) { - /* - * Clocks and PLL initialization. - */ - // HSI setup. - RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION; - while (!(RCC->CR & RCC_CR_HSIRDY)) - ; // Waits until HSI stable, it should already be. - // HSE setup. - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) - ; // Waits until HSE stable. - // PLL setup. - RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) - ; // Waits until PLL stable. - // Clock sources. - RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 | - RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 | - RCC_CFGR_MCO_NOCLOCK | USBPREBITS; - - /* - * Flash setup and final clock selection. - */ - FLASH->ACR = FLASHBITS; // Flash wait states depending on clock. - RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock. - while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL) - ; - - /* - * I/O ports initialization as specified in board.h. - */ - palInit(&pal_config); + stm32_clock_init(); } /* @@ -98,27 +39,13 @@ void hwinit1(void) { /* * NVIC/SCB initialization. - * Note: PRIGROUP 4:0 (4:4). - */ - SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1; - NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL); - NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK); - NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV); - - /* - * SysTick initialization. */ - SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT; + stm32_nvic_init(); /* - * Other subsystems initialization. + * HAL initialization. */ - dmaInit(); - sdInit(); - spiInit(); - mmcInit(); + halInit(); /* * ChibiOS/RT initialization. diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index d46678a3b..b2ff15bdd 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -17,20 +17,15 @@ along with this program. If not, see . */ -#include -#include -#include -#include -#include -#include -#include - -#include - #include #include -#include "board.h" +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "evtimer.h" + +#include "ff.h" /** * @brief FS object. -- cgit v1.2.3 From 5af98ce005cfffc0f19b7c14c048b511e35efe12 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 28 Nov 2009 16:20:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1337 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 88 ++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 042a82793..95989b6a2 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = +DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h new file mode 100644 index 000000000..ffcfd2a0b --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MII subsystem. + */ +#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) +#define CH_HAL_USE_MII FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ -- cgit v1.2.3 From 03933a5925ac71e4662d6152fad2237377a532cd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 29 Nov 2009 11:34:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1356 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/board.h | 10 ---------- demos/ARMCM3-STM32F103-GCC/board.h | 10 ---------- 2 files changed, 20 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h index 0f53e5b0e..bf04625c5 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h @@ -20,16 +20,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -/* - * Tricks required to make the TRUE/FALSE declaration inside the library - * compatible. - */ -#undef FALSE -#undef TRUE -#include -#define FALSE 0 -#define TRUE (!FALSE) - /* * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. */ diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index 0f53e5b0e..bf04625c5 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -20,16 +20,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -/* - * Tricks required to make the TRUE/FALSE declaration inside the library - * compatible. - */ -#undef FALSE -#undef TRUE -#include -#define FALSE 0 -#define TRUE (!FALSE) - /* * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. */ -- cgit v1.2.3 From 937efbc9b64d9ac5c10136e8d1e4fb359a6bdda6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 29 Nov 2009 13:37:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1357 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 13 +++--- demos/ARM7-AT91SAM7X-GCC/board.c | 86 +++---------------------------------- demos/ARM7-AT91SAM7X-GCC/halconf.h | 88 ++++++++++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-GCC/main.c | 9 ++-- 4 files changed, 102 insertions(+), 94 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-GCC/halconf.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index aa4adb2ac..0dd999e7a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -44,6 +44,8 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/AT91SAM7/platform.mk include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -53,11 +55,8 @@ include ${CHIBIOS}/test/test.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/at91lib/aic.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -88,9 +87,7 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AT91SAM7 \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various \ ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index 920ed7402..b9704971c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -17,26 +17,8 @@ along with this program. If not, see . */ -#include -#include -#include - -#include "board.h" -#include "at91lib/aic.h" - -/* - * FIQ Handler weak symbol defined in vectors.s. - */ -void FiqHandler(void); - -static CH_IRQ_HANDLER(SpuriousHandler) { - - CH_IRQ_PROLOGUE(); - - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} +#include "ch.h" +#include "hal.h" /* * SYS IRQ handling here. @@ -56,61 +38,14 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_EPILOGUE(); } -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const AT91SAM7PIOConfig config = -{ - {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, -#if defined(SAM7X128) || defined(SAM7X256) || defined(SAM7X512) - {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} -#endif -}; - /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA * segments initialization. */ void hwinit0(void) { - /* - * Flash Memory: 1 wait state, about 50 cycles in a microsecond. - */ - AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; - - /* - * Watchdog disabled. - */ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - /* - * Enables the main oscillator and waits 56 slow cycles as startup time. - */ - AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) - ; - - /* - * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 - * PLLfreq = 96109714 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | - (AT91C_CKGR_PLLCOUNT & (10 << 8)) | - (AT91C_CKGR_MUL & (72 << 16)); - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) - ; - - /* - * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) - ; - /* - * PIO initialization. - */ - palInit(&config); + at91sam7_clock_init(); } /* @@ -119,19 +54,11 @@ void hwinit0(void) { * and before invoking the main() function. */ void hwinit1(void) { - int i; /* - * Default AIC setup, the device drivers will modify it as needed. + * HAL initialization. */ - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; - for (i = 1; i < 31; i++) { - AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; - AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; - } - AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; + halInit(); /* * LCD pins setup. @@ -169,9 +96,8 @@ void hwinit1(void) { AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; /* - * Serial driver initialization, RTS/CTS pins enabled for USART0 only. + * RTS/CTS pins enabled for USART0 only. */ - sdInit(); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h new file mode 100644 index 000000000..648a113e7 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MII subsystem. + */ +#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) +#define CH_HAL_USE_MII FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index 36ae17fae..e1b7dae9b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -17,12 +17,9 @@ along with this program. If not, see . */ -#include -#include -#include -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" +#include "test.h" static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *p) { -- cgit v1.2.3 From 2e33e2772adefb783621f60f8cab452cf61abe29 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 29 Nov 2009 16:16:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1358 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.h | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 19 ++--- demos/ARM7-AT91SAM7X-LWIP-GCC/board.c | 92 ++----------------------- demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 88 +++++++++++++++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 6 +- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 8 +-- demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 88 +++++++++++++++++++++++ 7 files changed, 195 insertions(+), 108 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h index 2cb285429..c0b428561 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ b/demos/ARM7-AT91SAM7X-GCC/board.h @@ -21,7 +21,7 @@ #define _BOARD_H_ /* - * Select your platform by modifying the following line. + * Select your platform by modifying the following line. */ #if !defined(SAM7_PLATFORM) #define SAM7_PLATFORM SAM7X256 diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 404fb07e0..7255f4f3e 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -44,6 +44,8 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/AT91SAM7/platform.mk include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -54,20 +56,13 @@ include ./lwip/lwip.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/mii.c \ - ${CHIBIOS}/os/io/mac.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/mii_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/mac_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/at91lib/aic.c \ - ${CHIBIOS}/os/various/evtimer.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${LWNETIFSRC} \ ${LWCORESRC} \ ${LWIPV4SRC} \ ${LWAPISRC} \ + ${CHIBIOS}/os/various/evtimer.c \ ./lwip/arch/sys_arch.c \ ./lwip/lwipthread.c \ ./web/web.c \ @@ -101,9 +96,7 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(LWINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AT91SAM7 \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) $(LWINC) \ ${CHIBIOS}/os/various \ ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 \ ./lwip diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c index 7f129abaa..b9704971c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c @@ -17,27 +17,8 @@ along with this program. If not, see . */ -#include -#include -#include -#include - -#include "board.h" -#include "at91lib/aic.h" - -/* - * FIQ Handler weak symbol defined in vectors.s. - */ -void FiqHandler(void); - -static CH_IRQ_HANDLER(SpuriousHandler) { - - CH_IRQ_PROLOGUE(); - - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} +#include "ch.h" +#include "hal.h" /* * SYS IRQ handling here. @@ -57,61 +38,14 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_EPILOGUE(); } -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const AT91SAM7PIOConfig config = -{ - {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, -#if defined(SAM7X128) || defined(SAM7X256) || defined(SAM7X512) - {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} -#endif -}; - /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA * segments initialization. */ void hwinit0(void) { - /* - * Flash Memory: 1 wait state, about 50 cycles in a microsecond. - */ - AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; - /* - * Watchdog disabled. - */ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - /* - * Enables the main oscillator and waits 56 slow cycles as startup time. - */ - AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) - ; - - /* - * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 - * PLLfreq = 96109714 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | - (AT91C_CKGR_PLLCOUNT & (10 << 8)) | - (AT91C_CKGR_MUL & (72 << 16)); - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) - ; - - /* - * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) - ; - - /* - * PIO initialization. - */ - palInit(&config); + at91sam7_clock_init(); } /* @@ -120,19 +54,11 @@ void hwinit0(void) { * and before invoking the main() function. */ void hwinit1(void) { - int i; /* - * Default AIC setup, the device drivers will modify it as needed. + * HAL initialization. */ - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; - for (i = 1; i < 31; i++) { - AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; - AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; - } - AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; + halInit(); /* * LCD pins setup. @@ -170,18 +96,12 @@ void hwinit1(void) { AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; /* - * Serial driver initialization, RTS/CTS pins enabled for USART0 only. + * RTS/CTS pins enabled for USART0 only. */ - sdInit(); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - /* - * EMAC driver initialization. - */ - macInit(); - /* * ChibiOS/RT initialization. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h new file mode 100644 index 000000000..29fa51738 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MII subsystem. + */ +#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) +#define CH_HAL_USE_MII TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 36ca3fd37..4400445ac 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -58,9 +58,9 @@ * @{ */ -#include -#include -#include +#include "ch.h" +#include "hal.h" +#include "evtimer.h" #include "lwip/opt.h" diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index 14ac139d9..f097b059d 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -17,12 +17,10 @@ along with this program. If not, see . */ -#include -#include -#include -#include +#include "ch.h" +#include "hal.h" +#include "test.h" -#include "board.h" #include "lwip\lwipthread.h" #include "web\web.h" diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h new file mode 100644 index 000000000..29fa51738 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -0,0 +1,88 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MII subsystem. + */ +#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) +#define CH_HAL_USE_MII TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ -- cgit v1.2.3 From 6dfa752b3e76a1ae793b5d40429963364d8ab4b7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 29 Nov 2009 16:39:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1359 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 17 ++--- demos/ARM7-AT91SAM7X-UIP-GCC/board.c | 93 ++-------------------------- demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 9 +-- demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c | 16 ++--- 4 files changed, 22 insertions(+), 113 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index dcd6cecd5..575a758af 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -44,6 +44,8 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/AT91SAM7/platform.mk include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -62,16 +64,9 @@ USRC = ${CHIBIOS}/ext/uip-1.0/uip/uip_arp.c \ CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${USRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/mii.c \ - ${CHIBIOS}/os/io/mac.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/mii_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/mac_lld.c \ - ${CHIBIOS}/os/io/platforms/AT91SAM7/at91lib/aic.c \ ${CHIBIOS}/os/various/syscalls.c \ ${CHIBIOS}/os/various/evtimer.c \ web/webthread.c \ @@ -106,9 +101,7 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AT91SAM7 \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) $(LWINC) \ ${CHIBIOS}/os/various \ ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 \ ./web ${CHIBIOS}/ext/uip-1.0/uip ${CHIBIOS}/ext/uip-1.0/apps/webserver diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c index 9d0ed6e22..b9704971c 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c @@ -17,28 +17,8 @@ along with this program. If not, see . */ -#include -#include -#include -#include - -#include "board.h" -#include "at91lib/aic.h" - - -/* - * FIQ Handler weak symbol defined in vectors.s. - */ -void FiqHandler(void); - -static CH_IRQ_HANDLER(SpuriousHandler) { - - CH_IRQ_PROLOGUE(); - - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} +#include "ch.h" +#include "hal.h" /* * SYS IRQ handling here. @@ -58,61 +38,14 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_EPILOGUE(); } -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const AT91SAM7PIOConfig config = -{ - {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR}, -#if defined(SAM7X128) || defined(SAM7X256) || defined(SAM7X512) - {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR} -#endif -}; - /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA * segments initialization. */ void hwinit0(void) { - /* - * Flash Memory: 1 wait state, about 50 cycles in a microsecond. - */ - AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS; - /* - * Watchdog disabled. - */ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - /* - * Enables the main oscillator and waits 56 slow cycles as startup time. - */ - AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) - ; - - /* - * PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10 - * PLLfreq = 96109714 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) | - (AT91C_CKGR_PLLCOUNT & (10 << 8)) | - (AT91C_CKGR_MUL & (72 << 16)); - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) - ; - - /* - * Master clock = PLLfreq / 2 = 48054858 Hz (rounded) - */ - AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) - ; - - /* - * PIO initialization. - */ - palInit(&config); + at91sam7_clock_init(); } /* @@ -121,19 +54,11 @@ void hwinit0(void) { * and before invoking the main() function. */ void hwinit1(void) { - int i; /* - * Default AIC setup, the device drivers will modify it as needed. + * HAL initialization. */ - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler; - for (i = 1; i < 31; i++) { - AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL; - AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i; - } - AT91C_BASE_AIC->AIC_SPU = (AT91_REG)SpuriousHandler; + halInit(); /* * LCD pins setup. @@ -171,18 +96,12 @@ void hwinit1(void) { AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; /* - * Serial driver initialization, RTS/CTS pins enabled for USART0 only. + * RTS/CTS pins enabled for USART0 only. */ - sdInit(); AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - /* - * EMAC driver initialization. - */ - macInit(); - /* * ChibiOS/RT initialization. */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c index 03435d98b..283e01168 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -17,12 +17,9 @@ along with this program. If not, see . */ -#include -#include -#include -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" +#include "test.h" #include "web/webthread.h" diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c index 1be4df645..1235696d8 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c @@ -19,14 +19,14 @@ #include -#include -#include -#include - -#include -#include -#include -#include +#include "ch.h" +#include "hal.h" +#include "evtimer.h" + +#include "uip.h" +#include "uip_arp.h" +#include "httpd.h" +#include "clock-arch.h" #define IPADDR0 192 #define IPADDR1 168 -- cgit v1.2.3 From 3d87970a4d3f0f72560d725ecb284eaac1a69835 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 29 Nov 2009 18:51:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1364 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/halconf.h | 7 ------- demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 7 ------- demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 7 ------- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 7 ------- demos/ARMCM3-STM32F103-GCC/halconf.h | 7 ------- 5 files changed, 35 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index 648a113e7..2faba92d8 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -55,13 +55,6 @@ #define CH_HAL_USE_MAC FALSE #endif -/** - * @brief Enables the MII subsystem. - */ -#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) -#define CH_HAL_USE_MII FALSE -#endif - /** * @brief Enables the SERIAL subsystem. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 29fa51738..9f7060cf3 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -55,13 +55,6 @@ #define CH_HAL_USE_MAC TRUE #endif -/** - * @brief Enables the MII subsystem. - */ -#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) -#define CH_HAL_USE_MII TRUE -#endif - /** * @brief Enables the SERIAL subsystem. */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 29fa51738..9f7060cf3 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -55,13 +55,6 @@ #define CH_HAL_USE_MAC TRUE #endif -/** - * @brief Enables the MII subsystem. - */ -#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) -#define CH_HAL_USE_MII TRUE -#endif - /** * @brief Enables the SERIAL subsystem. */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index ffcfd2a0b..94136ff29 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -55,13 +55,6 @@ #define CH_HAL_USE_MAC FALSE #endif -/** - * @brief Enables the MII subsystem. - */ -#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) -#define CH_HAL_USE_MII FALSE -#endif - /** * @brief Enables the SERIAL subsystem. */ diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index 648a113e7..2faba92d8 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -55,13 +55,6 @@ #define CH_HAL_USE_MAC FALSE #endif -/** - * @brief Enables the MII subsystem. - */ -#if !defined(CH_HAL_USE_MII) || defined(__DOXYGEN__) -#define CH_HAL_USE_MII FALSE -#endif - /** * @brief Enables the SERIAL subsystem. */ -- cgit v1.2.3 From 39d171f7ef1cf093a1b1a05650afb0256b7c7ce1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 29 Nov 2009 21:07:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1366 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/board.c | 5 ----- demos/ARMCM3-STM32F103-GCC/board.c | 5 ----- 2 files changed, 10 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c index 58be4d77f..8c33354ae 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c @@ -37,11 +37,6 @@ void hwinit0(void) { */ void hwinit1(void) { - /* - * NVIC/SCB initialization. - */ - stm32_nvic_init(); - /* * HAL initialization. */ diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c index 58be4d77f..8c33354ae 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ b/demos/ARMCM3-STM32F103-GCC/board.c @@ -37,11 +37,6 @@ void hwinit0(void) { */ void hwinit1(void) { - /* - * NVIC/SCB initialization. - */ - stm32_nvic_init(); - /* * HAL initialization. */ -- cgit v1.2.3 From 770c4873d20623f6d4f678d62b67eb6218e259bf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 30 Nov 2009 19:11:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1367 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/board.c | 7 +++++-- demos/ARM7-AT91SAM7X-LWIP-GCC/board.c | 7 +++++-- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 8 ++++---- demos/ARM7-AT91SAM7X-UIP-GCC/board.c | 5 ++++- 4 files changed, 18 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c index b9704971c..fab8b0338 100644 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-GCC/board.c @@ -44,7 +44,10 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { * segments initialization. */ void hwinit0(void) { - + + /* Watchdog disabled.*/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + at91sam7_clock_init(); } @@ -56,7 +59,7 @@ void hwinit0(void) { void hwinit1(void) { /* - * HAL initialization. + * HAL initialization. */ halInit(); diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c index b9704971c..fab8b0338 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c @@ -44,7 +44,10 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { * segments initialization. */ void hwinit0(void) { - + + /* Watchdog disabled.*/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + at91sam7_clock_init(); } @@ -56,7 +59,7 @@ void hwinit0(void) { void hwinit1(void) { /* - * HAL initialization. + * HAL initialization. */ halInit(); diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index f097b059d..3b469aed4 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -21,8 +21,8 @@ #include "hal.h" #include "test.h" -#include "lwip\lwipthread.h" -#include "web\web.h" +#include "lwip/lwipthread.h" +#include "web/web.h" static WORKING_AREA(waThread1, 64); static msg_t Thread1(void *arg) { @@ -57,13 +57,13 @@ int main(int argc, char **argv) { chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); /* - * Creates the LWIP threads (it changes priority internally). + * Creates the LWIP threads (it changes priority internally). */ chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1, lwip_thread, NULL); /* - * Creates the HTTP thread (it changes priority internally). + * Creates the HTTP thread (it changes priority internally). */ chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1, http_server, NULL); diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c index b9704971c..c55b5869e 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c @@ -45,6 +45,9 @@ static CH_IRQ_HANDLER(SYSIrqHandler) { */ void hwinit0(void) { + /* Watchdog disabled.*/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + at91sam7_clock_init(); } @@ -56,7 +59,7 @@ void hwinit0(void) { void hwinit1(void) { /* - * HAL initialization. + * HAL initialization. */ halInit(); -- cgit v1.2.3 From 3d182788ee7386b0fa53b4aee08fe8146d67d3b0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 1 Dec 2009 16:32:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1369 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/halconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index 2faba92d8..44aae2773 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -45,7 +45,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN TRUE #endif /** -- cgit v1.2.3 From 8400c8e42e3644eec40ec85703cedabae6fd986e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 2 Dec 2009 20:13:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1371 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/halconf.h | 2 +- demos/MSP430-MSP430x1611-GCC/Makefile | 12 +++---- demos/MSP430-MSP430x1611-GCC/board.c | 64 ++++++++--------------------------- demos/MSP430-MSP430x1611-GCC/board.h | 2 -- demos/MSP430-MSP430x1611-GCC/main.c | 9 ++--- 5 files changed, 23 insertions(+), 66 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index 44aae2773..2faba92d8 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -45,7 +45,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN TRUE +#define CH_HAL_USE_CAN FALSE #endif /** diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 7a7a720a8..97de20466 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -40,6 +40,8 @@ LDSCRIPT = mspgcc/msp430x1611.x # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/MSP430/platform.mk include ${CHIBIOS}/os/ports/GCC/MSP430/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -48,10 +50,8 @@ include ${CHIBIOS}/test/test.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/MSP430/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/MSP430/serial_lld.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${CHIBIOS}/os/various/evtimer.c \ board.c main.c @@ -61,9 +61,7 @@ CPPSRC = # List ASM source files here ASMSRC = $(PORTASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/MSP430 \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various # diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c index 32f7c325b..93197bcfd 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ b/demos/MSP430-MSP430x1611-GCC/board.c @@ -17,26 +17,21 @@ along with this program. If not, see . */ -#include -#include -#include - #include -#include "board.h" +#include "ch.h" +#include "hal.h" -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const MSP430DIOConfig config = -{ - {VAL_P1OUT, VAL_P1DIR}, - {VAL_P2OUT, VAL_P2DIR}, - {VAL_P3OUT, VAL_P3DIR}, - {VAL_P4OUT, VAL_P4DIR}, - {VAL_P5OUT, VAL_P5DIR}, - {VAL_P6OUT, VAL_P6DIR}, -}; +CH_IRQ_HANDLER(TIMERA0_VECTOR) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} /* * Hardware initialization goes here. @@ -45,24 +40,9 @@ static const MSP430DIOConfig config = void hwinit(void) { /* - * Clock sources setup. - */ - DCOCTL = VAL_DCOCTL; - BCSCTL1 = VAL_BCSCTL1; -#if defined(MSP_USE_XT2CLK) - do { - int i; - IFG1 &= ~OFIFG; - for (i = 255; i > 0; i--) - asm("nop"); - } while (IFG1 & OFIFG); -#endif - BCSCTL2 = VAL_BCSCTL2; - - /* - * I/O ports initialization. + * HAL initialization. */ - palInit(&config); + halInit(); /* * Timer 0 setup, uses SMCLK as source. @@ -71,20 +51,4 @@ void hwinit(void) { TACTL = TACLR; /* Clean start. */ TACTL = TASSEL_2 | ID_2 | MC_1; /* Src=SMCLK, ID=4, cmp=TACCR0. */ TACCTL0 = CCIE; /* Interrupt on compare. */ - - /* - * Other subsystems. - */ - sdInit(); -} - -CH_IRQ_HANDLER(TIMERA0_VECTOR) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); } diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index 235a8303a..836603f80 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -20,8 +20,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include - /* * Clock settings. */ diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 3e729296b..91fb26f83 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -17,12 +17,9 @@ along with this program. If not, see . */ -#include -#include -#include -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" +#include "test.h" /* * Red LEDs blinker thread, times are in milliseconds. -- cgit v1.2.3 From 2f505cf183ad47f6b25677e864e2f426b28c7f6f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Dec 2009 09:07:21 +0000 Subject: MSP430 HAL integration git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1375 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/board.h | 30 +----------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h index 836603f80..8f22c6a8e 100644 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ b/demos/MSP430-MSP430x1611-GCC/board.h @@ -21,40 +21,12 @@ #define _BOARD_H_ /* - * Clock settings. + * Clock constants. */ -//#define MSP_USE_XT2CLK -#define MSP_USE_DCOCLK - -#if defined(MSP_USE_XT2CLK) && defined(MSP_USE_DCOCLK) -#error "Define MSP_USE_XT2CLK or MSP_USE_DCOCLK, not both" -#endif - #define LFXT1CLK 32768 #define XT2CLK 8000000 #define DCOCLK 750000 -#define ACLK LFXT1CLK -#if defined(MSP_USE_XT2CLK) -#define MCLK XT2CLK -#define SMCLK (XT2CLK / 8) -#elif defined(MSP_USE_DCOCLK) -#define MCLK DCOCLK -#define SMCLK DCOCLK -#else -#error "Default clock source not selected" -#endif - -#define VAL_DCOCTL (DCO0 | DCO1) -#if defined(MSP_USE_XT2CLK) -#define VAL_BCSCTL1 (RSEL2) -#define VAL_BCSCTL2 (SELM_2 | DIVM_0 | DIVS_3 | SELS) -#endif -#if defined(MSP_USE_DCOCLK) -#define VAL_BCSCTL1 (XT2OFF | RSEL2) -#define VAL_BCSCTL2 (SELM_0 | DIVM_0 | DIVS_0) -#endif - /* * Pin definitions for the Olimex MSP430-P1611 board. */ -- cgit v1.2.3 From 646d8a2376e3d476a3d00edb665770596fb252f6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Dec 2009 14:59:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1376 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/board.h | 44 +------------------------------- demos/ARMCM3-STM32F103-GCC/board.h | 44 +------------------------------- 2 files changed, 2 insertions(+), 86 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h index bf04625c5..588ea3c5d 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h @@ -21,53 +21,11 @@ #define _BOARD_H_ /* - * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. - */ -//#define SYSCLK_48 - -/* - * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. + * Board frequencies. */ #define LSECLK 32768 #define HSECLK 8000000 #define HSICLK 8000000 -#define PLLPRE 1 -#ifdef SYSCLK_48 - #define PLLMUL 6 -#else - #define PLLMUL 9 -#endif -#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) -#define SYSCLK PLLCLK -#define APB1CLK (SYSCLK / 2) -#define APB2CLK (SYSCLK / 2) -#define AHB1CLK (SYSCLK / 1) - -/* - * Values derived from the clock settings. - */ -#define PLLPREBITS ((PLLPRE - 1) << 17) -#define PLLMULBITS ((PLLMUL - 2) << 18) -#ifdef SYSCLK_48 - #define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS - #define FLASHBITS 0x00000011 -#else - #define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS - #define FLASHBITS 0x00000012 -#endif - -/* - * Extra definitions for RCC_CR register (missing from the ST header file). - */ -#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3) - -/* - * Extra definitions for RCC_CFGR register (missing from the ST header file). - */ -#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16) -#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16) -#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22) -#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22) /* * IO pins assignments. diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h index bf04625c5..588ea3c5d 100644 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ b/demos/ARMCM3-STM32F103-GCC/board.h @@ -21,53 +21,11 @@ #define _BOARD_H_ /* - * Uncomment this if you want a 48MHz system clock, else it will be 72MHz. - */ -//#define SYSCLK_48 - -/* - * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16. + * Board frequencies. */ #define LSECLK 32768 #define HSECLK 8000000 #define HSICLK 8000000 -#define PLLPRE 1 -#ifdef SYSCLK_48 - #define PLLMUL 6 -#else - #define PLLMUL 9 -#endif -#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL) -#define SYSCLK PLLCLK -#define APB1CLK (SYSCLK / 2) -#define APB2CLK (SYSCLK / 2) -#define AHB1CLK (SYSCLK / 1) - -/* - * Values derived from the clock settings. - */ -#define PLLPREBITS ((PLLPRE - 1) << 17) -#define PLLMULBITS ((PLLMUL - 2) << 18) -#ifdef SYSCLK_48 - #define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS - #define FLASHBITS 0x00000011 -#else - #define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS - #define FLASHBITS 0x00000012 -#endif - -/* - * Extra definitions for RCC_CR register (missing from the ST header file). - */ -#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3) - -/* - * Extra definitions for RCC_CFGR register (missing from the ST header file). - */ -#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16) -#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16) -#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22) -#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22) /* * IO pins assignments. -- cgit v1.2.3 From 456490bf06d9d6eccf7a02b18fba94058c81f26c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 08:28:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1388 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 792ff4fbd..10eb571ae 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -44,6 +44,8 @@ LDSCRIPT = ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/LPC214x/platform.mk include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -53,11 +55,8 @@ include ${CHIBIOS}/test/test.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/vic.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${CHIBIOS}/os/io/platforms/LPC214x/lpc214x_ssp.c \ ${CHIBIOS}/os/various/evtimer.c \ board.c buzzer.c mmcsd.c main.c @@ -90,9 +89,7 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/LPC214x \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various \ ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x -- cgit v1.2.3 From 3ff9afd04851ec97d66d6833520b49dc18f35ea4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 08:47:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1389 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/board.c | 57 +++--------------------------------------- 1 file changed, 3 insertions(+), 54 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 2c041b384..9c4c7e335 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -28,19 +28,6 @@ #include "mmcsd.h" #include "buzzer.h" -/* - * Non-vectored IRQs handling here. - */ -static CH_IRQ_HANDLER(IrqHandler) { - - CH_IRQ_PROLOGUE(); - - /* nothing */ - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} - /* * Timer 0 IRQ handling here. */ @@ -76,43 +63,7 @@ static const LPC214xFIOConfig config = */ void hwinit0(void) { - /* - * All peripherals clock disabled by default in order to save power. - */ - PCONP = PCRTC | PCTIM0; - - /* - * MAM setup. - */ - MAMTIM = 0x3; /* 3 cycles for flash accesses. */ - MAMCR = 0x2; /* MAM fully enabled. */ - - /* - * PLL setup for Fosc=12MHz and CCLK=48MHz. - * P=2 M=3. - */ - PLL *pll = PLL0Base; - pll->PLL_CFG = 0x23; /* P and M values. */ - pll->PLL_CON = 0x1; /* Enables the PLL 0. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - while (!(pll->PLL_STAT & 0x400)) - ; /* Wait for PLL lock. */ - - pll->PLL_CON = 0x3; /* Connects the PLL. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - - /* - * VPB setup. - * PCLK = CCLK / 4. - */ - VPBDIV = VPD_D4; - - /* - * I/O pins configuration. - */ - palInit(&config); + lpc214x_clock_init(); } /* @@ -123,10 +74,9 @@ void hwinit0(void) { void hwinit1(void) { /* - * Interrupt vectors assignment. + * HAL initialization. */ - vic_init(); - VICDefVectAddr = (IOREG32)IrqHandler; + halInit(); /* * System Timer initialization, 1ms intervals. @@ -143,7 +93,6 @@ void hwinit1(void) { /* * Other subsystems. */ - sdInit(); ssp_init(); InitMMC(); InitBuzzer(); -- cgit v1.2.3 From 06f43125b330a04111b8bbe3b475140703c97e22 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 08:56:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1390 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/Makefile | 2 +- demos/ARM7-LPC214x-GCC/board.c | 22 ++++------------------ demos/ARM7-LPC214x-GCC/board.h | 4 ---- demos/ARM7-LPC214x-GCC/buzzer.c | 6 +++--- demos/ARM7-LPC214x-GCC/main.c | 10 ++++------ demos/ARM7-LPC214x-GCC/mmcsd.c | 6 ++---- 6 files changed, 14 insertions(+), 36 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 10eb571ae..9d44185a4 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -57,7 +57,7 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${HALSRC} \ ${PLATFORMSRC} \ - ${CHIBIOS}/os/io/platforms/LPC214x/lpc214x_ssp.c \ + ${CHIBIOS}/os/hal/platforms/LPC214x/lpc214x_ssp.c \ ${CHIBIOS}/os/various/evtimer.c \ board.c buzzer.c mmcsd.c main.c diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c index 9c4c7e335..f81d2329a 100644 --- a/demos/ARM7-LPC214x-GCC/board.c +++ b/demos/ARM7-LPC214x-GCC/board.c @@ -17,17 +17,15 @@ along with this program. If not, see . */ -#include -#include -#include +#include "ch.h" +#include "hal.h" -#include "vic.h" #include "lpc214x_ssp.h" - -#include "board.h" #include "mmcsd.h" #include "buzzer.h" +#define VAL_TC0_PRESCALER 0 + /* * Timer 0 IRQ handling here. */ @@ -44,18 +42,6 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_EPILOGUE(); } -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const LPC214xFIOConfig config = -{ - VAL_PINSEL0, - VAL_PINSEL1, - VAL_PINSEL2, - {VAL_FIO0PIN, VAL_FIO0DIR}, - {VAL_FIO1PIN, VAL_FIO1DIR} -}; - /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA diff --git a/demos/ARM7-LPC214x-GCC/board.h b/demos/ARM7-LPC214x-GCC/board.h index 022383032..b66ce235d 100644 --- a/demos/ARM7-LPC214x-GCC/board.h +++ b/demos/ARM7-LPC214x-GCC/board.h @@ -20,8 +20,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include "lpc214x.h" - #define BOARD_OLIMEX_LCP_P2148 /* @@ -32,8 +30,6 @@ #define CCLK 48000000 #define PCLK 12000000 -#define VAL_TC0_PRESCALER 0 - /* * Pins configuration for Olimex LPC-P2148. * diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c index 1d3350bb2..2e7c0bd98 100644 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ b/demos/ARM7-LPC214x-GCC/buzzer.c @@ -24,10 +24,10 @@ * The driver also generates an event when the sound is done and the buzzer * goes silent. */ -#include -#include "lpc214x.h" -#include "board.h" +#include "ch.h" +#include "hal.h" + #include "buzzer.h" EventSource BuzzerSilentEventSource; diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 93b6fd768..d0a69b3d7 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -17,15 +17,13 @@ along with this program. If not, see . */ -#include -#include -#include -#include +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "evtimer.h" -#include "board.h" #include "mmcsd.h" #include "buzzer.h" -#include "evtimer.h" #define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c index 731f594a2..220d9c88a 100644 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ b/demos/ARM7-LPC214x-GCC/mmcsd.c @@ -17,12 +17,10 @@ along with this program. If not, see . */ -#include -#include +#include "ch.h" +#include "hal.h" -#include "board.h" #include "lpc214x_ssp.h" - #include "mmcsd.h" EventSource MMCInsertEventSource, MMCRemoveEventSource; -- cgit v1.2.3 From 93fc8b57778f698cbe7e0e202e33b5d56ce09039 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 10:36:29 +0000 Subject: HAL implemented for LPC214x. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1392 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 13 ++--- demos/ARM7-LPC214x-G++/board.c | 78 ++------------------------ demos/ARM7-LPC214x-G++/board.h | 4 -- demos/ARM7-LPC214x-G++/halconf.h | 96 ++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-G++/main.cpp | 11 ++-- demos/ARM7-LPC214x-GCC-minimal/Makefile | 11 ++-- demos/ARM7-LPC214x-GCC-minimal/board.c | 78 ++------------------------ demos/ARM7-LPC214x-GCC-minimal/board.h | 4 -- demos/ARM7-LPC214x-GCC-minimal/halconf.h | 96 ++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC-minimal/main.c | 6 +- demos/ARM7-LPC214x-GCC/halconf.h | 96 ++++++++++++++++++++++++++++++++ 11 files changed, 316 insertions(+), 177 deletions(-) create mode 100644 demos/ARM7-LPC214x-G++/halconf.h create mode 100644 demos/ARM7-LPC214x-GCC-minimal/halconf.h create mode 100644 demos/ARM7-LPC214x-GCC/halconf.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 3bb33abfe..8c20ec2b8 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -44,6 +44,8 @@ LDSCRIPT = ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/LPC214x/platform.mk include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -53,11 +55,8 @@ include ${CHIBIOS}/test/test.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/serial_lld.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/vic.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${CHIBIOS}/os/various/evtimer.c \ board.c @@ -89,9 +88,7 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/LPC214x \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various \ ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c index eba3f59e3..539adabee 100644 --- a/demos/ARM7-LPC214x-G++/board.c +++ b/demos/ARM7-LPC214x-G++/board.c @@ -17,30 +17,14 @@ along with this program. If not, see . */ -#include -#include -#include +#include "ch.h" +#include "hal.h" -#include "lpc214x.h" -#include "vic.h" //#include "lpc214x_ssp.h" - -#include "board.h" //#include "mmcsd.h" //#include "buzzer.h" -/* - * Non-vectored IRQs handling here. - */ -static CH_IRQ_HANDLER(IrqHandler) { - - CH_IRQ_PROLOGUE(); - - /* nothing */ - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} +#define VAL_TC0_PRESCALER 0 /* * Timer 0 IRQ handling here. @@ -58,18 +42,6 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_EPILOGUE(); } -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const LPC214xFIOConfig config = -{ - VAL_PINSEL0, - VAL_PINSEL1, - VAL_PINSEL2, - {VAL_FIO0PIN, VAL_FIO0DIR}, - {VAL_FIO1PIN, VAL_FIO1DIR} -}; - /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -77,43 +49,7 @@ static const LPC214xFIOConfig config = */ void hwinit0(void) { - /* - * All peripherals clock disabled by default in order to save power. - */ - PCONP = PCRTC | PCTIM0; - - /* - * MAM setup. - */ - MAMTIM = 0x3; /* 3 cycles for flash accesses. */ - MAMCR = 0x2; /* MAM fully enabled. */ - - /* - * PLL setup for Fosc=12MHz and CCLK=48MHz. - * P=2 M=3. - */ - PLL *pll = PLL0Base; - pll->PLL_CFG = 0x23; /* P and M values. */ - pll->PLL_CON = 0x1; /* Enables the PLL 0. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - while (!(pll->PLL_STAT & 0x400)) - ; /* Wait for PLL lock. */ - - pll->PLL_CON = 0x3; /* Connects the PLL. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - - /* - * VPB setup. - * PCLK = CCLK / 4. - */ - VPBDIV = VPD_D4; - - /* - * I/O pins configuration. - */ - palInit(&config); + lpc214x_clock_init(); } /* @@ -124,10 +60,9 @@ void hwinit0(void) { void hwinit1(void) { /* - * Interrupt vectors assignment. + * HAL initialization. */ - vic_init(); - VICDefVectAddr = (IOREG32)IrqHandler; + halInit(); /* * System Timer initialization, 1ms intervals. @@ -144,7 +79,6 @@ void hwinit1(void) { /* * Other subsystems. */ - sdInit(); // ssp_init(); // InitMMC(); // InitBuzzer(); diff --git a/demos/ARM7-LPC214x-G++/board.h b/demos/ARM7-LPC214x-G++/board.h index 022383032..b66ce235d 100644 --- a/demos/ARM7-LPC214x-G++/board.h +++ b/demos/ARM7-LPC214x-G++/board.h @@ -20,8 +20,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include "lpc214x.h" - #define BOARD_OLIMEX_LCP_P2148 /* @@ -32,8 +30,6 @@ #define CCLK 48000000 #define PCLK 12000000 -#define VAL_TC0_PRESCALER 0 - /* * Pins configuration for Olimex LPC-P2148. * diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h new file mode 100644 index 000000000..4e2e694c4 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index f0268045d..7b012d004 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -17,13 +17,10 @@ along with this program. If not, see . */ -#include -#include -#include -#include -#include - -#include "board.h" +#include "ch.hpp" +#include "hal.h" +#include "test.h" +#include "evtimer.h" #define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 21e9a0eea..8801183e4 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -44,6 +44,8 @@ LDSCRIPT = ch.ld # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/LPC214x/platform.mk include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk include ${CHIBIOS}/os/kernel/kernel.mk #include ${CHIBIOS}/test/test.mk @@ -53,9 +55,8 @@ include ${CHIBIOS}/os/kernel/kernel.mk CSRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/pal.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/pal_lld.c \ - ${CHIBIOS}/os/io/platforms/LPC214x/vic.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ board.c main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -86,9 +87,7 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/LPC214x \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various \ ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c index bcf430ade..539adabee 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ b/demos/ARM7-LPC214x-GCC-minimal/board.c @@ -17,30 +17,14 @@ along with this program. If not, see . */ -#include -#include +#include "ch.h" +#include "hal.h" -#include "lpc214x.h" -#include "vic.h" -//#include "lpc214x_serial.h" //#include "lpc214x_ssp.h" - -#include "board.h" //#include "mmcsd.h" //#include "buzzer.h" -/* - * Non-vectored IRQs handling here. - */ -static CH_IRQ_HANDLER(IrqHandler) { - - CH_IRQ_PROLOGUE(); - - /* nothing */ - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} +#define VAL_TC0_PRESCALER 0 /* * Timer 0 IRQ handling here. @@ -58,18 +42,6 @@ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_EPILOGUE(); } -/* - * Digital I/O ports static configuration as defined in @p board.h. - */ -static const LPC214xFIOConfig config = -{ - VAL_PINSEL0, - VAL_PINSEL1, - VAL_PINSEL2, - {VAL_FIO0PIN, VAL_FIO0DIR}, - {VAL_FIO1PIN, VAL_FIO1DIR} -}; - /* * Early initialization code. * This initialization is performed just after reset before BSS and DATA @@ -77,43 +49,7 @@ static const LPC214xFIOConfig config = */ void hwinit0(void) { - /* - * All peripherals clock disabled by default in order to save power. - */ - PCONP = PCRTC | PCTIM0; - - /* - * MAM setup. - */ - MAMTIM = 0x3; /* 3 cycles for flash accesses. */ - MAMCR = 0x2; /* MAM fully enabled. */ - - /* - * PLL setup for Fosc=12MHz and CCLK=48MHz. - * P=2 M=3. - */ - PLL *pll = PLL0Base; - pll->PLL_CFG = 0x23; /* P and M values. */ - pll->PLL_CON = 0x1; /* Enables the PLL 0. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - while (!(pll->PLL_STAT & 0x400)) - ; /* Wait for PLL lock. */ - - pll->PLL_CON = 0x3; /* Connects the PLL. */ - pll->PLL_FEED = 0xAA; - pll->PLL_FEED = 0x55; - - /* - * VPB setup. - * PCLK = CCLK / 4. - */ - VPBDIV = VPD_D4; - - /* - * I/O pins configuration. - */ - palInit(&config); + lpc214x_clock_init(); } /* @@ -124,10 +60,9 @@ void hwinit0(void) { void hwinit1(void) { /* - * Interrupt vectors assignment. + * HAL initialization. */ - vic_init(); - VICDefVectAddr = (IOREG32)IrqHandler; + halInit(); /* * System Timer initialization, 1ms intervals. @@ -144,7 +79,6 @@ void hwinit1(void) { /* * Other subsystems. */ -// sdInit(); // ssp_init(); // InitMMC(); // InitBuzzer(); diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h index 022383032..b66ce235d 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/board.h +++ b/demos/ARM7-LPC214x-GCC-minimal/board.h @@ -20,8 +20,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_ -#include "lpc214x.h" - #define BOARD_OLIMEX_LCP_P2148 /* @@ -32,8 +30,6 @@ #define CCLK 48000000 #define PCLK 12000000 -#define VAL_TC0_PRESCALER 0 - /* * Pins configuration for Olimex LPC-P2148. * diff --git a/demos/ARM7-LPC214x-GCC-minimal/halconf.h b/demos/ARM7-LPC214x-GCC-minimal/halconf.h new file mode 100644 index 000000000..63afdace0 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC-minimal/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c index 7ce5ffe95..940e77b5e 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ b/demos/ARM7-LPC214x-GCC-minimal/main.c @@ -17,10 +17,8 @@ along with this program. If not, see . */ -#include -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" /* * Red LEDs blinker thread, times are in milliseconds. diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h new file mode 100644 index 000000000..4e2e694c4 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ -- cgit v1.2.3 From cbbacdb239211fc33b0423b1213d2e58ac1692da Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 14:42:32 +0000 Subject: HAL support for AVR. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1394 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/Makefile | 10 ++-- demos/AVR-AT90CANx-GCC/board.c | 22 ++++----- demos/AVR-AT90CANx-GCC/board.h | 8 +++- demos/AVR-AT90CANx-GCC/halconf.h | 96 +++++++++++++++++++++++++++++++++++++++ demos/AVR-AT90CANx-GCC/main.c | 12 ++--- demos/AVR-ATmega128-GCC/Makefile | 10 ++-- demos/AVR-ATmega128-GCC/board.c | 22 ++++----- demos/AVR-ATmega128-GCC/board.h | 8 +++- demos/AVR-ATmega128-GCC/halconf.h | 96 +++++++++++++++++++++++++++++++++++++++ demos/AVR-ATmega128-GCC/main.c | 11 ++--- 10 files changed, 242 insertions(+), 53 deletions(-) create mode 100644 demos/AVR-AT90CANx-GCC/halconf.h create mode 100644 demos/AVR-ATmega128-GCC/halconf.h (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index 5754a6371..0b6943cab 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -81,6 +81,8 @@ OBJDIR = . # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/AVR/platform.mk include ${CHIBIOS}/os/ports/GCC/AVR/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -90,8 +92,8 @@ include ${CHIBIOS}/test/test.mk SRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/AVR/serial_lld.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${CHIBIOS}/os/various/evtimer.c \ board.c main.c @@ -127,9 +129,7 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AVR \ +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c index 2fdf128a1..b97bd94b5 100644 --- a/demos/AVR-AT90CANx-GCC/board.c +++ b/demos/AVR-AT90CANx-GCC/board.c @@ -17,10 +17,8 @@ along with this program. If not, see . */ -#include -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" CH_IRQ_HANDLER(TIMER0_COMP_vect) { @@ -71,16 +69,16 @@ void hwinit(void) { /* * Timer 0 setup. */ - TCCR0A = (1 << WGM01) | (0 << WGM00) | // CTC mode. - (0 << COM0A1) | (0 << COM0A0) | // OC0A disabled (normal I/O). - (0 << CS02) | (1 << CS01) | (1 << CS00); // CLK/64 clock source. + TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ + (0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */ + (0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */ OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; - TCNT0 = 0; // Reset counter. - TIFR0 = (1 << OCF0A); // Reset pending (if any). - TIMSK0 = (1 << OCIE0A); // Interrupt on compare. + TCNT0 = 0; /* Reset counter. */ + TIFR0 = (1 << OCF0A); /* Reset pending. */ + TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */ /* - * Other initializations. + * HAL initialization. */ - sdInit(); + halInit(); } diff --git a/demos/AVR-AT90CANx-GCC/board.h b/demos/AVR-AT90CANx-GCC/board.h index fefd6a39c..0abe920eb 100644 --- a/demos/AVR-AT90CANx-GCC/board.h +++ b/demos/AVR-AT90CANx-GCC/board.h @@ -81,6 +81,12 @@ #define PORTE_LED (1 << 4) #define PORTE_BUTTON (1 << 5) -void hwinit(void); +#ifdef __cplusplus +extern "C" { +#endif + void hwinit(void); +#ifdef __cplusplus +} +#endif #endif /* _BOARD_H_ */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h new file mode 100644 index 000000000..a3d17a3c9 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index a19b1e9c5..61df6a3ed 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -17,15 +17,9 @@ along with this program. If not, see . */ -#include -#include -#include - -#include - -#include "board.h" - -void hwinit(void); +#include "ch.h" +#include "hal.h" +#include "evtimer.h" static WORKING_AREA(waThread1, 32); static msg_t Thread1(void *arg) { diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index dcc7f7beb..1ae0a672a 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -81,6 +81,8 @@ OBJDIR = . # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/AVR/platform.mk include ${CHIBIOS}/os/ports/GCC/AVR/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -90,8 +92,8 @@ include ${CHIBIOS}/test/test.mk SRC = ${PORTSRC} \ ${KERNSRC} \ ${TESTSRC} \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/AVR/serial_lld.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ ${CHIBIOS}/os/various/evtimer.c \ lcd.c board.c main.c @@ -127,9 +129,7 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/AVR \ +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ ${CHIBIOS}/os/various diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c index 84e1565cb..8a9a69309 100644 --- a/demos/AVR-ATmega128-GCC/board.c +++ b/demos/AVR-ATmega128-GCC/board.c @@ -17,10 +17,8 @@ along with this program. If not, see . */ -#include -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" CH_IRQ_HANDLER(TIMER0_COMP_vect) { @@ -71,16 +69,16 @@ void hwinit(void) { /* * Timer 0 setup. */ - TCCR0 = (1 << WGM01) | (0 << WGM00) | // CTC mode. - (0 << COM01) | (0 << COM00) | // OC0A disabled (normal I/O). - (1 << CS02) | (0 << CS01) | (0 << CS00); // CLK/64 clock source. + TCCR0 = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ + (0 << COM01) | (0 << COM00) | /* OC0A disabled. */ + (1 << CS02) | (0 << CS01) | (0 << CS00); /* CLK/64 clock. */ OCR0 = F_CPU / 64 / CH_FREQUENCY - 1; - TCNT0 = 0; // Reset counter. - TIFR = (1 << OCF0); // Reset pending (if any). - TIMSK = (1 << OCIE0); // Interrupt on compare. + TCNT0 = 0; /* Reset counter. */ + TIFR = (1 << OCF0); /* Reset pending. */ + TIMSK = (1 << OCIE0); /* IRQ on compare. */ /* - * Other initializations. + * HAL initialization. */ - sdInit(); + halInit(); } diff --git a/demos/AVR-ATmega128-GCC/board.h b/demos/AVR-ATmega128-GCC/board.h index 97b9c684d..97da17097 100644 --- a/demos/AVR-ATmega128-GCC/board.h +++ b/demos/AVR-ATmega128-GCC/board.h @@ -105,6 +105,12 @@ #define PORTE_BUZZ1 (1 << 4) #define PORTE_BUZZ2 (1 << 5) -void hwinit(void); +#ifdef __cplusplus +extern "C" { +#endif + void hwinit(void); +#ifdef __cplusplus +} +#endif #endif /* _BOARD_H_ */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h new file mode 100644 index 000000000..a3d17a3c9 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index dc3fd33c3..28d3f1cef 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -17,17 +17,12 @@ along with this program. If not, see . */ -#include -#include -#include +#include "ch.h" +#include "hal.h" +#include "evtimer.h" -#include - -#include "board.h" #include "lcd.h" -void hwinit(void); - static WORKING_AREA(waThread1, 32); static msg_t Thread1(void *arg) { -- cgit v1.2.3 From 03ee1dcc181977a44af9a43906fb1d41055ab713 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 15:33:39 +0000 Subject: Updated reports. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1395 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/halconf.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index 2faba92d8..4e2e694c4 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -20,10 +20,18 @@ /** * @file templates/halconf.h * @brief HAL configuration header. - * @addtogroup HAL + * @addtogroup HAL_CONF * @{ */ +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + #ifndef _HALCONF_H_ #define _HALCONF_H_ @@ -55,6 +63,13 @@ #define CH_HAL_USE_MAC FALSE #endif +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + /** * @brief Enables the SERIAL subsystem. */ -- cgit v1.2.3 From 894e11f8f781dc17ff729acfddc4db1a3091951f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 15:44:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1396 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index 94136ff29..6fb0e97fa 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -20,10 +20,18 @@ /** * @file templates/halconf.h * @brief HAL configuration header. - * @addtogroup HAL + * @addtogroup HAL_CONF * @{ */ +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + #ifndef _HALCONF_H_ #define _HALCONF_H_ @@ -55,6 +63,13 @@ #define CH_HAL_USE_MAC FALSE #endif +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + /** * @brief Enables the SERIAL subsystem. */ -- cgit v1.2.3 From 31f54b93735bca0ef23b68dc1a1cf735800bbf14 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 17:44:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1398 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c | 2 +- demos/AVR-ATmega128-GCC/lcd.c | 7 ++----- demos/GNU-Linux-GCC/chcore.c | 2 +- demos/GNU-Linux-GCC/main.c | 2 +- demos/Win32-MinGW/chcore.c | 4 ++-- demos/Win32-MinGW/main.c | 4 ++-- 7 files changed, 10 insertions(+), 13 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index 0a78a3653..9fcf2a24a 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -51,7 +51,7 @@ * */ -#include +#include "ch.h" #include "lwip/opt.h" #include "lwip/mem.h" diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c index c64f2e47d..3d0c384d2 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c @@ -29,7 +29,7 @@ * @{ */ -#include +#include "ch.h" #include "lwip/opt.h" #include "lwip/arch.h" diff --git a/demos/AVR-ATmega128-GCC/lcd.c b/demos/AVR-ATmega128-GCC/lcd.c index eed0c896e..29a4d0c8c 100644 --- a/demos/AVR-ATmega128-GCC/lcd.c +++ b/demos/AVR-ATmega128-GCC/lcd.c @@ -17,11 +17,8 @@ along with this program. If not, see . */ -#include - -#include - -#include "board.h" +#include "ch.h" +#include "hal.h" #include "lcd.h" static void e_pulse(void) { diff --git a/demos/GNU-Linux-GCC/chcore.c b/demos/GNU-Linux-GCC/chcore.c index e7116edb4..6185b8f4e 100644 --- a/demos/GNU-Linux-GCC/chcore.c +++ b/demos/GNU-Linux-GCC/chcore.c @@ -28,7 +28,7 @@ * @{ */ -#include +#include "ch.h" static struct itimerval tempo; static bool_t pending = FALSE; diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c index 8d0d25879..07e16625c 100644 --- a/demos/GNU-Linux-GCC/main.c +++ b/demos/GNU-Linux-GCC/main.c @@ -19,7 +19,7 @@ #include -#include +#include "ch.h" static WORKING_AREA(waThread1, 2048); static msg_t Thread1(void *arg) { diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c index 8dcb3b9ad..f0555fab5 100644 --- a/demos/Win32-MinGW/chcore.c +++ b/demos/Win32-MinGW/chcore.c @@ -27,8 +27,8 @@ * @{ */ -#include -#include +#include "ch.h" +#include "hal.h" static LARGE_INTEGER nextcnt; static LARGE_INTEGER slice; diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 6a2b5367f..7f081c023 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -20,8 +20,8 @@ #include #include -#include -#include +#include "ch.h" +#include "hal.h" static uint32_t wdguard; static WORKING_AREA(wdarea, 2048); -- cgit v1.2.3 From a08b0561d6fea376c53e68f7479fe7a7e90b9ed6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 19:12:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1400 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/halconf.h | 81 ++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 demos/MSP430-MSP430x1611-GCC/halconf.h (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h new file mode 100644 index 000000000..2faba92d8 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ -- cgit v1.2.3 From 6d44bd72e3bd586dc84ff0fe65b1218173efa0a7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 8 Dec 2009 19:12:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1401 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 16 ++-- demos/Win32-MinGW/board.h | 23 +++++ demos/Win32-MinGW/chcore.c | 126 -------------------------- demos/Win32-MinGW/chcore.h | 211 -------------------------------------------- demos/Win32-MinGW/chtypes.h | 47 ---------- demos/Win32-MinGW/halconf.h | 96 ++++++++++++++++++++ demos/Win32-MinGW/main.c | 9 +- 7 files changed, 136 insertions(+), 392 deletions(-) create mode 100644 demos/Win32-MinGW/board.h delete mode 100644 demos/Win32-MinGW/chcore.c delete mode 100644 demos/Win32-MinGW/chcore.h delete mode 100644 demos/Win32-MinGW/chtypes.h create mode 100644 demos/Win32-MinGW/halconf.h (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 3552537ad..e690b7804 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -57,24 +57,26 @@ UADEFS = # Imported source files CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/Win32/platform.mk +include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk # List C source files here -SRC = ${KERNSRC} \ +SRC = ${PORTSRC} \ + ${KERNSRC} \ ${TESTSRC} \ - chcore.c \ - ${CHIBIOS}/os/io/serial.c \ - ${CHIBIOS}/os/io/platforms/Win32/serial_lld.c \ + ${HALSRC} \ + ${PLATFORMSRC} \ main.c # List ASM source files here ASRC = # List all user directories here -UINCDIR = $(KERNINC) $(TESTINC) \ - ${CHIBIOS}/os/io \ - ${CHIBIOS}/os/io/platforms/Win32 +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ + ${CHIBIOS}/os/various # List the user directory to look for the libraries here ULIBDIR = diff --git a/demos/Win32-MinGW/board.h b/demos/Win32-MinGW/board.h new file mode 100644 index 000000000..a6e056d58 --- /dev/null +++ b/demos/Win32-MinGW/board.h @@ -0,0 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#endif /* _BOARD_H_ */ diff --git a/demos/Win32-MinGW/chcore.c b/demos/Win32-MinGW/chcore.c deleted file mode 100644 index f0555fab5..000000000 --- a/demos/Win32-MinGW/chcore.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include - -#undef CDECL - -/** - * @addtogroup WIN32SIM_CORE - * @{ - */ - -#include "ch.h" -#include "hal.h" - -static LARGE_INTEGER nextcnt; -static LARGE_INTEGER slice; - -/* - * Simulated HW initialization. - */ -void InitCore(void) { - WSADATA wsaData; - - // Initialization. - if (WSAStartup(2, &wsaData) != 0) { - printf("Unable to locate a winsock DLL\n"); - exit(1); - } - - printf("Win32 ChibiOS/RT simulator\n\n"); - printf("Thread structure %d bytes\n", sizeof(Thread)); - if (!QueryPerformanceFrequency(&slice)) { - printf("QueryPerformanceFrequency() error"); - exit(1); - } - printf("Core Frequency %u Hz\n", (int)slice.LowPart); - slice.QuadPart /= CH_FREQUENCY; - QueryPerformanceCounter(&nextcnt); - nextcnt.QuadPart += slice.QuadPart; - - sdInit(); - fflush(stdout); -} - -/* - * Interrupt simulation. - */ -void ChkIntSources(void) { - LARGE_INTEGER n; - - if (sd_lld_interrupt_pending()) { - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); - return; - } - - // Interrupt Timer simulation (10ms interval). - QueryPerformanceCounter(&n); - if (n.QuadPart > nextcnt.QuadPart) { - nextcnt.QuadPart += slice.QuadPart; - chSysTimerHandlerI(); - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); - } -} - -/** - * Performs a context switch between two threads. - * @param otp the thread to be switched out - * @param ntp the thread to be switched in - */ -__attribute__((used)) -static void __dummy(Thread *otp, Thread *ntp) { - (void)otp; (void)ntp; - asm volatile (".globl @port_switch@8 \n\t" \ - "@port_switch@8: \n\t" \ - "push %ebp \n\t" \ - "push %esi \n\t" \ - "push %edi \n\t" \ - "push %ebx \n\t" \ - "movl %esp, 16(%ecx) \n\t" \ - "movl 16(%edx), %esp \n\t" \ - "pop %ebx \n\t" \ - "pop %edi \n\t" \ - "pop %esi \n\t" \ - "pop %ebp \n\t" \ - "ret"); -} - -/** - * Halts the system. In this implementation it just exits the simulation. - */ -__attribute__((fastcall)) -void port_halt(void) { - - exit(2); -} - -/** - * Threads return point, it just invokes @p chThdExit(). - */ -void threadexit(void) { - - asm volatile ("push %eax \n\t" \ - "call _chThdExit"); -} - -/** @} */ diff --git a/demos/Win32-MinGW/chcore.h b/demos/Win32-MinGW/chcore.h deleted file mode 100644 index fdeb245fb..000000000 --- a/demos/Win32-MinGW/chcore.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @addtogroup WIN32SIM_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/** - * Macro defining the a simulated architecture into Win32. - */ -#define CH_ARCHITECTURE_WIN32SIM - -/** - * Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "WIN32 Simulator" - -/** - * 32 bit stack alignment. - */ -typedef uint32_t stkalign_t; - -/** - * Generic x86 register. - */ -typedef void *regx86; - -/** - * Interrupt saved context. - * This structure represents the stack frame saved during a preemption-capable - * interrupt handler. - */ -struct extctx { -}; - -/** - * System saved context. - * @note In this demo the floating point registers are not saved. - */ -struct intctx { - regx86 ebx; - regx86 edi; - regx86 esi; - regx86 ebp; - regx86 eip; -}; - -/** - * Platform dependent part of the @p Thread structure. - * This structure usually contains just the saved stack pointer defined as a - * pointer to a @p intctx structure. - */ -struct context { - struct intctx volatile *esp; -}; - -#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) - -/** - * Platform dependent part of the @p chThdInit() API. - * This code usually setup the context switching frame represented by a - * @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - uint8_t *esp = (uint8_t *)workspace + wsize; \ - APUSH(esp, arg); \ - APUSH(esp, threadexit); \ - esp -= sizeof(struct intctx); \ - ((struct intctx *)esp)->eip = pf; \ - ((struct intctx *)esp)->ebx = 0; \ - ((struct intctx *)esp)->edi = 0; \ - ((struct intctx *)esp)->esi = 0; \ - ((struct intctx *)esp)->ebp = 0; \ - tp->p_ctx.esp = (struct intctx *)esp; \ -} - -/** - * Stack size for the system idle thread. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 256 -#endif - -/** - * Per-thread stack overhead for interrupts servicing, it is used in the - * calculation of the correct working area size. - * It requires stack space because the simulated "interrupt handlers" invoke - * Win32 APIs inside so it better have a lot of space. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 16384 -#endif - -/** - * Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - - /** - * Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(void *) * 2 + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * Macro used to allocate a thread working area aligned as both position and - * size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/** - * IRQ prologue code, inserted at the start of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * IRQ handler function declaration. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * Simulator initialization. - */ -#define port_init() InitCore() - -/** - * Does nothing in this simulator. - */ -#define port_lock() - -/** - * Does nothing in this simulator. - */ -#define port_unlock() - -/** - * Does nothing in this simulator. - */ -#define port_lock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_unlock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_disable() - -/** - * Does nothing in this simulator. - */ -#define port_suspend() - -/** - * Does nothing in this simulator. - */ -#define port_enable() - -/** - * In the simulator this does a polling pass on the simulated interrupt - * sources. - */ -#define port_wait_for_interrupt() ChkIntSources() - -#ifdef __cplusplus -extern "C" { -#endif - __attribute__((fastcall)) void port_switch(Thread *otp, Thread *ntp); - __attribute__((fastcall)) void port_halt(void); - void InitCore(void); - void ChkIntSources(void); - void threadexit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ diff --git a/demos/Win32-MinGW/chtypes.h b/demos/Win32-MinGW/chtypes.h deleted file mode 100644 index 354da269e..000000000 --- a/demos/Win32-MinGW/chtypes.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#define __need_ptrdiff_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -typedef int8_t bool_t; -typedef uint8_t tmode_t; -typedef uint8_t tstate_t; -typedef uint32_t tprio_t; -typedef int32_t msg_t; -typedef int32_t eventid_t; -typedef uint32_t eventmask_t; -typedef uint32_t systime_t; -typedef int32_t cnt_t; - -#define INLINE inline -#define PACK_STRUCT_STRUCT __attribute__((packed)) -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h new file mode 100644 index 000000000..a3d17a3c9 --- /dev/null +++ b/demos/Win32-MinGW/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 7f081c023..2b0c5ea15 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -290,7 +290,14 @@ static evhandler_t fhandlers[2] = { int main(void) { EventListener c1fel, c2fel; - // Startup ChibiOS/RT. + /* + * HAL initialization. + */ + halInit(); + + /* + * ChibiOS/RT initialization. + */ chSysInit(); sdStart(&SD1, NULL); -- cgit v1.2.3 From d939ef4cf5a4062d692262bca24abaf2314e4e85 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 9 Dec 2009 21:28:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1408 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 31c3c7a50..3b29983cb 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif -- cgit v1.2.3 From 2441aa72104fb7c01505947d8b774a182e84e83d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 9 Dec 2009 21:29:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1409 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 2 +- demos/ARM7-LPC214x-G++/chconf.h | 2 +- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 2 +- demos/ARM7-LPC214x-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F103-GCC/chconf.h | 2 +- demos/AVR-AT90CANx-GCC/chconf.h | 2 +- demos/AVR-ATmega128-GCC/chconf.h | 2 +- demos/GNU-Linux-GCC/chconf.h | 2 +- demos/MSP430-MSP430x1611-GCC/chconf.h | 2 +- demos/Win32-MinGW/chconf.h | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index b12b89b93..9b0cf833d 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 31c3c7a50..3b29983cb 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 31c3c7a50..3b29983cb 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h index fd2e6f6ad..460ee004a 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ b/demos/ARM7-LPC214x-GCC-minimal/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE FALSE #endif diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 31c3c7a50..3b29983cb 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index 31c3c7a50..3b29983cb 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 31c3c7a50..3b29983cb 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index f962e4c16..2a4916827 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index f962e4c16..2a4916827 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/GNU-Linux-GCC/chconf.h b/demos/GNU-Linux-GCC/chconf.h index dc3fcf69e..845ed5d9b 100644 --- a/demos/GNU-Linux-GCC/chconf.h +++ b/demos/GNU-Linux-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 7452a6778..aec56a4a7 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index cef71f8c5..ddd00b0f8 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -277,7 +277,7 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif -- cgit v1.2.3 From dea70dbc797e0936c2532ae55881437e06e169fa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Dec 2009 15:44:55 +0000 Subject: Added a small generic command line shell. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1411 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 3 +- demos/Win32-MinGW/main.c | 316 ++++++++++++++------------------------------- 2 files changed, 96 insertions(+), 223 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index e690b7804..76362dec1 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -21,7 +21,7 @@ CC = $(TRGT)gcc AS = $(TRGT)gcc -x assembler-with-cpp # List all default C defines here, like -D_DEBUG=1 -DDEFS = +DDEFS = -DSHELL_USE_IPRINTF=FALSE # List all default ASM defines here, like -D_DEBUG=1 DADEFS = @@ -69,6 +69,7 @@ SRC = ${PORTSRC} \ ${TESTSRC} \ ${HALSRC} \ ${PLATFORMSRC} \ + ${CHIBIOS}/os/various/shell.c \ main.c # List ASM source files here diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 2b0c5ea15..c2ead083e 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -17,53 +17,36 @@ along with this program. If not, see . */ -#include -#include - #include "ch.h" #include "hal.h" +#include "test.h" +#include "shell.h" -static uint32_t wdguard; -static WORKING_AREA(wdarea, 2048); - -static uint32_t cdguard; -static WORKING_AREA(cdarea, 2048); -static Thread *cdtp; - -static msg_t WatchdogThread(void *arg); -static msg_t ConsoleThread(void *arg); - -msg_t TestThread(void *p); +#define SHELL_WA_SIZE THD_WA_SIZE(4096) +#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) #define cprint(msg) chMsgSend(cdtp, (msg_t)msg) -/* - * Watchdog thread, it checks magic values located under the various stack - * areas. The system is halted if something is wrong. - */ -static msg_t WatchdogThread(void *arg) { +static Thread *cdtp; +static Thread *shelltp1; +static Thread *shelltp2; - (void)arg; - wdguard = 0xA51F2E3D; - cdguard = 0xA51F2E3D; - while (TRUE) { - if ((wdguard != 0xA51F2E3D) || - (cdguard != 0xA51F2E3D)) { - printf("Halted by watchdog"); - fflush(stdout); - chSysHalt(); - } - chThdSleep(50); - } - return 0; -} +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD1, + NULL +}; + +static const ShellConfig shell_cfg2 = { + (BaseChannel *)&SD2, + NULL +}; /* * Console print server done using synchronous messages. This makes the access * to the C printf() thread safe and the print operation atomic among threads. * In this example the message is the zero termitated string itself. */ -static msg_t ConsoleThread(void *arg) { +static msg_t console_thread(void *arg) { (void)arg; while (!chThdShouldTerminate()) { @@ -74,221 +57,87 @@ static msg_t ConsoleThread(void *arg) { return 0; } -static void PrintLineSD(SerialDriver *sd, char *msg) { - - while (*msg) - sdPut(sd, *msg++); -} - -static bool_t GetLineFDD(SerialDriver *sd, char *line, int size) { - char *p = line; - - while (TRUE) { - short c = chIQGet(&sd->d2.iqueue); - if (c < 0) - return TRUE; - if (c == 4) { - PrintLineSD(sd, "^D\r\n"); - return TRUE; - } - if (c == 8) { - if (p != line) { - sdPut(sd, (uint8_t)c); - sdPut(sd, 0x20); - sdPut(sd, (uint8_t)c); - p--; - } - continue; - } - if (c == '\r') { - PrintLineSD(sd, "\r\n"); - *p = 0; - return FALSE; - } - if (c < 0x20) - continue; - if (p < line + size - 1) { - sdPut(sd, (uint8_t)c); - *p++ = (uint8_t)c; - } - } -} - -/* - * Example thread, not much to see here. It simulates the CTRL-C but there - * are no real signals involved. +/** + * @brief Shell termination handler. + * + * @param[in] id event id. */ -static msg_t HelloWorldThread(void *arg) { - int i; - short c; - SerialDriver *sd = (SerialDriver *)arg; - - for (i = 0; i < 10; i++) { +static void termination_handler(eventid_t id) { - PrintLineSD(sd, "Hello World\r\n"); - c = sdGetTimeout(sd, 333); - switch (c) { - case Q_TIMEOUT: - continue; - case Q_RESET: - return 1; - case 3: - PrintLineSD(sd, "^C\r\n"); - return 0; - default: - chThdSleep(333); - } + (void)id; + if (shelltp1 && chThdTerminated(shelltp1)) { + chThdWait(shelltp1); + shelltp1 = NULL; + cprint("Init: shell on SD1 terminated\n"); + chSysLock(); + chOQResetI(&SD1.d2.oqueue); + chSysUnlock(); } - return 0; -} - -static bool_t checkend(SerialDriver *sd) { - - char * lp = strtok(NULL, " \009"); /* It is not thread safe but this is a demo.*/ - if (lp) { - PrintLineSD(sd, lp); - PrintLineSD(sd, " ?\r\n"); - return TRUE; + if (shelltp2 && chThdTerminated(shelltp2)) { + chThdWait(shelltp2); + shelltp2 = NULL; + cprint("Init: shell on SD2 terminated\n"); + chSysLock(); + chOQResetI(&SD2.d2.oqueue); + chSysUnlock(); } - return FALSE; } -/* - * Simple command shell thread, the argument is the serial line for the - * standard input and output. It recognizes few simple commands. +/** + * @brief SD1 status change handler. + * + * @param[in] id event id. */ -static msg_t ShellThread(void *arg) { - SerialDriver *sd = (SerialDriver *)arg; - char *lp, line[64]; - Thread *tp; - WORKING_AREA(tarea, 2048); - - chSysLock(); - chIQResetI(&sd->d2.iqueue); - chOQResetI(&sd->d2.oqueue); - chSysUnlock(); - PrintLineSD(sd, "ChibiOS/RT Command Shell\r\n\n"); - while (TRUE) { - PrintLineSD(sd, "ch> "); - if (GetLineFDD(sd, line, sizeof(line))) { - PrintLineSD(sd, "\nlogout"); - break; - } - lp = strtok(line, " \009"); // Note: not thread safe but it is just a demo. - if (lp) { - if ((stricmp(lp, "help") == 0) || - (stricmp(lp, "h") == 0) || - (stricmp(lp, "?") == 0)) { - if (checkend(sd)) - continue; - PrintLineSD(sd, "Commands:\r\n"); - PrintLineSD(sd, " help,h,? - This help\r\n"); - PrintLineSD(sd, " exit - Logout from ChibiOS/RT\r\n"); - PrintLineSD(sd, " time - Prints the system timer value\r\n"); - PrintLineSD(sd, " hello - Runs the Hello World demo thread\r\n"); - PrintLineSD(sd, " test - Runs the System Test thread\r\n"); - } - else if (stricmp(lp, "exit") == 0) { - if (checkend(sd)) - continue; - PrintLineSD(sd, "\nlogout"); - break; - } - else if (stricmp(lp, "time") == 0) { - if (checkend(sd)) - continue; - sprintf(line, "Time: %d\r\n", chTimeNow()); - PrintLineSD(sd, line); - } - else if (stricmp(lp, "hello") == 0) { - if (checkend(sd)) - continue; - tp = chThdCreateStatic(tarea, sizeof(tarea), - NORMALPRIO, HelloWorldThread, sd); - if (chThdWait(tp)) - break; // Lost connection while executing the hello thread. - } - else if (stricmp(lp, "test") == 0) { - if (checkend(sd)) - continue; - tp = chThdCreateStatic(tarea, sizeof(tarea), - NORMALPRIO, TestThread, arg); - if (chThdWait(tp)) - break; // Lost connection while executing the hello thread. - } - else { - PrintLineSD(sd, lp); - PrintLineSD(sd, " ?\r\n"); - } - } - } - return 0; -} - -static WORKING_AREA(s1area, 4096); -static Thread *s1; -EventListener s1tel; - -static void COM1Handler(eventid_t id) { +static void sd1_handler(eventid_t id) { sdflags_t flags; (void)id; - if (s1 && chThdTerminated(s1)) { - s1 = NULL; - cprint("Init: disconnection on SD1\n"); - } flags = sdGetAndClearFlags(&SD1); - if ((flags & SD_CONNECTED) && (s1 == NULL)) { + if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { cprint("Init: connection on SD1\n"); - s1 = chThdInit(s1area, sizeof(s1area), - NORMALPRIO, ShellThread, &SD1); - chEvtRegister(chThdGetExitEventSource(s1), &s1tel, 0); - chThdResume(s1); + shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); } - if ((flags & SD_DISCONNECTED) && (s1 != NULL)) { + if (flags & SD_DISCONNECTED) { + cprint("Init: disconnection on SD1\n"); chSysLock(); chIQResetI(&SD1.d2.iqueue); chSysUnlock(); } } -static WORKING_AREA(s2area, 4096); -static Thread *s2; -EventListener s2tel; - -static void COM2Handler(eventid_t id) { +/** + * @brief SD2 status change handler. + * + * @param[in] id event id. + */ +static void sd2_handler(eventid_t id) { sdflags_t flags; (void)id; - if (s2 && chThdTerminated(s2)) { - s2 = NULL; - cprint("Init: disconnection on SD2\n"); - } flags = sdGetAndClearFlags(&SD2); - if ((flags & SD_CONNECTED) && (s2 == NULL)) { + if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { cprint("Init: connection on SD2\n"); - s2 = chThdInit(s2area, sizeof(s1area), - NORMALPRIO, ShellThread, &SD2); - chEvtRegister(chThdGetExitEventSource(s2), &s2tel, 1); - chThdResume(s2); + shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); } - if ((flags & SD_DISCONNECTED) && (s2 != NULL)) { + if (flags & SD_DISCONNECTED) { + cprint("Init: disconnection on SD2\n"); chSysLock(); chIQResetI(&SD2.d2.iqueue); chSysUnlock(); } } -static evhandler_t fhandlers[2] = { - COM1Handler, - COM2Handler +static evhandler_t fhandlers[] = { + termination_handler, + sd1_handler, + sd2_handler }; /*------------------------------------------------------------------------* - * Simulator main, start here your threads, examples inside. * + * Simulator main. * *------------------------------------------------------------------------*/ int main(void) { - EventListener c1fel, c2fel; + EventListener sd1fel, sd2fel, tel; /* * HAL initialization. @@ -300,22 +149,45 @@ int main(void) { */ chSysInit(); + /* + * Serial ports (simulated) initialization. + */ sdStart(&SD1, NULL); sdStart(&SD2, NULL); - chThdCreateStatic(wdarea, sizeof(wdarea), NORMALPRIO + 2, WatchdogThread, NULL); - cdtp = chThdCreateStatic(cdarea, sizeof(cdarea), NORMALPRIO + 1, ConsoleThread, NULL); + /* + * Shell manager initialization. + */ + shellInit(); + chEvtRegister(&shell_terminated, &tel, 0); + + /* + * Console thread started. + */ + cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, + console_thread, NULL); - cprint("Console service started on SD1, SD2\n"); + /* + * Initializing connection/disconnection events. + */ + cprint("Shell service started on SD1, SD2\n"); cprint(" - Listening for connections on SD1\n"); - sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.d2.sevent, &c1fel, 0); + (void) sdGetAndClearFlags(&SD1); + chEvtRegister(&SD1.d2.sevent, &sd1fel, 1); cprint(" - Listening for connections on SD2\n"); - sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.d2.sevent, &c2fel, 1); + (void) sdGetAndClearFlags(&SD2); + chEvtRegister(&SD2.d2.sevent, &sd2fel, 2); + + /* + * Events servicing loop. + */ while (!chThdShouldTerminate()) chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); - chEvtUnregister(&SD1.d2.sevent, &c2fel); // Never invoked but this is an example... - chEvtUnregister(&SD2.d2.sevent, &c1fel); // Never invoked but this is an example... + + /* + * Clean simulator exit. + */ + chEvtUnregister(&SD1.d2.sevent, &sd1fel); + chEvtUnregister(&SD2.d2.sevent, &sd2fel); return 0; } -- cgit v1.2.3 From 4bb9e7735d4a84e6ddee2b5778906e6cd54db577 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Dec 2009 21:05:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1412 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chconf.h | 2 +- demos/Win32-MinGW/main.c | 24 ++++++++++++++++++++++-- 2 files changed, 23 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index ddd00b0f8..34575541a 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -80,7 +80,7 @@ * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0x20000 +#define CH_MEMCORE_SIZE 0x40000 #endif /*===========================================================================*/ diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index c2ead083e..22ea086c3 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -24,6 +24,7 @@ #define SHELL_WA_SIZE THD_WA_SIZE(4096) #define CONSOLE_WA_SIZE THD_WA_SIZE(4096) +#define TEST_WA_SIZE THD_WA_SIZE(4096) #define cprint(msg) chMsgSend(cdtp, (msg_t)msg) @@ -31,14 +32,33 @@ static Thread *cdtp; static Thread *shelltp1; static Thread *shelltp2; +void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: test"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + chThdWait(tp); +// TestThread(chp); +} + +static const ShellCommand commands[] = { + {"test", cmd_test}, + {NULL, NULL} +}; + static const ShellConfig shell_cfg1 = { (BaseChannel *)&SD1, - NULL + commands }; static const ShellConfig shell_cfg2 = { (BaseChannel *)&SD2, - NULL + commands }; /* -- cgit v1.2.3 From d980d7e3e434af2cd17ee2b04deaab65164204ce Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Dec 2009 22:26:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1413 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/chconf.h | 6 +----- demos/Win32-MinGW/main.c | 5 ++++- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 34575541a..2c3a29a30 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -80,7 +80,7 @@ * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0x40000 +#define CH_MEMCORE_SIZE 0x20000 #endif /*===========================================================================*/ @@ -419,8 +419,6 @@ #define THREAD_EXT_FIELDS \ struct { \ /* Add threads custom fields here.*/ \ - /* The thread termination \p EventSource.*/ \ - EventSource p_exitesource; \ }; #endif @@ -434,7 +432,6 @@ struct { \ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ /* Add threads initialization code here.*/ \ - chEvtInit(&tp->p_exitesource); \ } #endif @@ -449,7 +446,6 @@ struct { \ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ /* Add threads finalization code here.*/ \ - chEvtBroadcastI(&currp->p_exitesource); \ } #endif diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 22ea086c3..140f3bd79 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -42,8 +42,11 @@ void cmd_test(BaseChannel *chp, int argc, char *argv[]) { } tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), TestThread, chp); + if (tp == NULL) { + shellPrintLine(chp, "out of memory"); + return; + } chThdWait(tp); -// TestThread(chp); } static const ShellCommand commands[] = { -- cgit v1.2.3 From 0f8d30486bffb71cd431e67084fcc502411236b9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 11 Dec 2009 16:15:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1417 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/main.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'demos') diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 140f3bd79..01ca7cad9 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -91,6 +91,7 @@ static void termination_handler(eventid_t id) { if (shelltp1 && chThdTerminated(shelltp1)) { chThdWait(shelltp1); shelltp1 = NULL; + chThdSleepMilliseconds(10); cprint("Init: shell on SD1 terminated\n"); chSysLock(); chOQResetI(&SD1.d2.oqueue); @@ -99,6 +100,7 @@ static void termination_handler(eventid_t id) { if (shelltp2 && chThdTerminated(shelltp2)) { chThdWait(shelltp2); shelltp2 = NULL; + chThdSleepMilliseconds(10); cprint("Init: shell on SD2 terminated\n"); chSysLock(); chOQResetI(&SD2.d2.oqueue); -- cgit v1.2.3 From c46634d324e3b2f4abcd6332b06a4545fa74f428 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Dec 2009 13:46:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1431 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 9 +++-- demos/ARMCM3-STM32F103-GCC/board.c | 49 --------------------------- demos/ARMCM3-STM32F103-GCC/board.h | 67 ------------------------------------- 3 files changed, 6 insertions(+), 119 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-GCC/board.c delete mode 100644 demos/ARMCM3-STM32F103-GCC/board.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 87293f6f8..afd458186 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -57,8 +57,9 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/boards/OLIMEX_STM32_P103/board.mk include ${CHIBIOS}/os/hal/platforms/STM32/platform.mk +include ${CHIBIOS}/os/hal/hal.mk include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -70,9 +71,10 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${HALSRC} \ ${PLATFORMSRC} \ + ${BOARDSRC} \ ${CHIBIOS}/os/various/evtimer.c \ ${CHIBIOS}/os/various/syscalls.c \ - board.c main.c + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -102,7 +104,8 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) ${BOARDINC} \ ${CHIBIOS}/os/various # diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c deleted file mode 100644 index 8c33354ae..000000000 --- a/demos/ARMCM3-STM32F103-GCC/board.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - stm32_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h deleted file mode 100644 index 588ea3c5d..000000000 --- a/demos/ARMCM3-STM32F103-GCC/board.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Board frequencies. - */ -#define LSECLK 32768 -#define HSECLK 8000000 -#define HSICLK 8000000 - -/* - * IO pins assignments. - */ -#define GPIOA_BUTTON 0 -#define GPIOA_SPI1NSS 4 - -#define GPIOB_SPI2NSS 12 - -#define GPIOC_MMCWP 6 -#define GPIOC_MMCCP 7 -#define GPIOC_CANCNTL 10 -#define GPIOC_DISC 11 -#define GPIOC_LED 12 - -/* - * All inputs with pullups unless otherwise specified. - */ -#define VAL_GPIOACRL 0x88888884 // PA0:FI -#define VAL_GPIOACRH 0x88888888 -#define VAL_GPIOAODR 0xFFFFFFFF - -#define VAL_GPIOBCRL 0x88883888 // PB3:PP -#define VAL_GPIOBCRH 0x88888888 -#define VAL_GPIOBODR 0xFFFFFFFF - -#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI -#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP -#define VAL_GPIOCODR 0xFFFFFFFF - -#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI -#define VAL_GPIODCRH 0x88888888 -#define VAL_GPIODODR 0xFFFFFFFF - -#define VAL_GPIOECRL 0x88888888 -#define VAL_GPIOECRH 0x88888888 -#define VAL_GPIOEODR 0xFFFFFFFF - -#endif /* _BOARD_H_ */ -- cgit v1.2.3 From d844d13504de6523f6a5f77cd9ec8604584bdefe Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Dec 2009 13:55:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1433 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 9 +++-- demos/ARMCM3-STM32F103-FATFS-GCC/board.c | 49 ---------------------- demos/ARMCM3-STM32F103-FATFS-GCC/board.h | 67 ------------------------------- 3 files changed, 6 insertions(+), 119 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/board.c delete mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/board.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 95989b6a2..121d72b9f 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -57,8 +57,9 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/boards/OLIMEX_STM32_P103/board.mk include ${CHIBIOS}/os/hal/platforms/STM32/platform.mk +include ${CHIBIOS}/os/hal/hal.mk include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk @@ -71,10 +72,11 @@ CSRC = ${PORTSRC} \ ${TESTSRC} \ ${HALSRC} \ ${PLATFORMSRC} \ + ${BOARDSRC} \ ${FATFSSRC} \ ${CHIBIOS}/os/various/evtimer.c \ ${CHIBIOS}/os/various/syscalls.c \ - board.c main.c + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -104,7 +106,8 @@ TCPPSRC = ASMSRC = $(PORTASM) \ ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) ${BOARDINC} \ $(FATFSINC) \ ${CHIBIOS}/os/various diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c b/demos/ARMCM3-STM32F103-FATFS-GCC/board.c deleted file mode 100644 index 8c33354ae..000000000 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - stm32_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h b/demos/ARMCM3-STM32F103-FATFS-GCC/board.h deleted file mode 100644 index 588ea3c5d..000000000 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/board.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Board frequencies. - */ -#define LSECLK 32768 -#define HSECLK 8000000 -#define HSICLK 8000000 - -/* - * IO pins assignments. - */ -#define GPIOA_BUTTON 0 -#define GPIOA_SPI1NSS 4 - -#define GPIOB_SPI2NSS 12 - -#define GPIOC_MMCWP 6 -#define GPIOC_MMCCP 7 -#define GPIOC_CANCNTL 10 -#define GPIOC_DISC 11 -#define GPIOC_LED 12 - -/* - * All inputs with pullups unless otherwise specified. - */ -#define VAL_GPIOACRL 0x88888884 // PA0:FI -#define VAL_GPIOACRH 0x88888888 -#define VAL_GPIOAODR 0xFFFFFFFF - -#define VAL_GPIOBCRL 0x88883888 // PB3:PP -#define VAL_GPIOBCRH 0x88888888 -#define VAL_GPIOBODR 0xFFFFFFFF - -#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI -#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP -#define VAL_GPIOCODR 0xFFFFFFFF - -#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI -#define VAL_GPIODCRH 0x88888888 -#define VAL_GPIODODR 0xFFFFFFFF - -#define VAL_GPIOECRL 0x88888888 -#define VAL_GPIOECRH 0x88888888 -#define VAL_GPIOEODR 0xFFFFFFFF - -#endif /* _BOARD_H_ */ -- cgit v1.2.3 From 0b598c6990b28aba2eede3ca1208c30fe4dc62fe Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Dec 2009 14:36:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1434 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 35 ++++++----- demos/ARM7-AT91SAM7X-GCC/board.c | 112 --------------------------------- demos/ARM7-AT91SAM7X-GCC/board.h | 85 ------------------------- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 45 ++++++------- demos/ARM7-AT91SAM7X-LWIP-GCC/board.c | 112 --------------------------------- demos/ARM7-AT91SAM7X-LWIP-GCC/board.h | 85 ------------------------- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 58 ++++++++--------- demos/ARM7-AT91SAM7X-UIP-GCC/board.c | 112 --------------------------------- demos/ARM7-AT91SAM7X-UIP-GCC/board.h | 85 ------------------------- 9 files changed, 73 insertions(+), 656 deletions(-) delete mode 100644 demos/ARM7-AT91SAM7X-GCC/board.c delete mode 100644 demos/ARM7-AT91SAM7X-GCC/board.h delete mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/board.c delete mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/board.h delete mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/board.c delete mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/board.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index 0dd999e7a..e43fdf7e8 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -44,20 +44,22 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/AT91SAM7/platform.mk -include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - board.c main.c +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -85,11 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 # # Project, sources and paths @@ -177,4 +180,4 @@ ULIBS = # End of user defines ############################################################################## -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-GCC/board.c b/demos/ARM7-AT91SAM7X-GCC/board.c deleted file mode 100644 index fab8b0338..000000000 --- a/demos/ARM7-AT91SAM7X-GCC/board.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -/* - * SYS IRQ handling here. - */ -static CH_IRQ_HANDLER(SYSIrqHandler) { - - CH_IRQ_PROLOGUE(); - - if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { - (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - } - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - /* Watchdog disabled.*/ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - at91sam7_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * LCD pins setup. - */ - palClearPad(IOPORT2, PIOB_LCD_BL); - palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); - - palSetPad(IOPORT1, PIOA_LCD_RESET); - palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); - - /* - * Joystick and buttons setup. - */ - palSetGroupMode(IOPORT1, - PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | - PIOA_B4_MASK | PIOA_B5_MASK, - PAL_MODE_INPUT); - palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); - - /* - * MMC/SD slot setup. - */ - palSetGroupMode(IOPORT2, - PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, - PAL_MODE_INPUT); - - /* - * PIT Initialization. - */ - AIC_ConfigureIT(AT91C_ID_SYS, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), - SYSIrqHandler); - AIC_EnableIT(AT91C_ID_SYS); - AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; - AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - - /* - * RTS/CTS pins enabled for USART0 only. - */ - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; - AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARM7-AT91SAM7X-GCC/board.h b/demos/ARM7-AT91SAM7X-GCC/board.h deleted file mode 100644 index c0b428561..000000000 --- a/demos/ARM7-AT91SAM7X-GCC/board.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Select your platform by modifying the following line. - */ -#if !defined(SAM7_PLATFORM) -#define SAM7_PLATFORM SAM7X256 -#endif - -#include "at91sam7.h" - -#define BOARD_OLIMEX_SAM7_EX256 - -#define CLK 18432000 -#define MCK 48054857 - -/* - * Initial I/O setup. - */ -#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOA_OSR 0x00000000 /* Direction. */ -#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ - -#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOB_OSR 0x00000000 /* Direction. */ -#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ - -/* - * I/O definitions. - */ -#define PIOA_LCD_RESET 2 -#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) -#define PIOA_B1 7 -#define PIOA_B1_MASK (1 << PIOA_B1) -#define PIOA_B2 8 -#define PIOA_B2_MASK (1 << PIOA_B2) -#define PIOA_B3 9 -#define PIOA_B3_MASK (1 << PIOA_B3) -#define PIOA_B4 14 -#define PIOA_B4_MASK (1 << PIOA_B4) -#define PIOA_B5 15 -#define PIOA_B5_MASK (1 << PIOA_B5) -#define PIOA_USB_PUP 25 -#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) -#define PIOA_USB_PR 26 -#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) - -#define PIOB_PHY_PD 18 -#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) -#define PIOB_AUDIO_OUT 19 -#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) -#define PIOB_LCD_BL 20 -#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) -#define PIOB_MMC_WP 22 -#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) -#define PIOB_MMC_CP 23 -#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) -#define PIOB_SW1 24 -#define PIOB_SW1_MASK (1 << PIOB_SW1) -#define PIOB_SW2 25 -#define PIOB_SW2_MASK (1 << PIOB_SW2) -#define PIOB_PHY_IRQ 26 -#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) - -#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 7255f4f3e..f51cf1778 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -44,29 +44,31 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/AT91SAM7/platform.mk -include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk include ./lwip/lwip.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${LWNETIFSRC} \ - ${LWCORESRC} \ - ${LWIPV4SRC} \ - ${LWAPISRC} \ - ${CHIBIOS}/os/various/evtimer.c \ +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(LWNETIFSRC) \ + $(LWCORESRC) \ + $(LWIPV4SRC) \ + $(LWAPISRC) \ + $(CHIBIOS)/os/various/evtimer.c \ ./lwip/arch/sys_arch.c \ ./lwip/lwipthread.c \ ./web/web.c \ - board.c main.c + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -94,11 +96,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) $(LWINC) \ - ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 \ +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 \ ./lwip # @@ -187,4 +190,4 @@ ULIBS = # End of user defines ############################################################################## -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c deleted file mode 100644 index fab8b0338..000000000 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -/* - * SYS IRQ handling here. - */ -static CH_IRQ_HANDLER(SYSIrqHandler) { - - CH_IRQ_PROLOGUE(); - - if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { - (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - } - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - /* Watchdog disabled.*/ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - at91sam7_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * LCD pins setup. - */ - palClearPad(IOPORT2, PIOB_LCD_BL); - palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); - - palSetPad(IOPORT1, PIOA_LCD_RESET); - palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); - - /* - * Joystick and buttons setup. - */ - palSetGroupMode(IOPORT1, - PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | - PIOA_B4_MASK | PIOA_B5_MASK, - PAL_MODE_INPUT); - palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); - - /* - * MMC/SD slot setup. - */ - palSetGroupMode(IOPORT2, - PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, - PAL_MODE_INPUT); - - /* - * PIT Initialization. - */ - AIC_ConfigureIT(AT91C_ID_SYS, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), - SYSIrqHandler); - AIC_EnableIT(AT91C_ID_SYS); - AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; - AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - - /* - * RTS/CTS pins enabled for USART0 only. - */ - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; - AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h deleted file mode 100644 index c0b428561..000000000 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/board.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Select your platform by modifying the following line. - */ -#if !defined(SAM7_PLATFORM) -#define SAM7_PLATFORM SAM7X256 -#endif - -#include "at91sam7.h" - -#define BOARD_OLIMEX_SAM7_EX256 - -#define CLK 18432000 -#define MCK 48054857 - -/* - * Initial I/O setup. - */ -#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOA_OSR 0x00000000 /* Direction. */ -#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ - -#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOB_OSR 0x00000000 /* Direction. */ -#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ - -/* - * I/O definitions. - */ -#define PIOA_LCD_RESET 2 -#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) -#define PIOA_B1 7 -#define PIOA_B1_MASK (1 << PIOA_B1) -#define PIOA_B2 8 -#define PIOA_B2_MASK (1 << PIOA_B2) -#define PIOA_B3 9 -#define PIOA_B3_MASK (1 << PIOA_B3) -#define PIOA_B4 14 -#define PIOA_B4_MASK (1 << PIOA_B4) -#define PIOA_B5 15 -#define PIOA_B5_MASK (1 << PIOA_B5) -#define PIOA_USB_PUP 25 -#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) -#define PIOA_USB_PR 26 -#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) - -#define PIOB_PHY_PD 18 -#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) -#define PIOB_AUDIO_OUT 19 -#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) -#define PIOB_LCD_BL 20 -#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) -#define PIOB_MMC_WP 22 -#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) -#define PIOB_MMC_CP 23 -#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) -#define PIOB_SW1 24 -#define PIOB_SW1_MASK (1 << PIOB_SW1) -#define PIOB_SW2 25 -#define PIOB_SW2_MASK (1 << PIOB_SW2) -#define PIOB_PHY_IRQ 26 -#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) - -#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index 575a758af..419506193 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -44,34 +44,35 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/AT91SAM7/platform.mk -include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # List of the required uIP source files. -USRC = ${CHIBIOS}/ext/uip-1.0/uip/uip_arp.c \ - ${CHIBIOS}/ext/uip-1.0/uip/psock.c \ - ${CHIBIOS}/ext/uip-1.0/uip/uip.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/http-strings.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-fs.c \ - ${CHIBIOS}/ext/uip-1.0/apps/webserver/httpd-cgi.c +USRC = $(CHIBIOS)/ext/uip-1.0/uip/uip_arp.c \ + $(CHIBIOS)/ext/uip-1.0/uip/psock.c \ + $(CHIBIOS)/ext/uip-1.0/uip/uip.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/http-strings.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd-fs.c \ + $(CHIBIOS)/ext/uip-1.0/apps/webserver/httpd-cgi.c # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${USRC} \ - ${CHIBIOS}/os/various/syscalls.c \ - ${CHIBIOS}/os/various/evtimer.c \ +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(USRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/various/evtimer.c \ web/webthread.c \ - board.c main.c -# ${CHIBIOS}/os/io/platforms/AT91SAM7/sam7x_emac.c \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -99,12 +100,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) $(LWINC) \ - ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/AT91SAM7 \ - ./web ${CHIBIOS}/ext/uip-1.0/uip ${CHIBIOS}/ext/uip-1.0/apps/webserver +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 \ + ./web $(CHIBIOS)/ext/uip-1.0/uip $(CHIBIOS)/ext/uip-1.0/apps/webserver # # Project, sources and paths @@ -192,4 +194,4 @@ ULIBS = # End of user defines ############################################################################## -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c b/demos/ARM7-AT91SAM7X-UIP-GCC/board.c deleted file mode 100644 index c55b5869e..000000000 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/board.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -/* - * SYS IRQ handling here. - */ -static CH_IRQ_HANDLER(SYSIrqHandler) { - - CH_IRQ_PROLOGUE(); - - if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { - (void) AT91C_BASE_PITC->PITC_PIVR; - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - } - AT91C_BASE_AIC->AIC_EOICR = 0; - - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - /* Watchdog disabled.*/ - AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - at91sam7_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * LCD pins setup. - */ - palClearPad(IOPORT2, PIOB_LCD_BL); - palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL); - - palSetPad(IOPORT1, PIOA_LCD_RESET); - palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL); - - /* - * Joystick and buttons setup. - */ - palSetGroupMode(IOPORT1, - PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK | - PIOA_B4_MASK | PIOA_B5_MASK, - PAL_MODE_INPUT); - palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, PAL_MODE_INPUT); - - /* - * MMC/SD slot setup. - */ - palSetGroupMode(IOPORT2, - PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK, - PAL_MODE_INPUT); - - /* - * PIT Initialization. - */ - AIC_ConfigureIT(AT91C_ID_SYS, - AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1), - SYSIrqHandler); - AIC_EnableIT(AT91C_ID_SYS); - AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1; - AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - - /* - * RTS/CTS pins enabled for USART0 only. - */ - AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_RTS0 | AT91C_PA4_CTS0; - AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4; - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/board.h b/demos/ARM7-AT91SAM7X-UIP-GCC/board.h deleted file mode 100644 index c0b428561..000000000 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/board.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Select your platform by modifying the following line. - */ -#if !defined(SAM7_PLATFORM) -#define SAM7_PLATFORM SAM7X256 -#endif - -#include "at91sam7.h" - -#define BOARD_OLIMEX_SAM7_EX256 - -#define CLK 18432000 -#define MCK 48054857 - -/* - * Initial I/O setup. - */ -#define VAL_PIOA_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOA_OSR 0x00000000 /* Direction. */ -#define VAL_PIOA_PUSR 0xFFFFFFFF /* Pull-up. */ - -#define VAL_PIOB_ODSR 0x00000000 /* Output data. */ -#define VAL_PIOB_OSR 0x00000000 /* Direction. */ -#define VAL_PIOB_PUSR 0xFFFFFFFF /* Pull-up. */ - -/* - * I/O definitions. - */ -#define PIOA_LCD_RESET 2 -#define PIOA_LCD_RESET_MASK (1 << PIOA_LCD_RESET) -#define PIOA_B1 7 -#define PIOA_B1_MASK (1 << PIOA_B1) -#define PIOA_B2 8 -#define PIOA_B2_MASK (1 << PIOA_B2) -#define PIOA_B3 9 -#define PIOA_B3_MASK (1 << PIOA_B3) -#define PIOA_B4 14 -#define PIOA_B4_MASK (1 << PIOA_B4) -#define PIOA_B5 15 -#define PIOA_B5_MASK (1 << PIOA_B5) -#define PIOA_USB_PUP 25 -#define PIOA_USB_PUP_MASK (1 << PIOA_USB_PUP) -#define PIOA_USB_PR 26 -#define PIOA_USB_PR_MASK (1 << PIOA_USB_PR) - -#define PIOB_PHY_PD 18 -#define PIOB_PHY_PD_MASK (1 << PIOB_PHY_PD) -#define PIOB_AUDIO_OUT 19 -#define PIOB_AUDIO_OUT_MASK (1 << PIOB_AUDIO_OUT) -#define PIOB_LCD_BL 20 -#define PIOB_LCD_BL_MASK (1 << PIOB_LCD_BL) -#define PIOB_MMC_WP 22 -#define PIOB_MMC_WP_MASK (1 << PIOB_MMC_WP) -#define PIOB_MMC_CP 23 -#define PIOB_MMC_CP_MASK (1 << PIOB_MMC_CP) -#define PIOB_SW1 24 -#define PIOB_SW1_MASK (1 << PIOB_SW1) -#define PIOB_SW2 25 -#define PIOB_SW2_MASK (1 << PIOB_SW2) -#define PIOB_PHY_IRQ 26 -#define PIOB_PHY_IRQ_MASK (1 << PIOB_PHY_IRQ) - -#endif /* _BOARD_H_ */ -- cgit v1.2.3 From 901489dd3819834f615d48ee5e50880d6815500e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Dec 2009 14:39:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1435 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 46 +++++++++++++++---------------- demos/ARMCM3-STM32F103-GCC/Makefile | 42 ++++++++++++++-------------- 2 files changed, 44 insertions(+), 44 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 121d72b9f..a4822a4c7 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -57,25 +57,25 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/boards/OLIMEX_STM32_P103/board.mk -include ${CHIBIOS}/os/hal/platforms/STM32/platform.mk -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk -include ${CHIBIOS}/ext/fatfs/fatfs.mk +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCM3/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk +include $(CHIBIOS)/ext/fatfs/fatfs.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${BOARDSRC} \ - ${FATFSSRC} \ - ${CHIBIOS}/os/various/evtimer.c \ - ${CHIBIOS}/os/various/syscalls.c \ +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -104,12 +104,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) ${BOARDINC} \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(FATFSINC) \ - ${CHIBIOS}/os/various + $(CHIBIOS)/os/various # # Project, sources and paths @@ -198,10 +198,10 @@ ULIBS = ############################################################################## ifeq ($(USE_FWLIB),yes) - include ${CHIBIOS}/ext/stm32lib/stm32lib.mk - CSRC += ${STM32SRC} - INCDIR += ${STM32INC} + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index afd458186..fd97754ff 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -57,23 +57,23 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/boards/OLIMEX_STM32_P103/board.mk -include ${CHIBIOS}/os/hal/platforms/STM32/platform.mk -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/ports/GCC/ARMCM3/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCM3/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${BOARDSRC} \ - ${CHIBIOS}/os/various/evtimer.c \ - ${CHIBIOS}/os/various/syscalls.c \ +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -102,11 +102,11 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) ${BOARDINC} \ - ${CHIBIOS}/os/various + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various # # Project, sources and paths @@ -195,10 +195,10 @@ ULIBS = ############################################################################## ifeq ($(USE_FWLIB),yes) - include ${CHIBIOS}/ext/stm32lib/stm32lib.mk - CSRC += ${STM32SRC} - INCDIR += ${STM32INC} + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk -- cgit v1.2.3 From 1b3389efe138899953b586965b54457542df67cd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Dec 2009 15:05:45 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1436 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/Makefile | 33 ++++++++-------- demos/MSP430-MSP430x1611-GCC/board.c | 54 -------------------------- demos/MSP430-MSP430x1611-GCC/board.h | 71 ----------------------------------- 3 files changed, 18 insertions(+), 140 deletions(-) delete mode 100644 demos/MSP430-MSP430x1611-GCC/board.c delete mode 100644 demos/MSP430-MSP430x1611-GCC/board.h (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/Makefile b/demos/MSP430-MSP430x1611-GCC/Makefile index 97de20466..647080524 100644 --- a/demos/MSP430-MSP430x1611-GCC/Makefile +++ b/demos/MSP430-MSP430x1611-GCC/Makefile @@ -40,20 +40,22 @@ LDSCRIPT = mspgcc/msp430x1611.x # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/MSP430/platform.mk -include ${CHIBIOS}/os/ports/GCC/MSP430/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_MSP430_P1611/board.mk +include $(CHIBIOS)/os/hal/platforms/MSP430/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/MSP430/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # C sources here. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/various/evtimer.c \ - board.c main.c +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + main.c # C++ sources here. CPPSRC = @@ -61,8 +63,9 @@ CPPSRC = # List ASM source files here ASMSRC = $(PORTASM) -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various # # Project, sources and paths @@ -144,4 +147,4 @@ ULIBS = # End of user defines ############################################################################## -include ${CHIBIOS}/os/ports/GCC/MSP430/rules.mk +include $(CHIBIOS)/os/ports/GCC/MSP430/rules.mk diff --git a/demos/MSP430-MSP430x1611-GCC/board.c b/demos/MSP430-MSP430x1611-GCC/board.c deleted file mode 100644 index 93197bcfd..000000000 --- a/demos/MSP430-MSP430x1611-GCC/board.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include "ch.h" -#include "hal.h" - -CH_IRQ_HANDLER(TIMERA0_VECTOR) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/* - * Hardware initialization goes here. - * NOTE: Interrupts are still disabled. - */ -void hwinit(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * Timer 0 setup, uses SMCLK as source. - */ - TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit. */ - TACTL = TACLR; /* Clean start. */ - TACTL = TASSEL_2 | ID_2 | MC_1; /* Src=SMCLK, ID=4, cmp=TACCR0. */ - TACCTL0 = CCIE; /* Interrupt on compare. */ -} diff --git a/demos/MSP430-MSP430x1611-GCC/board.h b/demos/MSP430-MSP430x1611-GCC/board.h deleted file mode 100644 index 8f22c6a8e..000000000 --- a/demos/MSP430-MSP430x1611-GCC/board.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * Clock constants. - */ -#define LFXT1CLK 32768 -#define XT2CLK 8000000 -#define DCOCLK 750000 - -/* - * Pin definitions for the Olimex MSP430-P1611 board. - */ -#define P3_O_TXD0 4 -#define P3_O_TXD0_MASK (1 << P3_O_TXD0) -#define P3_I_RXD0 5 -#define P3_I_RXD0_MASK (1 << P3_I_RXD0) -#define P6_O_LED 0 -#define P6_O_LED_MASK (1 << P6_O_LED) -#define P6_I_BUTTON 1 -#define P6_I_BUTTON_MASK (1 << P6_I_BUTTON) - -/* - * Initial I/O ports settings. - */ -#define VAL_P1OUT 0x00 -#define VAL_P1DIR 0xFF - -#define VAL_P2OUT 0x00 -#define VAL_P2DIR 0xFF - -#define VAL_P3OUT P3_O_TXD0_MASK -#define VAL_P3DIR ~P3_I_RXD0_MASK - -#define VAL_P4OUT 0x00 -#define VAL_P4DIR 0xFF - -#define VAL_P5OUT 0x00 -#define VAL_P5DIR 0xFF - -#define VAL_P6OUT P6_O_LED_MASK -#define VAL_P6DIR ~P6_I_BUTTON_MASK - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ -- cgit v1.2.3 From b07970d18cd1168e2858ae5423e7f1ebf9e275be Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Dec 2009 17:02:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1438 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 38 +++++++------- demos/ARM7-LPC214x-G++/board.c | 90 --------------------------------- demos/ARM7-LPC214x-G++/board.h | 77 ---------------------------- demos/ARM7-LPC214x-GCC-minimal/Makefile | 35 +++++++------ demos/ARM7-LPC214x-GCC-minimal/board.c | 90 --------------------------------- demos/ARM7-LPC214x-GCC-minimal/board.h | 77 ---------------------------- 6 files changed, 39 insertions(+), 368 deletions(-) delete mode 100644 demos/ARM7-LPC214x-G++/board.c delete mode 100644 demos/ARM7-LPC214x-G++/board.h delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/board.c delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/board.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 8c20ec2b8..14cd28728 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -44,25 +44,26 @@ LDSCRIPT = ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/LPC214x/platform.mk -include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/various/evtimer.c \ - board.c +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CPPSRC = ${CHIBIOS}/os/various/ch.cpp main.cpp +CPPSRC = $(CHIBIOS)/os/various/ch.cpp main.cpp # C sources to be compiled in ARM mode regardless of the global setting. # NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler @@ -86,11 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x # # Project, sources and paths @@ -178,4 +180,4 @@ ULIBS = # End of user defines ############################################################################## -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-G++/board.c b/demos/ARM7-LPC214x-G++/board.c deleted file mode 100644 index 539adabee..000000000 --- a/demos/ARM7-LPC214x-G++/board.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -//#include "lpc214x_ssp.h" -//#include "mmcsd.h" -//#include "buzzer.h" - -#define VAL_TC0_PRESCALER 0 - -/* - * Timer 0 IRQ handling here. - */ -static CH_IRQ_HANDLER(T0IrqHandler) { - - CH_IRQ_PROLOGUE(); - T0IR = 1; /* Clear interrupt on match MR0. */ - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - lpc214x_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * System Timer initialization, 1ms intervals. - */ - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - VICIntEnable = INTMASK(SOURCE_Timer0); - TC *timer = T0Base; - timer->TC_PR = VAL_TC0_PRESCALER; - timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); - timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ - timer->TC_TCR = 2; /* Reset counter and prescaler. */ - timer->TC_TCR = 1; /* Timer enabled. */ - - /* - * Other subsystems. - */ -// ssp_init(); -// InitMMC(); -// InitBuzzer(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARM7-LPC214x-G++/board.h b/demos/ARM7-LPC214x-G++/board.h deleted file mode 100644 index b66ce235d..000000000 --- a/demos/ARM7-LPC214x-G++/board.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define BOARD_OLIMEX_LCP_P2148 - -/* - * The following values are implementation dependent. You may change them in - * order to match your HW. - */ -#define FOSC 12000000 -#define CCLK 48000000 -#define PCLK 12000000 - -/* - * Pins configuration for Olimex LPC-P2148. - * - * PINSEL0 - * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD - * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 - * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 - * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- - * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - * - * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 - * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 - * - * PINSEL2 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- - * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- - */ -#define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100840A8 -#define VAL_PINSEL2 0x00000004 -#define VAL_FIO0DIR 0xB0703C00 -#define VAL_FIO1DIR 0x00000000 -#define VAL_FIO0PIN 0xFFFFFFFF -#define VAL_FIO1PIN 0xFFFFFFFF - -#define PA_LED1 10 -#define PA_LED2 11 -#define PA_BUZZ1 12 -#define PA_BUZZ2 13 -#define PA_BSL 14 -#define PA_BUTTON1 15 -#define PA_BUTTON2 16 -#define PA_SSEL1 20 -#define PA_LEDUSB 31 - -#define PB_WP1 24 -#define PB_CP1 25 - -#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile index 8801183e4..4fe00385d 100644 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ b/demos/ARM7-LPC214x-GCC-minimal/Makefile @@ -44,20 +44,22 @@ LDSCRIPT = ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/LPC214x/platform.mk -include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -#include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - board.c main.c +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -85,11 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x # # Project, sources and paths @@ -177,4 +180,4 @@ ULIBS = # End of user defines ############################################################################## -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.c b/demos/ARM7-LPC214x-GCC-minimal/board.c deleted file mode 100644 index 539adabee..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/board.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -//#include "lpc214x_ssp.h" -//#include "mmcsd.h" -//#include "buzzer.h" - -#define VAL_TC0_PRESCALER 0 - -/* - * Timer 0 IRQ handling here. - */ -static CH_IRQ_HANDLER(T0IrqHandler) { - - CH_IRQ_PROLOGUE(); - T0IR = 1; /* Clear interrupt on match MR0. */ - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - lpc214x_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * System Timer initialization, 1ms intervals. - */ - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - VICIntEnable = INTMASK(SOURCE_Timer0); - TC *timer = T0Base; - timer->TC_PR = VAL_TC0_PRESCALER; - timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); - timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ - timer->TC_TCR = 2; /* Reset counter and prescaler. */ - timer->TC_TCR = 1; /* Timer enabled. */ - - /* - * Other subsystems. - */ -// ssp_init(); -// InitMMC(); -// InitBuzzer(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARM7-LPC214x-GCC-minimal/board.h b/demos/ARM7-LPC214x-GCC-minimal/board.h deleted file mode 100644 index b66ce235d..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/board.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define BOARD_OLIMEX_LCP_P2148 - -/* - * The following values are implementation dependent. You may change them in - * order to match your HW. - */ -#define FOSC 12000000 -#define CCLK 48000000 -#define PCLK 12000000 - -/* - * Pins configuration for Olimex LPC-P2148. - * - * PINSEL0 - * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD - * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 - * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 - * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- - * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - * - * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 - * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 - * - * PINSEL2 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- - * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- - */ -#define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100840A8 -#define VAL_PINSEL2 0x00000004 -#define VAL_FIO0DIR 0xB0703C00 -#define VAL_FIO1DIR 0x00000000 -#define VAL_FIO0PIN 0xFFFFFFFF -#define VAL_FIO1PIN 0xFFFFFFFF - -#define PA_LED1 10 -#define PA_LED2 11 -#define PA_BUZZ1 12 -#define PA_BUZZ2 13 -#define PA_BSL 14 -#define PA_BUTTON1 15 -#define PA_BUTTON2 16 -#define PA_SSEL1 20 -#define PA_LEDUSB 31 - -#define PB_WP1 24 -#define PB_CP1 25 - -#endif /* _BOARD_H_ */ -- cgit v1.2.3 From ce5974e5de90403c272854a2be4e47d924575186 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 Dec 2009 21:00:27 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1439 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/Makefile | 31 ++++++----- demos/AVR-AT90CANx-GCC/board.c | 84 ---------------------------- demos/AVR-AT90CANx-GCC/board.h | 92 ------------------------------- demos/AVR-ATmega128-GCC/Makefile | 31 ++++++----- demos/AVR-ATmega128-GCC/board.c | 84 ---------------------------- demos/AVR-ATmega128-GCC/board.h | 116 --------------------------------------- 6 files changed, 34 insertions(+), 404 deletions(-) delete mode 100644 demos/AVR-AT90CANx-GCC/board.c delete mode 100644 demos/AVR-AT90CANx-GCC/board.h delete mode 100644 demos/AVR-ATmega128-GCC/board.c delete mode 100644 demos/AVR-ATmega128-GCC/board.h (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/Makefile b/demos/AVR-AT90CANx-GCC/Makefile index 0b6943cab..11e902b59 100644 --- a/demos/AVR-AT90CANx-GCC/Makefile +++ b/demos/AVR-AT90CANx-GCC/Makefile @@ -81,21 +81,23 @@ OBJDIR = . # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/AVR/platform.mk -include ${CHIBIOS}/os/ports/GCC/AVR/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_AVR_CAN/board.mk +include $(CHIBIOS)/os/hal/platforms/AVR/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/AVR/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # List C source files here. (C dependencies are automatically generated.) -SRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/various/evtimer.c \ - board.c main.c +SRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + main.c # List C++ source files here. (C dependencies are automatically generated.) @@ -129,8 +131,9 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various # Compiler flag to set the C Standard level. diff --git a/demos/AVR-AT90CANx-GCC/board.c b/demos/AVR-AT90CANx-GCC/board.c deleted file mode 100644 index b97bd94b5..000000000 --- a/demos/AVR-AT90CANx-GCC/board.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -CH_IRQ_HANDLER(TIMER0_COMP_vect) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/* - * Board initialization code. - */ -void hwinit(void) { - - /* - * I/O ports setup. - */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; - - /* - * External interrupts setup, all disabled initially. - */ - EICRA = 0x00; - EICRB = 0x00; - EIMSK = 0x00; - - /* - * Enables Idle mode for SLEEP instruction. - */ - SMCR = (1 << SE); - - /* - * Timer 0 setup. - */ - TCCR0A = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ - (0 << COM0A1) | (0 << COM0A0) | /* OC0A disabled. */ - (0 << CS02) | (1 << CS01) | (1 << CS00); /* CLK/64 clock. */ - OCR0A = F_CPU / 64 / CH_FREQUENCY - 1; - TCNT0 = 0; /* Reset counter. */ - TIFR0 = (1 << OCF0A); /* Reset pending. */ - TIMSK0 = (1 << OCIE0A); /* IRQ on compare. */ - - /* - * HAL initialization. - */ - halInit(); -} diff --git a/demos/AVR-AT90CANx-GCC/board.h b/demos/AVR-AT90CANx-GCC/board.h deleted file mode 100644 index 0abe920eb..000000000 --- a/demos/AVR-AT90CANx-GCC/board.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define BOARD_OLIMEX_AVR_CAN - -/* - * All inputs with pullups. - */ -#define VAL_DDRA 0x00 -#define VAL_PORTA 0xFF - -/* - * All inputs with pullups. - */ -#define VAL_DDRB 0x00 -#define VAL_PORTB 0xFF - -/* - * All inputs with pullups. - */ -#define VAL_DDRC 0x00 -#define VAL_PORTC 0xFF - -/* PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 - * IN IN OUT IN OUT IN IN IN - * DDRD 0 0 1 0 1 0 0 0 - * PU HiZ VAL PU VAL HiZ HiZ HiZ - * PORTD 1 0 ?1 1 1 0 0 0 - */ -#define VAL_DDRD 0x28 -#define VAL_PORTD 0xB8 - -/* PE7 PE6 BUT LED PE3 PE2 PE1 PE0 - * IN IN IN OUT IN IN OUT IN - * DDRE 0 0 0 1 0 0 1 0 - * PU PU HiZ VAL PU PU VAL HiZ - * PORTE 1 1 0 1 1 1 1 0 - */ -#define VAL_DDRE 0x12 -#define VAL_PORTE 0xDE - -/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 - * x x x x IN IN IN IN - * DDRF 0 0 0 0 0 0 0 0 - * x x x x PU PU PU PU - * PORTF 0 0 0 0 1 1 1 1 - * - */ -#define VAL_DDRF 0x00 -#define VAL_PORTF 0x0F - -/* x x x x x PG2 PG1 PG0 - * x x x x x IN IN IN - * DDRG 0 0 0 0 0 0 0 0 - * x x x x x PU PU PU - * PORTG 0 0 0 0 0 1 1 1 - * - */ -#define VAL_DDRG 0x00 -#define VAL_PORTG 0x07 - -#define PORTE_LED (1 << 4) -#define PORTE_BUTTON (1 << 5) - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ diff --git a/demos/AVR-ATmega128-GCC/Makefile b/demos/AVR-ATmega128-GCC/Makefile index 1ae0a672a..3f42dce8e 100644 --- a/demos/AVR-ATmega128-GCC/Makefile +++ b/demos/AVR-ATmega128-GCC/Makefile @@ -81,21 +81,23 @@ OBJDIR = . # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/AVR/platform.mk -include ${CHIBIOS}/os/ports/GCC/AVR/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_AVR_MT_128/board.mk +include $(CHIBIOS)/os/hal/platforms/AVR/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/AVR/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # List C source files here. (C dependencies are automatically generated.) -SRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/various/evtimer.c \ - lcd.c board.c main.c +SRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + lcd.c main.c # List C++ source files here. (C dependencies are automatically generated.) @@ -129,8 +131,9 @@ DEBUG = dwarf-2 # Each directory must be seperated by a space. # Use forward slashes for directory separators. # For a directory that has spaces, enclose it in quotes. -EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various +EXTRAINCDIRS = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various # Compiler flag to set the C Standard level. diff --git a/demos/AVR-ATmega128-GCC/board.c b/demos/AVR-ATmega128-GCC/board.c deleted file mode 100644 index 8a9a69309..000000000 --- a/demos/AVR-ATmega128-GCC/board.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -CH_IRQ_HANDLER(TIMER0_COMP_vect) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - CH_IRQ_EPILOGUE(); -} - -/* - * Board initialization code. - */ -void hwinit(void) { - - /* - * I/O ports setup. - */ - DDRA = VAL_DDRA; - PORTA = VAL_PORTA; - DDRB = VAL_DDRB; - PORTB = VAL_PORTB; - DDRC = VAL_DDRC; - PORTC = VAL_PORTC; - DDRD = VAL_DDRD; - PORTD = VAL_PORTD; - DDRE = VAL_DDRE; - PORTE = VAL_PORTE; - DDRF = VAL_DDRF; - PORTF = VAL_PORTF; - DDRG = VAL_DDRG; - PORTG = VAL_PORTG; - - /* - * External interrupts setup, all disabled initially. - */ - EICRA = 0x00; - EICRB = 0x00; - EIMSK = 0x00; - - /* - * Enables Idle mode for SLEEP instruction. - */ - MCUCR = (1 << SE); - - /* - * Timer 0 setup. - */ - TCCR0 = (1 << WGM01) | (0 << WGM00) | /* CTC mode. */ - (0 << COM01) | (0 << COM00) | /* OC0A disabled. */ - (1 << CS02) | (0 << CS01) | (0 << CS00); /* CLK/64 clock. */ - OCR0 = F_CPU / 64 / CH_FREQUENCY - 1; - TCNT0 = 0; /* Reset counter. */ - TIFR = (1 << OCF0); /* Reset pending. */ - TIMSK = (1 << OCIE0); /* IRQ on compare. */ - - /* - * HAL initialization. - */ - halInit(); -} diff --git a/demos/AVR-ATmega128-GCC/board.h b/demos/AVR-ATmega128-GCC/board.h deleted file mode 100644 index 97da17097..000000000 --- a/demos/AVR-ATmega128-GCC/board.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define BOARD_OLIMEX_AVR_MT_128 - -/* PA7 RLY DS B5 B4 B3 B2 B1 - * IN OUT IN IN IN IN IN IN - * DDRA 0 1 0 0 0 0 0 0 - * PU VAL HiZ HiZ HiZ HiZ HiZ HiZ - * PORTA 1 0 0 0 0 0 0 0 - */ -#define VAL_DDRA 0x40 -#define VAL_PORTA 0x80 - -/* - * All inputs with pullups. - */ -#define VAL_DDRB 0x00 -#define VAL_PORTB 0xFF - -/* D7 D6 D5 D4 PC3 E R/W RS - * OUT OUT OUT OUT IN OUT OUT OUT - * DDRC 1 1 1 1 0 1 1 1 - * PU PU PU PU PU VAL VAL VAL - * PORTC 0 0 0 0 1 0 0 0 - */ -#define VAL_DDRC 0xF7 -#define VAL_PORTC 0x08 - -/* PD7 PD6 PD5 PD4 TXD RXD PD1 PD0 - * IN IN IN IN OUT IN IN IN - * DDRD 0 0 0 0 1 0 0 0 - * PU PU PU PU VAL HiZ PU PU - * PORTD 1 1 1 1 1 0 1 1 - */ -#define VAL_DDRD 0x08 -#define VAL_PORTD 0xFB - -/* PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0 - * IN IN OUT OUT IN IN OUT IN - * DDRE 0 0 1 1 0 0 1 0 - * PU PU VAL VAL PU PU VAL PU - * PORTE 1 1 1 1 1 1 1 1 - */ -#define VAL_DDRE 0x32 -#define VAL_PORTE 0xFF - -/* TDI TDO TMS TCK PF3 PF2 PF1 PF0 - * x x x x IN IN IN IN - * DDRF 0 0 0 0 0 0 0 0 - * x x x x PU PU PU PU - * PORTF 0 0 0 0 1 1 1 1 - * - */ -#define VAL_DDRF 0x00 -#define VAL_PORTF 0x0F - -/* x x x x x PG2 PG1 PG0 - * x x x x x IN IN IN - * DDRG 0 0 0 0 0 0 0 0 - * x x x x x PU PU PU - * PORTG 0 0 0 0 0 1 1 1 - * - */ -#define VAL_DDRG 0x00 -#define VAL_PORTG 0x07 - -#define PORTA_BUTTON1 (1 << 0) -#define PORTA_BUTTON2 (1 << 1) -#define PORTA_BUTTON3 (1 << 2) -#define PORTA_BUTTON4 (1 << 3) -#define PORTA_BUTTON5 (1 << 4) -#define PORTA_DALLAS (1 << 5) -#define PORTA_RELAY (1 << 6) - -#define PORTC_44780_RS (1 << 0) -#define PORTC_44780_RW (1 << 1) -#define PORTC_44780_E (1 << 2) -#define PORTC_44780_D4 (1 << 4) -#define PORTC_44780_D5 (1 << 5) -#define PORTC_44780_D6 (1 << 6) -#define PORTC_44780_D7 (1 << 7) -#define PORTC_44780_DATA (PORTC_44780_D4 | PORTC_44780_D5 | \ - PORTC_44780_D6 | PORTC_44780_D7) - -#define PORTE_BUZZ1 (1 << 4) -#define PORTE_BUZZ2 (1 << 5) - -#ifdef __cplusplus -extern "C" { -#endif - void hwinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _BOARD_H_ */ -- cgit v1.2.3 From c82d270d18cddcf15a0ccfcc95e861c33add8861 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Dec 2009 11:10:08 +0000 Subject: LPC214x SPI driver added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1442 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/halconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index 4e2e694c4..62f17c0bc 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -81,7 +81,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI TRUE #endif /** -- cgit v1.2.3 From 53217647e504da509e648735b47c6fe652cd5b90 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 19 Dec 2009 16:57:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1443 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/halconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index 62f17c0bc..4e2e694c4 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -81,7 +81,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#define CH_HAL_USE_SPI FALSE #endif /** -- cgit v1.2.3 From 4e37e938e5c861d758168705e8d681d18d9a6243 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Dec 2009 11:38:02 +0000 Subject: FatFS demo for LPC214x added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1445 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FatFS-GCC/Makefile | 188 +++++++++++++ demos/ARM7-LPC214x-FatFS-GCC/ch.ld | 101 +++++++ demos/ARM7-LPC214x-FatFS-GCC/chconf.h | 464 ++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-FatFS-GCC/halconf.h | 96 +++++++ demos/ARM7-LPC214x-FatFS-GCC/main.c | 263 ++++++++++++++++++ demos/ARM7-LPC214x-FatFS-GCC/readme.txt | 19 ++ 6 files changed, 1131 insertions(+) create mode 100644 demos/ARM7-LPC214x-FatFS-GCC/Makefile create mode 100644 demos/ARM7-LPC214x-FatFS-GCC/ch.ld create mode 100644 demos/ARM7-LPC214x-FatFS-GCC/chconf.h create mode 100644 demos/ARM7-LPC214x-FatFS-GCC/halconf.h create mode 100644 demos/ARM7-LPC214x-FatFS-GCC/main.c create mode 100644 demos/ARM7-LPC214x-FatFS-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FatFS-GCC/Makefile b/demos/ARM7-LPC214x-FatFS-GCC/Makefile new file mode 100644 index 000000000..f361c8d2a --- /dev/null +++ b/demos/ARM7-LPC214x-FatFS-GCC/Makefile @@ -0,0 +1,188 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk +include $(CHIBIOS)/ext/fatfs/fatfs.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(FATFSSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +TRGT = arm-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-FatFS-GCC/ch.ld b/demos/ARM7-LPC214x-FatFS-GCC/ch.ld new file mode 100644 index 000000000..9dd4d388e --- /dev/null +++ b/demos/ARM7-LPC214x-FatFS-GCC/ch.ld @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-LPC214x-FatFS-GCC/chconf.h b/demos/ARM7-LPC214x-FatFS-GCC/chconf.h new file mode 100644 index 000000000..3b29983cb --- /dev/null +++ b/demos/ARM7-LPC214x-FatFS-GCC/chconf.h @@ -0,0 +1,464 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @addtogroup config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented or some ports. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-FatFS-GCC/halconf.h b/demos/ARM7-LPC214x-FatFS-GCC/halconf.h new file mode 100644 index 000000000..6fb0e97fa --- /dev/null +++ b/demos/ARM7-LPC214x-FatFS-GCC/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-FatFS-GCC/main.c b/demos/ARM7-LPC214x-FatFS-GCC/main.c new file mode 100644 index 000000000..8da531413 --- /dev/null +++ b/demos/ARM7-LPC214x-FatFS-GCC/main.c @@ -0,0 +1,263 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "evtimer.h" + +#include "ff.h" + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0).*/ +static SPIConfig hs_spicfg = { + IOPORT1, + PA_SSEL1, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 0, + 2 +}; + +/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0).*/ +static SPIConfig ls_spicfg = { + IOPORT1, + PA_SSEL1, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 0, + 254 +}; + +/* MMC configuration (empty).*/ +static const MMCConfig mmc_cfg = {}; + +/* Card insertion verification.*/ +static bool_t mmc_is_inserted(void) { + return !palReadPad(IOPORT2, PB_CP1); +} + +/* Card protection verification.*/ +static bool_t mmc_is_protected(void) { + return palReadPad(IOPORT2, PB_WP1); +} + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + } + return 0; +} + +/* + * Yellow LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(200); + palSetPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(300); + } + return 0; +} + +static FRESULT scan_files(char *path) +{ + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + siprintf(&path[i], "/%s", fn); + res = scan_files(path); + if (res != FR_OK) + break; + path[i] = 0; + } + else { + iprintf("%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/* + * Executed as event handler at 500mS intervals. + */ +static void TimerHandler(eventid_t id) { + + (void)id; + if (!palReadPad(IOPORT1, PA_BUTTON1)) { + if (fs_ready) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + iprintf("FS: f_getfree() failed\r\n"); + return; + } + iprintf("FS: %lu free clusters, %u sectors per cluster, %lu bytes free\r\n", + clusters, MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); + fbuff[0] = 0; + scan_files((char *)fbuff); + } + } + else if (!palReadPad(IOPORT1, PA_BUTTON2)) { + static WORKING_AREA(waTestThread, 256); + Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), + NORMALPRIO, TestThread, &SD1); + chThdWait(tp); + } +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + iprintf("MMC: inserted\r\n"); + /* + * On insertion MMC initialization and FS mount. + */ + iprintf("MMC: initialization "); + if (mmcConnect(&MMCD1)) { + iprintf("failed\r\n"); + return; + } + iprintf("ok\r\n"); + iprintf("FS: mount "); + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + iprintf("failed\r\n"); + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; + iprintf("ok\r\n"); +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + iprintf("MMC: removed\r\n"); + fs_ready = FALSE; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + static const evhandler_t evhndl[] = { + TimerHandler, + InsertHandler, + RemoveHandler + }; + static EvTimer evt; + struct EventListener el0, el1, el2; + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Initializes the MMC driver to work with SPI2. + */ + mmcObjectInit(&MMCD1, &SPID1, + &ls_spicfg, &hs_spicfg, + mmc_is_protected, mmc_is_inserted); + mmcStart(&MMCD1, &mmc_cfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listed for events. + */ + evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + chEvtRegister(&MMCD1.mmc_inserted_event, &el1, 1); + chEvtRegister(&MMCD1.mmc_removed_event, &el2, 2); + while (TRUE)// chThdSleepMilliseconds(50); + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + return 0; +} diff --git a/demos/ARM7-LPC214x-FatFS-GCC/readme.txt b/demos/ARM7-LPC214x-FatFS-GCC/readme.txt new file mode 100644 index 000000000..83abee7c6 --- /dev/null +++ b/demos/ARM7-LPC214x-FatFS-GCC/readme.txt @@ -0,0 +1,19 @@ +***************************************************************************** +** ChibiOS/RT + FatFS demo for LPC214x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads. +By pressing button 1 a directory scan on the MMC slot is performed, by +pressing the button 2 the test suite is activated on serial port 1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. -- cgit v1.2.3 From d8db6bd8dc1496db7f50e480b81793a990f0b1df Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Dec 2009 13:15:00 +0000 Subject: Added sounds to the FatFS demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1447 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FatFS-GCC/main.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FatFS-GCC/main.c b/demos/ARM7-LPC214x-FatFS-GCC/main.c index 8da531413..70d1605bf 100644 --- a/demos/ARM7-LPC214x-FatFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FatFS-GCC/main.c @@ -24,6 +24,7 @@ #include "hal.h" #include "test.h" #include "evtimer.h" +#include "buzzer.h" #include "ff.h" @@ -172,6 +173,7 @@ static void TimerHandler(eventid_t id) { Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), NORMALPRIO, TestThread, &SD1); chThdWait(tp); + buzzPlay(500, MS2ST(100)); } } @@ -182,6 +184,8 @@ static void InsertHandler(eventid_t id) { FRESULT err; (void)id; + buzzPlayWait(1000, MS2ST(100)); + buzzPlayWait(2000, MS2ST(100)); iprintf("MMC: inserted\r\n"); /* * On insertion MMC initialization and FS mount. @@ -201,6 +205,7 @@ static void InsertHandler(eventid_t id) { } fs_ready = TRUE; iprintf("ok\r\n"); + buzzPlay(440, MS2ST(200)); } /* @@ -211,6 +216,8 @@ static void RemoveHandler(eventid_t id) { (void)id; iprintf("MMC: removed\r\n"); fs_ready = FALSE; + buzzPlayWait(2000, MS2ST(100)); + buzzPlayWait(1000, MS2ST(100)); } /* @@ -234,6 +241,11 @@ int main(int argc, char **argv) { */ sdStart(&SD1, NULL); + /* + * Buzzer driver initialization. + */ + buzzInit(); + /* * Initializes the MMC driver to work with SPI2. */ -- cgit v1.2.3 From dfd631cb67bf200991186fb33f4b1d4ab708ca6e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Dec 2009 14:07:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1448 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC-minimal/Makefile | 183 ------------ demos/ARM7-LPC214x-GCC-minimal/ch.ld | 101 ------- demos/ARM7-LPC214x-GCC-minimal/chconf.h | 464 ------------------------------ demos/ARM7-LPC214x-GCC-minimal/halconf.h | 96 ------- demos/ARM7-LPC214x-GCC-minimal/main.c | 81 ------ demos/ARM7-LPC214x-GCC-minimal/readme.txt | 18 -- demos/ARM7-LPC214x-GCC/Makefile | 37 +-- demos/ARM7-LPC214x-GCC/board.c | 90 ------ demos/ARM7-LPC214x-GCC/board.h | 77 ----- demos/ARM7-LPC214x-GCC/buzzer.c | 92 ------ demos/ARM7-LPC214x-GCC/buzzer.h | 35 --- demos/ARM7-LPC214x-GCC/main.c | 85 +----- demos/ARM7-LPC214x-GCC/mmcsd.c | 388 ------------------------- demos/ARM7-LPC214x-GCC/mmcsd.h | 66 ----- 14 files changed, 28 insertions(+), 1785 deletions(-) delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/Makefile delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/ch.ld delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/chconf.h delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/halconf.h delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/main.c delete mode 100644 demos/ARM7-LPC214x-GCC-minimal/readme.txt delete mode 100644 demos/ARM7-LPC214x-GCC/board.c delete mode 100644 demos/ARM7-LPC214x-GCC/board.h delete mode 100644 demos/ARM7-LPC214x-GCC/buzzer.c delete mode 100644 demos/ARM7-LPC214x-GCC/buzzer.h delete mode 100644 demos/ARM7-LPC214x-GCC/mmcsd.c delete mode 100644 demos/ARM7-LPC214x-GCC/mmcsd.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC-minimal/Makefile b/demos/ARM7-LPC214x-GCC-minimal/Makefile deleted file mode 100644 index 4fe00385d..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/Makefile +++ /dev/null @@ -1,183 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -#include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -TRGT = arm-elf- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC-minimal/ch.ld b/demos/ARM7-LPC214x-GCC-minimal/ch.ld deleted file mode 100644 index 9dd4d388e..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/ch.ld +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * LPC2148 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash - - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram - - /DISCARD/ : - { - *(.eh_*) - } -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-LPC214x-GCC-minimal/chconf.h b/demos/ARM7-LPC214x-GCC-minimal/chconf.h deleted file mode 100644 index 460ee004a..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/chconf.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @addtogroup config - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. - * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED FALSE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT FALSE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES FALSE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW FALSE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES FALSE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS FALSE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT FALSE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS FALSE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT FALSE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES FALSE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES FALSE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES FALSE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE FALSE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP FALSE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS FALSE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC FALSE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING FALSE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/halconf.h b/demos/ARM7-LPC214x-GCC-minimal/halconf.h deleted file mode 100644 index 63afdace0..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/halconf.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/demos/ARM7-LPC214x-GCC-minimal/main.c b/demos/ARM7-LPC214x-GCC-minimal/main.c deleted file mode 100644 index 940e77b5e..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/main.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - } - return 0; -} - -/* - * Yellow LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread2, 128); -static msg_t Thread2(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(200); - palSetPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(300); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Creates the blinker threads. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop. - */ - while (TRUE) - chThdSleepMilliseconds(1000); - return 0; -} diff --git a/demos/ARM7-LPC214x-GCC-minimal/readme.txt b/demos/ARM7-LPC214x-GCC-minimal/readme.txt deleted file mode 100644 index 363cd8dde..000000000 --- a/demos/ARM7-LPC214x-GCC-minimal/readme.txt +++ /dev/null @@ -1,18 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM7TDMI LPC214X. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex LPC-P2148 board. The port on other boards or other -members of the LPC2000 family should be an easy task. - -** The Demo ** - -This is a minimal demo, it just blinks the leds on the board by using multiple -threads, most subsystems are disabled. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 9d44185a4..a1056cbd7 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -44,22 +44,22 @@ LDSCRIPT = ch.ld # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/LPC214x/platform.mk -include ${CHIBIOS}/os/ports/GCC/ARM7/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. -CSRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/hal/platforms/LPC214x/lpc214x_ssp.c \ - ${CHIBIOS}/os/various/evtimer.c \ - board.c buzzer.c mmcsd.c main.c +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -87,11 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various \ - ${CHIBIOS}/os/ports/GCC/ARM7/LPC214x +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x # # Project, sources and paths @@ -179,4 +180,4 @@ ULIBS = # End of user defines ############################################################################## -include ${CHIBIOS}/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-GCC/board.c b/demos/ARM7-LPC214x-GCC/board.c deleted file mode 100644 index f81d2329a..000000000 --- a/demos/ARM7-LPC214x-GCC/board.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -#include "lpc214x_ssp.h" -#include "mmcsd.h" -#include "buzzer.h" - -#define VAL_TC0_PRESCALER 0 - -/* - * Timer 0 IRQ handling here. - */ -static CH_IRQ_HANDLER(T0IrqHandler) { - - CH_IRQ_PROLOGUE(); - T0IR = 1; /* Clear interrupt on match MR0. */ - - chSysLockFromIsr(); - chSysTimerHandlerI(); - chSysUnlockFromIsr(); - - VICVectAddr = 0; - CH_IRQ_EPILOGUE(); -} - -/* - * Early initialization code. - * This initialization is performed just after reset before BSS and DATA - * segments initialization. - */ -void hwinit0(void) { - - lpc214x_clock_init(); -} - -/* - * Late initialization code. - * This initialization is performed after BSS and DATA segments initialization - * and before invoking the main() function. - */ -void hwinit1(void) { - - /* - * HAL initialization. - */ - halInit(); - - /* - * System Timer initialization, 1ms intervals. - */ - SetVICVector(T0IrqHandler, 0, SOURCE_Timer0); - VICIntEnable = INTMASK(SOURCE_Timer0); - TC *timer = T0Base; - timer->TC_PR = VAL_TC0_PRESCALER; - timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1); - timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */ - timer->TC_TCR = 2; /* Reset counter and prescaler. */ - timer->TC_TCR = 1; /* Timer enabled. */ - - /* - * Other subsystems. - */ - ssp_init(); - InitMMC(); - InitBuzzer(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); -} diff --git a/demos/ARM7-LPC214x-GCC/board.h b/demos/ARM7-LPC214x-GCC/board.h deleted file mode 100644 index b66ce235d..000000000 --- a/demos/ARM7-LPC214x-GCC/board.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#define BOARD_OLIMEX_LCP_P2148 - -/* - * The following values are implementation dependent. You may change them in - * order to match your HW. - */ -#define FOSC 12000000 -#define CCLK 48000000 -#define PCLK 12000000 - -/* - * Pins configuration for Olimex LPC-P2148. - * - * PINSEL0 - * P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD - * 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0 - * 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 - * IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- -- - * 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 - * - * PINSEL1 - * P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0 - * 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16 - * 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00 - * OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN - * 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 - * - * PINSEL2 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG -- - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO -- - * 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00 - * -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- -- - */ -#define VAL_PINSEL0 0x00055555 -#define VAL_PINSEL1 0x100840A8 -#define VAL_PINSEL2 0x00000004 -#define VAL_FIO0DIR 0xB0703C00 -#define VAL_FIO1DIR 0x00000000 -#define VAL_FIO0PIN 0xFFFFFFFF -#define VAL_FIO1PIN 0xFFFFFFFF - -#define PA_LED1 10 -#define PA_LED2 11 -#define PA_BUZZ1 12 -#define PA_BUZZ2 13 -#define PA_BSL 14 -#define PA_BUTTON1 15 -#define PA_BUTTON2 16 -#define PA_SSEL1 20 -#define PA_LEDUSB 31 - -#define PB_WP1 24 -#define PB_CP1 25 - -#endif /* _BOARD_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/buzzer.c b/demos/ARM7-LPC214x-GCC/buzzer.c deleted file mode 100644 index 2e7c0bd98..000000000 --- a/demos/ARM7-LPC214x-GCC/buzzer.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * Buzzer driver for Olimex LPC-P2148. - * Uses the timer 1 for wave generation and a Virtual Timer for the sound - * duration. - * The driver also generates an event when the sound is done and the buzzer - * goes silent. - */ - -#include "ch.h" -#include "hal.h" - -#include "buzzer.h" - -EventSource BuzzerSilentEventSource; - -#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1) -#define StopCounter(t) ((t)->TC_EMR = 0, (t)->TC_TCR = 2) - -void InitBuzzer(void) { - - chEvtInit(&BuzzerSilentEventSource); - - /* - * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions. - * Enables Timer1 clock. - */ - PINSEL0 &= 0xF0FFFFFF; - PINSEL0 |= 0x0A000000; - PCONP = (PCONP & PCALL) | PCTIM1; - - /* - * Timer setup. - */ - TC *tc = T1Base; - StopCounter(tc); - tc->TC_CTCR = 0; // Clock source is PCLK. - tc->TC_PR = 0; // Prescaler disabled. - tc->TC_MCR = 2; // Clear TC on match MR0. -} - -static void stop(void *p) { - - StopCounter((TC *)p); - chEvtBroadcastI(&BuzzerSilentEventSource); -} - -void PlaySound(int freq, systime_t duration) { - static VirtualTimer bvt; - TC *tc = T1Base; - - chSysLock(); - - if (chVTIsArmedI(&bvt)) { // If a sound is already being played - chVTResetI(&bvt); // then aborts it. - StopCounter(tc); - } - - tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); - StartCounter(tc); - chVTSetI(&bvt, duration, stop, tc); - - chSysUnlock(); -} - -void PlaySoundWait(int freq, systime_t duration) { - TC *tc = T1Base; - - StopCounter(tc); - tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2)); - StartCounter(tc); - chThdSleep(duration); - StopCounter(tc); -} diff --git a/demos/ARM7-LPC214x-GCC/buzzer.h b/demos/ARM7-LPC214x-GCC/buzzer.h deleted file mode 100644 index 734cb1a44..000000000 --- a/demos/ARM7-LPC214x-GCC/buzzer.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BUZZER_H_ -#define _BUZZER_H_ - -#ifdef __cplusplus -extern "C" { -#endif - void InitBuzzer(void); - void PlaySound(int freq, systime_t duration); - void PlaySoundWait(int freq, systime_t duration); -#ifdef __cplusplus -} -#endif - -extern EventSource BuzzerSilentEventSource; - -#endif /* _BUZZER_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index d0a69b3d7..00aca0ec7 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -20,10 +20,6 @@ #include "ch.h" #include "hal.h" #include "test.h" -#include "evtimer.h" - -#include "mmcsd.h" -#include "buzzer.h" #define BOTH_BUTTONS (PAL_PORT_BIT(PA_BUTTON1) | PAL_PORT_BIT(PA_BUTTON2)) @@ -63,73 +59,11 @@ static msg_t Thread2(void *arg) { return 0; } -static WORKING_AREA(waTestThread, 128); - -/* - * Executed as event handler at 500mS intervals. - */ -static void TimerHandler(eventid_t id) { - - (void)id; - if (!(palReadPort(IOPORT1) & BOTH_BUTTONS)) { - Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), - NORMALPRIO, TestThread, &SD1); - chThdWait(tp); - PlaySound(500, MS2ST(100)); - } - else { - if (!palReadPad(IOPORT1, PA_BUTTON1)) - PlaySound(1000, MS2ST(100)); - if (!palReadPad(IOPORT1, PA_BUTTON2)) { - sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); - PlaySound(2000, MS2ST(100)); - } - } -} - -/* - * Plays sounds when a MMC/SD card is inserted, then initializes the MMC - * driver and reads a sector. - */ -static void InsertHandler(eventid_t id) { - static uint8_t rwbuf[512]; - MMCCSD data; - - (void)id; - PlaySoundWait(1000, MS2ST(100)); - PlaySoundWait(2000, MS2ST(100)); - if (mmcInit()) - return; - /* Card ready, do stuff.*/ - if (mmcGetSize(&data)) - return; - if (mmcRead(rwbuf, 0)) - return; - PlaySound(440, MS2ST(200)); -} - -/* - * Plays sounds when a MMC/SD card is removed. - */ -static void RemoveHandler(eventid_t id) { - - (void)id; - PlaySoundWait(2000, MS2ST(100)); - PlaySoundWait(1000, MS2ST(100)); -} - /* * Entry point, note, the main() function is already a thread in the system * on entry. */ int main(int argc, char **argv) { - static const evhandler_t evhndl[] = { - TimerHandler, - InsertHandler, - RemoveHandler - }; - static EvTimer evt; - struct EventListener el0, el1, el2; (void)argc; (void)argv; @@ -149,16 +83,15 @@ int main(int argc, char **argv) { } /* - * Normal main() activity, in this demo it serves events generated by - * various sources. + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the buttons state. */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - mmcStartPolling(); /* Starts the MMC connector polling. */ - chEvtRegister(&MMCInsertEventSource, &el1, 1); - chEvtRegister(&MMCRemoveEventSource, &el2, 2); - while (TRUE) /* Just serve events. */ - chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + while (TRUE) { + if (!palReadPad(IOPORT1, PA_BUTTON1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT1, PA_BUTTON2)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } return 0; } diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.c b/demos/ARM7-LPC214x-GCC/mmcsd.c deleted file mode 100644 index 220d9c88a..000000000 --- a/demos/ARM7-LPC214x-GCC/mmcsd.c +++ /dev/null @@ -1,388 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" - -#include "lpc214x_ssp.h" -#include "mmcsd.h" - -EventSource MMCInsertEventSource, MMCRemoveEventSource; - -static VirtualTimer vt; -static int cnt; - -/* - * Subsystem initialization. - */ -void InitMMC(void) { - - chEvtInit(&MMCInsertEventSource); - chEvtInit(&MMCRemoveEventSource); - cnt = POLLING_INTERVAL; -} - -void tmrfunc(void *par) { - - (void)par; - if (cnt) { - if (!palReadPad(IOPORT2, PB_CP1)) { - if (!--cnt) - chEvtBroadcastI(&MMCInsertEventSource); - } - else - cnt = POLLING_INTERVAL; - } - else { - if (palReadPad(IOPORT2, PB_CP1)) { - cnt = POLLING_INTERVAL; - chEvtBroadcastI(&MMCRemoveEventSource); - } - } - chVTSetI(&vt, 10, tmrfunc, NULL); -} - -/* - * Starts the card polling service. - */ -void mmcStartPolling(void) { - - chSysLock(); - - if (!chVTIsArmedI(&vt)) { - chVTSetI(&vt, 10, tmrfunc, NULL); - cnt = POLLING_INTERVAL; - } - - chSysUnlock(); -} - -/* - * Stops the card polling service. - */ -void mmcStopPolling(void) { - - chSysLock(); - - if (chVTIsArmedI(&vt)) { - chVTResetI(&vt); - cnt = POLLING_INTERVAL; - } - - chSysUnlock(); -} - -/* - * Returns TRUE if the card is safely inserted in the reader. - */ -bool_t mmcCardInserted (void) { - - return cnt == 0; -} - -static void wait(void) { - int i; - uint8_t buf[4]; - - for (i = 0; i < 16; i++) { - sspRW(buf, NULL, 1); - if (buf[0] == 0xFF) - break; - } - /* Looks like it is a loooong wait.*/ - while (TRUE) { - sspRW(buf, NULL, 1); - if (buf[0] == 0xFF) - break; -#ifdef NICE_WAITING - chThdSleep(1); /* Trying to be nice with the other threads.*/ -#endif - } -} - -static void sendhdr(uint8_t cmd, uint32_t arg) { - uint8_t buf[6]; - - /* - * Wait for the bus to become idle if a write operation was in progress. - */ - wait(); - - buf[0] = 0x40 | cmd; - buf[1] = arg >> 24; - buf[2] = arg >> 16; - buf[3] = arg >> 8; - buf[4] = arg; - buf[5] = 0x95; /* Valid for CMD0 ingnored by other commands. */ - sspRW(NULL, buf, 6); -} - -static uint8_t recvr1(void) { - int i; - uint8_t r1[1]; - - for (i = 0; i < 9; i++) { - sspRW(r1, NULL, 1); - if (r1[0] != 0xFF) - return r1[0]; - } - return 0xFF; /* Timeout.*/ -} - -static bool_t getdata(uint8_t *buf, uint32_t n) { - int i; - - for (i = 0; i < MMC_WAIT_DATA; i++) { - sspRW(buf, NULL, 1); - if (buf[0] == 0xFE) { - sspRW(buf, NULL, n); - sspRW(NULL, NULL, 2); /* CRC ignored.*/ - return FALSE; - } - } - return TRUE; /* Timeout.*/ -} - -/* - * Initializes a card after the power up by selecting the SPI mode. - */ -bool_t mmcInit(void) { - - /* - * Starting initialization with slow clock mode. - */ - ssp_setup(254, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); - - /* - * SPI mode selection. - */ - sspRW(NULL, NULL, 16); /* 128 clock pulses without ~CS asserted. */ - int i = 0; - while (TRUE) { - if (mmcSendCommand(CMDGOIDLE, 0) == 0x01) - break; - if (++i >= CMD0_RETRY) - return TRUE; - chThdSleep(10); - } - - /* - * Initialization. - */ - i = 0; - while (TRUE) { - uint8_t b = mmcSendCommand(CMDINIT, 0); - if (b == 0x00) - break; - if (b != 0x01) - return TRUE; - if (++i >= CMD1_RETRY) - return TRUE; - chThdSleep(10); - } - - /* - * Full speed. - */ - ssp_setup(2, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), 0); - return FALSE; -} - -/* - * Sends a simple command and returns a R1-type response. - */ -uint8_t mmcSendCommand(uint8_t cmd, uint32_t arg) { - uint8_t r1; - - sspAcquireBus(); - sendhdr(cmd, arg); - r1 = recvr1(); - sspReleaseBus(); - return r1; -} - -/* - * Reads the card info record. - * @param data the pointer to a \p MMCCSD structure - * @return \p TRUE if an error happened - */ -bool_t mmcGetSize(MMCCSD *data) { - uint8_t buf[16]; - - sspAcquireBus(); - sendhdr(CMDREADCSD, 0); - if (recvr1() != 0x00) { - sspReleaseBus(); - return TRUE; - } - if (getdata(buf, 16)) { - sspReleaseBus(); - return TRUE; - } - sspReleaseBus(); - - /* csize * multiplier */ - data->csize = (((buf[6] & 3) << 10) | (buf[7] << 2) | (buf[8] >> 6)) * - (1 << (2 + (((buf[9] & 3) << 1) | (buf[10] >> 7)))); - data->rdblklen = 1 << (buf[5] & 15); - return FALSE; -} - -/* - * Reads a block. - * @param blknum the block number - * @param buf the pointer to the read buffer - * @return \p TRUE if an error happened - */ -bool_t mmcRead(uint8_t *buf, uint32_t blknum) { - - sspAcquireBus(); - sendhdr(CMDREAD, blknum << 9); - if (recvr1() != 0x00) { - sspReleaseBus(); - return TRUE; - } - if (getdata(buf, 512)) { - sspReleaseBus(); - return TRUE; - } - sspReleaseBus(); - return FALSE; -} - -/* - * Reads multiple blocks. - * @param blknum the initial block - * @param n the number of blocks - * @param buf the pointer to the read buffer - * @return \p TRUE if an error happened - */ -bool_t mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { - static const uint8_t stopcmd[] = {0x40 | CMDSTOP, 0, 0, 0, 0, 1, 0xFF}; - - sspAcquireBus(); - sendhdr(CMDREADMULTIPLE, blknum << 9); - if (recvr1() != 0x00) { - sspReleaseBus(); - return TRUE; - } - while (n) { - if (getdata(buf, 512)) { - sspReleaseBus(); - return TRUE; - } - buf += 512; - n--; - } - sspRW(NULL, (uint8_t *)stopcmd, sizeof(stopcmd)); - if (recvr1() != 0x00) { - sspReleaseBus(); - return TRUE; - } - sspReleaseBus(); - return FALSE; -} - -/* - * Writes a block. - * @param blknum the block number - * @param buf the pointer to the write buffer - * @return \p TRUE if an error happened - * @note The function DOES NOT wait for the SPI bus to become free after - * sending the data, the bus check is done before sending commands to - * the card, this allows to not make useless busy waiting. The invoking - * thread can do other things while the data is being written. - */ -bool_t mmcWrite(uint8_t *buf, uint32_t blknum) { - static const uint8_t start[] = {0xFF, 0xFE}; - uint8_t b[4]; - - sspAcquireBus(); - sendhdr(CMDWRITE, blknum << 9); - if (recvr1() != 0x00) { - sspReleaseBus(); - return TRUE; - } - sspRW(NULL, (uint8_t *)start, 2); /* Data prologue.*/ - sspRW(NULL, buf, 512); /* Data.*/ - sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ - sspRW(b, NULL, 1); - sspReleaseBus(); - if ((b[0] & 0x1F) != 0x05) - return TRUE; - return FALSE; -} - -/* - * Writes multiple blocks. - * @param blknum the initial block - * @param n the number of blocks - * @param buf the pointer to the write buffer - * @return \p TRUE if an error happened - * @note The function DOES NOT wait for the SPI bus to become free after - * sending the data, the bus check is done before sending commands to - * the card, this allows to not make useless busy waiting. The invoking - * thread can do other things while the data is being written. - */ -bool_t mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n) { - static const uint8_t start[] = {0xFF, 0xFC}, - stop[] = {0xFD, 0xFF}; - uint8_t b[4]; - - sspAcquireBus(); - sendhdr(CMDWRITEMULTIPLE, blknum << 9); - if (recvr1() != 0x00) { - sspReleaseBus(); - return TRUE; - } - while (n) { - sspRW(NULL, (uint8_t *)start, sizeof(start)); /* Data prologue.*/ - sspRW(NULL, buf, 512); /* Data.*/ - sspRW(NULL, NULL, 2); /* CRC ignored in this version.*/ - sspRW(b, NULL, 1); - if ((b[0] & 0x1F) != 0x05) { - sspReleaseBus(); - return TRUE; - } - wait(); - buf += 512; - n--; - } - sspRW(NULL, (uint8_t *)stop, sizeof(stop)); /* Stops the transfer.*/ - sspReleaseBus(); - return FALSE; -} - -/* - * Makes sure that pending operations are completed before returning. - */ -void mmcSynch(void) { - uint8_t buf[4]; - - sspAcquireBus(); - while (TRUE) { - sspRW(buf, NULL, 1); - if (buf[0] == 0xFF) - break; -#ifdef NICE_WAITING - chThdSleep(1); /* Trying to be nice with the other threads.*/ -#endif - } - sspReleaseBus(); -} diff --git a/demos/ARM7-LPC214x-GCC/mmcsd.h b/demos/ARM7-LPC214x-GCC/mmcsd.h deleted file mode 100644 index d7ab4b348..000000000 --- a/demos/ARM7-LPC214x-GCC/mmcsd.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _MMCSD_H_ -#define _MMCSD_H_ - -#define NICE_WAITING - -#define CMD0_RETRY 10 -#define CMD1_RETRY 100 -#define POLLING_INTERVAL 10 -#define MMC_WAIT_DATA 10000 - -#define CMDGOIDLE 0 -#define CMDINIT 1 -#define CMDREADCSD 9 -#define CMDSTOP 12 -#define CMDREAD 17 -#define CMDREADMULTIPLE 18 -#define CMDWRITE 24 -#define CMDWRITEMULTIPLE 25 - -typedef struct { - uint32_t csize; - uint32_t rdblklen; -} MMCCSD; - -extern EventSource MMCInsertEventSource, MMCRemoveEventSource; - -#ifdef __cplusplus -} -#endif - void InitMMC(void); - - bool_t mmcInit(void); - void mmcStartPolling(void); - void mmcStopPolling(void); - bool_t mmcCardInserted (void); - uint8_t mmcSendCommand(uint8_t cmd, uint32_t arg); - bool_t mmcGetSize(MMCCSD *data); - bool_t mmcRead(uint8_t *buf, uint32_t blknum); - bool_t mmcReadMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); - bool_t mmcWrite(uint8_t *buf, uint32_t blknum); - bool_t mmcWriteMultiple(uint8_t *buf, uint32_t blknum, uint32_t n); - void mmcSynch(void); -#ifdef __cplusplus -} -#endif - -#endif /* _MMCSD_H_*/ -- cgit v1.2.3 From fc3ab8ef0728a38959a8fd9f9a1c632cafdc74f7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Dec 2009 14:13:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1449 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FatFS-GCC/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FatFS-GCC/Makefile b/demos/ARM7-LPC214x-FatFS-GCC/Makefile index f361c8d2a..adc7d7d68 100644 --- a/demos/ARM7-LPC214x-FatFS-GCC/Makefile +++ b/demos/ARM7-LPC214x-FatFS-GCC/Makefile @@ -59,8 +59,9 @@ CSRC = $(PORTSRC) \ $(TESTSRC) \ $(HALSRC) \ $(PLATFORMSRC) \ - $(BOARDSRC) \ $(FATFSSRC) \ + $(BOARDSRC) \ + ${BOARDPATH}/buzzer.c \ $(CHIBIOS)/os/various/evtimer.c \ $(CHIBIOS)/os/various/syscalls.c \ main.c -- cgit v1.2.3 From ae7fab31a0d6d8714b94ecce2d54feda7f29f198 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 20 Dec 2009 14:17:58 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1450 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/Makefile | 189 +++++++++++++ demos/ARM7-LPC214x-FATFS-GCC/ch.ld | 101 +++++++ demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 464 ++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 96 +++++++ demos/ARM7-LPC214x-FATFS-GCC/main.c | 275 +++++++++++++++++++ demos/ARM7-LPC214x-FATFS-GCC/readme.txt | 19 ++ demos/ARM7-LPC214x-FatFS-GCC/Makefile | 189 ------------- demos/ARM7-LPC214x-FatFS-GCC/ch.ld | 101 ------- demos/ARM7-LPC214x-FatFS-GCC/chconf.h | 464 -------------------------------- demos/ARM7-LPC214x-FatFS-GCC/halconf.h | 96 ------- demos/ARM7-LPC214x-FatFS-GCC/main.c | 275 ------------------- demos/ARM7-LPC214x-FatFS-GCC/readme.txt | 19 -- 12 files changed, 1144 insertions(+), 1144 deletions(-) create mode 100644 demos/ARM7-LPC214x-FATFS-GCC/Makefile create mode 100644 demos/ARM7-LPC214x-FATFS-GCC/ch.ld create mode 100644 demos/ARM7-LPC214x-FATFS-GCC/chconf.h create mode 100644 demos/ARM7-LPC214x-FATFS-GCC/halconf.h create mode 100644 demos/ARM7-LPC214x-FATFS-GCC/main.c create mode 100644 demos/ARM7-LPC214x-FATFS-GCC/readme.txt delete mode 100644 demos/ARM7-LPC214x-FatFS-GCC/Makefile delete mode 100644 demos/ARM7-LPC214x-FatFS-GCC/ch.ld delete mode 100644 demos/ARM7-LPC214x-FatFS-GCC/chconf.h delete mode 100644 demos/ARM7-LPC214x-FatFS-GCC/halconf.h delete mode 100644 demos/ARM7-LPC214x-FatFS-GCC/main.c delete mode 100644 demos/ARM7-LPC214x-FatFS-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile new file mode 100644 index 000000000..adc7d7d68 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -0,0 +1,189 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk +include $(CHIBIOS)/ext/fatfs/fatfs.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(FATFSSRC) \ + $(BOARDSRC) \ + ${BOARDPATH}/buzzer.c \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +TRGT = arm-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-FATFS-GCC/ch.ld b/demos/ARM7-LPC214x-FATFS-GCC/ch.ld new file mode 100644 index 000000000..9dd4d388e --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/ch.ld @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC2148 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 512k - 12k + ram : org = 0x40000200, len = 32k - 0x200 - 288 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; +__dma_start__ = 0x7FD00000; +__dma_size__ = 8k; +__dma_end__ = 0x7FD00000 + __dma_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h new file mode 100644 index 000000000..3b29983cb --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -0,0 +1,464 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @addtogroup config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented or some ports. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h new file mode 100644 index 000000000..6fb0e97fa --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c new file mode 100644 index 000000000..70d1605bf --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -0,0 +1,275 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "evtimer.h" +#include "buzzer.h" + +#include "ff.h" + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0).*/ +static SPIConfig hs_spicfg = { + IOPORT1, + PA_SSEL1, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 0, + 2 +}; + +/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0).*/ +static SPIConfig ls_spicfg = { + IOPORT1, + PA_SSEL1, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 0, + 254 +}; + +/* MMC configuration (empty).*/ +static const MMCConfig mmc_cfg = {}; + +/* Card insertion verification.*/ +static bool_t mmc_is_inserted(void) { + return !palReadPad(IOPORT2, PB_CP1); +} + +/* Card protection verification.*/ +static bool_t mmc_is_protected(void) { + return palReadPad(IOPORT2, PB_WP1); +} + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); + chThdSleepMilliseconds(200); + palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); + chThdSleepMilliseconds(800); + } + return 0; +} + +/* + * Yellow LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(200); + palSetPad(IOPORT1, PA_LEDUSB); + chThdSleepMilliseconds(300); + } + return 0; +} + +static FRESULT scan_files(char *path) +{ + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + siprintf(&path[i], "/%s", fn); + res = scan_files(path); + if (res != FR_OK) + break; + path[i] = 0; + } + else { + iprintf("%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/* + * Executed as event handler at 500mS intervals. + */ +static void TimerHandler(eventid_t id) { + + (void)id; + if (!palReadPad(IOPORT1, PA_BUTTON1)) { + if (fs_ready) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + iprintf("FS: f_getfree() failed\r\n"); + return; + } + iprintf("FS: %lu free clusters, %u sectors per cluster, %lu bytes free\r\n", + clusters, MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); + fbuff[0] = 0; + scan_files((char *)fbuff); + } + } + else if (!palReadPad(IOPORT1, PA_BUTTON2)) { + static WORKING_AREA(waTestThread, 256); + Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), + NORMALPRIO, TestThread, &SD1); + chThdWait(tp); + buzzPlay(500, MS2ST(100)); + } +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + buzzPlayWait(1000, MS2ST(100)); + buzzPlayWait(2000, MS2ST(100)); + iprintf("MMC: inserted\r\n"); + /* + * On insertion MMC initialization and FS mount. + */ + iprintf("MMC: initialization "); + if (mmcConnect(&MMCD1)) { + iprintf("failed\r\n"); + return; + } + iprintf("ok\r\n"); + iprintf("FS: mount "); + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + iprintf("failed\r\n"); + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; + iprintf("ok\r\n"); + buzzPlay(440, MS2ST(200)); +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + iprintf("MMC: removed\r\n"); + fs_ready = FALSE; + buzzPlayWait(2000, MS2ST(100)); + buzzPlayWait(1000, MS2ST(100)); +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + static const evhandler_t evhndl[] = { + TimerHandler, + InsertHandler, + RemoveHandler + }; + static EvTimer evt; + struct EventListener el0, el1, el2; + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Buzzer driver initialization. + */ + buzzInit(); + + /* + * Initializes the MMC driver to work with SPI2. + */ + mmcObjectInit(&MMCD1, &SPID1, + &ls_spicfg, &hs_spicfg, + mmc_is_protected, mmc_is_inserted); + mmcStart(&MMCD1, &mmc_cfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listed for events. + */ + evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ + evtStart(&evt); /* Starts the event timer. */ + chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ + chEvtRegister(&MMCD1.mmc_inserted_event, &el1, 1); + chEvtRegister(&MMCD1.mmc_removed_event, &el2, 2); + while (TRUE)// chThdSleepMilliseconds(50); + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + return 0; +} diff --git a/demos/ARM7-LPC214x-FATFS-GCC/readme.txt b/demos/ARM7-LPC214x-FATFS-GCC/readme.txt new file mode 100644 index 000000000..83abee7c6 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/readme.txt @@ -0,0 +1,19 @@ +***************************************************************************** +** ChibiOS/RT + FatFS demo for LPC214x. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex LPC-P2148 board. The port on other boards or other +members of the LPC2000 family should be an easy task. + +** The Demo ** + +The demo blinks the leds on the board by using multiple threads. +By pressing button 1 a directory scan on the MMC slot is performed, by +pressing the button 2 the test suite is activated on serial port 1. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARM7-LPC214x-FatFS-GCC/Makefile b/demos/ARM7-LPC214x-FatFS-GCC/Makefile deleted file mode 100644 index adc7d7d68..000000000 --- a/demos/ARM7-LPC214x-FatFS-GCC/Makefile +++ /dev/null @@ -1,189 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = no -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk -include $(CHIBIOS)/ext/fatfs/fatfs.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(FATFSSRC) \ - $(BOARDSRC) \ - ${BOARDPATH}/buzzer.c \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(FATFSINC) \ - $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = arm7tdmi - -TRGT = arm-elf- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-LPC214x-FatFS-GCC/ch.ld b/demos/ARM7-LPC214x-FatFS-GCC/ch.ld deleted file mode 100644 index 9dd4d388e..000000000 --- a/demos/ARM7-LPC214x-FatFS-GCC/ch.ld +++ /dev/null @@ -1,101 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * LPC2148 memory setup. - */ -__und_stack_size__ = 0x0004; -__abt_stack_size__ = 0x0004; -__fiq_stack_size__ = 0x0010; -__irq_stack_size__ = 0x0080; -__svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0400; -__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 512k - 12k - ram : org = 0x40000200, len = 32k - 0x200 - 288 -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; -__dma_start__ = 0x7FD00000; -__dma_size__ = 8k; -__dma_end__ = 0x7FD00000 + __dma_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)) - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash - - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram - - /DISCARD/ : - { - *(.eh_*) - } -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-LPC214x-FatFS-GCC/chconf.h b/demos/ARM7-LPC214x-FatFS-GCC/chconf.h deleted file mode 100644 index 3b29983cb..000000000 --- a/demos/ARM7-LPC214x-FatFS-GCC/chconf.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @addtogroup config - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. - * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/ARM7-LPC214x-FatFS-GCC/halconf.h b/demos/ARM7-LPC214x-FatFS-GCC/halconf.h deleted file mode 100644 index 6fb0e97fa..000000000 --- a/demos/ARM7-LPC214x-FatFS-GCC/halconf.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE -#endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE -#endif - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/demos/ARM7-LPC214x-FatFS-GCC/main.c b/demos/ARM7-LPC214x-FatFS-GCC/main.c deleted file mode 100644 index 70d1605bf..000000000 --- a/demos/ARM7-LPC214x-FatFS-GCC/main.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "evtimer.h" -#include "buzzer.h" - -#include "ff.h" - -/** - * @brief FS object. - */ -FATFS MMC_FS; - -/** - * MMC driver instance. - */ -MMCDriver MMCD1; - -/* FS mounted and ready.*/ -static bool_t fs_ready = FALSE; - -/* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0).*/ -static SPIConfig hs_spicfg = { - IOPORT1, - PA_SSEL1, - CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), - 0, - 2 -}; - -/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0).*/ -static SPIConfig ls_spicfg = { - IOPORT1, - PA_SSEL1, - CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), - 0, - 254 -}; - -/* MMC configuration (empty).*/ -static const MMCConfig mmc_cfg = {}; - -/* Card insertion verification.*/ -static bool_t mmc_is_inserted(void) { - return !palReadPad(IOPORT2, PB_CP1); -} - -/* Card protection verification.*/ -static bool_t mmc_is_protected(void) { - return palReadPad(IOPORT2, PB_WP1); -} - -/* Generic large buffer.*/ -uint8_t fbuff[1024]; - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - palClearPort(IOPORT1, PAL_PORT_BIT(PA_LED1)); - chThdSleepMilliseconds(200); - palSetPort(IOPORT1, PAL_PORT_BIT(PA_LED1) | PAL_PORT_BIT(PA_LED2)); - chThdSleepMilliseconds(800); - } - return 0; -} - -/* - * Yellow LED blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread2, 128); -static msg_t Thread2(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(200); - palSetPad(IOPORT1, PA_LEDUSB); - chThdSleepMilliseconds(300); - } - return 0; -} - -static FRESULT scan_files(char *path) -{ - FRESULT res; - FILINFO fno; - DIR dir; - int i; - char *fn; - - res = f_opendir(&dir, path); - if (res == FR_OK) { - i = strlen(path); - for (;;) { - res = f_readdir(&dir, &fno); - if (res != FR_OK || fno.fname[0] == 0) - break; - if (fno.fname[0] == '.') - continue; - fn = fno.fname; - if (fno.fattrib & AM_DIR) { - siprintf(&path[i], "/%s", fn); - res = scan_files(path); - if (res != FR_OK) - break; - path[i] = 0; - } - else { - iprintf("%s/%s\r\n", path, fn); - } - } - } - return res; -} - -/* - * Executed as event handler at 500mS intervals. - */ -static void TimerHandler(eventid_t id) { - - (void)id; - if (!palReadPad(IOPORT1, PA_BUTTON1)) { - if (fs_ready) { - FRESULT err; - uint32_t clusters; - FATFS *fsp; - - err = f_getfree("/", &clusters, &fsp); - if (err != FR_OK) { - iprintf("FS: f_getfree() failed\r\n"); - return; - } - iprintf("FS: %lu free clusters, %u sectors per cluster, %lu bytes free\r\n", - clusters, MMC_FS.csize, - clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); - fbuff[0] = 0; - scan_files((char *)fbuff); - } - } - else if (!palReadPad(IOPORT1, PA_BUTTON2)) { - static WORKING_AREA(waTestThread, 256); - Thread *tp = chThdCreateStatic(waTestThread, sizeof(waTestThread), - NORMALPRIO, TestThread, &SD1); - chThdWait(tp); - buzzPlay(500, MS2ST(100)); - } -} - -/* - * MMC card insertion event. - */ -static void InsertHandler(eventid_t id) { - FRESULT err; - - (void)id; - buzzPlayWait(1000, MS2ST(100)); - buzzPlayWait(2000, MS2ST(100)); - iprintf("MMC: inserted\r\n"); - /* - * On insertion MMC initialization and FS mount. - */ - iprintf("MMC: initialization "); - if (mmcConnect(&MMCD1)) { - iprintf("failed\r\n"); - return; - } - iprintf("ok\r\n"); - iprintf("FS: mount "); - err = f_mount(0, &MMC_FS); - if (err != FR_OK) { - iprintf("failed\r\n"); - mmcDisconnect(&MMCD1); - return; - } - fs_ready = TRUE; - iprintf("ok\r\n"); - buzzPlay(440, MS2ST(200)); -} - -/* - * MMC card removal event. - */ -static void RemoveHandler(eventid_t id) { - - (void)id; - iprintf("MMC: removed\r\n"); - fs_ready = FALSE; - buzzPlayWait(2000, MS2ST(100)); - buzzPlayWait(1000, MS2ST(100)); -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - static const evhandler_t evhndl[] = { - TimerHandler, - InsertHandler, - RemoveHandler - }; - static EvTimer evt; - struct EventListener el0, el1, el2; - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD1, NULL); - - /* - * Buzzer driver initialization. - */ - buzzInit(); - - /* - * Initializes the MMC driver to work with SPI2. - */ - mmcObjectInit(&MMCD1, &SPID1, - &ls_spicfg, &hs_spicfg, - mmc_is_protected, mmc_is_inserted); - mmcStart(&MMCD1, &mmc_cfg); - - /* - * Creates the blinker threads. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and listed for events. - */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - chEvtRegister(&MMCD1.mmc_inserted_event, &el1, 1); - chEvtRegister(&MMCD1.mmc_removed_event, &el2, 2); - while (TRUE)// chThdSleepMilliseconds(50); - chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); - return 0; -} diff --git a/demos/ARM7-LPC214x-FatFS-GCC/readme.txt b/demos/ARM7-LPC214x-FatFS-GCC/readme.txt deleted file mode 100644 index 83abee7c6..000000000 --- a/demos/ARM7-LPC214x-FatFS-GCC/readme.txt +++ /dev/null @@ -1,19 +0,0 @@ -***************************************************************************** -** ChibiOS/RT + FatFS demo for LPC214x. ** -***************************************************************************** - -** TARGET ** - -The demo runs on an Olimex LPC-P2148 board. The port on other boards or other -members of the LPC2000 family should be an easy task. - -** The Demo ** - -The demo blinks the leds on the board by using multiple threads. -By pressing button 1 a directory scan on the MMC slot is performed, by -pressing the button 2 the test suite is activated on serial port 1. - -** Build Procedure ** - -The demo was built using the YAGARTO toolchain but any toolchain based on GCC -and GNU userspace programs will work. -- cgit v1.2.3 From a2e989330ef587868921bf9ebc8079f939e57ad5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Dec 2009 20:11:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1460 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/Makefile | 26 ++++-- demos/GNU-Linux-GCC/board.h | 23 +++++ demos/GNU-Linux-GCC/chconf.h | 6 +- demos/GNU-Linux-GCC/halconf.h | 96 +++++++++++++++++++++ demos/GNU-Linux-GCC/main.c | 191 ++++++++++++++++++++++++++++++++++++++--- demos/GNU-Linux-GCC/readme.txt | 17 +++- 6 files changed, 334 insertions(+), 25 deletions(-) create mode 100644 demos/GNU-Linux-GCC/board.h create mode 100644 demos/GNU-Linux-GCC/halconf.h (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/Makefile b/demos/GNU-Linux-GCC/Makefile index 51a8b25db..6e433a990 100644 --- a/demos/GNU-Linux-GCC/Makefile +++ b/demos/GNU-Linux-GCC/Makefile @@ -16,12 +16,12 @@ # Start of default section # -TRGT = +TRGT = CC = $(TRGT)gcc AS = $(TRGT)gcc -x assembler-with-cpp # List all default C defines here, like -D_DEBUG=1 -DDEFS = +DDEFS = -DSHELL_USE_IPRINTF=FALSE # List all default ASM defines here, like -D_DEBUG=1 DADEFS = @@ -47,7 +47,7 @@ DLIBS = PROJECT = ch # Define linker script file here -LDSCRIPT= +LDSCRIPT = # List all user C define here, like -D_DEBUG=1 UDEFS = @@ -57,19 +57,27 @@ UADEFS = # Imported source files CHIBIOS = ../.. -include ${CHIBIOS}/src/kernel.mk +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/Linux/platform.mk +include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk # List C source files here -SRC = chcore.c main.c \ +SRC = ${PORTSRC} \ ${KERNSRC} \ - ${TESTSRC} + ${TESTSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ + ${CHIBIOS}/os/various/shell.c \ + main.c # List ASM source files here ASRC = # List all user directories here -UINCDIR = ${CHIBIOS}/src/include +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ + ${CHIBIOS}/os/various # List the user directory to look for the libraries here ULIBDIR = @@ -94,7 +102,7 @@ LIBS = $(DLIBS) $(ULIBS) LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d @@ -119,7 +127,7 @@ gcov: $(COV) -u $(subst /,\,$(SRC)) -mv *.gcov ./gcov -clean: +clean: -rm -f $(OBJS) -rm -f $(PROJECT) -rm -f $(PROJECT).map diff --git a/demos/GNU-Linux-GCC/board.h b/demos/GNU-Linux-GCC/board.h new file mode 100644 index 000000000..a6e056d58 --- /dev/null +++ b/demos/GNU-Linux-GCC/board.h @@ -0,0 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#endif /* _BOARD_H_ */ diff --git a/demos/GNU-Linux-GCC/chconf.h b/demos/GNU-Linux-GCC/chconf.h index 845ed5d9b..2c3a29a30 100644 --- a/demos/GNU-Linux-GCC/chconf.h +++ b/demos/GNU-Linux-GCC/chconf.h @@ -37,7 +37,7 @@ * setting also defines the system tick time unit. */ #if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 100 +#define CH_FREQUENCY 1000 #endif /** @@ -80,7 +80,7 @@ * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 +#define CH_MEMCORE_SIZE 0x20000 #endif /*===========================================================================*/ @@ -459,6 +459,8 @@ struct { \ } #endif +#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h new file mode 100644 index 000000000..a3d17a3c9 --- /dev/null +++ b/demos/GNU-Linux-GCC/halconf.h @@ -0,0 +1,96 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to change the device drivers settings found in the low level drivers + * headers, just define here the new settings and those will override the + * defaults defined in the LLD headers. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c index 07e16625c..c969f2208 100644 --- a/demos/GNU-Linux-GCC/main.c +++ b/demos/GNU-Linux-GCC/main.c @@ -20,34 +20,203 @@ #include #include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" -static WORKING_AREA(waThread1, 2048); -static msg_t Thread1(void *arg) { +#define SHELL_WA_SIZE THD_WA_SIZE(4096) +#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) +#define TEST_WA_SIZE THD_WA_SIZE(4096) - while (TRUE) { - chThdSleepMilliseconds(1000); - printf("-\n"); +#define cprint(msg) chMsgSend(cdtp, (msg_t)msg) + +static Thread *cdtp; +static Thread *shelltp1; +static Thread *shelltp2; + +void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: test"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + shellPrintLine(chp, "out of memory"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD1, + commands +}; + +static const ShellConfig shell_cfg2 = { + (BaseChannel *)&SD2, + commands +}; + +/* + * Console print server done using synchronous messages. This makes the access + * to the C printf() thread safe and the print operation atomic among threads. + * In this example the message is the zero termitated string itself. + */ +static msg_t console_thread(void *arg) { + + (void)arg; + while (!chThdShouldTerminate()) { + puts((char *)chMsgWait()); + fflush(stdout); + chMsgRelease(RDY_OK); } return 0; } +/** + * @brief Shell termination handler. + * + * @param[in] id event id. + */ +static void termination_handler(eventid_t id) { + + (void)id; + if (shelltp1 && chThdTerminated(shelltp1)) { + chThdWait(shelltp1); + shelltp1 = NULL; + chThdSleepMilliseconds(10); + cprint("Init: shell on SD1 terminated\n"); + chSysLock(); + chOQResetI(&SD1.d2.oqueue); + chSysUnlock(); + } + if (shelltp2 && chThdTerminated(shelltp2)) { + chThdWait(shelltp2); + shelltp2 = NULL; + chThdSleepMilliseconds(10); + cprint("Init: shell on SD2 terminated\n"); + chSysLock(); + chOQResetI(&SD2.d2.oqueue); + chSysUnlock(); + } +} + +/** + * @brief SD1 status change handler. + * + * @param[in] id event id. + */ +static void sd1_handler(eventid_t id) { + + sdflags_t flags; + + (void)id; + flags = sdGetAndClearFlags(&SD1); + if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { + cprint("Init: connection on SD1\n"); + shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); + } + if (flags & SD_DISCONNECTED) { + cprint("Init: disconnection on SD1\n"); + chSysLock(); + chIQResetI(&SD1.d2.iqueue); + chSysUnlock(); + } +} + +/** + * @brief SD2 status change handler. + * + * @param[in] id event id. + */ +static void sd2_handler(eventid_t id) { + + sdflags_t flags; + + (void)id; + flags = sdGetAndClearFlags(&SD2); + if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { + cprint("Init: connection on SD2\n"); + shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); + } + if (flags & SD_DISCONNECTED) { + cprint("Init: disconnection on SD2\n"); + chSysLock(); + chIQResetI(&SD2.d2.iqueue); + chSysUnlock(); + } +} + +static evhandler_t fhandlers[] = { + termination_handler, + sd1_handler, + sd2_handler +}; + /*------------------------------------------------------------------------* - * Simulator main, start here your threads, examples inside. * + * Simulator main. * *------------------------------------------------------------------------*/ int main(void) { + EventListener sd1fel, sd2fel, tel; + + /* + * HAL initialization. + */ + halInit(); /* - * ChibiOS/RT initialization. + * ChibiOS/RT initialization. */ chSysInit(); /* - * Starting threads. + * Serial ports (simulated) initialization. */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + sdStart(&SD1, NULL); + sdStart(&SD2, NULL); - while (TRUE) - chThdSleepSeconds(1); + /* + * Shell manager initialization. + */ + shellInit(); + chEvtRegister(&shell_terminated, &tel, 0); + /* + * Console thread started. + */ + cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, + console_thread, NULL); + + /* + * Initializing connection/disconnection events. + */ + cprint("Shell service started on SD1, SD2\n"); + cprint(" - Listening for connections on SD1\n"); + (void) sdGetAndClearFlags(&SD1); + chEvtRegister(&SD1.d2.sevent, &sd1fel, 1); + cprint(" - Listening for connections on SD2\n"); + (void) sdGetAndClearFlags(&SD2); + chEvtRegister(&SD2.d2.sevent, &sd2fel, 2); + + /* + * Events servicing loop. + */ + while (!chThdShouldTerminate()) + chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); + + /* + * Clean simulator exit. + */ + chEvtUnregister(&SD1.d2.sevent, &sd1fel); + chEvtUnregister(&SD2.d2.sevent, &sd2fel); return 0; } diff --git a/demos/GNU-Linux-GCC/readme.txt b/demos/GNU-Linux-GCC/readme.txt index 601358952..7db17cfa6 100644 --- a/demos/GNU-Linux-GCC/readme.txt +++ b/demos/GNU-Linux-GCC/readme.txt @@ -4,12 +4,23 @@ ** TARGET ** -The demo runs under Linux as an application program. +The demo runs under x86 Linux as an application program. The serial +I/O is simulated over TCP/IP sockets. ** The Demo ** -The demo just creates a thread. It is not complete yet. +The demo listens on the two serial ports, when a connection is detected a +thread is started that serves a small command shell. +The demo shows how create/terminate threads at runtime, how listen to events, +how ho work with serial ports, how use the messages. +You can develop your ChibiOS/RT application using this demo as a simulator +then you can recompile it for a different architecture. +See demo.c for details. ** Build Procedure ** -Makefile. +GCC required. + +** Connect to the demo ** + +In order to connect to the demo use telnet on the listening ports. -- cgit v1.2.3 From 8f30bbcc3488a2c92a40e7912716627169637232 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 23 Dec 2009 20:23:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1462 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/chcore.c | 108 ---------------------- demos/GNU-Linux-GCC/chcore.h | 209 ------------------------------------------- 2 files changed, 317 deletions(-) delete mode 100644 demos/GNU-Linux-GCC/chcore.c delete mode 100644 demos/GNU-Linux-GCC/chcore.h (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/chcore.c b/demos/GNU-Linux-GCC/chcore.c deleted file mode 100644 index 6185b8f4e..000000000 --- a/demos/GNU-Linux-GCC/chcore.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include -#include -#include -#include - -/** - * @addtogroup LINUXSIM_CORE - * @{ - */ - -#include "ch.h" - -static struct itimerval tempo; -static bool_t pending = FALSE; - -void timer(int numSignal) { - - pending = TRUE; -} - -/* - * Simulated HW initialization. - */ -void _init_core(void) { - - signal(SIGALRM, timer); - tempo.it_value.tv_sec = 0; - tempo.it_value.tv_usec = 10000; - tempo.it_interval.tv_sec = 0; - tempo.it_interval.tv_usec = 10000; - setitimer(ITIMER_REAL, &tempo, NULL); -} - -/* - * Interrupt simulation. - */ -void ChkIntSources(void) { - - if (pending) { - chSysTimerHandlerI(); - pending = FALSE; - } - - if (chSchIsRescRequiredExI()) - chSchDoRescheduleI(); -} - -/** - * Performs a context switch between two threads. - * @param otp the thread to be switched out - * @param ntp the thread to be switched in - */ -__attribute__((used)) -static void __dummy(Thread *otp, Thread *ntp) { - asm volatile (".globl port_switch \n\t" \ - "port_switch: \n\t" \ - "push %ebp \n\t" \ - "push %esi \n\t" \ - "push %edi \n\t" \ - "push %ebx \n\t" \ - "movl %esp, 16(%ecx) \n\t" \ - "movl 16(%edx), %esp \n\t" \ - "pop %ebx \n\t" \ - "pop %edi \n\t" \ - "pop %esi \n\t" \ - "pop %ebp \n\t" \ - "ret"); -} - -/** - * Halts the system. In this implementation it just exits the simulation. - */ -__attribute__((fastcall)) -void port_halt(void) { - - exit(2); -} - -/** - * Threads return point, it just invokes @p chThdExit(). - */ -void threadexit(void) { - - asm volatile ("push %eax \n\t" \ - "call chThdExit"); -} - -/** @} */ diff --git a/demos/GNU-Linux-GCC/chcore.h b/demos/GNU-Linux-GCC/chcore.h deleted file mode 100644 index 48a052513..000000000 --- a/demos/GNU-Linux-GCC/chcore.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @addtogroup WIN32SIM_CORE - * @{ - */ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/** - * Macro defining the a simulated architecture into Win32. - */ -#define CH_ARCHITECTURE_WIN32SIM - -/** - * Name of the implemented architecture. - */ -#define CH_ARCHITECTURE_NAME "WIN32 Simulator" - -/** - * 32 bit stack alignment. - */ -typedef uint32_t stkalign_t; - -/** - * Generic x86 register. - */ -typedef void *regx86; - -/** - * Interrupt saved context. - * This structure represents the stack frame saved during a preemption-capable - * interrupt handler. - */ -struct extctx { -}; - -/** - * System saved context. - * @note In this demo the floating point registers are not saved. - */ -struct intctx { - regx86 ebx; - regx86 edi; - regx86 esi; - regx86 ebp; - regx86 eip; -}; - -/** - * Platform dependent part of the @p Thread structure. - * This structure usually contains just the saved stack pointer defined as a - * pointer to a @p intctx structure. - */ -struct context { - struct intctx volatile *esp; -}; - -#define APUSH(p, a) (p) -= sizeof(void *), *(void **)(p) = (void*)(a) - -/** - * Platform dependent part of the @p chThdInit() API. - * This code usually setup the context switching frame represented by a - * @p intctx structure. - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - uint8_t *esp = (uint8_t *)workspace + wsize; \ - APUSH(esp, arg); \ - APUSH(esp, threadexit); \ - esp -= sizeof(struct intctx); \ - ((struct intctx *)esp)->eip = pf; \ - ((struct intctx *)esp)->ebx = 0; \ - ((struct intctx *)esp)->edi = 0; \ - ((struct intctx *)esp)->esi = 0; \ - ((struct intctx *)esp)->ebp = 0; \ - tp->p_ctx.esp = (struct intctx *)esp; \ -} - -/** - * Stack size for the system idle thread. - */ -#ifndef IDLE_THREAD_STACK_SIZE -#define IDLE_THREAD_STACK_SIZE 256 -#endif - -/** - * Per-thread stack overhead for interrupts servicing, it is used in the - * calculation of the correct working area size. - */ -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 0x8000 -#endif - -/** - * Enforces a correct alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) - - /** - * Computes the thread working area global size. - */ -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(void *) * 2 + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + (INT_REQUIRED_STACK)) - -/** - * Macro used to allocate a thread working area aligned as both position and - * size. - */ -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/** - * IRQ prologue code, inserted at the start of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_PROLOGUE() - -/** - * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to - * invoke system APIs. - */ -#define PORT_IRQ_EPILOGUE() - -/** - * IRQ handler function declaration. - */ -#define PORT_IRQ_HANDLER(id) void id(void) - -/** - * Simulator initialization. - */ -#define port_init() _init_core() - -/** - * Does nothing in this simulator. - */ -#define port_lock() - -/** - * Does nothing in this simulator. - */ -#define port_unlock() - -/** - * Does nothing in this simulator. - */ -#define port_lock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_unlock_from_isr() - -/** - * Does nothing in this simulator. - */ -#define port_disable() - -/** - * Does nothing in this simulator. - */ -#define port_suspend() - -/** - * Does nothing in this simulator. - */ -#define port_enable() - -/** - * In the simulator this does a polling pass on the simulated interrupt - * sources. - */ -#define port_wait_for_interrupt() ChkIntSources() - -#ifdef __cplusplus -extern "C" { -#endif - __attribute__((fastcall)) void port_switch(Thread *otp, Thread *ntp); - __attribute__((fastcall)) void port_halt(void); - void _init_core(void); - void ChkIntSources(void); - void threadexit(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ - -/** @} */ -- cgit v1.2.3 From 0873332c30f78769147f0cb16d71f38ed846a814 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 24 Dec 2009 09:38:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1463 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/Makefile | 2 +- demos/GNU-Linux-GCC/main.c | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/Makefile b/demos/GNU-Linux-GCC/Makefile index 6e433a990..9d38e2637 100644 --- a/demos/GNU-Linux-GCC/Makefile +++ b/demos/GNU-Linux-GCC/Makefile @@ -21,7 +21,7 @@ CC = $(TRGT)gcc AS = $(TRGT)gcc -x assembler-with-cpp # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSHELL_USE_IPRINTF=FALSE +DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c index c969f2208..4153b219a 100644 --- a/demos/GNU-Linux-GCC/main.c +++ b/demos/GNU-Linux-GCC/main.c @@ -28,7 +28,7 @@ #define CONSOLE_WA_SIZE THD_WA_SIZE(4096) #define TEST_WA_SIZE THD_WA_SIZE(4096) -#define cprint(msg) chMsgSend(cdtp, (msg_t)msg) +#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) static Thread *cdtp; static Thread *shelltp1; @@ -94,7 +94,7 @@ static void termination_handler(eventid_t id) { chThdWait(shelltp1); shelltp1 = NULL; chThdSleepMilliseconds(10); - cprint("Init: shell on SD1 terminated\n"); + cputs("Init: shell on SD1 terminated"); chSysLock(); chOQResetI(&SD1.d2.oqueue); chSysUnlock(); @@ -103,7 +103,7 @@ static void termination_handler(eventid_t id) { chThdWait(shelltp2); shelltp2 = NULL; chThdSleepMilliseconds(10); - cprint("Init: shell on SD2 terminated\n"); + cputs("Init: shell on SD2 terminated"); chSysLock(); chOQResetI(&SD2.d2.oqueue); chSysUnlock(); @@ -122,11 +122,11 @@ static void sd1_handler(eventid_t id) { (void)id; flags = sdGetAndClearFlags(&SD1); if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { - cprint("Init: connection on SD1\n"); + cputs("Init: connection on SD1"); shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); } if (flags & SD_DISCONNECTED) { - cprint("Init: disconnection on SD1\n"); + cputs("Init: disconnection on SD1"); chSysLock(); chIQResetI(&SD1.d2.iqueue); chSysUnlock(); @@ -145,11 +145,11 @@ static void sd2_handler(eventid_t id) { (void)id; flags = sdGetAndClearFlags(&SD2); if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { - cprint("Init: connection on SD2\n"); + cputs("Init: connection on SD2"); shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); } if (flags & SD_DISCONNECTED) { - cprint("Init: disconnection on SD2\n"); + cputs("Init: disconnection on SD2"); chSysLock(); chIQResetI(&SD2.d2.iqueue); chSysUnlock(); @@ -199,11 +199,11 @@ int main(void) { /* * Initializing connection/disconnection events. */ - cprint("Shell service started on SD1, SD2\n"); - cprint(" - Listening for connections on SD1\n"); + cputs("Shell service started on SD1, SD2"); + cputs(" - Listening for connections on SD1"); (void) sdGetAndClearFlags(&SD1); chEvtRegister(&SD1.d2.sevent, &sd1fel, 1); - cprint(" - Listening for connections on SD2\n"); + cputs(" - Listening for connections on SD2"); (void) sdGetAndClearFlags(&SD2); chEvtRegister(&SD2.d2.sevent, &sd2fel, 2); -- cgit v1.2.3 From 5d22110eeb4b5a9999ae259b7384a4608e725490 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 24 Dec 2009 09:57:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1465 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 2 +- demos/Win32-MinGW/main.c | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index 76362dec1..c1a452297 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -21,7 +21,7 @@ CC = $(TRGT)gcc AS = $(TRGT)gcc -x assembler-with-cpp # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSHELL_USE_IPRINTF=FALSE +DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 01ca7cad9..009ec4a89 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -26,7 +26,7 @@ #define CONSOLE_WA_SIZE THD_WA_SIZE(4096) #define TEST_WA_SIZE THD_WA_SIZE(4096) -#define cprint(msg) chMsgSend(cdtp, (msg_t)msg) +#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) static Thread *cdtp; static Thread *shelltp1; @@ -73,7 +73,7 @@ static msg_t console_thread(void *arg) { (void)arg; while (!chThdShouldTerminate()) { - printf((char *)chMsgWait()); + puts((char *)chMsgWait()); fflush(stdout); chMsgRelease(RDY_OK); } @@ -92,7 +92,7 @@ static void termination_handler(eventid_t id) { chThdWait(shelltp1); shelltp1 = NULL; chThdSleepMilliseconds(10); - cprint("Init: shell on SD1 terminated\n"); + cputs("Init: shell on SD1 terminated"); chSysLock(); chOQResetI(&SD1.d2.oqueue); chSysUnlock(); @@ -101,7 +101,7 @@ static void termination_handler(eventid_t id) { chThdWait(shelltp2); shelltp2 = NULL; chThdSleepMilliseconds(10); - cprint("Init: shell on SD2 terminated\n"); + cputs("Init: shell on SD2 terminated"); chSysLock(); chOQResetI(&SD2.d2.oqueue); chSysUnlock(); @@ -119,11 +119,11 @@ static void sd1_handler(eventid_t id) { (void)id; flags = sdGetAndClearFlags(&SD1); if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { - cprint("Init: connection on SD1\n"); + cputs("Init: connection on SD1"); shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); } if (flags & SD_DISCONNECTED) { - cprint("Init: disconnection on SD1\n"); + cputs("Init: disconnection on SD1"); chSysLock(); chIQResetI(&SD1.d2.iqueue); chSysUnlock(); @@ -141,11 +141,11 @@ static void sd2_handler(eventid_t id) { (void)id; flags = sdGetAndClearFlags(&SD2); if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { - cprint("Init: connection on SD2\n"); + cputs("Init: connection on SD2"); shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); } if (flags & SD_DISCONNECTED) { - cprint("Init: disconnection on SD2\n"); + cputs("Init: disconnection on SD2"); chSysLock(); chIQResetI(&SD2.d2.iqueue); chSysUnlock(); @@ -195,11 +195,11 @@ int main(void) { /* * Initializing connection/disconnection events. */ - cprint("Shell service started on SD1, SD2\n"); - cprint(" - Listening for connections on SD1\n"); + cputs("Shell service started on SD1, SD2"); + cputs(" - Listening for connections on SD1"); (void) sdGetAndClearFlags(&SD1); chEvtRegister(&SD1.d2.sevent, &sd1fel, 1); - cprint(" - Listening for connections on SD2\n"); + cputs(" - Listening for connections on SD2"); (void) sdGetAndClearFlags(&SD2); chEvtRegister(&SD2.d2.sevent, &sd2fel, 2); -- cgit v1.2.3 From d1ebc8d984433f27b0df9f55c89c0c0763cee838 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 24 Dec 2009 09:59:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1466 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/chtypes.h | 47 ------------------------------------------- 1 file changed, 47 deletions(-) delete mode 100644 demos/GNU-Linux-GCC/chtypes.h (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/chtypes.h b/demos/GNU-Linux-GCC/chtypes.h deleted file mode 100644 index 354da269e..000000000 --- a/demos/GNU-Linux-GCC/chtypes.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHTYPES_H_ -#define _CHTYPES_H_ - -#define __need_NULL -#define __need_size_t -#define __need_ptrdiff_t -#include - -#if !defined(_STDINT_H) && !defined(__STDINT_H_) -#include -#endif - -typedef int8_t bool_t; -typedef uint8_t tmode_t; -typedef uint8_t tstate_t; -typedef uint32_t tprio_t; -typedef int32_t msg_t; -typedef int32_t eventid_t; -typedef uint32_t eventmask_t; -typedef uint32_t systime_t; -typedef int32_t cnt_t; - -#define INLINE inline -#define PACK_STRUCT_STRUCT __attribute__((packed)) -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_END - -#endif /* _CHTYPES_H_ */ -- cgit v1.2.3 From da565f622c53f2fb23c1d66332ee764e44361ea3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 29 Dec 2009 16:22:45 +0000 Subject: New HAL configuration file ported to all demos. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1482 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/halconf.h | 67 +++++++++++++++++++++++++++++- demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 67 +++++++++++++++++++++++++++++- demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 67 +++++++++++++++++++++++++++++- demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 56 +++++++++++++++++++++++-- demos/ARM7-LPC214x-G++/halconf.h | 56 +++++++++++++++++++++++-- demos/ARM7-LPC214x-GCC/halconf.h | 56 +++++++++++++++++++++++-- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 56 +++++++++++++++++++++++-- demos/ARMCM3-STM32F103-GCC/halconf.h | 56 +++++++++++++++++++++++-- demos/AVR-AT90CANx-GCC/halconf.h | 56 +++++++++++++++++++++++-- demos/AVR-ATmega128-GCC/halconf.h | 56 +++++++++++++++++++++++-- demos/GNU-Linux-GCC/halconf.h | 56 +++++++++++++++++++++++-- demos/MSP430-MSP430x1611-GCC/halconf.h | 67 +++++++++++++++++++++++++++++- demos/Win32-MinGW/halconf.h | 56 +++++++++++++++++++++++-- 13 files changed, 741 insertions(+), 31 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index 2faba92d8..b7b320a58 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -20,13 +20,30 @@ /** * @file templates/halconf.h * @brief HAL configuration header. - * @addtogroup HAL + * @addtogroup HAL_CONF * @{ */ +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -34,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -41,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -48,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -55,6 +84,21 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -62,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -69,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -76,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 9f7060cf3..06f5de243 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -20,13 +20,30 @@ /** * @file templates/halconf.h * @brief HAL configuration header. - * @addtogroup HAL + * @addtogroup HAL_CONF * @{ */ +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -34,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -41,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -48,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -55,6 +84,21 @@ #define CH_HAL_USE_MAC TRUE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -62,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -69,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -76,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 9f7060cf3..06f5de243 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -20,13 +20,30 @@ /** * @file templates/halconf.h * @brief HAL configuration header. - * @addtogroup HAL + * @addtogroup HAL_CONF * @{ */ +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -34,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -41,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -48,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -55,6 +84,21 @@ #define CH_HAL_USE_MAC TRUE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -62,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -69,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -76,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index 6fb0e97fa..a0b41dc0d 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI TRUE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI TRUE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index 4e2e694c4..b7b320a58 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index 4e2e694c4..b7b320a58 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index 6fb0e97fa..a0b41dc0d 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI TRUE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI TRUE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index 4e2e694c4..b7b320a58 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index a3d17a3c9..376dfe816 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL FALSE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index a3d17a3c9..376dfe816 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL FALSE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h index a3d17a3c9..376dfe816 100644 --- a/demos/GNU-Linux-GCC/halconf.h +++ b/demos/GNU-Linux-GCC/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL FALSE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index 2faba92d8..b7b320a58 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -20,13 +20,30 @@ /** * @file templates/halconf.h * @brief HAL configuration header. - * @addtogroup HAL + * @addtogroup HAL_CONF * @{ */ +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -34,6 +51,10 @@ #define CH_HAL_USE_PAL TRUE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -41,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -48,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -55,6 +84,21 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -62,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -69,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -76,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index a3d17a3c9..376dfe816 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -27,14 +27,23 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to change the device drivers settings found in the low level drivers - * headers, just define here the new settings and those will override the - * defaults defined in the LLD headers. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ #define _HALCONF_H_ +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PAL subsystem. */ @@ -42,6 +51,10 @@ #define CH_HAL_USE_PAL FALSE #endif +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the ADC subsystem. */ @@ -49,6 +62,10 @@ #define CH_HAL_USE_ADC FALSE #endif +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the CAN subsystem. */ @@ -56,6 +73,10 @@ #define CH_HAL_USE_CAN FALSE #endif +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MAC subsystem. */ @@ -63,6 +84,10 @@ #define CH_HAL_USE_MAC FALSE #endif +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the PWM subsystem. */ @@ -70,6 +95,10 @@ #define CH_HAL_USE_PWM FALSE #endif +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SERIAL subsystem. */ @@ -77,6 +106,10 @@ #define CH_HAL_USE_SERIAL TRUE #endif +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the SPI subsystem. */ @@ -84,6 +117,15 @@ #define CH_HAL_USE_SPI FALSE #endif +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + /** * @brief Enables the MMC_SPI subsystem. */ @@ -91,6 +133,14 @@ #define CH_HAL_USE_MMC_SPI FALSE #endif +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + #endif /* _HALCONF_H_ */ /** @} */ -- cgit v1.2.3 From 55a13f13b9242dadad1949fe00f09056e1c05a7d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 11:07:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1489 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/halconf.h | 34 +++++++++------ demos/ARMCM3-STM32F103-GCC/mcuconf.h | 82 ++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+), 14 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index b7b320a58..c0f12c57d 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h new file mode 100644 index 000000000..f49b49597 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Drivers configuration for the Olimex STM33-P103 proto board. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 0xF0 Lowest, priority level reserved for PENDSV. + * 0xE0...0x40 Normal IRQs priority levels (0x80 used by SYSTICK). + * 0x30 Used by SVCALL, do not share. + * 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * ADC driver system settings. + */ +#define USE_STM32_ADC1 TRUE +#define STM32_ADC1_DMA_PRIORITY 3 +#define STM32_ADC1_IRQ_PRIORITY 0x50 +#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define USE_STM32_CAN1 TRUE +#define STM32_CAN1_IRQ_PRIORITY 0xB0 + +/* + * PWM driver system settings. + */ +#define USE_STM32_PWM1 TRUE +#define USE_STM32_PWM2 FALSE +#define USE_STM32_PWM3 FALSE +#define USE_STM32_PWM4 FALSE +#define STM32_PWM1_IRQ_PRIORITY 0x70 +#define STM32_PWM2_IRQ_PRIORITY 0x70 +#define STM32_PWM3_IRQ_PRIORITY 0x70 +#define STM32_PWM4_IRQ_PRIORITY 0x70 + +/* + * SERIAL driver system settings. + */ +#define USE_STM32_USART1 FALSE +#define USE_STM32_USART2 TRUE +#define USE_STM32_USART3 FALSE +#define STM32_USART1_PRIORITY 0xC0 +#define STM32_USART2_PRIORITY 0xC0 +#define STM32_USART3_PRIORITY 0xC0 + +/* + * SPI driver system settings. + */ +#define USE_STM32_SPI1 TRUE +#define USE_STM32_SPI2 TRUE +#define STM32_SPI1_DMA_PRIORITY 2 +#define STM32_SPI2_DMA_PRIORITY 2 +#define STM32_SPI1_IRQ_PRIORITY 0xA0 +#define STM32_SPI2_IRQ_PRIORITY 0xA0 +#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() -- cgit v1.2.3 From 5b7bad7e5fec14a8d4b15b699f85aacfad6befc2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 11:15:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1490 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 34 ++++++++----- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 82 ++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+), 14 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index a0b41dc0d..36802e62f 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#define CH_HAL_USE_SPI TRUE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE +#define CH_HAL_USE_MMC_SPI TRUE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h new file mode 100644 index 000000000..f49b49597 --- /dev/null +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Drivers configuration for the Olimex STM33-P103 proto board. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 0xF0 Lowest, priority level reserved for PENDSV. + * 0xE0...0x40 Normal IRQs priority levels (0x80 used by SYSTICK). + * 0x30 Used by SVCALL, do not share. + * 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * ADC driver system settings. + */ +#define USE_STM32_ADC1 TRUE +#define STM32_ADC1_DMA_PRIORITY 3 +#define STM32_ADC1_IRQ_PRIORITY 0x50 +#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define USE_STM32_CAN1 TRUE +#define STM32_CAN1_IRQ_PRIORITY 0xB0 + +/* + * PWM driver system settings. + */ +#define USE_STM32_PWM1 TRUE +#define USE_STM32_PWM2 FALSE +#define USE_STM32_PWM3 FALSE +#define USE_STM32_PWM4 FALSE +#define STM32_PWM1_IRQ_PRIORITY 0x70 +#define STM32_PWM2_IRQ_PRIORITY 0x70 +#define STM32_PWM3_IRQ_PRIORITY 0x70 +#define STM32_PWM4_IRQ_PRIORITY 0x70 + +/* + * SERIAL driver system settings. + */ +#define USE_STM32_USART1 FALSE +#define USE_STM32_USART2 TRUE +#define USE_STM32_USART3 FALSE +#define STM32_USART1_PRIORITY 0xC0 +#define STM32_USART2_PRIORITY 0xC0 +#define STM32_USART3_PRIORITY 0xC0 + +/* + * SPI driver system settings. + */ +#define USE_STM32_SPI1 TRUE +#define USE_STM32_SPI2 TRUE +#define STM32_SPI1_DMA_PRIORITY 2 +#define STM32_SPI2_DMA_PRIORITY 2 +#define STM32_SPI1_IRQ_PRIORITY 0xA0 +#define STM32_SPI2_IRQ_PRIORITY 0xA0 +#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() -- cgit v1.2.3 From dd4f5d5c1760fdeec3c6cdd70485d42680df0504 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 11:38:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1491 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/halconf.h | 34 +++++++++++-------- demos/ARM7-AT91SAM7X-GCC/mcuconf.h | 58 +++++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 34 +++++++++++-------- demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h | 58 +++++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 34 +++++++++++-------- demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h | 58 +++++++++++++++++++++++++++++++++ 6 files changed, 234 insertions(+), 42 deletions(-) create mode 100644 demos/ARM7-AT91SAM7X-GCC/mcuconf.h create mode 100644 demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h create mode 100644 demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index b7b320a58..c0f12c57d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARM7-AT91SAM7X-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h new file mode 100644 index 000000000..9e9fdc225 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h @@ -0,0 +1,58 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 06f5de243..0b5015496 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC TRUE +#define CH_HAL_USE_MAC TRUE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h new file mode 100644 index 000000000..9e9fdc225 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h @@ -0,0 +1,58 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 06f5de243..0b5015496 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC TRUE +#define CH_HAL_USE_MAC TRUE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h new file mode 100644 index 000000000..9e9fdc225 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h @@ -0,0 +1,58 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ -- cgit v1.2.3 From 93a5207c97213c420885600f8c0d72f7b5ec3766 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 11:58:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1492 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 34 ++++++++++++--------- demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h | 56 ++++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-G++/halconf.h | 34 ++++++++++++--------- demos/ARM7-LPC214x-G++/mcuconf.h | 56 ++++++++++++++++++++++++++++++++++ demos/ARM7-LPC214x-GCC/halconf.h | 34 ++++++++++++--------- demos/ARM7-LPC214x-GCC/mcuconf.h | 56 ++++++++++++++++++++++++++++++++++ 6 files changed, 228 insertions(+), 42 deletions(-) create mode 100644 demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h create mode 100644 demos/ARM7-LPC214x-G++/mcuconf.h create mode 100644 demos/ARM7-LPC214x-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index a0b41dc0d..36802e62f 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#define CH_HAL_USE_SPI TRUE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE +#define CH_HAL_USE_MMC_SPI TRUE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h new file mode 100644 index 000000000..fd9a6fc91 --- /dev/null +++ b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC214x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_LPC214x_UART0 TRUE +#define USE_LPC214x_UART1 TRUE +#define LPC214x_UART_FIFO_PRELOAD 16 +#define LPC214x_UART1_PRIORITY 1 +#define LPC214x_UART2_PRIORITY 2 + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index b7b320a58..c0f12c57d 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARM7-LPC214x-G++/mcuconf.h b/demos/ARM7-LPC214x-G++/mcuconf.h new file mode 100644 index 000000000..fd9a6fc91 --- /dev/null +++ b/demos/ARM7-LPC214x-G++/mcuconf.h @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC214x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_LPC214x_UART0 TRUE +#define USE_LPC214x_UART1 TRUE +#define LPC214x_UART_FIFO_PRELOAD 16 +#define LPC214x_UART1_PRIORITY 1 +#define LPC214x_UART2_PRIORITY 2 + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index b7b320a58..c0f12c57d 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/ARM7-LPC214x-GCC/mcuconf.h b/demos/ARM7-LPC214x-GCC/mcuconf.h new file mode 100644 index 000000000..fd9a6fc91 --- /dev/null +++ b/demos/ARM7-LPC214x-GCC/mcuconf.h @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC214x drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_LPC214x_UART0 TRUE +#define USE_LPC214x_UART1 TRUE +#define LPC214x_UART_FIFO_PRELOAD 16 +#define LPC214x_UART1_PRIORITY 1 +#define LPC214x_UART2_PRIORITY 2 + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE -- cgit v1.2.3 From 61038954f731debcf474b097a1f7283e4cf198fc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 12:41:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1493 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/halconf.h | 34 ++++++++++++++++++++-------------- demos/AVR-ATmega128-GCC/halconf.h | 34 ++++++++++++++++++++-------------- demos/GNU-Linux-GCC/halconf.h | 34 ++++++++++++++++++++-------------- demos/MSP430-MSP430x1611-GCC/halconf.h | 34 ++++++++++++++++++++-------------- demos/Win32-MinGW/halconf.h | 34 ++++++++++++++++++++-------------- 5 files changed, 100 insertions(+), 70 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index 376dfe816..c0f12c57d 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index 376dfe816..c0f12c57d 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h index 376dfe816..c0f12c57d 100644 --- a/demos/GNU-Linux-GCC/halconf.h +++ b/demos/GNU-Linux-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index b7b320a58..c0f12c57d 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index 376dfe816..c0f12c57d 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -/*#include "mcuconf.h"*/ +#include "mcuconf.h" /*===========================================================================*/ /* PAL driver related settings. */ @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ @@ -59,7 +59,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#define CH_HAL_USE_ADC FALSE #endif /*===========================================================================*/ @@ -70,7 +70,7 @@ * @brief Enables the CAN subsystem. */ #if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#define CH_HAL_USE_CAN FALSE #endif /*===========================================================================*/ @@ -81,7 +81,7 @@ * @brief Enables the MAC subsystem. */ #if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#define CH_HAL_USE_MAC FALSE #endif /*===========================================================================*/ @@ -92,7 +92,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#define CH_HAL_USE_PWM FALSE #endif /*===========================================================================*/ @@ -103,9 +103,15 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#define CH_HAL_USE_SERIAL TRUE #endif +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + /*===========================================================================*/ /* SPI driver related settings. */ /*===========================================================================*/ @@ -114,13 +120,13 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI FALSE #endif /* * Default SPI settings overrides (uncomment to override). */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ /*===========================================================================*/ /* MMC_SPI driver related settings. */ @@ -130,16 +136,16 @@ * @brief Enables the MMC_SPI subsystem. */ #if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#define CH_HAL_USE_MMC_SPI FALSE #endif /* * Default MMC_SPI settings overrides (uncomment to override). */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ #endif /* _HALCONF_H_ */ -- cgit v1.2.3 From 15e6fecf11e470abebe963177434f83883e63acf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 13:02:43 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1494 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 2 +- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 2 +- demos/AVR-AT90CANx-GCC/halconf.h | 2 +- demos/AVR-AT90CANx-GCC/mcuconf.h | 53 ++++++++++++++++++++++++++++++ demos/AVR-ATmega128-GCC/halconf.h | 2 +- demos/AVR-ATmega128-GCC/mcuconf.h | 53 ++++++++++++++++++++++++++++++ demos/GNU-Linux-GCC/halconf.h | 2 +- demos/MSP430-MSP430x1611-GCC/mcuconf.h | 52 +++++++++++++++++++++++++++++ demos/Win32-MinGW/halconf.h | 2 +- 9 files changed, 164 insertions(+), 6 deletions(-) create mode 100644 demos/AVR-AT90CANx-GCC/mcuconf.h create mode 100644 demos/AVR-ATmega128-GCC/mcuconf.h create mode 100644 demos/MSP430-MSP430x1611-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index f49b49597..568dffb11 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -18,7 +18,7 @@ */ /* - * Drivers configuration for the Olimex STM33-P103 proto board. + * STM32 drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the driver diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index f49b49597..568dffb11 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -18,7 +18,7 @@ */ /* - * Drivers configuration for the Olimex STM33-P103 proto board. + * STM32 drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. * Note that the settings for each driver only have effect if the driver diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index c0f12c57d..58d49966f 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL FALSE #endif /*===========================================================================*/ diff --git a/demos/AVR-AT90CANx-GCC/mcuconf.h b/demos/AVR-AT90CANx-GCC/mcuconf.h new file mode 100644 index 000000000..017289582 --- /dev/null +++ b/demos/AVR-AT90CANx-GCC/mcuconf.h @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AVR drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_AVR_USART0 FALSE +#define USE_AVR_USART1 TRUE + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index c0f12c57d..58d49966f 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL FALSE #endif /*===========================================================================*/ diff --git a/demos/AVR-ATmega128-GCC/mcuconf.h b/demos/AVR-ATmega128-GCC/mcuconf.h new file mode 100644 index 000000000..017289582 --- /dev/null +++ b/demos/AVR-ATmega128-GCC/mcuconf.h @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AVR drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_AVR_USART0 FALSE +#define USE_AVR_USART1 TRUE + +/* + * SPI driver system settings. + */ +#define USE_LPC214x_SPI1 TRUE diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h index c0f12c57d..58d49966f 100644 --- a/demos/GNU-Linux-GCC/halconf.h +++ b/demos/GNU-Linux-GCC/halconf.h @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL FALSE #endif /*===========================================================================*/ diff --git a/demos/MSP430-MSP430x1611-GCC/mcuconf.h b/demos/MSP430-MSP430x1611-GCC/mcuconf.h new file mode 100644 index 000000000..620cdd5e2 --- /dev/null +++ b/demos/MSP430-MSP430x1611-GCC/mcuconf.h @@ -0,0 +1,52 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * MSP430 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_MSP430_USART0 TRUE +#define USE_MSP430_USART1 FALSE + +/* + * SPI driver system settings. + */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index c0f12c57d..58d49966f 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#define CH_HAL_USE_PAL FALSE #endif /*===========================================================================*/ -- cgit v1.2.3 From bedb87c1e7cc9741c57c299d81d6e24c5e9c59c5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 13:35:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1495 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/main.c | 16 ++++++++-------- demos/Win32-MinGW/halconf.h | 2 +- demos/Win32-MinGW/main.c | 16 ++++++++-------- 3 files changed, 17 insertions(+), 17 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c index 4153b219a..113b94de6 100644 --- a/demos/GNU-Linux-GCC/main.c +++ b/demos/GNU-Linux-GCC/main.c @@ -96,7 +96,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD1 terminated"); chSysLock(); - chOQResetI(&SD1.d2.oqueue); + chOQResetI(&SD1.sd.oqueue); chSysUnlock(); } if (shelltp2 && chThdTerminated(shelltp2)) { @@ -105,7 +105,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD2 terminated"); chSysLock(); - chOQResetI(&SD2.d2.oqueue); + chOQResetI(&SD2.sd.oqueue); chSysUnlock(); } } @@ -128,7 +128,7 @@ static void sd1_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD1"); chSysLock(); - chIQResetI(&SD1.d2.iqueue); + chIQResetI(&SD1.sd.iqueue); chSysUnlock(); } } @@ -151,7 +151,7 @@ static void sd2_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD2"); chSysLock(); - chIQResetI(&SD2.d2.iqueue); + chIQResetI(&SD2.sd.iqueue); chSysUnlock(); } } @@ -202,10 +202,10 @@ int main(void) { cputs("Shell service started on SD1, SD2"); cputs(" - Listening for connections on SD1"); (void) sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.d2.sevent, &sd1fel, 1); + chEvtRegister(&SD1.sd.sevent, &sd1fel, 1); cputs(" - Listening for connections on SD2"); (void) sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.d2.sevent, &sd2fel, 2); + chEvtRegister(&SD2.sd.sevent, &sd2fel, 2); /* * Events servicing loop. @@ -216,7 +216,7 @@ int main(void) { /* * Clean simulator exit. */ - chEvtUnregister(&SD1.d2.sevent, &sd1fel); - chEvtUnregister(&SD2.d2.sevent, &sd2fel); + chEvtUnregister(&SD1.sd.sevent, &sd1fel); + chEvtUnregister(&SD2.sd.sevent, &sd2fel); return 0; } diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index 58d49966f..f80ceafb0 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -#include "mcuconf.h" +/*#include "mcuconf.h"*/ /*===========================================================================*/ /* PAL driver related settings. */ diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 009ec4a89..8acfda91d 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -94,7 +94,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD1 terminated"); chSysLock(); - chOQResetI(&SD1.d2.oqueue); + chOQResetI(&SD1.sd.oqueue); chSysUnlock(); } if (shelltp2 && chThdTerminated(shelltp2)) { @@ -103,7 +103,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD2 terminated"); chSysLock(); - chOQResetI(&SD2.d2.oqueue); + chOQResetI(&SD2.sd.oqueue); chSysUnlock(); } } @@ -125,7 +125,7 @@ static void sd1_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD1"); chSysLock(); - chIQResetI(&SD1.d2.iqueue); + chIQResetI(&SD1.sd.iqueue); chSysUnlock(); } } @@ -147,7 +147,7 @@ static void sd2_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD2"); chSysLock(); - chIQResetI(&SD2.d2.iqueue); + chIQResetI(&SD2.sd.iqueue); chSysUnlock(); } } @@ -198,10 +198,10 @@ int main(void) { cputs("Shell service started on SD1, SD2"); cputs(" - Listening for connections on SD1"); (void) sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.d2.sevent, &sd1fel, 1); + chEvtRegister(&SD1.sd.sevent, &sd1fel, 1); cputs(" - Listening for connections on SD2"); (void) sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.d2.sevent, &sd2fel, 2); + chEvtRegister(&SD2.sd.sevent, &sd2fel, 2); /* * Events servicing loop. @@ -212,7 +212,7 @@ int main(void) { /* * Clean simulator exit. */ - chEvtUnregister(&SD1.d2.sevent, &sd1fel); - chEvtUnregister(&SD2.d2.sevent, &sd2fel); + chEvtUnregister(&SD1.sd.sevent, &sd1fel); + chEvtUnregister(&SD2.sd.sevent, &sd2fel); return 0; } -- cgit v1.2.3 From edfe4ce4411e0b4f8f78db5c19bc6d553ac82a4f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Jan 2010 18:52:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1497 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/halconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h index 58d49966f..f80ceafb0 100644 --- a/demos/GNU-Linux-GCC/halconf.h +++ b/demos/GNU-Linux-GCC/halconf.h @@ -38,7 +38,7 @@ * settings file. This file can be used to include platform specific * header files or to override the low level drivers settings. */ -#include "mcuconf.h" +/*#include "mcuconf.h"*/ /*===========================================================================*/ /* PAL driver related settings. */ -- cgit v1.2.3 From de95f94fbeb425a7e36e664181824db6ed021ccc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 3 Jan 2010 12:42:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1500 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/main.c | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c index 70d1605bf..d76bae314 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -262,7 +262,7 @@ int main(int argc, char **argv) { /* * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and listed for events. + * sleeping in a loop and listen for events. */ evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ evtStart(&evt); /* Starts the event timer. */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index b2ff15bdd..7322ba1aa 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -211,7 +211,7 @@ int main(int argc, char **argv) { /* * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and listed for events. + * sleeping in a loop and listen for events. */ evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ evtStart(&evt); /* Starts the event timer. */ -- cgit v1.2.3 From 7e4202ae46606be697611dd6f5f867c4915dc046 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 6 Jan 2010 12:55:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1506 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-GCC/readme.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-GCC/readme.txt b/demos/ARM7-LPC214x-GCC/readme.txt index f55f5b4c6..32d036043 100644 --- a/demos/ARM7-LPC214x-GCC/readme.txt +++ b/demos/ARM7-LPC214x-GCC/readme.txt @@ -10,9 +10,8 @@ members of the LPC2000 family should be an easy task. ** The Demo ** The demo blinks the leds on the board by using multiple threads. By pressing -the buttons on the board it is possible to activate the buzzer and send a -message over the serial ports. Pressing both buttons activates the test -procedure on the serial port 1. +the buttons on the board it is possible to send a message over the serial +port or activate the test procedure. See main.c for details. Buzzer.c contains an interesting device driver example that uses a physical timer for the waveform generation and a virtual timer for the sound duration. -- cgit v1.2.3 From 11215c3bcb0b0cbe5794cfc92d0c20de6c8696d9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 22 Jan 2010 14:51:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1539 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/main.c | 16 ++++++++-------- demos/Win32-MinGW/main.c | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c index 113b94de6..8d4dd7d2a 100644 --- a/demos/GNU-Linux-GCC/main.c +++ b/demos/GNU-Linux-GCC/main.c @@ -96,7 +96,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD1 terminated"); chSysLock(); - chOQResetI(&SD1.sd.oqueue); + chOQResetI(&SD1.oqueue); chSysUnlock(); } if (shelltp2 && chThdTerminated(shelltp2)) { @@ -105,7 +105,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD2 terminated"); chSysLock(); - chOQResetI(&SD2.sd.oqueue); + chOQResetI(&SD2.oqueue); chSysUnlock(); } } @@ -128,7 +128,7 @@ static void sd1_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD1"); chSysLock(); - chIQResetI(&SD1.sd.iqueue); + chIQResetI(&SD1.iqueue); chSysUnlock(); } } @@ -151,7 +151,7 @@ static void sd2_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD2"); chSysLock(); - chIQResetI(&SD2.sd.iqueue); + chIQResetI(&SD2.iqueue); chSysUnlock(); } } @@ -202,10 +202,10 @@ int main(void) { cputs("Shell service started on SD1, SD2"); cputs(" - Listening for connections on SD1"); (void) sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.sd.sevent, &sd1fel, 1); + chEvtRegister(&SD1.sevent, &sd1fel, 1); cputs(" - Listening for connections on SD2"); (void) sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.sd.sevent, &sd2fel, 2); + chEvtRegister(&SD2.sevent, &sd2fel, 2); /* * Events servicing loop. @@ -216,7 +216,7 @@ int main(void) { /* * Clean simulator exit. */ - chEvtUnregister(&SD1.sd.sevent, &sd1fel); - chEvtUnregister(&SD2.sd.sevent, &sd2fel); + chEvtUnregister(&SD1.sevent, &sd1fel); + chEvtUnregister(&SD2.sevent, &sd2fel); return 0; } diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 8acfda91d..11123bffb 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -94,7 +94,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD1 terminated"); chSysLock(); - chOQResetI(&SD1.sd.oqueue); + chOQResetI(&SD1.oqueue); chSysUnlock(); } if (shelltp2 && chThdTerminated(shelltp2)) { @@ -103,7 +103,7 @@ static void termination_handler(eventid_t id) { chThdSleepMilliseconds(10); cputs("Init: shell on SD2 terminated"); chSysLock(); - chOQResetI(&SD2.sd.oqueue); + chOQResetI(&SD2.oqueue); chSysUnlock(); } } @@ -125,7 +125,7 @@ static void sd1_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD1"); chSysLock(); - chIQResetI(&SD1.sd.iqueue); + chIQResetI(&SD1.iqueue); chSysUnlock(); } } @@ -147,7 +147,7 @@ static void sd2_handler(eventid_t id) { if (flags & SD_DISCONNECTED) { cputs("Init: disconnection on SD2"); chSysLock(); - chIQResetI(&SD2.sd.iqueue); + chIQResetI(&SD2.iqueue); chSysUnlock(); } } @@ -198,10 +198,10 @@ int main(void) { cputs("Shell service started on SD1, SD2"); cputs(" - Listening for connections on SD1"); (void) sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.sd.sevent, &sd1fel, 1); + chEvtRegister(&SD1.sevent, &sd1fel, 1); cputs(" - Listening for connections on SD2"); (void) sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.sd.sevent, &sd2fel, 2); + chEvtRegister(&SD2.sevent, &sd2fel, 2); /* * Events servicing loop. @@ -212,7 +212,7 @@ int main(void) { /* * Clean simulator exit. */ - chEvtUnregister(&SD1.sd.sevent, &sd1fel); - chEvtUnregister(&SD2.sd.sevent, &sd2fel); + chEvtUnregister(&SD1.sevent, &sd1fel); + chEvtUnregister(&SD2.sevent, &sd2fel); return 0; } -- cgit v1.2.3 From edc56330a91f1f646d8b78ead8a89c46a5d841e6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 Jan 2010 18:32:02 +0000 Subject: Merged Egon's patch. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1542 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 8 ++++++++ demos/ARMCM3-STM32F103-GCC/mcuconf.h | 8 ++++++++ 2 files changed, 16 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index 568dffb11..988e6b79d 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -66,9 +66,17 @@ #define USE_STM32_USART1 FALSE #define USE_STM32_USART2 TRUE #define USE_STM32_USART3 FALSE +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define USE_STM32_UART4 FALSE +#define USE_STM32_UART5 FALSE +#endif #define STM32_USART1_PRIORITY 0xC0 #define STM32_USART2_PRIORITY 0xC0 #define STM32_USART3_PRIORITY 0xC0 +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define STM32_UART4_PRIORITY 0xC0 +#define STM32_UART5_PRIORITY 0xC0 +#endif /* * SPI driver system settings. diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 568dffb11..988e6b79d 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -66,9 +66,17 @@ #define USE_STM32_USART1 FALSE #define USE_STM32_USART2 TRUE #define USE_STM32_USART3 FALSE +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define USE_STM32_UART4 FALSE +#define USE_STM32_UART5 FALSE +#endif #define STM32_USART1_PRIORITY 0xC0 #define STM32_USART2_PRIORITY 0xC0 #define STM32_USART3_PRIORITY 0xC0 +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define STM32_UART4_PRIORITY 0xC0 +#define STM32_UART5_PRIORITY 0xC0 +#endif /* * SPI driver system settings. -- cgit v1.2.3 From e515bcf581c92643c21eb6ed53ba0d0b1604fe4b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 2 Feb 2010 20:20:12 +0000 Subject: Implemented registry subsystem (still in progress). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1558 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/chconf.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 3b29983cb..d0d7e7d41 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in -- cgit v1.2.3 From e32275f84af6e07cbe737262ce90c75f69b9a1c1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 3 Feb 2010 09:37:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1563 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 10 ++++++++++ demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 10 ++++++++++ demos/ARM7-LPC214x-G++/chconf.h | 10 ++++++++++ demos/ARM7-LPC214x-GCC/chconf.h | 10 ++++++++++ demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 10 ++++++++++ demos/AVR-AT90CANx-GCC/chconf.h | 10 ++++++++++ demos/AVR-ATmega128-GCC/chconf.h | 10 ++++++++++ demos/GNU-Linux-GCC/chconf.h | 10 ++++++++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 10 ++++++++++ demos/Win32-MinGW/chconf.h | 10 ++++++++++ 12 files changed, 120 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 3b29983cb..d0d7e7d41 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 9b0cf833d..24e8494c5 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 3b29983cb..d0d7e7d41 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index 3b29983cb..d0d7e7d41 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 3b29983cb..d0d7e7d41 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 3b29983cb..d0d7e7d41 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index 3b29983cb..d0d7e7d41 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 2a4916827..99548894e 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 2a4916827..99548894e 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/GNU-Linux-GCC/chconf.h b/demos/GNU-Linux-GCC/chconf.h index 2c3a29a30..8767ba170 100644 --- a/demos/GNU-Linux-GCC/chconf.h +++ b/demos/GNU-Linux-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index aec56a4a7..fc43618fb 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 2c3a29a30..8767ba170 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -123,6 +123,16 @@ /* Subsystem options. */ /*===========================================================================*/ +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + /** * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in -- cgit v1.2.3 From 217d1529c1a126054fbdb9e071cd103194fd499e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 3 Feb 2010 18:40:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1564 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/main.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 11123bffb..b43ad24db 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -32,7 +32,60 @@ static Thread *cdtp; static Thread *shelltp1; static Thread *shelltp2; -void cmd_test(BaseChannel *chp, int argc, char *argv[]) { +static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { + size_t n, size; + char buf[52]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: mem"); + return; + } + n = chHeapStatus(NULL, &size); + sprintf(buf, "core free memory : %i bytes", chCoreFree()); + shellPrintLine(chp, buf); + sprintf(buf, "heap fragments : %i", n); + shellPrintLine(chp, buf); + sprintf(buf, "heap free total : %i bytes", size); + shellPrintLine(chp, buf); +} + +static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { + static const char *states[] = { + "READY", + "CURRENT", + "SUSPENDED", + "WTSEM", + "WTMTX", + "WTCOND", + "SLEEPING", + "WTEXIT", + "WTOREVT", + "WTANDEVT", + "SNDMSG", + "WTMSG", + "FINAL" + }; + Thread *tp; + char buf[60]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: threads"); + return; + } + shellPrintLine(chp, " addr stack prio refs state time"); + tp = chRegFirstThread(); + do { + sprintf(buf, "%8p %8p %4i %4i %9s %i", + tp, tp->p_ctx.esp, tp->p_prio, tp->p_refs - 1, + states[tp->p_state], tp->p_time); + shellPrintLine(chp, buf); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { Thread *tp; (void)argv; @@ -50,6 +103,8 @@ void cmd_test(BaseChannel *chp, int argc, char *argv[]) { } static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, {"test", cmd_test}, {NULL, NULL} }; -- cgit v1.2.3 From b741fd09dfb205589f5e83aa5754ffa4af450e10 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 17 Feb 2010 18:57:36 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1627 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h | 4 ++-- demos/ARM7-LPC214x-G++/mcuconf.h | 4 ++-- demos/ARM7-LPC214x-GCC/mcuconf.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h index fd9a6fc91..a8b763e53 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h @@ -47,8 +47,8 @@ #define USE_LPC214x_UART0 TRUE #define USE_LPC214x_UART1 TRUE #define LPC214x_UART_FIFO_PRELOAD 16 -#define LPC214x_UART1_PRIORITY 1 -#define LPC214x_UART2_PRIORITY 2 +#define LPC214x_UART0_PRIORITY 1 +#define LPC214x_UART1_PRIORITY 2 /* * SPI driver system settings. diff --git a/demos/ARM7-LPC214x-G++/mcuconf.h b/demos/ARM7-LPC214x-G++/mcuconf.h index fd9a6fc91..a8b763e53 100644 --- a/demos/ARM7-LPC214x-G++/mcuconf.h +++ b/demos/ARM7-LPC214x-G++/mcuconf.h @@ -47,8 +47,8 @@ #define USE_LPC214x_UART0 TRUE #define USE_LPC214x_UART1 TRUE #define LPC214x_UART_FIFO_PRELOAD 16 -#define LPC214x_UART1_PRIORITY 1 -#define LPC214x_UART2_PRIORITY 2 +#define LPC214x_UART0_PRIORITY 1 +#define LPC214x_UART1_PRIORITY 2 /* * SPI driver system settings. diff --git a/demos/ARM7-LPC214x-GCC/mcuconf.h b/demos/ARM7-LPC214x-GCC/mcuconf.h index fd9a6fc91..a8b763e53 100644 --- a/demos/ARM7-LPC214x-GCC/mcuconf.h +++ b/demos/ARM7-LPC214x-GCC/mcuconf.h @@ -47,8 +47,8 @@ #define USE_LPC214x_UART0 TRUE #define USE_LPC214x_UART1 TRUE #define LPC214x_UART_FIFO_PRELOAD 16 -#define LPC214x_UART1_PRIORITY 1 -#define LPC214x_UART2_PRIORITY 2 +#define LPC214x_UART0_PRIORITY 1 +#define LPC214x_UART1_PRIORITY 2 /* * SPI driver system settings. -- cgit v1.2.3 From 5d983fd514b3fcad1f7a27faf74e21789d93e99a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 19 Feb 2010 18:19:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1637 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC563-GCC/Makefile | 153 +++++++++++++ demos/PPC-SPC563-GCC/ch.ld | 111 ++++++++++ demos/PPC-SPC563-GCC/chconf.h | 476 +++++++++++++++++++++++++++++++++++++++++ demos/PPC-SPC563-GCC/halconf.h | 152 +++++++++++++ demos/PPC-SPC563-GCC/main.c | 99 +++++++++ 5 files changed, 991 insertions(+) create mode 100644 demos/PPC-SPC563-GCC/Makefile create mode 100644 demos/PPC-SPC563-GCC/ch.ld create mode 100644 demos/PPC-SPC563-GCC/chconf.h create mode 100644 demos/PPC-SPC563-GCC/halconf.h create mode 100644 demos/PPC-SPC563-GCC/main.c (limited to 'demos') diff --git a/demos/PPC-SPC563-GCC/Makefile b/demos/PPC-SPC563-GCC/Makefile new file mode 100644 index 000000000..65b19bc35 --- /dev/null +++ b/demos/PPC-SPC563-GCC/Makefile @@ -0,0 +1,153 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = no +endif + +# Enable register caching optimization (read documentation). +# Option not tested on MSP430, DO NOT USE. +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = ./ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/GENERIC_SPC563/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC563/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/memstreams.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/PPC/SPC56x/ivor.s \ + $(CHIBIOS)/os/ports/GCC/PPC/SPC56x/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames + +TRGT = powerpc-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/demos/PPC-SPC563-GCC/ch.ld b/demos/PPC-SPC563-GCC/ch.ld new file mode 100644 index 000000000..53243cdf7 --- /dev/null +++ b/demos/PPC-SPC563-GCC/ch.ld @@ -0,0 +1,111 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC563M64 memory setup. + */ +__irq_stack_size__ = 0x0400; +__process_stack_size__ = 0x0800; +__stacks_total_size__ = __irq_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 1536k + ram : org = 0x40000000, len = 94k +} + +/* + * Derived constants. + */ +__flash_size__ = LENGTH(flash); +__flash_start__ = ORIGIN(flash); +__flash_end__ = ORIGIN(flash) + LENGTH(flash); + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +SECTIONS +{ + . = ORIGIN(flash); + + .text : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.bam)) + KEEP(*(.handlers)) + . = ALIGN(0x800); + KEEP(*(.vectors)) + *(.text .stub .text.* .gnu.linkonce.t.*) + *(.glue_7t); + *(.glue_7); + *(.ctors); + *(.dtors); + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata .sdata.* .gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__ - __stacks_total_size__; +} diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h new file mode 100644 index 000000000..ee9a82aeb --- /dev/null +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -0,0 +1,476 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @addtogroup config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h new file mode 100644 index 000000000..f80ceafb0 --- /dev/null +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c new file mode 100644 index 000000000..c2afbf5b0 --- /dev/null +++ b/demos/PPC-SPC563-GCC/main.c @@ -0,0 +1,99 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "memstreams.h" + +int a = 1234; +uint8_t report_buffer[8192]; + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + + SIU.GPDO[GPIO_LED1].R = 1; + SIU.GPDO[GPIO_LED2].R = 1; + SIU.GPDO[GPIO_LED3].R = 1; + SIU.GPDO[GPIO_LED4].R = 1; + + while (TRUE) { + SIU.GPDO[GPIO_LED1].R = 0; + chThdSleepMilliseconds(100); + SIU.GPDO[GPIO_LED2].R = 0; + chThdSleepMilliseconds(100); + SIU.GPDO[GPIO_LED3].R = 0; + chThdSleepMilliseconds(100); + SIU.GPDO[GPIO_LED4].R = 0; + chThdSleepMilliseconds(100); + SIU.GPDO[GPIO_LED1].R = 1; + chThdSleepMilliseconds(100); + SIU.GPDO[GPIO_LED2].R = 1; + chThdSleepMilliseconds(100); + SIU.GPDO[GPIO_LED3].R = 1; + chThdSleepMilliseconds(100); + SIU.GPDO[GPIO_LED4].R = 1; + chThdSleepMilliseconds(300); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (SIU.GPDI[GPIO_BUTTON1].B.PDI) { + volatile msg_t result; +#if 0 + MemoryStream report; + + msObjectInit(&report, report_buffer, sizeof(report_buffer), 0); + result = TestThread(&report); +#else + result = TestThread(&SD1); +#endif + } + chThdSleepMilliseconds(1000); + } + return 0; +} -- cgit v1.2.3 From a90a90ffcf0f90b2a4b6c24dc5a60e72652549f1 Mon Sep 17 00:00:00 2001 From: liamstask Date: Sat, 20 Feb 2010 19:55:00 +0000 Subject: adding simulator support for OS X git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1645 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/Makefile | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/Makefile b/demos/GNU-Linux-GCC/Makefile index 9d38e2637..f32f3c760 100644 --- a/demos/GNU-Linux-GCC/Makefile +++ b/demos/GNU-Linux-GCC/Makefile @@ -92,7 +92,6 @@ OPT = -ggdb -O2 -fomit-frame-pointer # End of user defines ############################################################################################## - INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) DEFS = $(DDEFS) $(UDEFS) @@ -100,9 +99,21 @@ ADEFS = $(DADEFS) $(UADEFS) OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) LIBS = $(DLIBS) $(ULIBS) -LDFLAGS = -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(<:.c=.lst) $(DEFS) +CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm $(DEFS) + +ifeq ($(HOST_OSX),yes) + OSX_SDK = /Developer/SDKs/MacOSX10.5.sdk + OSX_ARCH = -mmacosx-version-min=10.3 -arch i386 + + CPFLAGS += -isysroot $(OSX_SDK) $(OSX_ARCH) + LDFLAGS = -Wl -Map=$(PROJECT).map,-syslibroot,$(OSX_SDK),$(LIBDIR) + LIBS += $(OSX_ARCH) +else + # Linux, or other + CPFLAGS += -Wa,-alms=$(<:.c=.lst) + LDFLAGS += -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif # Generate dependency information CPFLAGS += -MD -MP -MF .dep/$(@F).d -- cgit v1.2.3 From 157b6f9695e7f72f2d54b231c19cb4045710ed01 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Feb 2010 07:24:53 +0000 Subject: Updated license dates. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1646 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/ch.ld | 2 +- demos/ARM7-AT91SAM7X-GCC/chconf.h | 4 ++-- demos/ARM7-AT91SAM7X-GCC/halconf.h | 10 +++++----- demos/ARM7-AT91SAM7X-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-GCC/mcuconf.h | 4 ++-- demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 4 ++-- demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 10 +++++----- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 16 ++++++++-------- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h | 4 ++-- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h | 4 ++-- demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c | 6 +++--- demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 4 ++-- demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 10 +++++----- demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h | 4 ++-- demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h | 2 +- demos/ARM7-LPC214x-FATFS-GCC/ch.ld | 2 +- demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 4 ++-- demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 10 +++++----- demos/ARM7-LPC214x-FATFS-GCC/main.c | 8 ++++---- demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h | 4 ++-- demos/ARM7-LPC214x-G++/ch.ld | 2 +- demos/ARM7-LPC214x-G++/chconf.h | 4 ++-- demos/ARM7-LPC214x-G++/halconf.h | 10 +++++----- demos/ARM7-LPC214x-G++/main.cpp | 2 +- demos/ARM7-LPC214x-G++/mcuconf.h | 4 ++-- demos/ARM7-LPC214x-GCC/ch.ld | 2 +- demos/ARM7-LPC214x-GCC/chconf.h | 4 ++-- demos/ARM7-LPC214x-GCC/halconf.h | 10 +++++----- demos/ARM7-LPC214x-GCC/main.c | 2 +- demos/ARM7-LPC214x-GCC/mcuconf.h | 4 ++-- demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 4 ++-- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 10 +++++----- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 6 +++--- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 6 +++--- demos/ARMCM3-STM32F103-GCC/ch.ld | 2 +- demos/ARMCM3-STM32F103-GCC/chconf.h | 4 ++-- demos/ARMCM3-STM32F103-GCC/halconf.h | 10 +++++----- demos/ARMCM3-STM32F103-GCC/main.c | 2 +- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 6 +++--- demos/AVR-AT90CANx-GCC/chconf.h | 4 ++-- demos/AVR-AT90CANx-GCC/halconf.h | 10 +++++----- demos/AVR-AT90CANx-GCC/main.c | 2 +- demos/AVR-AT90CANx-GCC/mcuconf.h | 4 ++-- demos/AVR-ATmega128-GCC/chconf.h | 4 ++-- demos/AVR-ATmega128-GCC/halconf.h | 10 +++++----- demos/AVR-ATmega128-GCC/lcd.c | 2 +- demos/AVR-ATmega128-GCC/lcd.h | 2 +- demos/AVR-ATmega128-GCC/main.c | 2 +- demos/AVR-ATmega128-GCC/mcuconf.h | 4 ++-- demos/GNU-Linux-GCC/board.h | 2 +- demos/GNU-Linux-GCC/chconf.h | 4 ++-- demos/GNU-Linux-GCC/halconf.h | 10 +++++----- demos/GNU-Linux-GCC/main.c | 18 +++++++++--------- demos/MSP430-MSP430x1611-GCC/chconf.h | 4 ++-- demos/MSP430-MSP430x1611-GCC/halconf.h | 10 +++++----- demos/MSP430-MSP430x1611-GCC/main.c | 2 +- demos/MSP430-MSP430x1611-GCC/mcuconf.h | 4 ++-- demos/PPC-SPC563-GCC/ch.ld | 2 +- demos/PPC-SPC563-GCC/chconf.h | 4 ++-- demos/PPC-SPC563-GCC/halconf.h | 10 +++++----- demos/PPC-SPC563-GCC/main.c | 2 +- demos/Win32-MinGW/board.h | 2 +- demos/Win32-MinGW/chconf.h | 4 ++-- demos/Win32-MinGW/halconf.h | 10 +++++----- demos/Win32-MinGW/main.c | 18 +++++++++--------- 76 files changed, 190 insertions(+), 190 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 944a7f29d..277336359 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index d0d7e7d41..300a85579 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index c0f12c57d..763b0019a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index e1b7dae9b..a560bc439 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h index 9e9fdc225..be2bcc852 100644 --- a/demos/ARM7-AT91SAM7X-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld b/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld index 944a7f29d..277336359 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 24e8494c5..47f38904b 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 0b5015496..1ad94f04b 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h index 2a1175f5f..62d037e80 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/cc.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h index d690e63e9..99b4a7197 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/perf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index 9fcf2a24a..c164a7a4e 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h index a054ae761..f52b9d08b 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 4400445ac..8065a6b61 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -80,12 +80,12 @@ #define FRAME_RECEIVED_ID 2 /** - * Stack area for the LWIP-MAC thread. + * Stack area for the LWIP-MAC thread. */ WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); /* - * Initialization. + * Initialization. */ static void low_level_init(struct netif *netif) { /* set MAC hardware address length */ @@ -102,7 +102,7 @@ static void low_level_init(struct netif *netif) { } /* - * Transmits a frame. + * Transmits a frame. */ static err_t low_level_output(struct netif *netif, struct pbuf *p) { struct pbuf *q; @@ -132,7 +132,7 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p) { } /* - * Receives a frame. + * Receives a frame. */ static struct pbuf *low_level_input(struct netif *netif) { MACReceiveDescriptor rd; @@ -212,9 +212,9 @@ static err_t ethernetif_init(struct netif *netif) { /** * @brief LWIP handling thread. - * - * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL - * @return The function does not return. + * + * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL + * @return The function does not return. */ msg_t lwip_thread(void *p) { EvTimer evt; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h index b086ce7ef..0fe5d9473 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -103,7 +103,7 @@ #endif /** - * @brief Runtime TCP/IP settings. + * @brief Runtime TCP/IP settings. */ struct lwipthread_opts { uint8_t *macaddress; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index 3b469aed4..4d90741c1 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h index 9e9fdc225..be2bcc852 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c index 3d0c384d2..1bea06de4 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -19,7 +19,7 @@ /* * This file is a modified version of the lwIP web server demo. The original - * author is unknown because the file didn't contain any license information. + * author is unknown because the file didn't contain any license information. */ /** @@ -87,7 +87,7 @@ static void http_server_serve(struct netconn *conn) { WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE); /** - * HTTP server thread. + * HTTP server thread. */ msg_t http_server(void *p) { struct netconn *conn, *newconn; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h index f53cfcb44..991ce117c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/web/web.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld b/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld index 944a7f29d..277336359 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index d0d7e7d41..300a85579 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 0b5015496..1ad94f04b 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c index 283e01168..5db4864b9 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h index 9e9fdc225..be2bcc852 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c index 1235696d8..bbf08b820 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h index bd71b4dc4..e6f14822a 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-LPC214x-FATFS-GCC/ch.ld b/demos/ARM7-LPC214x-FATFS-GCC/ch.ld index 9dd4d388e..e68868f72 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/ch.ld +++ b/demos/ARM7-LPC214x-FATFS-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index d0d7e7d41..300a85579 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index 36802e62f..525bae43a 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c index d76bae314..80d383356 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -188,7 +188,7 @@ static void InsertHandler(eventid_t id) { buzzPlayWait(2000, MS2ST(100)); iprintf("MMC: inserted\r\n"); /* - * On insertion MMC initialization and FS mount. + * On insertion MMC initialization and FS mount. */ iprintf("MMC: initialization "); if (mmcConnect(&MMCD1)) { @@ -242,12 +242,12 @@ int main(int argc, char **argv) { sdStart(&SD1, NULL); /* - * Buzzer driver initialization. + * Buzzer driver initialization. */ buzzInit(); /* - * Initializes the MMC driver to work with SPI2. + * Initializes the MMC driver to work with SPI2. */ mmcObjectInit(&MMCD1, &SPID1, &ls_spicfg, &hs_spicfg, diff --git a/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h index a8b763e53..9d785c9b6 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index 15d0fbe2f..1ce752804 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index d0d7e7d41..300a85579 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index c0f12c57d..763b0019a 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 7b012d004..b6b7c83ba 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-LPC214x-G++/mcuconf.h b/demos/ARM7-LPC214x-G++/mcuconf.h index a8b763e53..9d785c9b6 100644 --- a/demos/ARM7-LPC214x-G++/mcuconf.h +++ b/demos/ARM7-LPC214x-G++/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index 9dd4d388e..e68868f72 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index d0d7e7d41..300a85579 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index c0f12c57d..763b0019a 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 00aca0ec7..9ac1b7698 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARM7-LPC214x-GCC/mcuconf.h b/demos/ARM7-LPC214x-GCC/mcuconf.h index a8b763e53..9d785c9b6 100644 --- a/demos/ARM7-LPC214x-GCC/mcuconf.h +++ b/demos/ARM7-LPC214x-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld b/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld index 9d18539f8..0dd8cfeab 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index d0d7e7d41..300a85579 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index 36802e62f..525bae43a 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 7322ba1aa..8295e509b 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -144,7 +144,7 @@ static void InsertHandler(eventid_t id) { (void)id; iprintf("MMC: inserted\r\n"); /* - * On insertion MMC initialization and FS mount. + * On insertion MMC initialization and FS mount. */ iprintf("MMC: initialization "); if (mmcConnect(&MMCD1)) { @@ -195,7 +195,7 @@ int main(int argc, char **argv) { sdStart(&SD2, NULL); /* - * Initializes the MMC driver to work with SPI2. + * Initializes the MMC driver to work with SPI2. */ palSetPadMode(IOPORT2, GPIOB_SPI2NSS, PAL_MODE_OUTPUT_PUSHPULL); palSetPad(IOPORT2, GPIOB_SPI2NSS); diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index 988e6b79d..e6216b886 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -31,11 +31,11 @@ * 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it. * * DMA priorities: - * 0...3 Lowest...Highest. + * 0...3 Lowest...Highest. */ /* - * ADC driver system settings. + * ADC driver system settings. */ #define USE_STM32_ADC1 TRUE #define STM32_ADC1_DMA_PRIORITY 3 diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index 22d5546a1..1405765cd 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index d0d7e7d41..300a85579 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index c0f12c57d..763b0019a 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 2e62d944d..0072f0958 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 988e6b79d..e6216b886 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -31,11 +31,11 @@ * 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it. * * DMA priorities: - * 0...3 Lowest...Highest. + * 0...3 Lowest...Highest. */ /* - * ADC driver system settings. + * ADC driver system settings. */ #define USE_STM32_ADC1 TRUE #define STM32_ADC1_DMA_PRIORITY 3 diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 99548894e..c32d36bdc 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index 58d49966f..bd2f3e4fd 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL FALSE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 61df6a3ed..f922efed0 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/AVR-AT90CANx-GCC/mcuconf.h b/demos/AVR-AT90CANx-GCC/mcuconf.h index 017289582..bd31976f2 100644 --- a/demos/AVR-AT90CANx-GCC/mcuconf.h +++ b/demos/AVR-AT90CANx-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 99548894e..c32d36bdc 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index 58d49966f..bd2f3e4fd 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL FALSE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/AVR-ATmega128-GCC/lcd.c b/demos/AVR-ATmega128-GCC/lcd.c index 29a4d0c8c..30be58416 100644 --- a/demos/AVR-ATmega128-GCC/lcd.c +++ b/demos/AVR-ATmega128-GCC/lcd.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/AVR-ATmega128-GCC/lcd.h b/demos/AVR-ATmega128-GCC/lcd.h index 12ffd127e..3b3cdd050 100644 --- a/demos/AVR-ATmega128-GCC/lcd.h +++ b/demos/AVR-ATmega128-GCC/lcd.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index 28d3f1cef..b63d793b5 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/AVR-ATmega128-GCC/mcuconf.h b/demos/AVR-ATmega128-GCC/mcuconf.h index 017289582..bd31976f2 100644 --- a/demos/AVR-ATmega128-GCC/mcuconf.h +++ b/demos/AVR-ATmega128-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/GNU-Linux-GCC/board.h b/demos/GNU-Linux-GCC/board.h index a6e056d58..7b89d92d0 100644 --- a/demos/GNU-Linux-GCC/board.h +++ b/demos/GNU-Linux-GCC/board.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/GNU-Linux-GCC/chconf.h b/demos/GNU-Linux-GCC/chconf.h index 8767ba170..2f45fb0f3 100644 --- a/demos/GNU-Linux-GCC/chconf.h +++ b/demos/GNU-Linux-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h index f80ceafb0..40264527c 100644 --- a/demos/GNU-Linux-GCC/halconf.h +++ b/demos/GNU-Linux-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ /*#include "mcuconf.h"*/ @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL FALSE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c index 8d4dd7d2a..28e136bc8 100644 --- a/demos/GNU-Linux-GCC/main.c +++ b/demos/GNU-Linux-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -84,8 +84,8 @@ static msg_t console_thread(void *arg) { /** * @brief Shell termination handler. - * - * @param[in] id event id. + * + * @param[in] id event id. */ static void termination_handler(eventid_t id) { @@ -179,25 +179,25 @@ int main(void) { chSysInit(); /* - * Serial ports (simulated) initialization. + * Serial ports (simulated) initialization. */ sdStart(&SD1, NULL); sdStart(&SD2, NULL); /* - * Shell manager initialization. + * Shell manager initialization. */ shellInit(); chEvtRegister(&shell_terminated, &tel, 0); /* - * Console thread started. + * Console thread started. */ cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, console_thread, NULL); /* - * Initializing connection/disconnection events. + * Initializing connection/disconnection events. */ cputs("Shell service started on SD1, SD2"); cputs(" - Listening for connections on SD1"); @@ -208,13 +208,13 @@ int main(void) { chEvtRegister(&SD2.sevent, &sd2fel, 2); /* - * Events servicing loop. + * Events servicing loop. */ while (!chThdShouldTerminate()) chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); /* - * Clean simulator exit. + * Clean simulator exit. */ chEvtUnregister(&SD1.sevent, &sd1fel); chEvtUnregister(&SD2.sevent, &sd2fel); diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index fc43618fb..5629c38e3 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index c0f12c57d..763b0019a 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 91fb26f83..3bac249d0 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/MSP430-MSP430x1611-GCC/mcuconf.h b/demos/MSP430-MSP430x1611-GCC/mcuconf.h index 620cdd5e2..d0cba2d41 100644 --- a/demos/MSP430-MSP430x1611-GCC/mcuconf.h +++ b/demos/MSP430-MSP430x1611-GCC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -26,7 +26,7 @@ */ /* - * ADC driver system settings. + * ADC driver system settings. */ /* diff --git a/demos/PPC-SPC563-GCC/ch.ld b/demos/PPC-SPC563-GCC/ch.ld index 53243cdf7..5cea0b9b9 100644 --- a/demos/PPC-SPC563-GCC/ch.ld +++ b/demos/PPC-SPC563-GCC/ch.ld @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h index ee9a82aeb..557c2a5a1 100644 --- a/demos/PPC-SPC563-GCC/chconf.h +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -400,7 +400,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index f80ceafb0..40264527c 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ /*#include "mcuconf.h"*/ @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL FALSE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index c2afbf5b0..df59fd598 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/Win32-MinGW/board.h b/demos/Win32-MinGW/board.h index a6e056d58..7b89d92d0 100644 --- a/demos/Win32-MinGW/board.h +++ b/demos/Win32-MinGW/board.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 8767ba170..2f45fb0f3 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -396,7 +396,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index f80ceafb0..40264527c 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ /*#include "mcuconf.h"*/ @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL FALSE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index b43ad24db..1418b70ec 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -137,8 +137,8 @@ static msg_t console_thread(void *arg) { /** * @brief Shell termination handler. - * - * @param[in] id event id. + * + * @param[in] id event id. */ static void termination_handler(eventid_t id) { @@ -230,25 +230,25 @@ int main(void) { chSysInit(); /* - * Serial ports (simulated) initialization. + * Serial ports (simulated) initialization. */ sdStart(&SD1, NULL); sdStart(&SD2, NULL); /* - * Shell manager initialization. + * Shell manager initialization. */ shellInit(); chEvtRegister(&shell_terminated, &tel, 0); /* - * Console thread started. + * Console thread started. */ cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, console_thread, NULL); /* - * Initializing connection/disconnection events. + * Initializing connection/disconnection events. */ cputs("Shell service started on SD1, SD2"); cputs(" - Listening for connections on SD1"); @@ -259,13 +259,13 @@ int main(void) { chEvtRegister(&SD2.sevent, &sd2fel, 2); /* - * Events servicing loop. + * Events servicing loop. */ while (!chThdShouldTerminate()) chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); /* - * Clean simulator exit. + * Clean simulator exit. */ chEvtUnregister(&SD1.sevent, &sd1fel); chEvtUnregister(&SD2.sevent, &sd2fel); -- cgit v1.2.3 From 1c03b33539fac79a32ac10db444a1b0a7af0d65f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Feb 2010 11:14:39 +0000 Subject: Simulator PAL driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1649 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/halconf.h | 2 +- demos/Win32-MinGW/halconf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h index 40264527c..b325b7238 100644 --- a/demos/GNU-Linux-GCC/halconf.h +++ b/demos/GNU-Linux-GCC/halconf.h @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index 40264527c..b325b7238 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ -- cgit v1.2.3 From 0a09cc089d0c8947b4309952482a24a1cafd2477 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Feb 2010 11:29:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1650 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Posix-GCC/Makefile | 156 +++++++++++++++ demos/Posix-GCC/board.h | 23 +++ demos/Posix-GCC/chconf.h | 476 +++++++++++++++++++++++++++++++++++++++++++++ demos/Posix-GCC/halconf.h | 152 +++++++++++++++ demos/Posix-GCC/main.c | 222 +++++++++++++++++++++ demos/Posix-GCC/readme.txt | 26 +++ 6 files changed, 1055 insertions(+) create mode 100644 demos/Posix-GCC/Makefile create mode 100644 demos/Posix-GCC/board.h create mode 100644 demos/Posix-GCC/chconf.h create mode 100644 demos/Posix-GCC/halconf.h create mode 100644 demos/Posix-GCC/main.c create mode 100644 demos/Posix-GCC/readme.txt (limited to 'demos') diff --git a/demos/Posix-GCC/Makefile b/demos/Posix-GCC/Makefile new file mode 100644 index 000000000..f32f3c760 --- /dev/null +++ b/demos/Posix-GCC/Makefile @@ -0,0 +1,156 @@ +# +# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! +# +############################################################################################## +# +# On command line: +# +# make all = Create project +# +# make clean = Clean project files. +# +# To rebuild project do "make clean" and "make all". +# + +############################################################################################## +# Start of default section +# + +TRGT = +CC = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################################## + +############################################################################################## +# Start of user section +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT = + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# Imported source files +CHIBIOS = ../.. +include ${CHIBIOS}/os/hal/hal.mk +include ${CHIBIOS}/os/hal/platforms/Linux/platform.mk +include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk +include ${CHIBIOS}/os/kernel/kernel.mk +include ${CHIBIOS}/test/test.mk + +# List C source files here +SRC = ${PORTSRC} \ + ${KERNSRC} \ + ${TESTSRC} \ + ${HALSRC} \ + ${PLATFORMSRC} \ + ${CHIBIOS}/os/various/shell.c \ + main.c + +# List ASM source files here +ASRC = + +# List all user directories here +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ + ${CHIBIOS}/os/various + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# Define optimisation level here +OPT = -ggdb -O2 -fomit-frame-pointer + +# +# End of user defines +############################################################################################## + +INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) +LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) +DEFS = $(DDEFS) $(UDEFS) +ADEFS = $(DADEFS) $(UADEFS) +OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) +LIBS = $(DLIBS) $(ULIBS) + +ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) +CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm $(DEFS) + +ifeq ($(HOST_OSX),yes) + OSX_SDK = /Developer/SDKs/MacOSX10.5.sdk + OSX_ARCH = -mmacosx-version-min=10.3 -arch i386 + + CPFLAGS += -isysroot $(OSX_SDK) $(OSX_ARCH) + LDFLAGS = -Wl -Map=$(PROJECT).map,-syslibroot,$(OSX_SDK),$(LIBDIR) + LIBS += $(OSX_ARCH) +else + # Linux, or other + CPFLAGS += -Wa,-alms=$(<:.c=.lst) + LDFLAGS += -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) +endif + +# Generate dependency information +CPFLAGS += -MD -MP -MF .dep/$(@F).d + +# +# makefile rules +# + +all: $(OBJS) $(PROJECT) + +%o : %c + $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ + +%o : %s + $(AS) -c $(ASFLAGS) $< -o $@ + +$(PROJECT): $(OBJS) + $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ + +gcov: + -mkdir gcov + $(COV) -u $(subst /,\,$(SRC)) + -mv *.gcov ./gcov + +clean: + -rm -f $(OBJS) + -rm -f $(PROJECT) + -rm -f $(PROJECT).map + -rm -f $(SRC:.c=.c.bak) + -rm -f $(SRC:.c=.lst) + -rm -f $(ASRC:.s=.s.bak) + -rm -f $(ASRC:.s=.lst) + -rm -fR .dep + +# +# Include the dependency files, should be the last of the makefile +# +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + +# *** EOF *** diff --git a/demos/Posix-GCC/board.h b/demos/Posix-GCC/board.h new file mode 100644 index 000000000..7b89d92d0 --- /dev/null +++ b/demos/Posix-GCC/board.h @@ -0,0 +1,23 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#endif /* _BOARD_H_ */ diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h new file mode 100644 index 000000000..2f45fb0f3 --- /dev/null +++ b/demos/Posix-GCC/chconf.h @@ -0,0 +1,476 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @addtogroup config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0x20000 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented or some ports. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h new file mode 100644 index 000000000..b325b7238 --- /dev/null +++ b/demos/Posix-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +/*#include "mcuconf.h"*/ + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/Posix-GCC/main.c b/demos/Posix-GCC/main.c new file mode 100644 index 000000000..28e136bc8 --- /dev/null +++ b/demos/Posix-GCC/main.c @@ -0,0 +1,222 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(4096) +#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) +#define TEST_WA_SIZE THD_WA_SIZE(4096) + +#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) + +static Thread *cdtp; +static Thread *shelltp1; +static Thread *shelltp2; + +void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: test"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + shellPrintLine(chp, "out of memory"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD1, + commands +}; + +static const ShellConfig shell_cfg2 = { + (BaseChannel *)&SD2, + commands +}; + +/* + * Console print server done using synchronous messages. This makes the access + * to the C printf() thread safe and the print operation atomic among threads. + * In this example the message is the zero termitated string itself. + */ +static msg_t console_thread(void *arg) { + + (void)arg; + while (!chThdShouldTerminate()) { + puts((char *)chMsgWait()); + fflush(stdout); + chMsgRelease(RDY_OK); + } + return 0; +} + +/** + * @brief Shell termination handler. + * + * @param[in] id event id. + */ +static void termination_handler(eventid_t id) { + + (void)id; + if (shelltp1 && chThdTerminated(shelltp1)) { + chThdWait(shelltp1); + shelltp1 = NULL; + chThdSleepMilliseconds(10); + cputs("Init: shell on SD1 terminated"); + chSysLock(); + chOQResetI(&SD1.oqueue); + chSysUnlock(); + } + if (shelltp2 && chThdTerminated(shelltp2)) { + chThdWait(shelltp2); + shelltp2 = NULL; + chThdSleepMilliseconds(10); + cputs("Init: shell on SD2 terminated"); + chSysLock(); + chOQResetI(&SD2.oqueue); + chSysUnlock(); + } +} + +/** + * @brief SD1 status change handler. + * + * @param[in] id event id. + */ +static void sd1_handler(eventid_t id) { + + sdflags_t flags; + + (void)id; + flags = sdGetAndClearFlags(&SD1); + if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { + cputs("Init: connection on SD1"); + shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); + } + if (flags & SD_DISCONNECTED) { + cputs("Init: disconnection on SD1"); + chSysLock(); + chIQResetI(&SD1.iqueue); + chSysUnlock(); + } +} + +/** + * @brief SD2 status change handler. + * + * @param[in] id event id. + */ +static void sd2_handler(eventid_t id) { + + sdflags_t flags; + + (void)id; + flags = sdGetAndClearFlags(&SD2); + if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { + cputs("Init: connection on SD2"); + shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); + } + if (flags & SD_DISCONNECTED) { + cputs("Init: disconnection on SD2"); + chSysLock(); + chIQResetI(&SD2.iqueue); + chSysUnlock(); + } +} + +static evhandler_t fhandlers[] = { + termination_handler, + sd1_handler, + sd2_handler +}; + +/*------------------------------------------------------------------------* + * Simulator main. * + *------------------------------------------------------------------------*/ +int main(void) { + EventListener sd1fel, sd2fel, tel; + + /* + * HAL initialization. + */ + halInit(); + + /* + * ChibiOS/RT initialization. + */ + chSysInit(); + + /* + * Serial ports (simulated) initialization. + */ + sdStart(&SD1, NULL); + sdStart(&SD2, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + chEvtRegister(&shell_terminated, &tel, 0); + + /* + * Console thread started. + */ + cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, + console_thread, NULL); + + /* + * Initializing connection/disconnection events. + */ + cputs("Shell service started on SD1, SD2"); + cputs(" - Listening for connections on SD1"); + (void) sdGetAndClearFlags(&SD1); + chEvtRegister(&SD1.sevent, &sd1fel, 1); + cputs(" - Listening for connections on SD2"); + (void) sdGetAndClearFlags(&SD2); + chEvtRegister(&SD2.sevent, &sd2fel, 2); + + /* + * Events servicing loop. + */ + while (!chThdShouldTerminate()) + chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); + + /* + * Clean simulator exit. + */ + chEvtUnregister(&SD1.sevent, &sd1fel); + chEvtUnregister(&SD2.sevent, &sd2fel); + return 0; +} diff --git a/demos/Posix-GCC/readme.txt b/demos/Posix-GCC/readme.txt new file mode 100644 index 000000000..7db17cfa6 --- /dev/null +++ b/demos/Posix-GCC/readme.txt @@ -0,0 +1,26 @@ +***************************************************************************** +** ChibiOS/RT port for x86 into a Linux process ** +***************************************************************************** + +** TARGET ** + +The demo runs under x86 Linux as an application program. The serial +I/O is simulated over TCP/IP sockets. + +** The Demo ** + +The demo listens on the two serial ports, when a connection is detected a +thread is started that serves a small command shell. +The demo shows how create/terminate threads at runtime, how listen to events, +how ho work with serial ports, how use the messages. +You can develop your ChibiOS/RT application using this demo as a simulator +then you can recompile it for a different architecture. +See demo.c for details. + +** Build Procedure ** + +GCC required. + +** Connect to the demo ** + +In order to connect to the demo use telnet on the listening ports. -- cgit v1.2.3 From fe7b598fa217929aad1097233efa57acb7ce8783 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Feb 2010 11:31:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1651 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/GNU-Linux-GCC/Makefile | 156 -------------- demos/GNU-Linux-GCC/board.h | 23 -- demos/GNU-Linux-GCC/chconf.h | 476 ----------------------------------------- demos/GNU-Linux-GCC/halconf.h | 152 ------------- demos/GNU-Linux-GCC/main.c | 222 ------------------- demos/GNU-Linux-GCC/readme.txt | 26 --- 6 files changed, 1055 deletions(-) delete mode 100644 demos/GNU-Linux-GCC/Makefile delete mode 100644 demos/GNU-Linux-GCC/board.h delete mode 100644 demos/GNU-Linux-GCC/chconf.h delete mode 100644 demos/GNU-Linux-GCC/halconf.h delete mode 100644 demos/GNU-Linux-GCC/main.c delete mode 100644 demos/GNU-Linux-GCC/readme.txt (limited to 'demos') diff --git a/demos/GNU-Linux-GCC/Makefile b/demos/GNU-Linux-GCC/Makefile deleted file mode 100644 index f32f3c760..000000000 --- a/demos/GNU-Linux-GCC/Makefile +++ /dev/null @@ -1,156 +0,0 @@ -# -# !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!! -# -############################################################################################## -# -# On command line: -# -# make all = Create project -# -# make clean = Clean project files. -# -# To rebuild project do "make clean" and "make all". -# - -############################################################################################## -# Start of default section -# - -TRGT = -CC = $(TRGT)gcc -AS = $(TRGT)gcc -x assembler-with-cpp - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################################## - -############################################################################################## -# Start of user section -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT = - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# Imported source files -CHIBIOS = ../.. -include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/Linux/platform.mk -include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk -include ${CHIBIOS}/os/kernel/kernel.mk -include ${CHIBIOS}/test/test.mk - -# List C source files here -SRC = ${PORTSRC} \ - ${KERNSRC} \ - ${TESTSRC} \ - ${HALSRC} \ - ${PLATFORMSRC} \ - ${CHIBIOS}/os/various/shell.c \ - main.c - -# List ASM source files here -ASRC = - -# List all user directories here -UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ - ${CHIBIOS}/os/various - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# Define optimisation level here -OPT = -ggdb -O2 -fomit-frame-pointer - -# -# End of user defines -############################################################################################## - -INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR)) -LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR)) -DEFS = $(DDEFS) $(UDEFS) -ADEFS = $(DADEFS) $(UADEFS) -OBJS = $(ASRC:.s=.o) $(SRC:.c=.o) -LIBS = $(DLIBS) $(ULIBS) - -ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS) -CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm $(DEFS) - -ifeq ($(HOST_OSX),yes) - OSX_SDK = /Developer/SDKs/MacOSX10.5.sdk - OSX_ARCH = -mmacosx-version-min=10.3 -arch i386 - - CPFLAGS += -isysroot $(OSX_SDK) $(OSX_ARCH) - LDFLAGS = -Wl -Map=$(PROJECT).map,-syslibroot,$(OSX_SDK),$(LIBDIR) - LIBS += $(OSX_ARCH) -else - # Linux, or other - CPFLAGS += -Wa,-alms=$(<:.c=.lst) - LDFLAGS += -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR) -endif - -# Generate dependency information -CPFLAGS += -MD -MP -MF .dep/$(@F).d - -# -# makefile rules -# - -all: $(OBJS) $(PROJECT) - -%o : %c - $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@ - -%o : %s - $(AS) -c $(ASFLAGS) $< -o $@ - -$(PROJECT): $(OBJS) - $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@ - -gcov: - -mkdir gcov - $(COV) -u $(subst /,\,$(SRC)) - -mv *.gcov ./gcov - -clean: - -rm -f $(OBJS) - -rm -f $(PROJECT) - -rm -f $(PROJECT).map - -rm -f $(SRC:.c=.c.bak) - -rm -f $(SRC:.c=.lst) - -rm -f $(ASRC:.s=.s.bak) - -rm -f $(ASRC:.s=.lst) - -rm -fR .dep - -# -# Include the dependency files, should be the last of the makefile -# --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# *** EOF *** diff --git a/demos/GNU-Linux-GCC/board.h b/demos/GNU-Linux-GCC/board.h deleted file mode 100644 index 7b89d92d0..000000000 --- a/demos/GNU-Linux-GCC/board.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#endif /* _BOARD_H_ */ diff --git a/demos/GNU-Linux-GCC/chconf.h b/demos/GNU-Linux-GCC/chconf.h deleted file mode 100644 index 2f45fb0f3..000000000 --- a/demos/GNU-Linux-GCC/chconf.h +++ /dev/null @@ -1,476 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @addtogroup config - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. - * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0x20000 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/GNU-Linux-GCC/halconf.h b/demos/GNU-Linux-GCC/halconf.h deleted file mode 100644 index b325b7238..000000000 --- a/demos/GNU-Linux-GCC/halconf.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -/*#include "mcuconf.h"*/ - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/demos/GNU-Linux-GCC/main.c b/demos/GNU-Linux-GCC/main.c deleted file mode 100644 index 28e136bc8..000000000 --- a/demos/GNU-Linux-GCC/main.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include - -#include "ch.h" -#include "hal.h" -#include "test.h" -#include "shell.h" - -#define SHELL_WA_SIZE THD_WA_SIZE(4096) -#define CONSOLE_WA_SIZE THD_WA_SIZE(4096) -#define TEST_WA_SIZE THD_WA_SIZE(4096) - -#define cputs(msg) chMsgSend(cdtp, (msg_t)msg) - -static Thread *cdtp; -static Thread *shelltp1; -static Thread *shelltp2; - -void cmd_test(BaseChannel *chp, int argc, char *argv[]) { - Thread *tp; - - (void)argv; - if (argc > 0) { - shellPrintLine(chp, "Usage: test"); - return; - } - tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), - TestThread, chp); - if (tp == NULL) { - shellPrintLine(chp, "out of memory"); - return; - } - chThdWait(tp); -} - -static const ShellCommand commands[] = { - {"test", cmd_test}, - {NULL, NULL} -}; - -static const ShellConfig shell_cfg1 = { - (BaseChannel *)&SD1, - commands -}; - -static const ShellConfig shell_cfg2 = { - (BaseChannel *)&SD2, - commands -}; - -/* - * Console print server done using synchronous messages. This makes the access - * to the C printf() thread safe and the print operation atomic among threads. - * In this example the message is the zero termitated string itself. - */ -static msg_t console_thread(void *arg) { - - (void)arg; - while (!chThdShouldTerminate()) { - puts((char *)chMsgWait()); - fflush(stdout); - chMsgRelease(RDY_OK); - } - return 0; -} - -/** - * @brief Shell termination handler. - * - * @param[in] id event id. - */ -static void termination_handler(eventid_t id) { - - (void)id; - if (shelltp1 && chThdTerminated(shelltp1)) { - chThdWait(shelltp1); - shelltp1 = NULL; - chThdSleepMilliseconds(10); - cputs("Init: shell on SD1 terminated"); - chSysLock(); - chOQResetI(&SD1.oqueue); - chSysUnlock(); - } - if (shelltp2 && chThdTerminated(shelltp2)) { - chThdWait(shelltp2); - shelltp2 = NULL; - chThdSleepMilliseconds(10); - cputs("Init: shell on SD2 terminated"); - chSysLock(); - chOQResetI(&SD2.oqueue); - chSysUnlock(); - } -} - -/** - * @brief SD1 status change handler. - * - * @param[in] id event id. - */ -static void sd1_handler(eventid_t id) { - - sdflags_t flags; - - (void)id; - flags = sdGetAndClearFlags(&SD1); - if ((flags & SD_CONNECTED) && (shelltp1 == NULL)) { - cputs("Init: connection on SD1"); - shelltp1 = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO + 1); - } - if (flags & SD_DISCONNECTED) { - cputs("Init: disconnection on SD1"); - chSysLock(); - chIQResetI(&SD1.iqueue); - chSysUnlock(); - } -} - -/** - * @brief SD2 status change handler. - * - * @param[in] id event id. - */ -static void sd2_handler(eventid_t id) { - - sdflags_t flags; - - (void)id; - flags = sdGetAndClearFlags(&SD2); - if ((flags & SD_CONNECTED) && (shelltp2 == NULL)) { - cputs("Init: connection on SD2"); - shelltp2 = shellCreate(&shell_cfg2, SHELL_WA_SIZE, NORMALPRIO + 10); - } - if (flags & SD_DISCONNECTED) { - cputs("Init: disconnection on SD2"); - chSysLock(); - chIQResetI(&SD2.iqueue); - chSysUnlock(); - } -} - -static evhandler_t fhandlers[] = { - termination_handler, - sd1_handler, - sd2_handler -}; - -/*------------------------------------------------------------------------* - * Simulator main. * - *------------------------------------------------------------------------*/ -int main(void) { - EventListener sd1fel, sd2fel, tel; - - /* - * HAL initialization. - */ - halInit(); - - /* - * ChibiOS/RT initialization. - */ - chSysInit(); - - /* - * Serial ports (simulated) initialization. - */ - sdStart(&SD1, NULL); - sdStart(&SD2, NULL); - - /* - * Shell manager initialization. - */ - shellInit(); - chEvtRegister(&shell_terminated, &tel, 0); - - /* - * Console thread started. - */ - cdtp = chThdCreateFromHeap(NULL, CONSOLE_WA_SIZE, NORMALPRIO + 1, - console_thread, NULL); - - /* - * Initializing connection/disconnection events. - */ - cputs("Shell service started on SD1, SD2"); - cputs(" - Listening for connections on SD1"); - (void) sdGetAndClearFlags(&SD1); - chEvtRegister(&SD1.sevent, &sd1fel, 1); - cputs(" - Listening for connections on SD2"); - (void) sdGetAndClearFlags(&SD2); - chEvtRegister(&SD2.sevent, &sd2fel, 2); - - /* - * Events servicing loop. - */ - while (!chThdShouldTerminate()) - chEvtDispatch(fhandlers, chEvtWaitOne(ALL_EVENTS)); - - /* - * Clean simulator exit. - */ - chEvtUnregister(&SD1.sevent, &sd1fel); - chEvtUnregister(&SD2.sevent, &sd2fel); - return 0; -} diff --git a/demos/GNU-Linux-GCC/readme.txt b/demos/GNU-Linux-GCC/readme.txt deleted file mode 100644 index 7db17cfa6..000000000 --- a/demos/GNU-Linux-GCC/readme.txt +++ /dev/null @@ -1,26 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for x86 into a Linux process ** -***************************************************************************** - -** TARGET ** - -The demo runs under x86 Linux as an application program. The serial -I/O is simulated over TCP/IP sockets. - -** The Demo ** - -The demo listens on the two serial ports, when a connection is detected a -thread is started that serves a small command shell. -The demo shows how create/terminate threads at runtime, how listen to events, -how ho work with serial ports, how use the messages. -You can develop your ChibiOS/RT application using this demo as a simulator -then you can recompile it for a different architecture. -See demo.c for details. - -** Build Procedure ** - -GCC required. - -** Connect to the demo ** - -In order to connect to the demo use telnet on the listening ports. -- cgit v1.2.3 From 680d8ef195f97f39894223d1f4062ca05d525c48 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Feb 2010 11:38:56 +0000 Subject: Renamed the Linux simulator in "Posix" because it now supports OS X. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1654 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Posix-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/Posix-GCC/Makefile b/demos/Posix-GCC/Makefile index f32f3c760..37caaf9bd 100644 --- a/demos/Posix-GCC/Makefile +++ b/demos/Posix-GCC/Makefile @@ -58,7 +58,7 @@ UADEFS = # Imported source files CHIBIOS = ../.. include ${CHIBIOS}/os/hal/hal.mk -include ${CHIBIOS}/os/hal/platforms/Linux/platform.mk +include ${CHIBIOS}/os/hal/platforms/Posix/platform.mk include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk include ${CHIBIOS}/os/kernel/kernel.mk include ${CHIBIOS}/test/test.mk -- cgit v1.2.3 From 582ace5597d3bdefcd06b8b4ab673f48c81b969c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Feb 2010 16:29:48 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1660 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC563-GCC/Makefile | 5 +- demos/PPC-SPC563-GCC/main.c | 105 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 104 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/PPC-SPC563-GCC/Makefile b/demos/PPC-SPC563-GCC/Makefile index 65b19bc35..057de4ae0 100644 --- a/demos/PPC-SPC563-GCC/Makefile +++ b/demos/PPC-SPC563-GCC/Makefile @@ -55,7 +55,8 @@ CSRC = $(PORTSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/memstreams.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/syscalls.c \ main.c # C++ sources here. @@ -109,7 +110,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = +DDEFS = -DPPC_VARIANT=PPC_VARIANT_e200z3 # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index df59fd598..db05b1283 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -17,13 +17,97 @@ along with this program. If not, see . */ +#include + #include "ch.h" #include "hal.h" #include "test.h" -#include "memstreams.h" +#include "shell.h" + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { + size_t n, size; + char buf[52]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: mem"); + return; + } + n = chHeapStatus(NULL, &size); + siprintf(buf, "core free memory : %i bytes", chCoreFree()); + shellPrintLine(chp, buf); + siprintf(buf, "heap fragments : %i", n); + shellPrintLine(chp, buf); + siprintf(buf, "heap free total : %i bytes", size); + shellPrintLine(chp, buf); +} -int a = 1234; -uint8_t report_buffer[8192]; +static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { + static const char *states[] = { + "READY", + "CURRENT", + "SUSPENDED", + "WTSEM", + "WTMTX", + "WTCOND", + "SLEEPING", + "WTEXIT", + "WTOREVT", + "WTANDEVT", + "SNDMSG", + "WTMSG", + "FINAL" + }; + Thread *tp; + char buf[60]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: threads"); + return; + } + shellPrintLine(chp, " addr stack prio refs state time"); + tp = chRegFirstThread(); + do { + siprintf(buf, "%8p %8p %4u %4i %9s %u", + tp, tp->p_ctx.sp, (unsigned int)tp->p_prio, tp->p_refs - 1, + states[tp->p_state], (unsigned int)tp->p_time); + shellPrintLine(chp, buf); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: test"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + shellPrintLine(chp, "out of memory"); + return; + } + chThdWait(tp); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD1, + commands +}; /* * LEDs blinker thread, times are in milliseconds. @@ -32,7 +116,7 @@ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { (void)arg; - + SIU.GPDO[GPIO_LED1].R = 1; SIU.GPDO[GPIO_LED2].R = 1; SIU.GPDO[GPIO_LED3].R = 1; @@ -64,6 +148,7 @@ static msg_t Thread1(void *arg) { * on entry. */ int main(int argc, char **argv) { + Thread *shelltp = NULL; (void)argc; (void)argv; @@ -73,6 +158,11 @@ int main(int argc, char **argv) { */ sdStart(&SD1, NULL); + /* + * Shell manager initialization. + */ + shellInit(); + /* * Creates the blinker thread. */ @@ -82,6 +172,13 @@ int main(int argc, char **argv) { * Normal main() thread activity. */ while (TRUE) { + + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } if (SIU.GPDI[GPIO_BUTTON1].B.PDI) { volatile msg_t result; #if 0 -- cgit v1.2.3 From c319732c56b1f38b6201962416795ca8eaff172f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Feb 2010 18:09:56 +0000 Subject: Renamed SPC563 platform to a generic SPC56x. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1663 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC563-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/PPC-SPC563-GCC/Makefile b/demos/PPC-SPC563-GCC/Makefile index 057de4ae0..6aaee3ea4 100644 --- a/demos/PPC-SPC563-GCC/Makefile +++ b/demos/PPC-SPC563-GCC/Makefile @@ -41,7 +41,7 @@ LDSCRIPT = ./ch.ld # Imported source files CHIBIOS = ../.. include $(CHIBIOS)/boards/GENERIC_SPC563/board.mk -include $(CHIBIOS)/os/hal/platforms/SPC563/platform.mk +include $(CHIBIOS)/os/hal/platforms/SPC56x/platform.mk include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/ports/GCC/PPC/port.mk include $(CHIBIOS)/os/kernel/kernel.mk -- cgit v1.2.3 From 01f258f5e20e34a04a491ce9cab64a5bb48b4b7b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Feb 2010 08:25:00 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1677 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC563-GCC/main.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'demos') diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index db05b1283..b846fb405 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -179,6 +179,7 @@ int main(int argc, char **argv) { chThdRelease(shelltp); /* Recovers memory of the previous shell. */ shelltp = NULL; /* Triggers spawning of a new shell. */ } +#if 0 if (SIU.GPDI[GPIO_BUTTON1].B.PDI) { volatile msg_t result; #if 0 @@ -190,6 +191,7 @@ int main(int argc, char **argv) { result = TestThread(&SD1); #endif } +#endif chThdSleepMilliseconds(1000); } return 0; -- cgit v1.2.3 From 943389a5584d3df71d176e508fbcdef3ba201c74 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 3 Mar 2010 10:51:59 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1702 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC563-GCC/main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index b846fb405..f2101c130 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -72,8 +72,9 @@ static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { shellPrintLine(chp, " addr stack prio refs state time"); tp = chRegFirstThread(); do { - siprintf(buf, "%8p %8p %4u %4i %9s %u", - tp, tp->p_ctx.sp, (unsigned int)tp->p_prio, tp->p_refs - 1, + siprintf(buf, "%8lx %8lx %4u %4i %9s %u", + (uint32_t)tp, (uint32_t)tp->p_ctx.sp, + (unsigned int)tp->p_prio, tp->p_refs - 1, states[tp->p_state], (unsigned int)tp->p_time); shellPrintLine(chp, buf); tp = chRegNextThread(tp); -- cgit v1.2.3 From b69948bc4883423fde36e63e2ef5d2d16f7ec71c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 5 Mar 2010 19:01:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1713 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 167 +++++++++++++ demos/STM8S-STM8S208-RC/ch.rprj | 4 + demos/STM8S-STM8S208-RC/chconf.h | 480 ++++++++++++++++++++++++++++++++++++++ demos/STM8S-STM8S208-RC/halconf.h | 152 ++++++++++++ demos/STM8S-STM8S208-RC/main.c | 75 ++++++ demos/STM8S-STM8S208-RC/mcuconf.h | 39 ++++ 6 files changed, 917 insertions(+) create mode 100644 demos/STM8S-STM8S208-RC/ch.rapp create mode 100644 demos/STM8S-STM8S208-RC/ch.rprj create mode 100644 demos/STM8S-STM8S208-RC/chconf.h create mode 100644 demos/STM8S-STM8S208-RC/halconf.h create mode 100644 demos/STM8S-STM8S208-RC/main.c create mode 100644 demos/STM8S-STM8S208-RC/mcuconf.h (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp new file mode 100644 index 000000000..e2f6cea41 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -0,0 +1,167 @@ + + + + + + + + + + +
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+ + + + + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj new file mode 100644 index 000000000..f38f0949c --- /dev/null +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h new file mode 100644 index 000000000..7f7c10431 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -0,0 +1,480 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 3072 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES FALSE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE FALSE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP FALSE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC FALSE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h new file mode 100644 index 000000000..c0f12c57d --- /dev/null +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S208-RC/main.c b/demos/STM8S-STM8S208-RC/main.c new file mode 100644 index 000000000..f427eddee --- /dev/null +++ b/demos/STM8S-STM8S208-RC/main.c @@ -0,0 +1,75 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT2, PB_LED(7)); + chThdSleepMilliseconds(500); + palSetPad(IOPORT2, PB_LED(7)); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Entry point. + */ +void main(void) { + + /* + * Board/HAL initialization. + */ + hwinit(); + + /* + * OS initialization. + */ + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (palReadPad(IOPORT7, PG_BT5) == PAL_LOW) + TestThread(&SD1); + if (palReadPad(IOPORT7, PG_BT6) == PAL_LOW) + sdWriteTimeout(&SD1, "Hello World!\r\n", 14, TIME_INFINITE); + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM8S-STM8S208-RC/mcuconf.h b/demos/STM8S-STM8S208-RC/mcuconf.h new file mode 100644 index 000000000..146ce6719 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/mcuconf.h @@ -0,0 +1,39 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI +#define STM8_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8_CPU_DIVIDER CLK_CPU_DIV1 + +/* + * SERIAL driver system settings. + */ +#define USE_STM8_UART1 TRUE +#define USE_STM8_UART3 FALSE -- cgit v1.2.3 From a528517b440c7b45ad4da7e7ae8c66247dc7c2f0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 5 Mar 2010 19:06:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1714 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 6 +++--- demos/STM8S-STM8S208-RC/chconf.h | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index e2f6cea41..9c2ea401b 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -65,9 +65,9 @@ - + - + @@ -104,7 +104,7 @@ - + diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index 7f7c10431..76f9b3453 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -293,7 +293,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE FALSE +#define CH_USE_MEMCORE TRUE #endif /** @@ -307,7 +307,7 @@ * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP FALSE +#define CH_USE_HEAP TRUE #endif /** @@ -332,7 +332,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS FALSE +#define CH_USE_MEMPOOLS TRUE #endif /** @@ -345,7 +345,7 @@ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC FALSE +#define CH_USE_DYNAMIC TRUE #endif /*===========================================================================*/ -- cgit v1.2.3 From 9df188751bad888ee1c1b9dbb1f6d731637fcc99 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Mar 2010 13:24:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1725 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/readme.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 demos/STM8S-STM8S208-RC/readme.txt (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/readme.txt b/demos/STM8S-STM8S208-RC/readme.txt new file mode 100644 index 000000000..011f75c56 --- /dev/null +++ b/demos/STM8S-STM8S208-RC/readme.txt @@ -0,0 +1,16 @@ +***************************************************************************** +** ChibiOS/RT demo for STM8S208RB. ** +***************************************************************************** + +** TARGET ** + +The demo runs on a Raisonance REva+STM8S208RB board. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port. + +** Build Procedure ** + +From withing the Ride7 IDE open the project, compile and run it. -- cgit v1.2.3 From eb5721207ec3c63c8fcddd39810b851ff72264f6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 7 Mar 2010 08:32:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1727 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 66 +++++++++++++++++++-------------------- demos/STM8S-STM8S208-RC/ch.rprj | 2 +- demos/STM8S-STM8S208-RC/chconf.h | 4 +-- demos/STM8S-STM8S208-RC/halconf.h | 10 +++--- demos/STM8S-STM8S208-RC/main.c | 2 +- demos/STM8S-STM8S208-RC/mcuconf.h | 2 +- 6 files changed, 43 insertions(+), 43 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 9c2ea401b..487fe17a7 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -1,5 +1,5 @@ - + @@ -10,15 +10,15 @@
- +
- + - + - + - + @@ -34,15 +34,15 @@
- +
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- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index f38f0949c..dc557d7be 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index 76f9b3453..26d33b883 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -404,7 +404,7 @@ * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. + * runtime measurement of the used stack. * * @note The default is @p FALSE. */ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index c0f12c57d..763b0019a 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -27,7 +27,7 @@ /* * HAL configuration file, this file allows to enable or disable the various * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * to override the device drivers default settings. */ #ifndef _HALCONF_H_ @@ -36,7 +36,7 @@ /* * Uncomment the following line in order to include a mcu-related * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. + * header files or to override the low level drivers settings. */ #include "mcuconf.h" @@ -45,7 +45,7 @@ /*===========================================================================*/ /** - * @brief Enables the PAL subsystem. + * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) #define CH_HAL_USE_PAL TRUE @@ -124,7 +124,7 @@ #endif /* - * Default SPI settings overrides (uncomment to override). + * Default SPI settings overrides (uncomment to override). */ /*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ diff --git a/demos/STM8S-STM8S208-RC/main.c b/demos/STM8S-STM8S208-RC/main.c index f427eddee..4e714fc15 100644 --- a/demos/STM8S-STM8S208-RC/main.c +++ b/demos/STM8S-STM8S208-RC/main.c @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. diff --git a/demos/STM8S-STM8S208-RC/mcuconf.h b/demos/STM8S-STM8S208-RC/mcuconf.h index 146ce6719..227499992 100644 --- a/demos/STM8S-STM8S208-RC/mcuconf.h +++ b/demos/STM8S-STM8S208-RC/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. This file is part of ChibiOS/RT. -- cgit v1.2.3 From 1585e2851cd4d862b4e08efd2b200f0401110133 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 9 Mar 2010 13:43:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1733 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp | 139 +++++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj | 4 + demos/STM8S-STM8S208-RC/ch.rapp | 66 +++++++-------- 3 files changed, 176 insertions(+), 33 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp create mode 100644 demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp b/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp new file mode 100644 index 000000000..3dbacd826 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp @@ -0,0 +1,139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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- +
- +
- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index dc557d7be..bf57adfd4 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - + \ No newline at end of file -- cgit v1.2.3 From c7837bab2ee164d6bb4fb47948ee5fe33162b449 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 14 Mar 2010 09:54:23 +0000 Subject: AVR and simulator still missing. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1740 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/mcuconf.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/mcuconf.h b/demos/MSP430-MSP430x1611-GCC/mcuconf.h index d0cba2d41..72c180648 100644 --- a/demos/MSP430-MSP430x1611-GCC/mcuconf.h +++ b/demos/MSP430-MSP430x1611-GCC/mcuconf.h @@ -25,6 +25,11 @@ * is enabled in halconf.h. */ +/* + * HAL driver system settings. + */ +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK + /* * ADC driver system settings. */ -- cgit v1.2.3 From 79075f9e81d9d56be5da3bf6cdae56f4ace950de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 19 Mar 2010 12:48:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1755 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/ARM7-LPC214x-G++/chconf.h | 215 ++++++++++++++++-------------- demos/ARM7-LPC214x-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/ARMCM3-STM32F103-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/AVR-AT90CANx-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/AVR-ATmega128-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/MSP430-MSP430x1611-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/PPC-SPC563-GCC/chconf.h | 215 +++++++++++++++--------------- demos/Posix-GCC/chconf.h | 215 ++++++++++++++++-------------- demos/STM8S-STM8S208-RC/chconf.h | 1 + demos/Win32-MinGW/chconf.h | 215 ++++++++++++++++-------------- 15 files changed, 1568 insertions(+), 1443 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 300a85579..046d28300 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 47f38904b..367215352 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -435,11 +444,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -449,12 +458,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -463,7 +472,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 300a85579..046d28300 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index 300a85579..046d28300 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 300a85579..046d28300 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 300a85579..046d28300 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index 300a85579..046d28300 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 300a85579..046d28300 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index c32d36bdc..2cda27e83 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 128 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index c32d36bdc..2cda27e83 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 128 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 5629c38e3..2a40e33e2 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 10 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 512 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h index 557c2a5a1..046d28300 100644 --- a/demos/PPC-SPC563-GCC/chconf.h +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,22 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero * disables the preemption for threads with equal priority and the * round robin becomes cooperative. Note that higher priority * threads can still preempt, the kernel is always preemptive. * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -64,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -90,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -126,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. + * @brief Atomic semaphore API. * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -349,73 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -426,20 +431,22 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) #define THREAD_EXT_FIELDS \ - /* Add threads custom fields here.*/ +struct { \ + /* Add threads custom fields here.*/ \ +}; #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -448,12 +455,12 @@ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -462,7 +469,7 @@ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h index 2f45fb0f3..dd249746f 100644 --- a/demos/Posix-GCC/chconf.h +++ b/demos/Posix-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0x20000 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index 26d33b883..5643c94e7 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -24,6 +24,7 @@ * contains the application specific kernel settings. * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 2f45fb0f3..dd249746f 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0x20000 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,219 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads registry APIs. + * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) #define CH_USE_REGISTRY TRUE #endif /** - * @brief Threads synchronization APIs. + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -347,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -422,7 +431,7 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ #if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) @@ -433,11 +442,11 @@ struct { \ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ #if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) #define THREAD_EXT_INIT(tp) { \ @@ -446,12 +455,12 @@ struct { \ #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ #if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) #define THREAD_EXT_EXIT(tp) { \ @@ -460,7 +469,7 @@ struct { \ #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -- cgit v1.2.3 From 7a55853754afa52e82fdb28835b8ae0900d2f04e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 20 Mar 2010 07:41:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1762 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 5 +++++ demos/ARMCM3-STM32F103-GCC/mcuconf.h | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index e6216b886..13e210f5a 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -34,6 +34,11 @@ * 0...3 Lowest...Highest. */ +/* + * HAL driver settings. + */ +#define STM32_SYSCLK 72 + /* * ADC driver system settings. */ diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index e6216b886..13e210f5a 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -34,6 +34,11 @@ * 0...3 Lowest...Highest. */ +/* + * HAL driver settings. + */ +#define STM32_SYSCLK 72 + /* * ADC driver system settings. */ -- cgit v1.2.3 From 04ad87d77bcf62ab400d522a16a3c4f0433821de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 20 Mar 2010 07:45:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1764 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 2 +- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index 13e210f5a..f7ce9ef55 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -35,7 +35,7 @@ */ /* - * HAL driver settings. + * HAL driver system settings. */ #define STM32_SYSCLK 72 diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 13e210f5a..f7ce9ef55 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -35,7 +35,7 @@ */ /* - * HAL driver settings. + * HAL driver system settings. */ #define STM32_SYSCLK 72 -- cgit v1.2.3 From 167f5bc8781dd66539cd5db5a48f465457d9a8bb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Mar 2010 12:29:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1769 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 35 ++++++++++++++++++----------------- 2 files changed, 20 insertions(+), 19 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index fd97754ff..347a6f7e0 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCM3/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = +DDEFS = -DSTM32F10X_MD # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index f7ce9ef55..ae6a7a125 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -25,10 +25,11 @@ * is enabled in halconf.h. * * IRQ priorities: - * 0xF0 Lowest, priority level reserved for PENDSV. - * 0xE0...0x40 Normal IRQs priority levels (0x80 used by SYSTICK). - * 0x30 Used by SVCALL, do not share. - * 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it. + * 15 Lowest, priority level reserved for PENDSV. + * 14...4 Normal IRQs priority levels (0x80 used by SYSTICK). + * 3 Used by SVCALL, do not share. + * 2...0 Fast interrupts, can preempt the kernel but cannot use it + * directly. * * DMA priorities: * 0...3 Lowest...Highest. @@ -44,14 +45,14 @@ */ #define USE_STM32_ADC1 TRUE #define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 0x50 +#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5) #define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() /* * CAN driver system settings. */ #define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 0xB0 +#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11) /* * PWM driver system settings. @@ -60,10 +61,10 @@ #define USE_STM32_PWM2 FALSE #define USE_STM32_PWM3 FALSE #define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 0x70 -#define STM32_PWM2_IRQ_PRIORITY 0x70 -#define STM32_PWM3_IRQ_PRIORITY 0x70 -#define STM32_PWM4_IRQ_PRIORITY 0x70 +#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7) /* * SERIAL driver system settings. @@ -75,12 +76,12 @@ #define USE_STM32_UART4 FALSE #define USE_STM32_UART5 FALSE #endif -#define STM32_USART1_PRIORITY 0xC0 -#define STM32_USART2_PRIORITY 0xC0 -#define STM32_USART3_PRIORITY 0xC0 +#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12) #if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 0xC0 -#define STM32_UART5_PRIORITY 0xC0 +#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12) +#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12) #endif /* @@ -90,6 +91,6 @@ #define USE_STM32_SPI2 TRUE #define STM32_SPI1_DMA_PRIORITY 2 #define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 0xA0 -#define STM32_SPI2_IRQ_PRIORITY 0xA0 +#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10) +#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10) #define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() -- cgit v1.2.3 From 36f96c9fef7b5670dc9ab1c73c928d66b5bf4492 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Mar 2010 13:39:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1771 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 6 ++--- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 35 +++++++++++++++--------------- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- 3 files changed, 23 insertions(+), 22 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index a4822a4c7..ced25453b 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCM3/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/ext/fatfs/fatfs.mk @@ -104,7 +104,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ @@ -156,7 +156,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 +DDEFS = -DSTM32F10X_MD -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index f7ce9ef55..ae6a7a125 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -25,10 +25,11 @@ * is enabled in halconf.h. * * IRQ priorities: - * 0xF0 Lowest, priority level reserved for PENDSV. - * 0xE0...0x40 Normal IRQs priority levels (0x80 used by SYSTICK). - * 0x30 Used by SVCALL, do not share. - * 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it. + * 15 Lowest, priority level reserved for PENDSV. + * 14...4 Normal IRQs priority levels (0x80 used by SYSTICK). + * 3 Used by SVCALL, do not share. + * 2...0 Fast interrupts, can preempt the kernel but cannot use it + * directly. * * DMA priorities: * 0...3 Lowest...Highest. @@ -44,14 +45,14 @@ */ #define USE_STM32_ADC1 TRUE #define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 0x50 +#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5) #define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() /* * CAN driver system settings. */ #define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 0xB0 +#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11) /* * PWM driver system settings. @@ -60,10 +61,10 @@ #define USE_STM32_PWM2 FALSE #define USE_STM32_PWM3 FALSE #define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 0x70 -#define STM32_PWM2_IRQ_PRIORITY 0x70 -#define STM32_PWM3_IRQ_PRIORITY 0x70 -#define STM32_PWM4_IRQ_PRIORITY 0x70 +#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7) /* * SERIAL driver system settings. @@ -75,12 +76,12 @@ #define USE_STM32_UART4 FALSE #define USE_STM32_UART5 FALSE #endif -#define STM32_USART1_PRIORITY 0xC0 -#define STM32_USART2_PRIORITY 0xC0 -#define STM32_USART3_PRIORITY 0xC0 +#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12) #if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 0xC0 -#define STM32_UART5_PRIORITY 0xC0 +#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12) +#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12) #endif /* @@ -90,6 +91,6 @@ #define USE_STM32_SPI2 TRUE #define STM32_SPI1_DMA_PRIORITY 2 #define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 0xA0 -#define STM32_SPI2_IRQ_PRIORITY 0xA0 +#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10) +#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10) #define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 347a6f7e0..0c6ba31ba 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From 2dc90132f594e40469dade7412168fe89b10134f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Mar 2010 10:55:10 +0000 Subject: Cortex-M0 related files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1779 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-LPC1114-GCC/Makefile | 192 +++++++++++++++ demos/ARMCM3-LPC1114-GCC/ch.ld | 94 ++++++++ demos/ARMCM3-LPC1114-GCC/chconf.h | 483 +++++++++++++++++++++++++++++++++++++ demos/ARMCM3-LPC1114-GCC/halconf.h | 152 ++++++++++++ demos/ARMCM3-LPC1114-GCC/main.c | 69 ++++++ demos/ARMCM3-LPC1114-GCC/mcuconf.h | 57 +++++ 6 files changed, 1047 insertions(+) create mode 100644 demos/ARMCM3-LPC1114-GCC/Makefile create mode 100644 demos/ARMCM3-LPC1114-GCC/ch.ld create mode 100644 demos/ARMCM3-LPC1114-GCC/chconf.h create mode 100644 demos/ARMCM3-LPC1114-GCC/halconf.h create mode 100644 demos/ARMCM3-LPC1114-GCC/main.c create mode 100644 demos/ARMCM3-LPC1114-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARMCM3-LPC1114-GCC/Makefile b/demos/ARMCM3-LPC1114-GCC/Makefile new file mode 100644 index 000000000..59a108cfe --- /dev/null +++ b/demos/ARMCM3-LPC1114-GCC/Makefile @@ -0,0 +1,192 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +#include $(CHIBIOS)/boards/EA_LPCXPRESSO_MB/board.mk +#include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-LPC1114-GCC/ch.ld b/demos/ARMCM3-LPC1114-GCC/ch.ld new file mode 100644 index 000000000..8497ebeea --- /dev/null +++ b/demos/ARMCM3-LPC1114-GCC/ch.ld @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1114 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(4) SUBALIGN(4) + { + _text = .; + KEEP(*(vectors)); + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-LPC1114-GCC/chconf.h b/demos/ARMCM3-LPC1114-GCC/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARMCM3-LPC1114-GCC/chconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1114-GCC/halconf.h b/demos/ARMCM3-LPC1114-GCC/halconf.h new file mode 100644 index 000000000..ef45f36bd --- /dev/null +++ b/demos/ARMCM3-LPC1114-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL FALSE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1114-GCC/main.c b/demos/ARMCM3-LPC1114-GCC/main.c new file mode 100644 index 000000000..0072f0958 --- /dev/null +++ b/demos/ARMCM3-LPC1114-GCC/main.c @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/ARMCM3-LPC1114-GCC/mcuconf.h b/demos/ARMCM3-LPC1114-GCC/mcuconf.h new file mode 100644 index 000000000..d87dccc7b --- /dev/null +++ b/demos/ARMCM3-LPC1114-GCC/mcuconf.h @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1114 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3 Lowest, priority level reserved for PENDSV, do not share or + * use for non-OS-capable low priority handlers. + * 2...1 Normal IRQs priority levels, use for OS-capable handlers. + * 0 Used by SVCALL, do not share or use for non-OS-capable high + * priority handlers. + */ + +/* + * HAL driver system settings. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ + +/* + * SPI driver system settings. + */ -- cgit v1.2.3 From 9d3415bdf3d355fea5e0d09c062ebdad15bb2d4a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Mar 2010 13:31:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1782 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 192 +++++++++++++++ demos/ARMCM0-LPC1114-GCC/ch.ld | 94 ++++++++ demos/ARMCM0-LPC1114-GCC/chconf.h | 483 +++++++++++++++++++++++++++++++++++++ demos/ARMCM0-LPC1114-GCC/halconf.h | 152 ++++++++++++ demos/ARMCM0-LPC1114-GCC/main.c | 69 ++++++ demos/ARMCM0-LPC1114-GCC/mcuconf.h | 57 +++++ demos/ARMCM3-LPC1114-GCC/Makefile | 192 --------------- demos/ARMCM3-LPC1114-GCC/ch.ld | 94 -------- demos/ARMCM3-LPC1114-GCC/chconf.h | 483 ------------------------------------- demos/ARMCM3-LPC1114-GCC/halconf.h | 152 ------------ demos/ARMCM3-LPC1114-GCC/main.c | 69 ------ demos/ARMCM3-LPC1114-GCC/mcuconf.h | 57 ----- 12 files changed, 1047 insertions(+), 1047 deletions(-) create mode 100644 demos/ARMCM0-LPC1114-GCC/Makefile create mode 100644 demos/ARMCM0-LPC1114-GCC/ch.ld create mode 100644 demos/ARMCM0-LPC1114-GCC/chconf.h create mode 100644 demos/ARMCM0-LPC1114-GCC/halconf.h create mode 100644 demos/ARMCM0-LPC1114-GCC/main.c create mode 100644 demos/ARMCM0-LPC1114-GCC/mcuconf.h delete mode 100644 demos/ARMCM3-LPC1114-GCC/Makefile delete mode 100644 demos/ARMCM3-LPC1114-GCC/ch.ld delete mode 100644 demos/ARMCM3-LPC1114-GCC/chconf.h delete mode 100644 demos/ARMCM3-LPC1114-GCC/halconf.h delete mode 100644 demos/ARMCM3-LPC1114-GCC/main.c delete mode 100644 demos/ARMCM3-LPC1114-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile new file mode 100644 index 000000000..59a108cfe --- /dev/null +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -0,0 +1,192 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +#include $(CHIBIOS)/boards/EA_LPCXPRESSO_MB/board.mk +#include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk +#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM0-LPC1114-GCC/ch.ld b/demos/ARMCM0-LPC1114-GCC/ch.ld new file mode 100644 index 000000000..8497ebeea --- /dev/null +++ b/demos/ARMCM0-LPC1114-GCC/ch.ld @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1114 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(4) SUBALIGN(4) + { + _text = .; + KEEP(*(vectors)); + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM0-LPC1114-GCC/chconf.h b/demos/ARMCM0-LPC1114-GCC/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARMCM0-LPC1114-GCC/chconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h new file mode 100644 index 000000000..ef45f36bd --- /dev/null +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL FALSE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c new file mode 100644 index 000000000..0072f0958 --- /dev/null +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/ARMCM0-LPC1114-GCC/mcuconf.h b/demos/ARMCM0-LPC1114-GCC/mcuconf.h new file mode 100644 index 000000000..d87dccc7b --- /dev/null +++ b/demos/ARMCM0-LPC1114-GCC/mcuconf.h @@ -0,0 +1,57 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1114 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3 Lowest, priority level reserved for PENDSV, do not share or + * use for non-OS-capable low priority handlers. + * 2...1 Normal IRQs priority levels, use for OS-capable handlers. + * 0 Used by SVCALL, do not share or use for non-OS-capable high + * priority handlers. + */ + +/* + * HAL driver system settings. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ + +/* + * SPI driver system settings. + */ diff --git a/demos/ARMCM3-LPC1114-GCC/Makefile b/demos/ARMCM3-LPC1114-GCC/Makefile deleted file mode 100644 index 59a108cfe..000000000 --- a/demos/ARMCM3-LPC1114-GCC/Makefile +++ /dev/null @@ -1,192 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -#include $(CHIBIOS)/boards/EA_LPCXPRESSO_MB/board.mk -#include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk -#include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -#include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m0 - -TRGT = arm-none-eabi- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DLPC1114 - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-LPC1114-GCC/ch.ld b/demos/ARMCM3-LPC1114-GCC/ch.ld deleted file mode 100644 index 8497ebeea..000000000 --- a/demos/ARMCM3-LPC1114-GCC/ch.ld +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * LPC1114 memory setup. - */ -__main_stack_size__ = 0x0100; -__process_stack_size__ = 0x0100; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x00000000, len = 32k - ram : org = 0x10000000, len = 8k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(4) SUBALIGN(4) - { - _text = .; - KEEP(*(vectors)); - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash - - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram - - /DISCARD/ : - { - *(.eh_*) - } -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-LPC1114-GCC/chconf.h b/demos/ARMCM3-LPC1114-GCC/chconf.h deleted file mode 100644 index 046d28300..000000000 --- a/demos/ARMCM3-LPC1114-GCC/chconf.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/ARMCM3-LPC1114-GCC/halconf.h b/demos/ARMCM3-LPC1114-GCC/halconf.h deleted file mode 100644 index ef45f36bd..000000000 --- a/demos/ARMCM3-LPC1114-GCC/halconf.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL FALSE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/demos/ARMCM3-LPC1114-GCC/main.c b/demos/ARMCM3-LPC1114-GCC/main.c deleted file mode 100644 index 0072f0958..000000000 --- a/demos/ARMCM3-LPC1114-GCC/main.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - palSetPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (TRUE) { - if (palReadPad(IOPORT1, GPIOA_BUTTON)) - TestThread(&SD2); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/demos/ARMCM3-LPC1114-GCC/mcuconf.h b/demos/ARMCM3-LPC1114-GCC/mcuconf.h deleted file mode 100644 index d87dccc7b..000000000 --- a/demos/ARMCM3-LPC1114-GCC/mcuconf.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * LPC1114 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 3 Lowest, priority level reserved for PENDSV, do not share or - * use for non-OS-capable low priority handlers. - * 2...1 Normal IRQs priority levels, use for OS-capable handlers. - * 0 Used by SVCALL, do not share or use for non-OS-capable high - * priority handlers. - */ - -/* - * HAL driver system settings. - */ - -/* - * ADC driver system settings. - */ - -/* - * CAN driver system settings. - */ - -/* - * PWM driver system settings. - */ - -/* - * SERIAL driver system settings. - */ - -/* - * SPI driver system settings. - */ -- cgit v1.2.3 From a6c627641ed547ca3ee968bceb2c366a2dfe263e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Mar 2010 15:08:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1784 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 2 +- demos/ARMCM0-LPC1114-GCC/main.c | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index 59a108cfe..dcfec8ce6 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -148,7 +148,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DLPC1114 +DDEFS = -DLPC1114 -D__NEWLIB__ # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 0072f0958..0dd187ecd 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -18,8 +18,8 @@ */ #include "ch.h" -#include "hal.h" -#include "test.h" +//#include "hal.h" +//#include "test.h" /* * Red LEDs blinker thread, times are in milliseconds. @@ -29,9 +29,9 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { - palClearPad(IOPORT3, GPIOC_LED); +// palClearPad(IOPORT3, GPIOC_LED); chThdSleepMilliseconds(500); - palSetPad(IOPORT3, GPIOC_LED); +// palSetPad(IOPORT3, GPIOC_LED); chThdSleepMilliseconds(500); } return 0; @@ -49,7 +49,7 @@ int main(int argc, char **argv) { /* * Activates the serial driver 2 using the driver default configuration. */ - sdStart(&SD2, NULL); +// sdStart(&SD2, NULL); /* * Creates the blinker thread. @@ -61,8 +61,8 @@ int main(int argc, char **argv) { * sleeping in a loop and check the button state. */ while (TRUE) { - if (palReadPad(IOPORT1, GPIOA_BUTTON)) - TestThread(&SD2); +// if (palReadPad(IOPORT1, GPIOA_BUTTON)) +// TestThread(&SD2); chThdSleepMilliseconds(500); } return 0; -- cgit v1.2.3 From a6c62e43d8b79fb55f717658e6963e15ccfa1e5a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Mar 2010 16:33:03 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1787 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 6 +++--- demos/ARMCM0-LPC1114-GCC/main.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index dcfec8ce6..0722b8604 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -52,9 +52,9 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. -#include $(CHIBIOS)/boards/EA_LPCXPRESSO_MB/board.mk -#include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk -#include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1114/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk +include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk include $(CHIBIOS)/os/kernel/kernel.mk #include $(CHIBIOS)/test/test.mk diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 0dd187ecd..11c3eb76b 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -18,7 +18,7 @@ */ #include "ch.h" -//#include "hal.h" +#include "hal.h" //#include "test.h" /* -- cgit v1.2.3 From 14e3252a6e637d3fbf435433b876536d610e5336 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Mar 2010 16:37:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1788 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index 0722b8604..e776ab4c5 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From 32d5fbbb2109a98bb753b4dd9c75ff26d5697ef1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Mar 2010 09:14:23 +0000 Subject: Fixed n00bness in cmsis files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1793 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index e776ab4c5..6b828dee3 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -53,9 +53,9 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1114/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk +include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk include $(CHIBIOS)/os/kernel/kernel.mk #include $(CHIBIOS)/test/test.mk @@ -97,7 +97,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From 57413b1a96485c36d09c284834ab37db52bd62a7 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 29 Mar 2010 09:12:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1802 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 4 ++-- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index ced25453b..c9354ec9e 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/ext/fatfs/fatfs.mk @@ -104,7 +104,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 0c6ba31ba..347a6f7e0 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From 1134fe2a87e70cad601394793f0f01cfef066b70 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 30 Mar 2010 17:04:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1814 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 32 +- demos/ARMCM3-STM32F103-GCC-ALT/Makefile | 204 ++++++++++++ demos/ARMCM3-STM32F103-GCC-ALT/ch.ld | 94 ++++++ demos/ARMCM3-STM32F103-GCC-ALT/chconf.h | 483 +++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC-ALT/halconf.h | 152 +++++++++ demos/ARMCM3-STM32F103-GCC-ALT/main.c | 69 +++++ demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h | 92 ++++++ demos/ARMCM3-STM32F103-GCC-ALT/readme.txt | 28 ++ demos/ARMCM3-STM32F103-GCC/mcuconf.h | 32 +- 9 files changed, 1150 insertions(+), 36 deletions(-) create mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/Makefile create mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/ch.ld create mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/chconf.h create mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/halconf.h create mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/main.c create mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h create mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/readme.txt (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index ae6a7a125..28ae05e73 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -25,11 +25,7 @@ * is enabled in halconf.h. * * IRQ priorities: - * 15 Lowest, priority level reserved for PENDSV. - * 14...4 Normal IRQs priority levels (0x80 used by SYSTICK). - * 3 Used by SVCALL, do not share. - * 2...0 Fast interrupts, can preempt the kernel but cannot use it - * directly. + * 15...0 Lowest...Highest. * * DMA priorities: * 0...3 Lowest...Highest. @@ -45,14 +41,14 @@ */ #define USE_STM32_ADC1 TRUE #define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5) +#define STM32_ADC1_IRQ_PRIORITY 5 #define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() /* * CAN driver system settings. */ #define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11) +#define STM32_CAN1_IRQ_PRIORITY 11 /* * PWM driver system settings. @@ -61,10 +57,10 @@ #define USE_STM32_PWM2 FALSE #define USE_STM32_PWM3 FALSE #define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7) -#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7) -#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7) -#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM4_IRQ_PRIORITY 7 /* * SERIAL driver system settings. @@ -76,12 +72,12 @@ #define USE_STM32_UART4 FALSE #define USE_STM32_UART5 FALSE #endif -#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12) -#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12) -#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART1_PRIORITY 12 +#define STM32_USART2_PRIORITY 12 +#define STM32_USART3_PRIORITY 12 #if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12) -#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12) +#define STM32_UART4_PRIORITY 12 +#define STM32_UART5_PRIORITY 12 #endif /* @@ -91,6 +87,6 @@ #define USE_STM32_SPI2 TRUE #define STM32_SPI1_DMA_PRIORITY 2 #define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10) -#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10) +#define STM32_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI2_IRQ_PRIORITY 10 #define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/Makefile b/demos/ARMCM3-STM32F103-GCC-ALT/Makefile new file mode 100644 index 000000000..36567e197 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/Makefile @@ -0,0 +1,204 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +TRGT = arm-elf- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTM32F10X_MD + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld b/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld new file mode 100644 index 000000000..1405765cd --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F103 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0400; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 20k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)); + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h new file mode 100644 index 000000000..763b0019a --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/main.c b/demos/ARMCM3-STM32F103-GCC-ALT/main.c new file mode 100644 index 000000000..0072f0958 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/main.c @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h new file mode 100644 index 000000000..28ae05e73 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h @@ -0,0 +1,92 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SYSCLK 72 + +/* + * ADC driver system settings. + */ +#define USE_STM32_ADC1 TRUE +#define STM32_ADC1_DMA_PRIORITY 3 +#define STM32_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define USE_STM32_CAN1 TRUE +#define STM32_CAN1_IRQ_PRIORITY 11 + +/* + * PWM driver system settings. + */ +#define USE_STM32_PWM1 TRUE +#define USE_STM32_PWM2 FALSE +#define USE_STM32_PWM3 FALSE +#define USE_STM32_PWM4 FALSE +#define STM32_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM4_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define USE_STM32_USART1 FALSE +#define USE_STM32_USART2 TRUE +#define USE_STM32_USART3 FALSE +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define USE_STM32_UART4 FALSE +#define USE_STM32_UART5 FALSE +#endif +#define STM32_USART1_PRIORITY 12 +#define STM32_USART2_PRIORITY 12 +#define STM32_USART3_PRIORITY 12 +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define STM32_UART4_PRIORITY 12 +#define STM32_UART5_PRIORITY 12 +#endif + +/* + * SPI driver system settings. + */ +#define USE_STM32_SPI1 TRUE +#define USE_STM32_SPI2 TRUE +#define STM32_SPI1_DMA_PRIORITY 2 +#define STM32_SPI2_DMA_PRIORITY 2 +#define STM32_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt b/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt new file mode 100644 index 000000000..353dd2658 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** +***************************************************************************** + +** TARGET ** + +The demo will on an Olimex STM32-P103 board. + +** The Demo ** + +The demo flashes the board LED using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +COM2 (USART2). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain, +YAGARTO and an experimental WinARM build including GCC 4.3.0. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index ae6a7a125..28ae05e73 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -25,11 +25,7 @@ * is enabled in halconf.h. * * IRQ priorities: - * 15 Lowest, priority level reserved for PENDSV. - * 14...4 Normal IRQs priority levels (0x80 used by SYSTICK). - * 3 Used by SVCALL, do not share. - * 2...0 Fast interrupts, can preempt the kernel but cannot use it - * directly. + * 15...0 Lowest...Highest. * * DMA priorities: * 0...3 Lowest...Highest. @@ -45,14 +41,14 @@ */ #define USE_STM32_ADC1 TRUE #define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5) +#define STM32_ADC1_IRQ_PRIORITY 5 #define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() /* * CAN driver system settings. */ #define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11) +#define STM32_CAN1_IRQ_PRIORITY 11 /* * PWM driver system settings. @@ -61,10 +57,10 @@ #define USE_STM32_PWM2 FALSE #define USE_STM32_PWM3 FALSE #define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7) -#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7) -#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7) -#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7) +#define STM32_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM4_IRQ_PRIORITY 7 /* * SERIAL driver system settings. @@ -76,12 +72,12 @@ #define USE_STM32_UART4 FALSE #define USE_STM32_UART5 FALSE #endif -#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12) -#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12) -#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12) +#define STM32_USART1_PRIORITY 12 +#define STM32_USART2_PRIORITY 12 +#define STM32_USART3_PRIORITY 12 #if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12) -#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12) +#define STM32_UART4_PRIORITY 12 +#define STM32_UART5_PRIORITY 12 #endif /* @@ -91,6 +87,6 @@ #define USE_STM32_SPI2 TRUE #define STM32_SPI1_DMA_PRIORITY 2 #define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10) -#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10) +#define STM32_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI2_IRQ_PRIORITY 10 #define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() -- cgit v1.2.3 From 803fbc154737e527386cfd56e706c7b8f9a152e8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 31 Mar 2010 17:10:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1821 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC-ALT/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/Makefile b/demos/ARMCM3-STM32F103-GCC-ALT/Makefile index 36567e197..347a6f7e0 100644 --- a/demos/ARMCM3-STM32F103-GCC-ALT/Makefile +++ b/demos/ARMCM3-STM32F103-GCC-ALT/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 347a6f7e0..36567e197 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk -- cgit v1.2.3 From 3bc41906b36968c2a2e7a753e572e7067fa737a3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 31 Mar 2010 20:35:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1823 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 36567e197..681c9c790 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTM32F10X_MD +DDEFS = -DSTM32F10X_MD -DCORTEX_USE_BASEPRI=TRUE # List all default ASM defines here, like -D_DEBUG=1 DADEFS = -- cgit v1.2.3 From c047b2198006076a00ebfe9cff9e8537aeb8ca96 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 2 Apr 2010 08:11:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1825 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC-ALT/Makefile | 204 ------------- demos/ARMCM3-STM32F103-GCC-ALT/ch.ld | 94 ------ demos/ARMCM3-STM32F103-GCC-ALT/chconf.h | 483 ------------------------------ demos/ARMCM3-STM32F103-GCC-ALT/halconf.h | 152 ---------- demos/ARMCM3-STM32F103-GCC-ALT/main.c | 69 ----- demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h | 92 ------ demos/ARMCM3-STM32F103-GCC-ALT/readme.txt | 28 -- 7 files changed, 1122 deletions(-) delete mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/Makefile delete mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/ch.ld delete mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/chconf.h delete mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/halconf.h delete mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/main.c delete mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h delete mode 100644 demos/ARMCM3-STM32F103-GCC-ALT/readme.txt (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/Makefile b/demos/ARMCM3-STM32F103-GCC-ALT/Makefile deleted file mode 100644 index 347a6f7e0..000000000 --- a/demos/ARMCM3-STM32F103-GCC-ALT/Makefile +++ /dev/null @@ -1,204 +0,0 @@ -############################################################################## -# Build global options -# NOTE: Can be overridden externally. -# - -# Compiler options here. -ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 -endif - -# C++ specific options here (added to USE_OPT). -ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti -endif - -# Enable this if you want the linker to remove unused code and data -ifeq ($(USE_LINK_GC),) - USE_LINK_GC = yes -endif - -# If enabled, this option allows to compile the application in THUMB mode. -ifeq ($(USE_THUMB),) - USE_THUMB = yes -endif - -# Enable register caching optimization (read documentation). -ifeq ($(USE_CURRP_CACHING),) - USE_CURRP_CACHING = no -endif - -# -# Build global options -############################################################################## - -############################################################################## -# Architecture or project specific options -# - -# Enable this if you really want to use the STM FWLib. -ifeq ($(USE_FWLIB),) - USE_FWLIB = no -endif - -# -# Architecture or project specific options -############################################################################## - -############################################################################## -# Project, sources and paths -# - -# Define project name here -PROJECT = ch - -# Define linker script file here -LDSCRIPT= ch.ld - -# Imported source files -CHIBIOS = ../.. -include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk - -# C sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CSRC = $(PORTSRC) \ - $(KERNSRC) \ - $(TESTSRC) \ - $(HALSRC) \ - $(PLATFORMSRC) \ - $(BOARDSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ - $(CHIBIOS)/os/various/syscalls.c \ - main.c - -# C++ sources that can be compiled in ARM or THUMB mode depending on the global -# setting. -CPPSRC = - -# C sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACSRC = - -# C++ sources to be compiled in ARM mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -ACPPSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCSRC = - -# C sources to be compiled in THUMB mode regardless of the global setting. -# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler -# option that results in lower performance and larger code size. -TCPPSRC = - -# List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s - -INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ - $(CHIBIOS)/os/various - -# -# Project, sources and paths -############################################################################## - -############################################################################## -# Compiler settings -# - -MCU = cortex-m3 - -TRGT = arm-elf- -CC = $(TRGT)gcc -CPPC = $(TRGT)g++ -# Enable loading with g++ only if you need C++ runtime support. -# NOTE: You can use C++ even without C++ support if you are careful. C++ -# runtime support makes code size explode. -LD = $(TRGT)gcc -#LD = $(TRGT)g++ -CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp -OD = $(TRGT)objdump -HEX = $(CP) -O ihex -BIN = $(CP) -O binary - -# ARM-specific options here -AOPT = - -# THUMB-specific options here -TOPT = -mthumb -DTHUMB - -# Define C warning options here -CWARN = -Wall -Wextra -Wstrict-prototypes - -# Define C++ warning options here -CPPWARN = -Wall -Wextra - -# -# Compiler settings -############################################################################## - -############################################################################## -# Start of default section -# - -# List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTM32F10X_MD - -# List all default ASM defines here, like -D_DEBUG=1 -DADEFS = - -# List all default directories to look for include files here -DINCDIR = - -# List the default directory to look for the libraries here -DLIBDIR = - -# List all default libraries here -DLIBS = - -# -# End of default section -############################################################################## - -############################################################################## -# Start of user section -# - -# List all user C define here, like -D_DEBUG=1 -UDEFS = - -# Define ASM defines here -UADEFS = - -# List all user directories here -UINCDIR = - -# List the user directory to look for the libraries here -ULIBDIR = - -# List all user libraries here -ULIBS = - -# -# End of user defines -############################################################################## - -ifeq ($(USE_FWLIB),yes) - include $(CHIBIOS)/ext/stm32lib/stm32lib.mk - CSRC += $(STM32SRC) - INCDIR += $(STM32INC) - USE_OPT += -DUSE_STDPERIPH_DRIVER -endif - -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld b/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld deleted file mode 100644 index 1405765cd..000000000 --- a/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld +++ /dev/null @@ -1,94 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * ST32F103 memory setup. - */ -__main_stack_size__ = 0x0200; -__process_stack_size__ = 0x0400; -__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; - -MEMORY -{ - flash : org = 0x08000000, len = 128k - ram : org = 0x20000000, len = 20k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -SECTIONS -{ - . = 0; - - .text : ALIGN(16) SUBALIGN(16) - { - _text = .; - KEEP(*(vectors)); - *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; - } > flash - - _textdata = _etext; - - .data : - { - _data = .; - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - _edata = .; - } > ram AT > flash - - .bss : - { - _bss_start = .; - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - _bss_end = .; - } > ram - - /DISCARD/ : - { - *(.eh_*) - } -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h deleted file mode 100644 index 046d28300..000000000 --- a/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef _CHCONF_H_ -#define _CHCONF_H_ - -/*===========================================================================*/ -/* Kernel parameters. */ -/*===========================================================================*/ - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 -#endif - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 20 -#endif - -/** - * @brief Nested locks. - * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() - * operations is allowed.
- * For performance and code size reasons the recommended setting - * is to leave this option disabled.
- * You may use this option if you need to merge ChibiOS/RT with - * external libraries that require nested lock/unlock operations. - * - * @note T he default is @p FALSE. - */ -#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE -#endif - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. - */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 -#endif - -/*===========================================================================*/ -/* Performance options. */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED TRUE -#endif - -/** - * @brief Exotic optimization. - * @details If defined then a CPU register is used as storage for the global - * @p currp variable. Caching this variable in a register greatly - * improves both space and time OS efficiency. A side effect is that - * one less register has to be saved during the context switch - * resulting in lower RAM usage and faster context switch. - * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. - */ -#if defined(__DOXYGEN__) -#define CH_CURRP_REGISTER_CACHE "reg" -#endif - -/*===========================================================================*/ -/* Subsystem options. */ -/*===========================================================================*/ - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE -#endif - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE -#endif - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE -#endif - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE -#endif - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE -#endif - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. - */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS TRUE -#endif - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. - */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE -#endif - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE -#endif - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. - */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT TRUE -#endif - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE -#endif - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. - */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE -#endif - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE -#endif - -/** - * @brief I/O Queues APIs. - * @details If enabled then the I/O queues APIs are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE -#endif - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE -#endif - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE -#endif - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE -#endif - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. - */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE -#endif - -/*===========================================================================*/ -/* Debug options. */ -/*===========================================================================*/ - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS FALSE -#endif - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS FALSE -#endif - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the context switch circular trace buffer is - * activated. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE FALSE -#endif - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK FALSE -#endif - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS FALSE -#endif - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. - */ -#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE -#endif - -/*===========================================================================*/ -/* Kernel hooks. */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure hook. - * @details User fields added to the end of the @p Thread structure. - */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; -#endif - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. - */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ -} -#endif - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. - */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ -} -#endif - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} -#endif - -#endif /* _CHCONF_H_ */ - -/** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h deleted file mode 100644 index 763b0019a..000000000 --- a/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @addtogroup HAL_CONF - * @{ - */ - -/* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. - */ - -#ifndef _HALCONF_H_ -#define _HALCONF_H_ - -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ -#include "mcuconf.h" - -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the ADC subsystem. - */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MAC subsystem. - */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE -#endif - -/*===========================================================================*/ -/* PWM driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the PWM subsystem. - */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE -#endif - -/* - * Default SERIAL settings overrides (uncomment to override). - */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the SPI subsystem. - */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE -#endif - -/* - * Default SPI settings overrides (uncomment to override). - */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE -#endif - -/* - * Default MMC_SPI settings overrides (uncomment to override). - */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ - -#endif /* _HALCONF_H_ */ - -/** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/main.c b/demos/ARMCM3-STM32F103-GCC-ALT/main.c deleted file mode 100644 index 0072f0958..000000000 --- a/demos/ARMCM3-STM32F103-GCC-ALT/main.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include "ch.h" -#include "hal.h" -#include "test.h" - -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - palSetPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - } - return 0; -} - -/* - * Entry point, note, the main() function is already a thread in the system - * on entry. - */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; - - /* - * Activates the serial driver 2 using the driver default configuration. - */ - sdStart(&SD2, NULL); - - /* - * Creates the blinker thread. - */ - chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); - - /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. - */ - while (TRUE) { - if (palReadPad(IOPORT1, GPIOA_BUTTON)) - TestThread(&SD2); - chThdSleepMilliseconds(500); - } - return 0; -} diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h deleted file mode 100644 index 28ae05e73..000000000 --- a/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/* - * STM32 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. - * - * IRQ priorities: - * 15...0 Lowest...Highest. - * - * DMA priorities: - * 0...3 Lowest...Highest. - */ - -/* - * HAL driver system settings. - */ -#define STM32_SYSCLK 72 - -/* - * ADC driver system settings. - */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() - -/* - * CAN driver system settings. - */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 - -/* - * PWM driver system settings. - */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 - -/* - * SERIAL driver system settings. - */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif - -/* - * SPI driver system settings. - */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt b/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt deleted file mode 100644 index 353dd2658..000000000 --- a/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt +++ /dev/null @@ -1,28 +0,0 @@ -***************************************************************************** -** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. ** -***************************************************************************** - -** TARGET ** - -The demo will on an Olimex STM32-P103 board. - -** The Demo ** - -The demo flashes the board LED using a thread, by pressing the button located -on the board the test procedure is activated with output on the serial port -COM2 (USART2). - -** Build Procedure ** - -The demo has been tested by using the free Codesourcery GCC-based toolchain, -YAGARTO and an experimental WinARM build including GCC 4.3.0. -Just modify the TRGT line in the makefile in order to use different GCC ports. - -** Notes ** - -Some files used by the demo are not part of ChibiOS/RT but are copyright of -ST Microelectronics and are licensed under a different license. -Also note that not all the files present in the ST library are distribited -with ChibiOS/RT, you can find the whole library on the ST web site: - - http://www.st.com -- cgit v1.2.3 From 876463f7215f0166ef9b7cafca77c7dca966d632 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 2 Apr 2010 08:59:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1827 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 4 ++-- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index c9354ec9e..550e60ec8 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/ext/fatfs/fatfs.mk @@ -104,7 +104,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 681c9c790..5284c7ad2 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From cec33ff0e62d3666f6a1828d78891d63da191e20 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 2 Apr 2010 12:47:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1831 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 6 +++--- demos/ARMCM0-LPC1114-GCC/halconf.h | 2 +- demos/ARMCM0-LPC1114-GCC/main.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index 6b828dee3..e776ab4c5 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -53,9 +53,9 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1114/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk +include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk include $(CHIBIOS)/os/kernel/kernel.mk #include $(CHIBIOS)/test/test.mk @@ -97,7 +97,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h index ef45f36bd..eee631fe0 100644 --- a/demos/ARMCM0-LPC1114-GCC/halconf.h +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -48,7 +48,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#define CH_HAL_USE_PAL TRUE #endif /*===========================================================================*/ diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 11c3eb76b..74b7f5a78 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -29,9 +29,9 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { -// palClearPad(IOPORT3, GPIOC_LED); + palClearPad(IOPORT1, GPIO0_LED); chThdSleepMilliseconds(500); -// palSetPad(IOPORT3, GPIOC_LED); + palSetPad(IOPORT1, GPIO0_LED); chThdSleepMilliseconds(500); } return 0; -- cgit v1.2.3 From 39021902482ee2309e9234bb6f5c642500629b2b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 2 Apr 2010 14:38:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1834 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/halconf.h | 2 +- demos/ARMCM0-LPC1114-GCC/mcuconf.h | 6 +----- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h index eee631fe0..763b0019a 100644 --- a/demos/ARMCM0-LPC1114-GCC/halconf.h +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -103,7 +103,7 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL FALSE +#define CH_HAL_USE_SERIAL TRUE #endif /* diff --git a/demos/ARMCM0-LPC1114-GCC/mcuconf.h b/demos/ARMCM0-LPC1114-GCC/mcuconf.h index d87dccc7b..abab32579 100644 --- a/demos/ARMCM0-LPC1114-GCC/mcuconf.h +++ b/demos/ARMCM0-LPC1114-GCC/mcuconf.h @@ -25,11 +25,7 @@ * is enabled in halconf.h. * * IRQ priorities: - * 3 Lowest, priority level reserved for PENDSV, do not share or - * use for non-OS-capable low priority handlers. - * 2...1 Normal IRQs priority levels, use for OS-capable handlers. - * 0 Used by SVCALL, do not share or use for non-OS-capable high - * priority handlers. + * 3...0 Lowest...highest. */ /* -- cgit v1.2.3 From 220341765d0934143787dcdf0dfa40577059f884 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Apr 2010 12:17:37 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1837 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 2 +- demos/ARMCM0-LPC1114-GCC/main.c | 50 ++++++++++++++++++++++++++++++++------- 2 files changed, 42 insertions(+), 10 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index e776ab4c5..48383738c 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -57,7 +57,7 @@ include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk include $(CHIBIOS)/os/kernel/kernel.mk -#include $(CHIBIOS)/test/test.mk +include $(CHIBIOS)/test/test.mk # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 74b7f5a78..45496acfc 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -19,24 +19,55 @@ #include "ch.h" #include "hal.h" -//#include "test.h" +#include "test.h" /* - * Red LEDs blinker thread, times are in milliseconds. + * Red LED blinker thread, times are in milliseconds. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { - palClearPad(IOPORT1, GPIO0_LED); + palClearPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); - palSetPad(IOPORT1, GPIO0_LED); + palSetPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); } return 0; } +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + while (TRUE) { + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3R)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + } + return 0; +} + /* * Entry point, note, the main() function is already a thread in the system * on entry. @@ -47,22 +78,23 @@ int main(int argc, char **argv) { (void)argv; /* - * Activates the serial driver 2 using the driver default configuration. + * Activates the serial driver 1 using the driver default configuration. */ -// sdStart(&SD2, NULL); + sdStart(&SD1, NULL); /* - * Creates the blinker thread. + * Creates the blinker threads. */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); /* * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop and check the button state. */ while (TRUE) { -// if (palReadPad(IOPORT1, GPIOA_BUTTON)) -// TestThread(&SD2); + if (!palReadPad(GPIO0, GPIO0_SW3)) + TestThread(&SD1); chThdSleepMilliseconds(500); } return 0; -- cgit v1.2.3 From 25e96c1c3070db2b6266d358eee3af1315751e52 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 4 Apr 2010 17:08:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1850 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-LPC1343-GCC/Makefile | 192 +++++++++++++++ demos/ARMCM3-LPC1343-GCC/ch.ld | 94 ++++++++ demos/ARMCM3-LPC1343-GCC/chconf.h | 483 +++++++++++++++++++++++++++++++++++++ demos/ARMCM3-LPC1343-GCC/halconf.h | 152 ++++++++++++ demos/ARMCM3-LPC1343-GCC/main.c | 101 ++++++++ demos/ARMCM3-LPC1343-GCC/mcuconf.h | 53 ++++ 6 files changed, 1075 insertions(+) create mode 100644 demos/ARMCM3-LPC1343-GCC/Makefile create mode 100644 demos/ARMCM3-LPC1343-GCC/ch.ld create mode 100644 demos/ARMCM3-LPC1343-GCC/chconf.h create mode 100644 demos/ARMCM3-LPC1343-GCC/halconf.h create mode 100644 demos/ARMCM3-LPC1343-GCC/main.c create mode 100644 demos/ARMCM3-LPC1343-GCC/mcuconf.h (limited to 'demos') diff --git a/demos/ARMCM3-LPC1343-GCC/Makefile b/demos/ARMCM3-LPC1343-GCC/Makefile new file mode 100644 index 000000000..cf093150e --- /dev/null +++ b/demos/ARMCM3-LPC1343-GCC/Makefile @@ -0,0 +1,192 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1343/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC13xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-LPC1343-GCC/ch.ld b/demos/ARMCM3-LPC1343-GCC/ch.ld new file mode 100644 index 000000000..8497ebeea --- /dev/null +++ b/demos/ARMCM3-LPC1343-GCC/ch.ld @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC1114 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(4) SUBALIGN(4) + { + _text = .; + KEEP(*(vectors)); + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-LPC1343-GCC/chconf.h b/demos/ARMCM3-LPC1343-GCC/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARMCM3-LPC1343-GCC/chconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1343-GCC/halconf.h b/demos/ARMCM3-LPC1343-GCC/halconf.h new file mode 100644 index 000000000..763b0019a --- /dev/null +++ b/demos/ARMCM3-LPC1343-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-LPC1343-GCC/main.c b/demos/ARMCM3-LPC1343-GCC/main.c new file mode 100644 index 000000000..45496acfc --- /dev/null +++ b/demos/ARMCM3-LPC1343-GCC/main.c @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + palSetPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + while (TRUE) { + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3R)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3B) | + PAL_PORT_BIT(GPIO1_LED3R) | + PAL_PORT_BIT(GPIO1_LED3G)); + palSetPort(GPIO1, PAL_PORT_BIT(GPIO1_LED3G)); + chThdSleepMilliseconds(250); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (!palReadPad(GPIO0, GPIO0_SW3)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/ARMCM3-LPC1343-GCC/mcuconf.h b/demos/ARMCM3-LPC1343-GCC/mcuconf.h new file mode 100644 index 000000000..5eb8abe4a --- /dev/null +++ b/demos/ARMCM3-LPC1343-GCC/mcuconf.h @@ -0,0 +1,53 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC13xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ + +/* + * SPI driver system settings. + */ -- cgit v1.2.3 From 2845cdc28e12559381d361a3c509091611bd20b4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 4 Apr 2010 17:35:45 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1851 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-LPC1343-GCC/Makefile | 6 +++--- demos/ARMCM3-LPC1343-GCC/ch.ld | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-LPC1343-GCC/Makefile b/demos/ARMCM3-LPC1343-GCC/Makefile index cf093150e..009ccacb6 100644 --- a/demos/ARMCM3-LPC1343-GCC/Makefile +++ b/demos/ARMCM3-LPC1343-GCC/Makefile @@ -111,9 +111,9 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ # Compiler settings # -MCU = cortex-m0 +MCU = cortex-m3 -TRGT = arm-none-eabi- +TRGT = arm-elf- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. @@ -148,7 +148,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DLPC1114 -D__NEWLIB__ +DDEFS = -DLPC1348 -D__NEWLIB__ # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-LPC1343-GCC/ch.ld b/demos/ARMCM3-LPC1343-GCC/ch.ld index 8497ebeea..a7f0cda45 100644 --- a/demos/ARMCM3-LPC1343-GCC/ch.ld +++ b/demos/ARMCM3-LPC1343-GCC/ch.ld @@ -18,7 +18,7 @@ */ /* - * LPC1114 memory setup. + * LPC1343 memory setup. */ __main_stack_size__ = 0x0100; __process_stack_size__ = 0x0100; -- cgit v1.2.3 From 3076655c398c84a8a8ab79e9364693233df7e006 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 5 Apr 2010 08:12:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1856 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index 48383738c..544c58679 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -53,9 +53,9 @@ LDSCRIPT= ch.ld # Imported source files CHIBIOS = ../.. include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_1114/board.mk -include $(CHIBIOS)/os/hal/platforms/LPC111x/platform.mk +include $(CHIBIOS)/os/hal/platforms/LPC11xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -97,7 +97,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC111x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From 9abcfe6c2dbeeb5098c5e41c727265525e7d01b4 Mon Sep 17 00:00:00 2001 From: liamstask Date: Wed, 14 Apr 2010 16:07:34 +0000 Subject: * add more stats tracking to lwip sys_arch.c - in doing so, check for failed allocations git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1866 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c | 24 +++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c index c164a7a4e..517bfba03 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/arch/sys_arch.c @@ -56,6 +56,7 @@ #include "lwip/opt.h" #include "lwip/mem.h" #include "lwip/sys.h" +#include "lwip/stats.h" #include "arch/cc.h" #include "arch/sys_arch.h" @@ -67,13 +68,20 @@ void sys_init(void) { sys_sem_t sys_sem_new(u8_t count) { sys_sem_t sem = chHeapAlloc(NULL, sizeof(Semaphore)); - chSemInit(sem, (cnt_t)count); + if (sem == 0) { + SYS_STATS_INC(sem.err); + } + else { + chSemInit(sem, (cnt_t)count); + SYS_STATS_INC(sem.used); + } return sem; } void sys_sem_free(sys_sem_t sem) { chHeapFree(sem); + SYS_STATS_DEC(sem.used); } void sys_sem_signal(sys_sem_t sem) { @@ -95,16 +103,22 @@ u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) { } sys_mbox_t sys_mbox_new(int size) { - sys_mbox_t mbox; - - mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size); - chMBInit(mbox, (void *)(((uint8_t *)mbox) + sizeof(Mailbox)), size); + + sys_mbox_t mbox = chHeapAlloc(NULL, sizeof(Mailbox) + sizeof(msg_t) * size); + if (mbox == 0) { + SYS_STATS_INC(mbox.err); + } + else { + chMBInit(mbox, (void *)(((uint8_t *)mbox) + sizeof(Mailbox)), size); + SYS_STATS_INC(mbox.used); + } return mbox; } void sys_mbox_free(sys_mbox_t mbox) { chHeapFree(mbox); + SYS_STATS_DEC(mbox.used); } void sys_mbox_post(sys_mbox_t mbox, void *msg) { -- cgit v1.2.3 From a147f92f9d64e358a2b9c8f1e431d4ac1a166537 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 17 Apr 2010 15:52:38 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1870 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-LPC1343-GCC/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-LPC1343-GCC/Makefile b/demos/ARMCM3-LPC1343-GCC/Makefile index 009ccacb6..d85428b16 100644 --- a/demos/ARMCM3-LPC1343-GCC/Makefile +++ b/demos/ARMCM3-LPC1343-GCC/Makefile @@ -113,7 +113,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = cortex-m3 -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. -- cgit v1.2.3 From 6e8ee658598c5e1176bec50f36148112158aae49 Mon Sep 17 00:00:00 2001 From: liamstask Date: Mon, 19 Apr 2010 15:43:56 +0000 Subject: * small note in the Posix demo readme on how to build for OS X git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1877 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Posix-GCC/readme.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/Posix-GCC/readme.txt b/demos/Posix-GCC/readme.txt index 7db17cfa6..a1b5b4489 100644 --- a/demos/Posix-GCC/readme.txt +++ b/demos/Posix-GCC/readme.txt @@ -19,7 +19,8 @@ See demo.c for details. ** Build Procedure ** -GCC required. +GCC required. The Makefile defaults to building for a Linux host. +To build on OS X, use the following command: `make HOST_OSX=yes` ** Connect to the demo ** -- cgit v1.2.3 From 3621ac37b0cbab7737d215db0335017561856a10 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 20 Apr 2010 15:39:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1881 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 68 ++++++++++++++++++++--------------------- demos/STM8S-STM8S208-RC/ch.rprj | 2 +- 2 files changed, 35 insertions(+), 35 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 89621d480..3f90dd82b 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -1,6 +1,6 @@ - - + + @@ -10,15 +10,15 @@
- +
- + - + - + - + @@ -34,15 +34,15 @@
- +
- + - + - + - + @@ -53,17 +53,17 @@
- +
- + - + - + - + - + @@ -78,11 +78,11 @@ - + - + @@ -97,11 +97,11 @@ - + - + - + @@ -109,21 +109,21 @@
- +
- +
- +
- +
@@ -134,33 +134,33 @@
- +
- +
- +
- +
- +
- +
- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index bf57adfd4..dc557d7be 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - + \ No newline at end of file -- cgit v1.2.3 From 75792b3d6af243e043e66b1b2f7199229d430ef8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 21 Apr 2010 14:11:12 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1882 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 62 ++++++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 3f90dd82b..d9da5716d 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -10,15 +10,15 @@
- +
- + - + - + - + @@ -34,15 +34,15 @@
- +
- + - + - + - + @@ -53,17 +53,17 @@
- +
- + - + - + - + - + @@ -78,11 +78,11 @@ - + - + @@ -97,11 +97,11 @@ - + - + @@ -109,21 +109,21 @@
- +
- +
- +
- +
@@ -134,33 +134,33 @@
- +
- +
- +
- +
- +
- +
- + -- cgit v1.2.3 From e53a1a32089e2f0d1983cc92d1d4a6d28c4db07f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Apr 2010 09:31:04 +0000 Subject: Added command shell to the STM32 FatFs demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1890 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 205 ++++++++++++++++++++-------- demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt | 8 +- 3 files changed, 157 insertions(+), 58 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 550e60ec8..1094cf3ca 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -74,7 +74,7 @@ CSRC = $(PORTSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ $(FATFSSRC) \ - $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ $(CHIBIOS)/os/various/syscalls.c \ main.c diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 8295e509b..ddd85c8fc 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -23,10 +23,15 @@ #include "ch.h" #include "hal.h" #include "test.h" +#include "shell.h" #include "evtimer.h" #include "ff.h" +/*===========================================================================*/ +/* MMC/SPI related. */ +/*===========================================================================*/ + /** * @brief FS object. */ @@ -58,22 +63,6 @@ static bool_t mmc_is_protected(void) {return !palReadPad(IOPORT3, GPIOC_MMCWP);} /* Generic large buffer.*/ uint8_t fbuff[1024]; -/* - * Red LEDs blinker thread, times are in milliseconds. - */ -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { - - (void)arg; - while (TRUE) { - palClearPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - palSetPad(IOPORT3, GPIOC_LED); - chThdSleepMilliseconds(500); - } - return 0; -} - static FRESULT scan_files(char *path) { FRESULT res; @@ -107,32 +96,140 @@ static FRESULT scan_files(char *path) return res; } +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { + size_t n, size; + char buf[52]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: mem"); + return; + } + n = chHeapStatus(NULL, &size); + siprintf(buf, "core free memory : %lu bytes", chCoreFree()); + shellPrintLine(chp, buf); + siprintf(buf, "heap fragments : %lu", n); + shellPrintLine(chp, buf); + siprintf(buf, "heap free total : %lu bytes", size); + shellPrintLine(chp, buf); +} + +static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { + static const char *states[] = { + "READY", + "CURRENT", + "SUSPENDED", + "WTSEM", + "WTMTX", + "WTCOND", + "SLEEPING", + "WTEXIT", + "WTOREVT", + "WTANDEVT", + "SNDMSG", + "WTMSG", + "FINAL" + }; + Thread *tp; + char buf[60]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: threads"); + return; + } + shellPrintLine(chp, " addr stack prio refs state time"); + tp = chRegFirstThread(); + do { + siprintf(buf, "%8lx %8lx %4u %4i %9s %u", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (unsigned int)tp->p_prio, tp->p_refs - 1, + states[tp->p_state], (unsigned int)tp->p_time); + shellPrintLine(chp, buf); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: test"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + shellPrintLine(chp, "out of memory"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseChannel *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: tree"); + return; + } + if (!fs_ready) { + shellPrintLine(chp, "File System not mounted"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + shellPrintLine(chp, "FS: f_getfree() failed"); + return; + } + siprintf((void *)fbuff, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); + shellPrintLine(chp, (void *)fbuff); + fbuff[0] = 0; + scan_files((char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD2, + commands +}; + /* - * Executed as event handler at 500mS intervals. + * Red LEDs blinker thread, times are in milliseconds. */ -static void TimerHandler(eventid_t id) { +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { - (void)id; - if (palReadPad(IOPORT1, GPIOA_BUTTON)) { - if (fs_ready) { - FRESULT err; - uint32_t clusters; - FATFS *fsp; - - err = f_getfree("/", &clusters, &fsp); - if (err != FR_OK) { - iprintf("FS: f_getfree() failed\r\n"); - return; - } - iprintf("FS: %lu free clusters, %u sectors per cluster, %lu bytes free\r\n", - clusters, MMC_FS.csize, - clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); - fbuff[0] = 0; - scan_files((char *)fbuff); - } + (void)arg; + while (TRUE) { + palTogglePad(IOPORT3, GPIOC_LED); + if (fs_ready) + chThdSleepMilliseconds(200); else - TestThread(&SD2); + chThdSleepMilliseconds(500); } + return 0; } /* @@ -142,25 +239,18 @@ static void InsertHandler(eventid_t id) { FRESULT err; (void)id; - iprintf("MMC: inserted\r\n"); /* * On insertion MMC initialization and FS mount. */ - iprintf("MMC: initialization "); if (mmcConnect(&MMCD1)) { - iprintf("failed\r\n"); return; } - iprintf("ok\r\n"); - iprintf("FS: mount "); err = f_mount(0, &MMC_FS); if (err != FR_OK) { - iprintf("failed\r\n"); mmcDisconnect(&MMCD1); return; } fs_ready = TRUE; - iprintf("ok\r\n"); } /* @@ -169,7 +259,6 @@ static void InsertHandler(eventid_t id) { static void RemoveHandler(eventid_t id) { (void)id; - iprintf("MMC: removed\r\n"); fs_ready = FALSE; } @@ -179,12 +268,11 @@ static void RemoveHandler(eventid_t id) { */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { - TimerHandler, InsertHandler, RemoveHandler }; - static EvTimer evt; - struct EventListener el0, el1, el2; + Thread *shelltp = NULL; + struct EventListener el0, el1; (void)argc; (void)argv; @@ -194,6 +282,11 @@ int main(int argc, char **argv) { */ sdStart(&SD2, NULL); + /* + * Shell manager initialization. + */ + shellInit(); + /* * Initializes the MMC driver to work with SPI2. */ @@ -213,12 +306,16 @@ int main(int argc, char **argv) { * Normal main() thread activity, in this demo it does nothing except * sleeping in a loop and listen for events. */ - evtInit(&evt, MS2ST(500)); /* Initializes an event timer object. */ - evtStart(&evt); /* Starts the event timer. */ - chEvtRegister(&evt.et_es, &el0, 0); /* Registers on the timer event source. */ - chEvtRegister(&MMCD1.mmc_inserted_event, &el1, 1); - chEvtRegister(&MMCD1.mmc_removed_event, &el2, 2); - while (TRUE) + chEvtRegister(&MMCD1.mmc_inserted_event, &el0, 0); + chEvtRegister(&MMCD1.mmc_removed_event, &el1, 1); + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + } return 0; } diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt index 65f40a89a..619e89aa5 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt @@ -11,9 +11,11 @@ The demo will on an Olimex STM32-P103 board. This demo shows how to integrate the FatFs file system and use the SPI and MMC drivers. The demo flashes the board LED using a thread and monitors the MMC slot for -a card insertion. By pressing the button located on the board while a card is -inserted a directory dump on the serial port is performed, if a card is not -inserted then the test procedure is activated. +a card insertion. When a card is inserted then the file system is mounted +and the LED flashes faster. +A command line shell is spawned on SD2, all the interaction with the demo is +performed using the command shell, type "help" for a list of the available +commands. ** Build Procedure ** -- cgit v1.2.3 From bc9d319ddb279f973404c2b1abf15ec1091bd891 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 May 2010 12:31:05 +0000 Subject: Improved code coverage. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1902 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 2 +- demos/PPC-SPC563-GCC/main.c | 2 +- demos/Win32-MinGW/main.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index ddd85c8fc..cfe5fde8b 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -113,7 +113,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { return; } n = chHeapStatus(NULL, &size); - siprintf(buf, "core free memory : %lu bytes", chCoreFree()); + siprintf(buf, "core free memory : %lu bytes", chCoreStatus()); shellPrintLine(chp, buf); siprintf(buf, "heap fragments : %lu", n); shellPrintLine(chp, buf); diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index f2101c130..6e65e2263 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -37,7 +37,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { return; } n = chHeapStatus(NULL, &size); - siprintf(buf, "core free memory : %i bytes", chCoreFree()); + siprintf(buf, "core free memory : %i bytes", chCoreStatus()); shellPrintLine(chp, buf); siprintf(buf, "heap fragments : %i", n); shellPrintLine(chp, buf); diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index 1418b70ec..aa6d29716 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -42,7 +42,7 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { return; } n = chHeapStatus(NULL, &size); - sprintf(buf, "core free memory : %i bytes", chCoreFree()); + sprintf(buf, "core free memory : %i bytes", chCoreStatus()); shellPrintLine(chp, buf); sprintf(buf, "heap fragments : %i", n); shellPrintLine(chp, buf); -- cgit v1.2.3 From 9d256a8b42e827204c80205cc47a982d5c5c7b52 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 4 May 2010 19:55:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1903 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/Makefile | 3 ++- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 3 ++- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 3 ++- demos/ARM7-LPC214x-FATFS-GCC/Makefile | 3 ++- demos/ARM7-LPC214x-G++/Makefile | 3 ++- demos/ARM7-LPC214x-GCC/Makefile | 3 ++- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 3 ++- demos/ARMCM3-STM32F103-GCC/Makefile | 3 ++- 8 files changed, 16 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index e43fdf7e8..f9db0679b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -104,7 +104,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = arm7tdmi -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index f51cf1778..3890b27ed 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -114,7 +114,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = arm7tdmi -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index 419506193..641cbdb76 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -118,7 +118,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = arm7tdmi -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile index adc7d7d68..99ff790e9 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/Makefile +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -110,7 +110,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = arm7tdmi -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 14cd28728..0cc8f6e53 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -104,7 +104,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = arm7tdmi -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index a1056cbd7..99b7202cd 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -104,7 +104,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = arm7tdmi -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 1094cf3ca..22e059a39 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -121,7 +121,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = cortex-m3 -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 5284c7ad2..59949cd15 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -118,7 +118,8 @@ INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ MCU = cortex-m3 -TRGT = arm-elf- +#TRGT = arm-elf- +TRGT = arm-none-eabi- CC = $(TRGT)gcc CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support. -- cgit v1.2.3 From 4b1df104c9190e943b7f3e0d544b235f5cb2dce4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 5 May 2010 09:24:21 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1904 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-G++/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 0cc8f6e53..549fd8f1f 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -10,7 +10,7 @@ endif # C++ specific options here (added to USE_OPT). ifeq ($(USE_CPPOPT),) - USE_CPPOPT = -fno-rtti + USE_CPPOPT = -fno-rtti -fno-exceptions endif # Enable this if you want the linker to remove unused code and data -- cgit v1.2.3 From bf0c75c33e3c4ec0e19637d5da45e24f537295d9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 9 May 2010 17:52:30 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1911 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 1 - 1 file changed, 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 28ae05e73..f96d0421a 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -34,7 +34,6 @@ /* * HAL driver system settings. */ -#define STM32_SYSCLK 72 /* * ADC driver system settings. -- cgit v1.2.3 From 302956a3d929002fb5c1b2ef03c331186f498d01 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 9 May 2010 18:02:08 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1912 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 5 ++++- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index 28ae05e73..b4b44dd33 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -34,7 +34,10 @@ /* * HAL driver system settings. */ -#define STM32_SYSCLK 72 +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLCLKOUT 72000000 /* * ADC driver system settings. diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index f96d0421a..b4b44dd33 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -34,6 +34,10 @@ /* * HAL driver system settings. */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLCLKOUT 72000000 /* * ADC driver system settings. -- cgit v1.2.3 From fee72530476c5b9eed43fde792df9de367d56800 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 13 May 2010 14:02:17 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1915 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 6 +- demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt | 2 +- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 6 +- demos/ARMCM3-STM32F103-GCC/readme.txt | 2 +- demos/ARMCM3-STM32F107-GCC/Makefile | 205 ++++++++++++ demos/ARMCM3-STM32F107-GCC/ch.ld | 94 ++++++ demos/ARMCM3-STM32F107-GCC/chconf.h | 483 ++++++++++++++++++++++++++++ demos/ARMCM3-STM32F107-GCC/halconf.h | 152 +++++++++ demos/ARMCM3-STM32F107-GCC/main.c | 69 ++++ demos/ARMCM3-STM32F107-GCC/mcuconf.h | 102 ++++++ demos/ARMCM3-STM32F107-GCC/readme.txt | 25 ++ 13 files changed, 1144 insertions(+), 6 deletions(-) create mode 100644 demos/ARMCM3-STM32F107-GCC/Makefile create mode 100644 demos/ARMCM3-STM32F107-GCC/ch.ld create mode 100644 demos/ARMCM3-STM32F107-GCC/chconf.h create mode 100644 demos/ARMCM3-STM32F107-GCC/halconf.h create mode 100644 demos/ARMCM3-STM32F107-GCC/main.c create mode 100644 demos/ARMCM3-STM32F107-GCC/mcuconf.h create mode 100644 demos/ARMCM3-STM32F107-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 22e059a39..a1c7a5668 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -157,7 +157,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTM32F10X_MD -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 +DDEFS = -DSTDOUT_SD=SD2 -DSTDIN_SD=SD2 # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index b4b44dd33..511460ac4 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -37,7 +37,11 @@ #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLCLKOUT 72000000 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 /* * ADC driver system settings. diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt index 619e89aa5..4178478bb 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 59949cd15..623ddc8ee 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -154,7 +154,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DSTM32F10X_MD -DCORTEX_USE_BASEPRI=TRUE +DDEFS = -DCORTEX_USE_BASEPRI=TRUE # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index b4b44dd33..511460ac4 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -37,7 +37,11 @@ #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLCLKOUT 72000000 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 /* * ADC driver system settings. diff --git a/demos/ARMCM3-STM32F103-GCC/readme.txt b/demos/ARMCM3-STM32F103-GCC/readme.txt index 353dd2658..5329bfb35 100644 --- a/demos/ARMCM3-STM32F103-GCC/readme.txt +++ b/demos/ARMCM3-STM32F103-GCC/readme.txt @@ -4,7 +4,7 @@ ** TARGET ** -The demo will on an Olimex STM32-P103 board. +The demo runs on an Olimex STM32-P103 board. ** The Demo ** diff --git a/demos/ARMCM3-STM32F107-GCC/Makefile b/demos/ARMCM3-STM32F107-GCC/Makefile new file mode 100644 index 000000000..f8767cfdf --- /dev/null +++ b/demos/ARMCM3-STM32F107-GCC/Makefile @@ -0,0 +1,205 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM3210C_EVAL/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DCORTEX_USE_BASEPRI=TRUE + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F107-GCC/ch.ld b/demos/ARMCM3-STM32F107-GCC/ch.ld new file mode 100644 index 000000000..c0aa83278 --- /dev/null +++ b/demos/ARMCM3-STM32F107-GCC/ch.ld @@ -0,0 +1,94 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F107 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0400; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x08000000, len = 256k + ram : org = 0x20000000, len = 64k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)); + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-STM32F107-GCC/chconf.h b/demos/ARMCM3-STM32F107-GCC/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARMCM3-STM32F107-GCC/chconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107-GCC/halconf.h b/demos/ARMCM3-STM32F107-GCC/halconf.h new file mode 100644 index 000000000..763b0019a --- /dev/null +++ b/demos/ARMCM3-STM32F107-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F107-GCC/main.c b/demos/ARMCM3-STM32F107-GCC/main.c new file mode 100644 index 000000000..b831d2c37 --- /dev/null +++ b/demos/ARMCM3-STM32F107-GCC/main.c @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { +// palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); +// palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { +// if (palReadPad(IOPORT1, GPIOA_BUTTON)) +// TestThread(&SD2); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/ARMCM3-STM32F107-GCC/mcuconf.h b/demos/ARMCM3-STM32F107-GCC/mcuconf.h new file mode 100644 index 000000000..2591523ed --- /dev/null +++ b/demos/ARMCM3-STM32F107-GCC/mcuconf.h @@ -0,0 +1,102 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1_VALUE 5 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PREDIV2_VALUE 5 +#define STM32_PLL2MUL_VALUE 8 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 + +/* + * ADC driver system settings. + */ +#define USE_STM32_ADC1 TRUE +#define STM32_ADC1_DMA_PRIORITY 3 +#define STM32_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define USE_STM32_CAN1 TRUE +#define STM32_CAN1_IRQ_PRIORITY 11 + +/* + * PWM driver system settings. + */ +#define USE_STM32_PWM1 TRUE +#define USE_STM32_PWM2 FALSE +#define USE_STM32_PWM3 FALSE +#define USE_STM32_PWM4 FALSE +#define STM32_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM4_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define USE_STM32_USART1 FALSE +#define USE_STM32_USART2 TRUE +#define USE_STM32_USART3 FALSE +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define USE_STM32_UART4 FALSE +#define USE_STM32_UART5 FALSE +#endif +#define STM32_USART1_PRIORITY 12 +#define STM32_USART2_PRIORITY 12 +#define STM32_USART3_PRIORITY 12 +#if defined(STM32F10X_HD) || defined(STM32F10X_CL) +#define STM32_UART4_PRIORITY 12 +#define STM32_UART5_PRIORITY 12 +#endif + +/* + * SPI driver system settings. + */ +#define USE_STM32_SPI1 TRUE +#define USE_STM32_SPI2 TRUE +#define STM32_SPI1_DMA_PRIORITY 2 +#define STM32_SPI2_DMA_PRIORITY 2 +#define STM32_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F107-GCC/readme.txt b/demos/ARMCM3-STM32F107-GCC/readme.txt new file mode 100644 index 000000000..959a23363 --- /dev/null +++ b/demos/ARMCM3-STM32F107-GCC/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F107. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM3210C-EVAL board. + +** The Demo ** + + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain, +YAGARTO and an experimental WinARM build including GCC 4.3.0. +Just modify the TRGT line in the makefile in order to use different GCC ports. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 55b7744199ce9771ac761fc708d173bc487145e8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 14 May 2010 06:43:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1916 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 1 + demos/ARMCM3-STM32F103-GCC/mcuconf.h | 1 + demos/ARMCM3-STM32F107-GCC/main.c | 8 ++++---- demos/ARMCM3-STM32F107-GCC/mcuconf.h | 1 + 4 files changed, 7 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index 511460ac4..731ec9f85 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -42,6 +42,7 @@ #define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK /* * ADC driver system settings. diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 511460ac4..731ec9f85 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -42,6 +42,7 @@ #define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK /* * ADC driver system settings. diff --git a/demos/ARMCM3-STM32F107-GCC/main.c b/demos/ARMCM3-STM32F107-GCC/main.c index b831d2c37..bddf485c0 100644 --- a/demos/ARMCM3-STM32F107-GCC/main.c +++ b/demos/ARMCM3-STM32F107-GCC/main.c @@ -29,9 +29,9 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { -// palClearPad(IOPORT3, GPIOC_LED); + palClearPad(IOPORT4, 7); chThdSleepMilliseconds(500); -// palSetPad(IOPORT3, GPIOC_LED); + palSetPad(IOPORT4, 7); chThdSleepMilliseconds(500); } return 0; @@ -61,8 +61,8 @@ int main(int argc, char **argv) { * sleeping in a loop and check the button state. */ while (TRUE) { -// if (palReadPad(IOPORT1, GPIOA_BUTTON)) -// TestThread(&SD2); + if (palReadPad(IOPORT2, 9) == 0) + TestThread(&SD2); chThdSleepMilliseconds(500); } return 0; diff --git a/demos/ARMCM3-STM32F107-GCC/mcuconf.h b/demos/ARMCM3-STM32F107-GCC/mcuconf.h index 2591523ed..e4d7f155c 100644 --- a/demos/ARMCM3-STM32F107-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F107-GCC/mcuconf.h @@ -45,6 +45,7 @@ #define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK /* * ADC driver system settings. -- cgit v1.2.3 From f0f02c897c2f5042cdd54896bb876a1d7dec1970 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 14 May 2010 08:14:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1919 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 62 ++++++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index d9da5716d..0dd5a4435 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -10,15 +10,15 @@
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- +
- +
- + -- cgit v1.2.3 From d6e56d6e7fee513c7436816a7abaaf6a6c3fb007 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 14 May 2010 09:23:32 +0000 Subject: Fixed bug 3001528. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1920 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 64 ++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 0dd5a4435..8378004bc 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -10,15 +10,15 @@
- +
- + - + - + - + @@ -34,15 +34,15 @@
- +
- + - + - + - + @@ -53,17 +53,17 @@
- +
- + - + - + - + - + @@ -78,13 +78,13 @@ - + - + - + @@ -97,11 +97,11 @@ - + - + @@ -109,21 +109,21 @@
- +
- +
- +
- +
@@ -134,33 +134,33 @@
- +
- +
- +
- +
- +
- +
- + -- cgit v1.2.3 From ae6fcc0782505d0afa0c48b30c84a3ab0d66373b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 19 May 2010 17:19:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1938 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/mcuconf.h | 1 - demos/AVR-ATmega128-GCC/mcuconf.h | 1 - 2 files changed, 2 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/mcuconf.h b/demos/AVR-AT90CANx-GCC/mcuconf.h index bd31976f2..85a8cc2a6 100644 --- a/demos/AVR-AT90CANx-GCC/mcuconf.h +++ b/demos/AVR-AT90CANx-GCC/mcuconf.h @@ -50,4 +50,3 @@ /* * SPI driver system settings. */ -#define USE_LPC214x_SPI1 TRUE diff --git a/demos/AVR-ATmega128-GCC/mcuconf.h b/demos/AVR-ATmega128-GCC/mcuconf.h index bd31976f2..85a8cc2a6 100644 --- a/demos/AVR-ATmega128-GCC/mcuconf.h +++ b/demos/AVR-ATmega128-GCC/mcuconf.h @@ -50,4 +50,3 @@ /* * SPI driver system settings. */ -#define USE_LPC214x_SPI1 TRUE -- cgit v1.2.3 From 04076d3d539f4deb1bce2d47e10153a7a7e104f3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 22 May 2010 09:07:50 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1948 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-GCC/ch.ld | 35 ++++++++++++---------- demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld | 35 ++++++++++++---------- demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld | 35 ++++++++++++---------- demos/ARM7-LPC214x-FATFS-GCC/ch.ld | 41 ++++++++++++++------------ demos/ARM7-LPC214x-G++/ch.ld | 43 +++++++++++++++------------ demos/ARM7-LPC214x-GCC/ch.ld | 41 ++++++++++++++------------ demos/ARMCM0-LPC1114-GCC/ch.ld | 53 +++++++++++++++++++++++----------- demos/ARMCM3-LPC1343-GCC/ch.ld | 53 +++++++++++++++++++++++----------- demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld | 51 ++++++++++++++++++++++---------- demos/ARMCM3-STM32F103-GCC/ch.ld | 53 +++++++++++++++++++++++----------- demos/ARMCM3-STM32F107-GCC/ch.ld | 51 ++++++++++++++++++++++---------- 11 files changed, 308 insertions(+), 183 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-GCC/ch.ld b/demos/ARM7-AT91SAM7X-GCC/ch.ld index 277336359..67fe8d223 100644 --- a/demos/ARM7-AT91SAM7X-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-GCC/ch.ld @@ -47,18 +47,28 @@ SECTIONS _text = .; KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -84,11 +94,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld b/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld index 277336359..67fe8d223 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/ch.ld @@ -47,18 +47,28 @@ SECTIONS _text = .; KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -84,11 +94,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld b/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld index 277336359..67fe8d223 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/ch.ld @@ -47,18 +47,28 @@ SECTIONS _text = .; KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -84,11 +94,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-FATFS-GCC/ch.ld b/demos/ARM7-LPC214x-FATFS-GCC/ch.ld index e68868f72..8515eeac7 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/ch.ld +++ b/demos/ARM7-LPC214x-FATFS-GCC/ch.ld @@ -43,25 +43,35 @@ __dma_end__ = 0x7FD00000 + __dma_size__; SECTIONS { - . = 0; + . = 0; - .text : ALIGN(16) SUBALIGN(16) - { + .text : ALIGN(16) SUBALIGN(16) + { _text = .; KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -87,11 +97,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-G++/ch.ld b/demos/ARM7-LPC214x-G++/ch.ld index 1ce752804..8515eeac7 100644 --- a/demos/ARM7-LPC214x-G++/ch.ld +++ b/demos/ARM7-LPC214x-G++/ch.ld @@ -25,7 +25,7 @@ __abt_stack_size__ = 0x0004; __fiq_stack_size__ = 0x0010; __irq_stack_size__ = 0x0080; __svc_stack_size__ = 0x0004; -__sys_stack_size__ = 0x0800; +__sys_stack_size__ = 0x0400; __stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; MEMORY @@ -43,25 +43,35 @@ __dma_end__ = 0x7FD00000 + __dma_size__; SECTIONS { - . = 0; + . = 0; - .text : ALIGN(16) SUBALIGN(16) - { + .text : ALIGN(16) SUBALIGN(16) + { _text = .; KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -87,11 +97,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARM7-LPC214x-GCC/ch.ld b/demos/ARM7-LPC214x-GCC/ch.ld index e68868f72..8515eeac7 100644 --- a/demos/ARM7-LPC214x-GCC/ch.ld +++ b/demos/ARM7-LPC214x-GCC/ch.ld @@ -43,25 +43,35 @@ __dma_end__ = 0x7FD00000 + __dma_size__; SECTIONS { - . = 0; + . = 0; - .text : ALIGN(16) SUBALIGN(16) - { + .text : ALIGN(16) SUBALIGN(16) + { _text = .; KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.ctors) + *(.dtors) } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -87,11 +97,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARMCM0-LPC1114-GCC/ch.ld b/demos/ARMCM0-LPC1114-GCC/ch.ld index 8497ebeea..0eff7df98 100644 --- a/demos/ARMCM0-LPC1114-GCC/ch.ld +++ b/demos/ARMCM0-LPC1114-GCC/ch.ld @@ -38,23 +38,47 @@ SECTIONS { . = 0; - .text : ALIGN(4) SUBALIGN(4) + .text : ALIGN(16) SUBALIGN(16) { _text = .; - KEEP(*(vectors)); + KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ctors : + { + PROVIDE(_ctors_start_ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(_ctors_end_ = .); + } > flash + + .dtors : + { + PROVIDE(_dtors_start_ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(_dtors_end_ = .); } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -80,11 +104,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARMCM3-LPC1343-GCC/ch.ld b/demos/ARMCM3-LPC1343-GCC/ch.ld index a7f0cda45..83028c619 100644 --- a/demos/ARMCM3-LPC1343-GCC/ch.ld +++ b/demos/ARMCM3-LPC1343-GCC/ch.ld @@ -38,23 +38,47 @@ SECTIONS { . = 0; - .text : ALIGN(4) SUBALIGN(4) + .text : ALIGN(16) SUBALIGN(16) { _text = .; - KEEP(*(vectors)); + KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ctors : + { + PROVIDE(_ctors_start_ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(_ctors_end_ = .); + } > flash + + .dtors : + { + PROVIDE(_dtors_start_ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(_dtors_end_ = .); } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -80,11 +104,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld b/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld index 0dd8cfeab..44f494121 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/ch.ld @@ -41,20 +41,44 @@ SECTIONS .text : ALIGN(16) SUBALIGN(16) { _text = .; - KEEP(*(vectors)); + KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ctors : + { + PROVIDE(_ctors_start_ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(_ctors_end_ = .); + } > flash + + .dtors : + { + PROVIDE(_dtors_start_ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(_dtors_end_ = .); } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -80,11 +104,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARMCM3-STM32F103-GCC/ch.ld b/demos/ARMCM3-STM32F103-GCC/ch.ld index 1405765cd..44f494121 100644 --- a/demos/ARMCM3-STM32F103-GCC/ch.ld +++ b/demos/ARMCM3-STM32F103-GCC/ch.ld @@ -20,7 +20,7 @@ /* * ST32F103 memory setup. */ -__main_stack_size__ = 0x0200; +__main_stack_size__ = 0x0400; __process_stack_size__ = 0x0400; __stacks_total_size__ = __main_stack_size__ + __process_stack_size__; @@ -41,20 +41,44 @@ SECTIONS .text : ALIGN(16) SUBALIGN(16) { _text = .; - KEEP(*(vectors)); + KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ctors : + { + PROVIDE(_ctors_start_ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(_ctors_end_ = .); + } > flash + + .dtors : + { + PROVIDE(_dtors_start_ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(_dtors_end_ = .); } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -80,11 +104,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); diff --git a/demos/ARMCM3-STM32F107-GCC/ch.ld b/demos/ARMCM3-STM32F107-GCC/ch.ld index c0aa83278..0595192db 100644 --- a/demos/ARMCM3-STM32F107-GCC/ch.ld +++ b/demos/ARMCM3-STM32F107-GCC/ch.ld @@ -41,20 +41,44 @@ SECTIONS .text : ALIGN(16) SUBALIGN(16) { _text = .; - KEEP(*(vectors)); + KEEP(*(vectors)) *(.text) - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.glue_7t); - *(.glue_7); - *(.gcc*); - *(.ctors); - *(.dtors); - . = ALIGN(4); - _etext = .; + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ctors : + { + PROVIDE(_ctors_start_ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(_ctors_end_ = .); + } > flash + + .dtors : + { + PROVIDE(_dtors_start_ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(_dtors_end_ = .); } > flash + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; _textdata = _etext; .data : @@ -80,11 +104,6 @@ SECTIONS . = ALIGN(4); _bss_end = .; } > ram - - /DISCARD/ : - { - *(.eh_*) - } } PROVIDE(end = .); -- cgit v1.2.3 From a5e0616537530926193d73c2e41bf780d4a55f05 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 29 May 2010 06:09:11 +0000 Subject: Added AT91SAM7S256 demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1961 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-GCC/Makefile | 184 ++++++++++++ demos/ARM7-AT91SAM7S-GCC/ch.ld | 98 +++++++ demos/ARM7-AT91SAM7S-GCC/chconf.h | 464 +++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7S-GCC/halconf.h | 152 ++++++++++ demos/ARM7-AT91SAM7S-GCC/main.c | 67 +++++ demos/ARM7-AT91SAM7S-GCC/mcuconf.h | 58 ++++ demos/ARM7-AT91SAM7S-GCC/readme.txt | 28 ++ demos/ARM7-AT91SAM7X-GCC/readme.txt | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt | 2 +- 10 files changed, 1054 insertions(+), 3 deletions(-) create mode 100644 demos/ARM7-AT91SAM7S-GCC/Makefile create mode 100644 demos/ARM7-AT91SAM7S-GCC/ch.ld create mode 100644 demos/ARM7-AT91SAM7S-GCC/chconf.h create mode 100644 demos/ARM7-AT91SAM7S-GCC/halconf.h create mode 100644 demos/ARM7-AT91SAM7S-GCC/main.c create mode 100644 demos/ARM7-AT91SAM7S-GCC/mcuconf.h create mode 100644 demos/ARM7-AT91SAM7S-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-GCC/Makefile b/demos/ARM7-AT91SAM7S-GCC/Makefile new file mode 100644 index 000000000..fcb9ae999 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-GCC/Makefile @@ -0,0 +1,184 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_SAM7_P256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7S-GCC/ch.ld b/demos/ARM7-AT91SAM7S-GCC/ch.ld new file mode 100644 index 000000000..277336359 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-GCC/ch.ld @@ -0,0 +1,98 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7S-GCC/chconf.h b/demos/ARM7-AT91SAM7S-GCC/chconf.h new file mode 100644 index 000000000..0f86d95fa --- /dev/null +++ b/demos/ARM7-AT91SAM7S-GCC/chconf.h @@ -0,0 +1,464 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @addtogroup config + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the round robin mechanism. + * + * @note Disabling round robin makes the kernel more compact and generally + * faster but forbids multiple threads at the same priority level. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemWaitSignal() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. It + * may not be implemented or some ports. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h new file mode 100644 index 000000000..763b0019a --- /dev/null +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7S-GCC/main.c b/demos/ARM7-AT91SAM7S-GCC/main.c new file mode 100644 index 000000000..4077ffb58 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-GCC/main.c @@ -0,0 +1,67 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *p) { + + (void)p; + while (TRUE) { + palSetPad(IOPORT1, PIOA_LED1); + chThdSleepMilliseconds(100); + palClearPad(IOPORT1, PIOA_LED1); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + (void)argc; + (void)argv; + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + if (!palReadPad(IOPORT1, PIOA_B1)) + sdWrite(&SD1, (uint8_t *)"Hello World!\r\n", 14); + if (!palReadPad(IOPORT1, PIOA_B2)) + TestThread(&SD1); + } + + return 0; +} diff --git a/demos/ARM7-AT91SAM7S-GCC/mcuconf.h b/demos/ARM7-AT91SAM7S-GCC/mcuconf.h new file mode 100644 index 000000000..be2bcc852 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-GCC/mcuconf.h @@ -0,0 +1,58 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ diff --git a/demos/ARM7-AT91SAM7S-GCC/readme.txt b/demos/ARM7-AT91SAM7S-GCC/readme.txt new file mode 100644 index 000000000..626516048 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-GCC/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM7TDMI AT91SAM7S256. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM7-P256 board. + +** The Demo ** + +The demo currently just flashes the LED1 using a thread. +The button B1 prints an "Hello World!" string on RS232_0, the button B2 +activates che ChibiOS/RT test suite, output on RS232_0(port baudrate 38400). + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright +and are licensed under a different license, see the header present in all the +source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. +Also note that not all the files present in the Atmel library are distribuited +with ChibiOS/RT, you can find the whole library on the Atmel web site: + + http://www.atmel.com diff --git a/demos/ARM7-AT91SAM7X-GCC/readme.txt b/demos/ARM7-AT91SAM7X-GCC/readme.txt index 986d5ec7c..1b5240c97 100644 --- a/demos/ARM7-AT91SAM7X-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-GCC/readme.txt @@ -21,7 +21,7 @@ and GNU userspace programs will work. Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright and are licensed under a different license, see the header present in all the -source files under ./demos/AT91SAM7X256/at91lib for details. +source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. Also note that not all the files present in the Atmel library are distribuited with ChibiOS/RT, you can find the whole library on the Atmel web site: diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt index 7b6460326..7d3f7175a 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt @@ -24,7 +24,7 @@ The demo requires the patcher lwIP 1.3.1 stack, see: ./ext/readme.txt Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright and are licensed under a different license, see the header present in all the -source files under ./demos/AT91SAM7X256/at91lib for details. +source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. Also note that not all the files present in the Atmel library are distribuited with ChibiOS/RT, you can find the whole library on the Atmel web site: diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt index 129f245c2..9d3b84e97 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/readme.txt @@ -24,7 +24,7 @@ The demo requires the patcher uIP 1.0 stack, see: ./ext/readme.txt Some files used by the demo are not part of ChibiOS/RT but are Atmel copyright and are licensed under a different license, see the header present in all the -source files under ./demos/AT91SAM7X256/at91lib for details. +source files under ./demos/os/hal/platform/AT91SAM7/at91lib for details. Also note that not all the files present in the Atmel library are distribuited with ChibiOS/RT, you can find the whole library on the Atmel web site: -- cgit v1.2.3 From b2db83ef52aa6668193bdc71a88b81d3aefefea0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 2 Jun 2010 11:34:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1983 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 74 +++++++++++++++++------------------------ demos/STM8S-STM8S208-RC/ch.rprj | 4 +-- 2 files changed, 33 insertions(+), 45 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 8378004bc..499f89206 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -1,5 +1,5 @@ - + @@ -10,15 +10,15 @@
- +
- + - + - + - + @@ -28,21 +28,9 @@ - - - - -
- - -
- - - - - - - + + + @@ -53,17 +41,17 @@
- +
- + - + - + - + - + @@ -78,13 +66,13 @@ - + - + - + @@ -97,11 +85,11 @@ - + - + @@ -109,21 +97,21 @@
- +
- +
- +
- +
@@ -134,33 +122,33 @@
- +
- +
- +
- +
- +
- +
- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index dc557d7be..d066d7b79 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - - + + \ No newline at end of file -- cgit v1.2.3 From fd41cf487a4e4e6d949efecdedc16b3e67d5d0b4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 4 Jun 2010 12:33:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1997 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-GCC/chconf.h | 4 ++++ demos/ARM7-AT91SAM7X-GCC/chconf.h | 4 ++++ demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 4 ++++ demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 4 ++++ demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 4 ++++ demos/ARM7-LPC214x-G++/chconf.h | 4 ++++ demos/ARM7-LPC214x-GCC/chconf.h | 4 ++++ demos/ARMCM0-LPC1114-GCC/chconf.h | 4 ++++ demos/ARMCM3-LPC1343-GCC/chconf.h | 4 ++++ demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 4 ++++ demos/ARMCM3-STM32F103-GCC/chconf.h | 4 ++++ demos/ARMCM3-STM32F107-GCC/chconf.h | 4 ++++ demos/AVR-AT90CANx-GCC/chconf.h | 4 ++++ demos/AVR-ATmega128-GCC/chconf.h | 4 ++++ demos/MSP430-MSP430x1611-GCC/chconf.h | 4 ++++ demos/PPC-SPC563-GCC/chconf.h | 4 ++++ demos/Posix-GCC/chconf.h | 4 ++++ demos/STM8S-STM8S208-RC/chconf.h | 4 ++++ demos/Win32-MinGW/chconf.h | 4 ++++ 19 files changed, 76 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-GCC/chconf.h b/demos/ARM7-AT91SAM7S-GCC/chconf.h index 0f86d95fa..8cada3cd9 100644 --- a/demos/ARM7-AT91SAM7S-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/chconf.h @@ -459,6 +459,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 367215352..6ddb1d2d1 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -481,6 +481,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index 046d28300..c49dc7571 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -480,4 +480,8 @@ struct { \ #endif /* _CHCONF_H_ */ +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + /** @} */ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 046d28300..c49dc7571 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -480,4 +480,8 @@ struct { \ #endif /* _CHCONF_H_ */ +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARMCM0-LPC1114-GCC/chconf.h b/demos/ARMCM0-LPC1114-GCC/chconf.h index 046d28300..c49dc7571 100644 --- a/demos/ARMCM0-LPC1114-GCC/chconf.h +++ b/demos/ARMCM0-LPC1114-GCC/chconf.h @@ -480,4 +480,8 @@ struct { \ #endif /* _CHCONF_H_ */ +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + /** @} */ diff --git a/demos/ARMCM3-LPC1343-GCC/chconf.h b/demos/ARMCM3-LPC1343-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/ARMCM3-LPC1343-GCC/chconf.h +++ b/demos/ARMCM3-LPC1343-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F107-GCC/chconf.h b/demos/ARMCM3-STM32F107-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/ARMCM3-STM32F107-GCC/chconf.h +++ b/demos/ARMCM3-STM32F107-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 2cda27e83..33dcfdfca 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 2cda27e83..33dcfdfca 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 2a40e33e2..f92563155 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h index 046d28300..6522e0b3b 100644 --- a/demos/PPC-SPC563-GCC/chconf.h +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -478,6 +478,10 @@ struct { \ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h index dd249746f..c1aa2b710 100644 --- a/demos/Posix-GCC/chconf.h +++ b/demos/Posix-GCC/chconf.h @@ -482,4 +482,8 @@ struct { \ #endif /* _CHCONF_H_ */ +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + /** @} */ diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index 5643c94e7..a426256ef 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -476,6 +476,10 @@ } #endif +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index dd249746f..59a895f70 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -480,6 +480,10 @@ struct { \ #define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ -- cgit v1.2.3 From 3da2df07a90526e9085c84ed8fab5e35eb8a68a5 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 4 Jun 2010 12:37:42 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1999 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 4 ++-- demos/ARM7-LPC214x-G++/chconf.h | 4 ++-- demos/ARMCM0-LPC1114-GCC/chconf.h | 4 ++-- demos/Posix-GCC/chconf.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index c49dc7571..6522e0b3b 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -478,10 +478,10 @@ struct { \ } #endif -#endif /* _CHCONF_H_ */ - /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#endif /* _CHCONF_H_ */ + /** @} */ diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index c49dc7571..6522e0b3b 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -478,10 +478,10 @@ struct { \ } #endif -#endif /* _CHCONF_H_ */ - /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#endif /* _CHCONF_H_ */ + /** @} */ diff --git a/demos/ARMCM0-LPC1114-GCC/chconf.h b/demos/ARMCM0-LPC1114-GCC/chconf.h index c49dc7571..6522e0b3b 100644 --- a/demos/ARMCM0-LPC1114-GCC/chconf.h +++ b/demos/ARMCM0-LPC1114-GCC/chconf.h @@ -478,10 +478,10 @@ struct { \ } #endif -#endif /* _CHCONF_H_ */ - /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#endif /* _CHCONF_H_ */ + /** @} */ diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h index c1aa2b710..59a895f70 100644 --- a/demos/Posix-GCC/chconf.h +++ b/demos/Posix-GCC/chconf.h @@ -480,10 +480,10 @@ struct { \ #define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) -#endif /* _CHCONF_H_ */ - /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ +#endif /* _CHCONF_H_ */ + /** @} */ -- cgit v1.2.3 From 0970c44b086287eac3c6c147a390fddb0f9de552 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 15 Jun 2010 17:19:01 +0000 Subject: Fixed bug 3016619. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2021 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/chconf.h | 6 +++--- demos/AVR-AT90CANx-GCC/halconf.h | 2 +- demos/AVR-ATmega128-GCC/chconf.h | 6 +++--- demos/AVR-ATmega128-GCC/halconf.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 33dcfdfca..ccab98d65 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -308,7 +308,7 @@ * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE +#define CH_USE_HEAP FALSE #endif /** @@ -333,7 +333,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE +#define CH_USE_MEMPOOLS FALSE #endif /** @@ -346,7 +346,7 @@ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE +#define CH_USE_DYNAMIC FALSE #endif /*===========================================================================*/ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index bd2f3e4fd..7859d0f0e 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -110,7 +110,7 @@ * Default SERIAL settings overrides (uncomment to override). */ /*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#define SERIAL_BUFFERS_SIZE 16 /*===========================================================================*/ /* SPI driver related settings. */ diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 33dcfdfca..ccab98d65 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -308,7 +308,7 @@ * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP TRUE +#define CH_USE_HEAP FALSE #endif /** @@ -333,7 +333,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE +#define CH_USE_MEMPOOLS FALSE #endif /** @@ -346,7 +346,7 @@ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC TRUE +#define CH_USE_DYNAMIC FALSE #endif /*===========================================================================*/ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index bd2f3e4fd..7859d0f0e 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -110,7 +110,7 @@ * Default SERIAL settings overrides (uncomment to override). */ /*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#define SERIAL_BUFFERS_SIZE 16 /*===========================================================================*/ /* SPI driver related settings. */ -- cgit v1.2.3 From 88bea4b8c200fad936c063718289250ce49cda61 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 25 Jun 2010 08:55:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2038 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw | 16 + .../cosmic/cosmic.stp | 2124 +++++++++++++++++++ .../STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c | 101 + demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h | 485 +++++ demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 152 ++ demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c | 75 + demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h | 40 + .../raisonance/raisonance.stp | 2145 ++++++++++++++++++++ 8 files changed, 5138 insertions(+) create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h create mode 100644 demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw new file mode 100644 index 000000000..015f8e015 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw @@ -0,0 +1,16 @@ +; STMicroelectronics Workspace file + +[Version] +Keyword=ST7Workspace-V0.7 + +[Project0] +Filename=cosmic\cosmic.stp +Dependencies= + +[Project1] +Filename=raisonance\raisonance.stp +Dependencies= +[Options] +ActiveProject=cosmic +ActiveConfig=Debug +AddSortedElements=0 diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp new file mode 100644 index 000000000..b4667e94e --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -0,0 +1,2124 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=cosmic +Toolset=STM8 Cosmic + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=cosmic +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,3,15,59,36 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,5,25,14,45,56 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,5,25,14,45,56 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,5,25,14,45,56 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile$(OutputPath)$(TargetSName).lkf +String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 +String.4.0=$(OutputPath)$(TargetFName) +String.5.0= +String.6.0=2010,6,4,10,29,4 +String.100.0= +String.101.0=crtsi.st7 +String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it +String.102.1=+seg .text -a .const -n .text +String.102.2=+seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +String.102.3=+seg .bsct -b 0x0 -m 0x100 -n .bsct +String.102.4=+seg .ubsct -a .bsct -n .ubsct +String.102.5=+seg .bit -a .ubsct -n .bit -id +String.102.6=+seg .share -a .bit -n .share -is +String.102.7=+seg .data -b 0x100 -m 0x700 -n .data +String.102.8=+seg .bss -a .data -n .bss +String.103.0=Code,Constants[0x8080-0xffff]=.const,.text +String.103.1=Eeprom[0x4000-0x43ff]=.eeprom +String.103.2=Zero Page[0x0-0xff]=.bsct,.ubsct,.bit,.share +String.103.3=Ram[0x100-0x7ff]=.data,.bss +String.104.0=0x7ff +String.105.0=libisl0.sm8;libm0.sm8 +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=chex -o $(OutputPath)$(TargetSName).s19 $(OutputPath)$(TargetSName).sm8 +String.6.0=2010,5,25,14,45,56 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,5,25,14,45,56 + +[Root.Config.1.Settings.0] +String.6.0=2010,6,3,15,59,36 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,5,25,14,45,56 +String.100.0=$(TargetFName) +String.101.0= +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; + +[Root.Config.1.Settings.2] +String.2.0= +String.6.0=2010,5,25,14,45,56 +String.100.0=STM8S105C6 + +[Root.Config.1.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Config.1.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Config.1.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,5,25,14,45,56 +String.8.0= + +[Root.Config.1.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen 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b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Exception handler type. + */ +typedef void @far @interrupt (*interrupt_handler_t)(void); + +/* + * Various external symbols. + */ +void _stext(void); +@far @interrupt void vector13(void); +@far @interrupt void vector17(void); +@far @interrupt void vector18(void); +@far @interrupt void vector20(void); +@far @interrupt void vector21(void); + +/** + * @brief Exception vector type. + */ +typedef struct { + uint8_t ev_instruction; + interrupt_handler_t ev_handler; +} exception_vector_t; + +/** + * @brief Undefined interrupt handler. + * @note It should never be invoked. + */ +@far @interrupt static void vector (void) +{ + return; +} + +/** + * @brief Exceptions table. + */ +exception_vector_t const _vectab[] = { + {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, vector}, /* trap */ + {0x82, vector}, /* vector0 */ + {0x82, vector}, /* vector1 */ + {0x82, vector}, /* vector2 */ + {0x82, vector}, /* vector3 */ + {0x82, vector}, /* vector4 */ + {0x82, vector}, /* vector5 */ + {0x82, vector}, /* vector6 */ + {0x82, vector}, /* vector7 */ + {0x82, vector}, /* vector8 */ + {0x82, vector}, /* vector9 */ + {0x82, vector}, /* vector10 */ + {0x82, vector}, /* vector11 */ + {0x82, vector}, /* vector12 */ + {0x82, vector13}, /* vector13 */ + {0x82, vector}, /* vector14 */ + {0x82, vector}, /* vector15 */ + {0x82, vector}, /* vector16 */ +#if USE_STM8_UART1 + {0x82, vector17}, /* vector17 */ + {0x82, vector18}, /* vector18 */ +#else + {0x82, vector}, /* vector17 */ + {0x82, vector}, /* vector18 */ +#endif + {0x82, vector}, /* vector19 */ +#if USE_STM8_UART2 || USE_STM8_UART3 + {0x82, vector20}, /* vector20 */ + {0x82, vector21}, /* vector21 */ +#else + {0x82, vector}, /* vector20 */ + {0x82, vector}, /* vector21 */ +#endif + {0x82, vector}, /* vector22 */ + {0x82, vector}, /* vector23 */ + {0x82, vector}, /* vector24 */ + {0x82, vector}, /* vector25 */ + {0x82, vector}, /* vector26 */ + {0x82, vector}, /* vector27 */ + {0x82, vector}, /* vector28 */ + {0x82, vector}, /* vector29 */ +}; diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h new file mode 100644 index 000000000..55036c05d --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h @@ -0,0 +1,485 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h new file mode 100644 index 000000000..e68d87a79 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +#define SERIAL_BUFFERS_SIZE 16 + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI FALSE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI FALSE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c new file mode 100644 index 000000000..35321bf62 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c @@ -0,0 +1,75 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + palSetPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Entry point. + */ +void main(void) { + + /* + * Board/HAL initialization. + */ + hwinit(); + + /* + * OS initialization. + */ + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (palReadPad(GPIOG, 0) == PAL_LOW) + TestThread(&SD2); + if (palReadPad(GPIOG, 1) == PAL_LOW) + sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE); + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h new file mode 100644 index 000000000..cf2ebd963 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h @@ -0,0 +1,40 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI +#define STM8_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8_CPU_DIVIDER CLK_CPU_DIV1 + +/* + * SERIAL driver system settings. + */ +#define USE_STM8_UART1 FALSE +#define USE_STM8_UART2 TRUE +#define USE_STM8_UART3 FALSE diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp new file mode 100644 index 000000000..6ccb368b0 --- /dev/null +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -0,0 +1,2145 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=raisonance +Toolset=Raisonance + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=raisonance +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,4,10,30,46 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Program Files\Raisonance\Ride +String.103.0=bin +String.104.0=INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,6,4,10,10,40 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,11,38,46 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,10,30,46 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,6,4,10,10,40 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] DEBUGLINES DEBUGPUBLICS DEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) +String.3.1=omf2elf $(OutputPath)$(TargetSName).aof +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,6,4,12,15,0 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.0] +String.6.0=2010,6,4,11,25,50 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Program Files\Raisonance\Ride +String.103.0=bin +String.104.0=INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; + +[Root.Config.1.Settings.2] +String.2.0= +String.6.0=2010,6,4,10,10,40 +String.100.0=STM8S105C6 + +[Root.Config.1.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,12,11,58 + +[Root.Config.1.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,6,4,10,10,40 +String.8.0= + +[Root.Config.1.Settings.6] +String.2.0=Running Linker +String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] NODEBUGLINES NODEBUGPUBLICS NODEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) +String.3.1=omf2elf $(OutputPath)$(TargetSName).aof +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,6,4,12,15,0 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.1.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files] +ElemType=Folder +PathName=Source Files +Child=Root.Source Files...\demo\main.c +Next=Root.Include Files +Config.0=Root.Source Files.Config.0 +Config.1=Root.Source Files.Config.1 + +[Root.Source Files.Config.0] +Settings.0.0=Root.Source Files.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Config.0.Settings.3 + +[Root.Source Files.Config.1] +Settings.1.0=Root.Source Files.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Config.1.Settings.3 + +[Root.Source Files.Config.0.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,11,38,46 + +[Root.Source Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,10,30,46 + +[Root.Source Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,12,11,58 + +[Root.Source Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Config.1.Settings.3] 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PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,12,11,58 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chregistry.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source 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Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,29 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) 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$(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,10,30,46 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,12,11,58 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.c + +[Root.Source Files.Source Files\test] +ElemType=Folder +PathName=Source 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+String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,11,9,20 + +[Root.Include Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,4,10,30,46 + +[Root.Include Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB 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Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel] +ElemType=Folder +PathName=Include Files\os\kernel +Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h +Next=Root.Include Files.Include Files\os.Include Files\os\port + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chvt.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chthreads.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chthreads.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chthreads.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsys.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsys.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chsys.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chstreams.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chstreams.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chstreams.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsem.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chsem.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chsem.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chschd.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chschd.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chschd.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chregistry.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chregistry.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chregistry.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chqueues.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chqueues.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chqueues.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmtx.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmtx.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmtx.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmsg.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmsg.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmsg.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmempools.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmempools.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmempools.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmemcore.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmemcore.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmemcore.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmboxes.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chmboxes.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chmboxes.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chlists.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chlists.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chlists.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chioch.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chioch.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chioch.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chinline.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chinline.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chinline.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chheap.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chevents.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdebug.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chcond.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chcond.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chcond.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h] +ElemType=File +PathName=..\..\..\os\kernel\include\ch.h + +[Root.Include Files.Include Files\os.Include Files\os\port] +ElemType=Folder +PathName=Include Files\os\port +Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chtypes.h +Next=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chcore.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chcore.h] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.h + +[Root.Include Files.Include Files\test] +ElemType=Folder +PathName=Include Files\test +Child=Root.Include Files.Include Files\test...\..\..\test\testsem.h + +[Root.Include Files.Include Files\test...\..\..\test\testsem.h] +ElemType=File +PathName=..\..\..\test\testsem.h +Next=Root.Include Files.Include Files\test...\..\..\test\testqueues.h + +[Root.Include Files.Include Files\test...\..\..\test\testqueues.h] +ElemType=File +PathName=..\..\..\test\testqueues.h +Next=Root.Include Files.Include Files\test...\..\..\test\testpools.h + +[Root.Include Files.Include Files\test...\..\..\test\testpools.h] +ElemType=File +PathName=..\..\..\test\testpools.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmtx.h + +[Root.Include Files.Include Files\test...\..\..\test\testmtx.h] +ElemType=File +PathName=..\..\..\test\testmtx.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmsg.h + +[Root.Include Files.Include Files\test...\..\..\test\testmsg.h] +ElemType=File +PathName=..\..\..\test\testmsg.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmbox.h + +[Root.Include Files.Include Files\test...\..\..\test\testmbox.h] +ElemType=File +PathName=..\..\..\test\testmbox.h +Next=Root.Include Files.Include Files\test...\..\..\test\testheap.h + +[Root.Include Files.Include Files\test...\..\..\test\testheap.h] +ElemType=File +PathName=..\..\..\test\testheap.h +Next=Root.Include Files.Include Files\test...\..\..\test\testevt.h + +[Root.Include Files.Include Files\test...\..\..\test\testevt.h] +ElemType=File +PathName=..\..\..\test\testevt.h +Next=Root.Include Files.Include Files\test...\..\..\test\testdyn.h + +[Root.Include Files.Include Files\test...\..\..\test\testdyn.h] +ElemType=File +PathName=..\..\..\test\testdyn.h +Next=Root.Include Files.Include Files\test...\..\..\test\testbmk.h + +[Root.Include Files.Include Files\test...\..\..\test\testbmk.h] +ElemType=File +PathName=..\..\..\test\testbmk.h +Next=Root.Include Files.Include Files\test...\..\..\test\test.h + +[Root.Include Files.Include Files\test...\..\..\test\test.h] +ElemType=File +PathName=..\..\..\test\test.h +Next=Root.Include Files.Include Files\test...\..\..\test\testthd.h + +[Root.Include Files.Include Files\test...\..\..\test\testthd.h] +ElemType=File +PathName=..\..\..\test\testthd.h \ No newline at end of file -- cgit v1.2.3 From 1ef97a2da260c0734e71ef6697072b270014696f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Jun 2010 10:15:11 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2043 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw | 2 +- demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp | 4 ++-- demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw index 015f8e015..a6630271a 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw @@ -12,5 +12,5 @@ Filename=raisonance\raisonance.stp Dependencies= [Options] ActiveProject=cosmic -ActiveConfig=Debug +ActiveConfig=Release AddSortedElements=0 diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index b4667e94e..3d8bdbcd2 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index 6ccb368b0..348f71544 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -130,7 +130,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 -- cgit v1.2.3 From 17bc42e5dc7d5d983a2d108b8599639604f92ee0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Jun 2010 12:37:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2044 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 58 +++++++++++++++++++-------------------- demos/STM8S-STM8S208-RC/ch.rprj | 4 +-- demos/STM8S-STM8S208-RC/mcuconf.h | 1 + 3 files changed, 32 insertions(+), 31 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 499f89206..5f89b1c92 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -1,5 +1,5 @@ - + @@ -10,15 +10,15 @@
- +
- + - + - + - + @@ -30,7 +30,7 @@ - + @@ -41,17 +41,17 @@
- +
- + - + - + - + - + @@ -66,11 +66,11 @@ - + - + @@ -85,11 +85,11 @@ - + - + - + @@ -97,21 +97,21 @@
- +
- +
- +
- +
@@ -122,33 +122,33 @@
- +
- +
- +
- +
- +
- +
- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index d066d7b79..dc557d7be 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - - + + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/mcuconf.h b/demos/STM8S-STM8S208-RC/mcuconf.h index 227499992..c2148ac5b 100644 --- a/demos/STM8S-STM8S208-RC/mcuconf.h +++ b/demos/STM8S-STM8S208-RC/mcuconf.h @@ -36,4 +36,5 @@ * SERIAL driver system settings. */ #define USE_STM8_UART1 TRUE +#define USE_STM8_UART2 FALSE #define USE_STM8_UART3 FALSE -- cgit v1.2.3 From fbd7777e1ff57f36d5163345c4f0a2b5e7c43f3f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 26 Jun 2010 15:46:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2045 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../cosmic/cosmic.stp | 5 +- .../raisonance/raisonance.stp | 197 +++++++++++---------- 2 files changed, 102 insertions(+), 100 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index 3d8bdbcd2..bdf62f54f 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -83,10 +83,10 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,6,26,17,30,51 [Root.Config.0.Settings.4] String.2.0=Assembling $(InputFile)... @@ -156,6 +156,7 @@ Int.108=0 String.6.0=2010,5,25,14,45,56 String.100.0=$(TargetFName) String.101.0= +String.102.0= String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; [Root.Config.1.Settings.2] diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index 348f71544..fd48997a1 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -83,17 +83,17 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,38,46 +String.6.0=2010,6,26,17,42,15 [Root.Config.0.Settings.4] String.2.0=Assembling $(InputFile)... String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,30,46 +String.6.0=2010,6,26,17,46,5 [Root.Config.0.Settings.5] String.2.0=Running Pre-Link step @@ -142,6 +142,7 @@ Int.108=0 String.6.0=2010,6,4,10,10,40 String.100.0=$(TargetFName) String.101.0= +String.102.0= String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; [Root.Config.1.Settings.2] @@ -151,17 +152,17 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 [Root.Config.1.Settings.4] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,6,26,17,22,23 [Root.Config.1.Settings.5] String.2.0=Running Pre-Link step @@ -218,17 +219,17 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,38,46 +String.6.0=2010,6,26,17,42,15 [Root.Source Files.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,30,46 +String.6.0=2010,6,26,17,46,5 [Root.Source Files.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -245,17 +246,17 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -299,7 +300,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files...\demo\main.c.Config.1.Settings.0] @@ -317,10 +318,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\board] @@ -354,14 +355,14 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 [Root.Source Files.Source Files\board.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,30,46 +String.6.0=2010,6,26,17,46,5 [Root.Source Files.Source Files\board.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -378,17 +379,17 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\board.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\board.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -438,14 +439,14 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,30,46 +String.6.0=2010,6,26,17,46,5 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -462,17 +463,17 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -586,7 +587,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,5,11,28,3 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0] @@ -604,10 +605,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,5,11,27,18 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c] @@ -645,7 +646,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0] @@ -663,10 +664,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c] @@ -704,7 +705,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0] @@ -722,10 +723,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c] @@ -763,7 +764,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0] @@ -781,10 +782,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c] @@ -822,7 +823,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] @@ -840,10 +841,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] @@ -881,7 +882,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] @@ -899,10 +900,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] @@ -940,7 +941,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] @@ -958,10 +959,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] @@ -999,7 +1000,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] @@ -1017,10 +1018,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] @@ -1058,7 +1059,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] @@ -1076,10 +1077,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] @@ -1117,7 +1118,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] @@ -1135,10 +1136,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] @@ -1176,7 +1177,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] @@ -1194,10 +1195,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] @@ -1235,7 +1236,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] @@ -1253,10 +1254,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] @@ -1294,7 +1295,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] @@ -1312,10 +1313,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] @@ -1353,7 +1354,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,5,11,28,14 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] @@ -1371,10 +1372,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,5,11,27,37 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] @@ -1412,7 +1413,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] @@ -1430,10 +1431,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] @@ -1471,7 +1472,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] @@ -1489,10 +1490,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] @@ -1529,7 +1530,7 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 String.8.0=Debug [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] @@ -1547,10 +1548,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\port] @@ -1583,14 +1584,14 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,30,46 +String.6.0=2010,6,26,17,46,5 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -1607,17 +1608,17 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -1660,14 +1661,14 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 [Root.Source Files.Source Files\test.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,30,46 +String.6.0=2010,6,26,17,46,5 [Root.Source Files.Source Files\test.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -1684,17 +1685,17 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\test.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\test.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -1792,14 +1793,14 @@ String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,11,9,20 +String.6.0=2010,6,26,17,42,15 [Root.Include Files.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,30,46 +String.6.0=2010,6,26,17,46,5 [Root.Include Files.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -1816,17 +1817,17 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,12,11,58 +String.6.0=2010,6,26,17,22,23 [Root.Include Files.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET ERRORPRINT +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,6,26,17,22,23 [Root.Include Files.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) -- cgit v1.2.3 From a2d796acefbf2f32ee67403239a577988d04ca68 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Jul 2010 06:50:42 +0000 Subject: Updated STM8 scores using the latest RKit, there is a general improvement. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2046 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 154 ++++++++++++++++++++-------------------- demos/STM8S-STM8S208-RC/ch.rprj | 4 +- 2 files changed, 79 insertions(+), 79 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 5f89b1c92..3573b8505 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -1,117 +1,117 @@ - - - - - - + + + + + +
- +
- + - + - + - + - - - - - - - - - + + + + + + + + + - + - - - - + + + +
- +
- + - + - + - + - + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - - + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - - + + + - +
- +
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- +
@@ -122,33 +122,33 @@
- +
- +
- +
- +
- +
- +
- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index dc557d7be..ad8b9b39e 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - - + + \ No newline at end of file -- cgit v1.2.3 From 3efae5da4a8da8a0d76db680f9031887eb9bc9a2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 3 Jul 2010 07:53:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2051 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile | 189 ++++++++++++ demos/ARM7-AT91SAM7S-FATFS-GCC/ch.ld | 110 +++++++ demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h | 483 ++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 152 ++++++++++ demos/ARM7-AT91SAM7S-FATFS-GCC/main.c | 350 ++++++++++++++++++++++ demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h | 59 ++++ demos/ARM7-AT91SAM7S-FATFS-GCC/readme.txt | 24 ++ demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile | 189 ++++++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/ch.ld | 110 +++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h | 483 ++++++++++++++++++++++++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 152 ++++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/main.c | 332 ++++++++++++++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h | 59 ++++ demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt | 24 ++ 14 files changed, 2716 insertions(+) create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/ch.ld create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/main.c create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h create mode 100644 demos/ARM7-AT91SAM7S-FATFS-GCC/readme.txt create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/ch.ld create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/main.c create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h create mode 100644 demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile new file mode 100644 index 000000000..576b7ecbc --- /dev/null +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile @@ -0,0 +1,189 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_SAM7_P256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk +include $(CHIBIOS)/ext/fatfs/fatfs.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(FATFSSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/ch.ld b/demos/ARM7-AT91SAM7S-FATFS-GCC/ch.ld new file mode 100644 index 000000000..50ab38952 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/ch.ld @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h new file mode 100644 index 000000000..525bae43a --- /dev/null +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI TRUE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI TRUE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c new file mode 100644 index 000000000..478d2a606 --- /dev/null +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c @@ -0,0 +1,350 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "evtimer.h" +#include "ff.h" + +#define MAX_SPI_BITRATE 100 +#define MIN_SPI_BITRATE 250 + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (__MHz, NCPHA=1, CPOL=0).*/ +static SPIConfig hs_spicfg = { + IOPORT1, + PIOA_MMC_NPCS0, + AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, + (MAX_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 +}; + +/* Low speed SPI configuration (192KHz, NCPHA=1, CPOL=0).*/ +static SPIConfig ls_spicfg = { + IOPORT1, + PIOA_MMC_NPCS0, + AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, + (MIN_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 +}; + +/* MMC configuration (empty).*/ +static const MMCConfig mmc_cfg = {}; + +/* Card insertion verification.*/ +static bool_t mmc_is_inserted(void) { + return !palReadPad(IOPORT1, PIOA_MMC_CP); +} + +/* Card protection verification.*/ +static bool_t mmc_is_protected(void) { + return palReadPad(IOPORT1, PIOA_MMC_WP); +} + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +static FRESULT scan_files(char *path) +{ + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + siprintf(&path[i], "/%s", fn); + res = scan_files(path); + if (res != FR_OK) + break; + path[i] = 0; + } + else { + iprintf("%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { + size_t n, size; + char buf[52]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: mem"); + return; + } + n = chHeapStatus(NULL, &size); + siprintf(buf, "core free memory : %lu bytes", chCoreStatus()); + shellPrintLine(chp, buf); + siprintf(buf, "heap fragments : %lu", n); + shellPrintLine(chp, buf); + siprintf(buf, "heap free total : %lu bytes", size); + shellPrintLine(chp, buf); +} + +static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { + static const char *states[] = { + "READY", + "CURRENT", + "SUSPENDED", + "WTSEM", + "WTMTX", + "WTCOND", + "SLEEPING", + "WTEXIT", + "WTOREVT", + "WTANDEVT", + "SNDMSG", + "WTMSG", + "FINAL" + }; + Thread *tp; + char buf[60]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: threads"); + return; + } + shellPrintLine(chp, " addr stack prio refs state time"); + tp = chRegFirstThread(); + do { + siprintf(buf, "%8lx %8lx %4u %4i %9s %u", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (unsigned int)tp->p_prio, tp->p_refs - 1, + states[tp->p_state], (unsigned int)tp->p_time); + shellPrintLine(chp, buf); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: test"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + shellPrintLine(chp, "out of memory"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseChannel *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: tree"); + return; + } + if (!fs_ready) { + shellPrintLine(chp, "File System not mounted"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + shellPrintLine(chp, "FS: f_getfree() failed"); + return; + } + siprintf((void *)fbuff, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); + shellPrintLine(chp, (void *)fbuff); + fbuff[0] = 0; + scan_files((char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD1, + commands +}; + +/* + * LED1 blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palTogglePad(IOPORT1, PIOA_LED1); + if (fs_ready) + chThdSleepMilliseconds(200); + else + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * LED2 blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 64); +static msg_t Thread2(void *p) { + + (void)p; + while (TRUE) { + palSetPad(IOPORT1, PIOA_LED2); + chThdSleepMilliseconds(100); + palClearPad(IOPORT1, PIOA_LED2); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + /* + * On insertion MMC initialization and FS mount. + */ + if (mmcConnect(&MMCD1)) { + return; + } + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + fs_ready = FALSE; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + static const evhandler_t evhndl[] = { + InsertHandler, + RemoveHandler + }; + Thread *shelltp = NULL; + struct EventListener el0, el1; + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes the MMC driver to work with SPI. + */ + palSetPadMode(IOPORT1, PIOA_MMC_NPCS0, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT1, PIOA_MMC_NPCS0); + mmcObjectInit(&MMCD1, &SPID, + &ls_spicfg, &hs_spicfg, + mmc_is_protected, mmc_is_inserted); + mmcStart(&MMCD1, &mmc_cfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + chEvtRegister(&MMCD1.mmc_inserted_event, &el0, 0); + chEvtRegister(&MMCD1.mmc_removed_event, &el1, 1); + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + } + return 0; +} diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h new file mode 100644 index 000000000..a8c41b07b --- /dev/null +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h @@ -0,0 +1,59 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ +#define USE_AT91SAM7_SPI TRUE diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/readme.txt b/demos/ARM7-AT91SAM7S-FATFS-GCC/readme.txt new file mode 100644 index 000000000..cc9659d8e --- /dev/null +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/readme.txt @@ -0,0 +1,24 @@ +***************************************************************************** +** ChibiOS/RT + FatFS demo for SAM7. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM-P256 board. The port on other boards or other +members of the SAM7 family should be an easy task. + +** The Demo ** + +This demo shows how to integrate the FatFs file system and use the SPI and MMC +drivers. +The demo flashes the board LEDs using two threads and monitors the MMC slot for +a card insertion. When a card is inserted then the file system is mounted +and the LED1 flashes faster. +A command line shell is spawned on SD1, all the interaction with the demo is +performed using the command shell, type "help" for a list of the available +commands. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile new file mode 100644 index 000000000..c74d12ab6 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile @@ -0,0 +1,189 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk +include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk +include $(CHIBIOS)/ext/fatfs/fatfs.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(FATFSSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(FATFSINC) \ + $(CHIBIOS)/os/various \ + $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = arm7tdmi + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DSTDOUT_SD=SD1 -DSTDIN_SD=SD1 + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/ch.ld b/demos/ARM7-AT91SAM7X-FATFS-GCC/ch.ld new file mode 100644 index 000000000..50ab38952 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/ch.ld @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7X256 memory setup. + */ +__und_stack_size__ = 0x0004; +__abt_stack_size__ = 0x0004; +__fiq_stack_size__ = 0x0010; +__irq_stack_size__ = 0x0080; +__svc_stack_size__ = 0x0004; +__sys_stack_size__ = 0x0400; +__stacks_total_size__ = __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__; + +MEMORY +{ + flash : org = 0x100000, len = 256k + ram : org = 0x200020, len = 64k - 0x20 +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*); + *(.rodata); + *(.rodata.*); + *(.glue_7t); + *(.glue_7); + *(.gcc*); + *(.ctors); + *(.dtors); + . = ALIGN(4); + _etext = .; + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + /DISCARD/ : + { + *(.eh_*) + } +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h @@ -0,0 +1,483 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure hook. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ +}; +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h new file mode 100644 index 000000000..525bae43a --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -0,0 +1,152 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @addtogroup HAL_CONF + * @{ + */ + +/* + * HAL configuration file, this file allows to enable or disable the various + * device drivers from your application. You may also use this file in order + * to override the device drivers default settings. + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +/* + * Uncomment the following line in order to include a mcu-related + * settings file. This file can be used to include platform specific + * header files or to override the low level drivers settings. + */ +#include "mcuconf.h" + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_PAL TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) +#define CH_HAL_USE_ADC FALSE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) +#define CH_HAL_USE_CAN FALSE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) +#define CH_HAL_USE_MAC FALSE +#endif + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) +#define CH_HAL_USE_PWM FALSE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define CH_HAL_USE_SERIAL TRUE +#endif + +/* + * Default SERIAL settings overrides (uncomment to override). + */ +/*#define SERIAL_DEFAULT_BITRATE 38400*/ +/*#define SERIAL_BUFFERS_SIZE 64*/ + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_SPI TRUE +#endif + +/* + * Default SPI settings overrides (uncomment to override). + */ +/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define CH_HAL_USE_MMC_SPI TRUE +#endif + +/* + * Default MMC_SPI settings overrides (uncomment to override). + */ +/*#define MMC_SECTOR_SIZE 512*/ +/*#define MMC_NICE_WAITING TRUE*/ +/*#define MMC_POLLING_INTERVAL 10*/ +/*#define MMC_POLLING_DELAY 10*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c new file mode 100644 index 000000000..fc8139146 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -0,0 +1,332 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include +#include + +#include "ch.h" +#include "hal.h" +#include "test.h" +#include "shell.h" +#include "evtimer.h" +#include "ff.h" + +#define MAX_SPI_BITRATE 100 +#define MIN_SPI_BITRATE 250 + +/** + * @brief FS object. + */ +FATFS MMC_FS; + +/** + * MMC driver instance. + */ +MMCDriver MMCD1; + +/* FS mounted and ready.*/ +static bool_t fs_ready = FALSE; + +/* Maximum speed SPI configuration (__MHz, NCPHA=1, CPOL=0).*/ +static SPIConfig hs_spicfg = { + IOPORT1, + PIOA_CS_MMC, + AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, + (MAX_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 +}; + +/* Low speed SPI configuration (192KHz, NCPHA=1, CPOL=0).*/ +static SPIConfig ls_spicfg = { + IOPORT1, + PIOA_CS_MMC, + AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, + (MIN_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 +}; + +/* MMC configuration (empty).*/ +static const MMCConfig mmc_cfg = {}; + +/* Card insertion verification.*/ +static bool_t mmc_is_inserted(void) { + return !palReadPad(IOPORT2, PIOB_MMC_CP); +} + +/* Card protection verification.*/ +static bool_t mmc_is_protected(void) { + return palReadPad(IOPORT2, PIOB_MMC_WP); +} + +/* Generic large buffer.*/ +uint8_t fbuff[1024]; + +static FRESULT scan_files(char *path) +{ + FRESULT res; + FILINFO fno; + DIR dir; + int i; + char *fn; + + res = f_opendir(&dir, path); + if (res == FR_OK) { + i = strlen(path); + for (;;) { + res = f_readdir(&dir, &fno); + if (res != FR_OK || fno.fname[0] == 0) + break; + if (fno.fname[0] == '.') + continue; + fn = fno.fname; + if (fno.fattrib & AM_DIR) { + siprintf(&path[i], "/%s", fn); + res = scan_files(path); + if (res != FR_OK) + break; + path[i] = 0; + } + else { + iprintf("%s/%s\r\n", path, fn); + } + } + } + return res; +} + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define TEST_WA_SIZE THD_WA_SIZE(256) + +static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { + size_t n, size; + char buf[52]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: mem"); + return; + } + n = chHeapStatus(NULL, &size); + siprintf(buf, "core free memory : %lu bytes", chCoreStatus()); + shellPrintLine(chp, buf); + siprintf(buf, "heap fragments : %lu", n); + shellPrintLine(chp, buf); + siprintf(buf, "heap free total : %lu bytes", size); + shellPrintLine(chp, buf); +} + +static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) { + static const char *states[] = { + "READY", + "CURRENT", + "SUSPENDED", + "WTSEM", + "WTMTX", + "WTCOND", + "SLEEPING", + "WTEXIT", + "WTOREVT", + "WTANDEVT", + "SNDMSG", + "WTMSG", + "FINAL" + }; + Thread *tp; + char buf[60]; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: threads"); + return; + } + shellPrintLine(chp, " addr stack prio refs state time"); + tp = chRegFirstThread(); + do { + siprintf(buf, "%8lx %8lx %4u %4i %9s %u", + (uint32_t)tp, (uint32_t)tp->p_ctx.r13, + (unsigned int)tp->p_prio, tp->p_refs - 1, + states[tp->p_state], (unsigned int)tp->p_time); + shellPrintLine(chp, buf); + tp = chRegNextThread(tp); + } while (tp != NULL); +} + +static void cmd_test(BaseChannel *chp, int argc, char *argv[]) { + Thread *tp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: test"); + return; + } + tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(), + TestThread, chp); + if (tp == NULL) { + shellPrintLine(chp, "out of memory"); + return; + } + chThdWait(tp); +} + +static void cmd_tree(BaseChannel *chp, int argc, char *argv[]) { + FRESULT err; + uint32_t clusters; + FATFS *fsp; + + (void)argv; + if (argc > 0) { + shellPrintLine(chp, "Usage: tree"); + return; + } + if (!fs_ready) { + shellPrintLine(chp, "File System not mounted"); + return; + } + err = f_getfree("/", &clusters, &fsp); + if (err != FR_OK) { + shellPrintLine(chp, "FS: f_getfree() failed"); + return; + } + siprintf((void *)fbuff, + "FS: %lu free clusters, %lu sectors per cluster, %lu bytes free", + clusters, (uint32_t)MMC_FS.csize, + clusters * (uint32_t)MMC_FS.csize * (uint32_t)MMC_SECTOR_SIZE); + shellPrintLine(chp, (void *)fbuff); + fbuff[0] = 0; + scan_files((char *)fbuff); +} + +static const ShellCommand commands[] = { + {"mem", cmd_mem}, + {"threads", cmd_threads}, + {"test", cmd_test}, + {"tree", cmd_tree}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseChannel *)&SD1, + commands +}; + +/* + * LCD blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *p) { + + (void)p; + while (TRUE) { + palSetPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); + } + return 0; +} + +/* + * MMC card insertion event. + */ +static void InsertHandler(eventid_t id) { + FRESULT err; + + (void)id; + /* + * On insertion MMC initialization and FS mount. + */ + if (mmcConnect(&MMCD1)) { + return; + } + err = f_mount(0, &MMC_FS); + if (err != FR_OK) { + mmcDisconnect(&MMCD1); + return; + } + fs_ready = TRUE; +} + +/* + * MMC card removal event. + */ +static void RemoveHandler(eventid_t id) { + + (void)id; + fs_ready = FALSE; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + static const evhandler_t evhndl[] = { + InsertHandler, + RemoveHandler + }; + Thread *shelltp = NULL; + struct EventListener el0, el1; + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Shell manager initialization. + */ + shellInit(); + + /* + * Initializes the MMC driver to work with SPI. + */ + palSetPadMode(IOPORT1, PIOA_CS_MMC, PAL_MODE_OUTPUT_PUSHPULL); + palSetPad(IOPORT1, PIOA_CS_MMC); + mmcObjectInit(&MMCD1, &SPID, + &ls_spicfg, &hs_spicfg, + mmc_is_protected, mmc_is_inserted); + mmcStart(&MMCD1, &mmc_cfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and listen for events. + */ + chEvtRegister(&MMCD1.mmc_inserted_event, &el0, 0); + chEvtRegister(&MMCD1.mmc_removed_event, &el1, 1); + while (TRUE) { + if (!shelltp) + shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO); + else if (chThdTerminated(shelltp)) { + chThdRelease(shelltp); /* Recovers memory of the previous shell. */ + shelltp = NULL; /* Triggers spawning of a new shell. */ + } + chEvtDispatch(evhndl, chEvtWaitOne(ALL_EVENTS)); + } + return 0; +} diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h new file mode 100644 index 000000000..a8c41b07b --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h @@ -0,0 +1,59 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * AT91SAM7 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * ADC driver system settings. + */ + +/* + * CAN driver system settings. + */ + +/* + * MAC driver system settings. + */ +#define MAC_TRANSMIT_BUFFERS 2 +#define MAC_RECEIVE_BUFFERS 2 +#define MAC_BUFFERS_SIZE 1518 +#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3) + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +#define USE_SAM7_USART0 TRUE +#define USE_SAM7_USART1 TRUE +#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) +#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2) + +/* + * SPI driver system settings. + */ +#define USE_AT91SAM7_SPI TRUE diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt b/demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt new file mode 100644 index 000000000..4430e8b41 --- /dev/null +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/readme.txt @@ -0,0 +1,24 @@ +***************************************************************************** +** ChibiOS/RT + FatFS demo for SAM7. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an Olimex SAM-EX256 board. The port on other boards or other +members of the SAM7 family should be an easy task. + +** The Demo ** + +This demo shows how to integrate the FatFs file system and use the SPI and MMC +drivers. +The demo flashes the board LCD background using a thread and monitors the MMC +slot for a card insertion. When a card is inserted then the file system is +mounted and the LCD background flashes faster. +A command line shell is spawned on SD1, all the interaction with the demo is +performed using the command shell, type "help" for a list of the available +commands. + +** Build Procedure ** + +The demo was built using the YAGARTO toolchain but any toolchain based on GCC +and GNU userspace programs will work. -- cgit v1.2.3 From eb9865920d6cac47b4779cc0887ed31a270062e6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Jul 2010 06:30:48 +0000 Subject: Removed -mabi=apcs-gnu from the Cortex-Mx makefiles. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2064 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 2 +- demos/ARMCM3-LPC1343-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F107-GCC/Makefile | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index 544c58679..5c481ec20 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARMCM3-LPC1343-GCC/Makefile b/demos/ARMCM3-LPC1343-GCC/Makefile index d85428b16..0bc5276b4 100644 --- a/demos/ARMCM3-LPC1343-GCC/Makefile +++ b/demos/ARMCM3-LPC1343-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index a1c7a5668..8926ccbfc 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 623ddc8ee..bf9247aba 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARMCM3-STM32F107-GCC/Makefile b/demos/ARMCM3-STM32F107-GCC/Makefile index f8767cfdf..c199576c6 100644 --- a/demos/ARMCM3-STM32F107-GCC/Makefile +++ b/demos/ARMCM3-STM32F107-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From 0a189322ef87493d9381d8baf82ebae8e1009819 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 11 Jul 2010 10:24:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2067 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index cfe5fde8b..0802ec7bc 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -113,11 +113,11 @@ static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { return; } n = chHeapStatus(NULL, &size); - siprintf(buf, "core free memory : %lu bytes", chCoreStatus()); + siprintf(buf, "core free memory : %u bytes", chCoreStatus()); shellPrintLine(chp, buf); - siprintf(buf, "heap fragments : %lu", n); + siprintf(buf, "heap fragments : %u", n); shellPrintLine(chp, buf); - siprintf(buf, "heap free total : %lu bytes", size); + siprintf(buf, "heap free total : %u bytes", size); shellPrintLine(chp, buf); } -- cgit v1.2.3 From 131b177925913634bd96e02e7a9f7d529a122df0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Jul 2010 09:10:47 +0000 Subject: Updated all the halconf.h files in the tree. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2088 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 11 +++++++++++ demos/ARM7-AT91SAM7S-GCC/halconf.h | 11 +++++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 11 +++++++++++ demos/ARM7-AT91SAM7X-GCC/halconf.h | 11 +++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 11 +++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 11 +++++++++++ demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 11 +++++++++++ demos/ARM7-LPC214x-G++/halconf.h | 11 +++++++++++ demos/ARM7-LPC214x-GCC/halconf.h | 11 +++++++++++ demos/ARMCM0-LPC1114-GCC/halconf.h | 11 +++++++++++ demos/ARMCM3-LPC1343-GCC/halconf.h | 11 +++++++++++ demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 11 +++++++++++ demos/ARMCM3-STM32F103-GCC/halconf.h | 11 +++++++++++ demos/ARMCM3-STM32F107-GCC/halconf.h | 11 +++++++++++ demos/AVR-AT90CANx-GCC/halconf.h | 11 +++++++++++ demos/AVR-ATmega128-GCC/halconf.h | 11 +++++++++++ demos/MSP430-MSP430x1611-GCC/halconf.h | 11 +++++++++++ demos/PPC-SPC563-GCC/halconf.h | 11 +++++++++++ demos/Posix-GCC/halconf.h | 11 +++++++++++ demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 11 +++++++++++ demos/STM8S-STM8S208-RC/halconf.h | 11 +++++++++++ demos/Win32-MinGW/halconf.h | 11 +++++++++++ 22 files changed, 242 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index 525bae43a..c941995ee 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index 525bae43a..c941995ee 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 1ad94f04b..ab1b7677c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 1ad94f04b..ab1b7677c 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index 525bae43a..c941995ee 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARMCM0-LPC1114-GCC/halconf.h +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-LPC1343-GCC/halconf.h b/demos/ARMCM3-LPC1343-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARMCM3-LPC1343-GCC/halconf.h +++ b/demos/ARMCM3-LPC1343-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index 525bae43a..c941995ee 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F107-GCC/halconf.h b/demos/ARMCM3-STM32F107-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/ARMCM3-STM32F107-GCC/halconf.h +++ b/demos/ARMCM3-STM32F107-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index 7859d0f0e..de9c05fdf 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index 7859d0f0e..de9c05fdf 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index 40264527c..74aaff977 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index b325b7238..b870f61b8 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index e68d87a79..67d6c6d08 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index 763b0019a..a9d7369b9 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index b325b7238..b870f61b8 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -147,6 +147,17 @@ /*#define MMC_POLLING_INTERVAL 10*/ /*#define MMC_POLLING_DELAY 10*/ +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) +#define CH_HAL_USE_UART FALSE +#endif + #endif /* _HALCONF_H_ */ /** @} */ -- cgit v1.2.3 From 8249123228e7de9f1694905d090f91a063306bdf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 27 Jul 2010 14:44:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2095 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 731ec9f85..723b5b991 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -98,3 +98,10 @@ #define STM32_SPI1_IRQ_PRIORITY 10 #define STM32_SPI2_IRQ_PRIORITY 10 #define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 1 -- cgit v1.2.3 From da5080f92aa8b725e99d26269c714294c32e9d82 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 30 Jul 2010 18:02:52 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2098 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 723b5b991..6e2caf61d 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -103,5 +103,12 @@ * UART driver system settings. */ #define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE #define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 1 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK() chSysHalt() -- cgit v1.2.3 From a2cfd2054ad5da4dbf8b583a7eaf164d9dac6006 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 8 Aug 2010 07:57:28 +0000 Subject: Fixed bug 3041414. Various improvements to the STM32 HAL. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2119 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 109 +++++++++++++++------------ demos/ARMCM3-STM32F103-GCC/mcuconf.h | 101 +++++++++++++------------ demos/ARMCM3-STM32F107-GCC/mcuconf.h | 115 +++++++++++++++++------------ 3 files changed, 181 insertions(+), 144 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index 731ec9f85..42022d23c 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -21,8 +21,8 @@ * STM32 drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. * * IRQ priorities: * 15...0 Lowest...Highest. @@ -34,67 +34,84 @@ /* * HAL driver system settings. */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCO STM32_MCO_NOCLOCK +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK /* * ADC driver system settings. */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 3 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt() /* * CAN driver system settings. */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 /* * PWM driver system settings. */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM_PWM4_IRQ_PRIORITY 7 /* * SERIAL driver system settings. */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 /* * SPI driver system settings. */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 2 +#define STM32_SPI_SPI2_DMA_PRIORITY 2 +#define STM32_SPI_SPI3_DMA_PRIORITY 2 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 6e2caf61d..42022d23c 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -21,8 +21,8 @@ * STM32 drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. * * IRQ priorities: * 15...0 Lowest...Highest. @@ -34,76 +34,77 @@ /* * HAL driver system settings. */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 -#define STM32_PLLMUL_VALUE 9 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCO STM32_MCO_NOCLOCK +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK /* * ADC driver system settings. */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 3 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt() /* * CAN driver system settings. */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 /* * PWM driver system settings. */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM_PWM4_IRQ_PRIORITY 7 /* * SERIAL driver system settings. */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 /* * SPI driver system settings. */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 2 +#define STM32_SPI_SPI2_DMA_PRIORITY 2 +#define STM32_SPI_SPI3_DMA_PRIORITY 2 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt() /* * UART driver system settings. */ -#define STM32_UART_USE_USART1 TRUE -#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE #define STM32_UART_USE_USART3 FALSE #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 @@ -111,4 +112,6 @@ #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F107-GCC/mcuconf.h b/demos/ARMCM3-STM32F107-GCC/mcuconf.h index e4d7f155c..b11c2aae9 100644 --- a/demos/ARMCM3-STM32F107-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F107-GCC/mcuconf.h @@ -21,8 +21,8 @@ * STM32 drivers configuration. * The following settings override the default settings present in * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the driver - * is enabled in halconf.h. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. * * IRQ priorities: * 15...0 Lowest...Highest. @@ -34,70 +34,87 @@ /* * HAL driver system settings. */ -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 -#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 -#define STM32_PREDIV1_VALUE 5 -#define STM32_PLLMUL_VALUE 9 -#define STM32_PREDIV2_VALUE 5 -#define STM32_PLL2MUL_VALUE 8 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV2 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_ADCPRE STM32_ADCPRE_DIV4 -#define STM32_MCO STM32_MCO_NOCLOCK +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2 +#define STM32_PREDIV1_VALUE 5 +#define STM32_PLLMUL_VALUE 9 +#define STM32_PREDIV2_VALUE 5 +#define STM32_PLL2MUL_VALUE 8 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK /* * ADC driver system settings. */ -#define USE_STM32_ADC1 TRUE -#define STM32_ADC1_DMA_PRIORITY 3 -#define STM32_ADC1_IRQ_PRIORITY 5 -#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 3 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt() /* * CAN driver system settings. */ -#define USE_STM32_CAN1 TRUE -#define STM32_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 /* * PWM driver system settings. */ -#define USE_STM32_PWM1 TRUE -#define USE_STM32_PWM2 FALSE -#define USE_STM32_PWM3 FALSE -#define USE_STM32_PWM4 FALSE -#define STM32_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM4_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM_PWM4_IRQ_PRIORITY 7 /* * SERIAL driver system settings. */ -#define USE_STM32_USART1 FALSE -#define USE_STM32_USART2 TRUE -#define USE_STM32_USART3 FALSE -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define USE_STM32_UART4 FALSE -#define USE_STM32_UART5 FALSE -#endif -#define STM32_USART1_PRIORITY 12 -#define STM32_USART2_PRIORITY 12 -#define STM32_USART3_PRIORITY 12 -#if defined(STM32F10X_HD) || defined(STM32F10X_CL) -#define STM32_UART4_PRIORITY 12 -#define STM32_UART5_PRIORITY 12 -#endif +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 /* * SPI driver system settings. */ -#define USE_STM32_SPI1 TRUE -#define USE_STM32_SPI2 TRUE -#define STM32_SPI1_DMA_PRIORITY 2 -#define STM32_SPI2_DMA_PRIORITY 2 -#define STM32_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 2 +#define STM32_SPI_SPI2_DMA_PRIORITY 2 +#define STM32_SPI_SPI3_DMA_PRIORITY 2 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt() -- cgit v1.2.3 From 138c0f900d823b2c953038048bc40b14610f958a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 21 Aug 2010 08:38:14 +0000 Subject: Added new kernel hooks (on halt and on systick). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2136 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h | 50 ++-- demos/ARM7-AT91SAM7S-GCC/chconf.h | 267 +++++++++++++--------- demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h | 50 ++-- demos/ARM7-AT91SAM7X-GCC/chconf.h | 46 ++-- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 42 +++- demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 46 ++-- demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 46 ++-- demos/ARM7-LPC214x-G++/chconf.h | 46 ++-- demos/ARM7-LPC214x-GCC/chconf.h | 46 ++-- demos/ARMCM0-LPC1114-GCC/chconf.h | 46 ++-- demos/ARMCM3-LPC1343-GCC/chconf.h | 46 ++-- demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 46 ++-- demos/ARMCM3-STM32F103-GCC/chconf.h | 46 ++-- demos/ARMCM3-STM32F107-GCC/chconf.h | 46 ++-- demos/AVR-AT90CANx-GCC/chconf.h | 46 ++-- demos/AVR-ATmega128-GCC/chconf.h | 46 ++-- demos/MSP430-MSP430x1611-GCC/chconf.h | 46 ++-- demos/PPC-SPC563-GCC/chconf.h | 46 ++-- demos/Posix-GCC/chconf.h | 46 ++-- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h | 42 +++- demos/STM8S-STM8S208-RC/chconf.h | 50 ++-- demos/Win32-MinGW/chconf.h | 46 ++-- 22 files changed, 853 insertions(+), 384 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h index 046d28300..8f2c4b3e3 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,11 +471,37 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ } #endif +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7S-GCC/chconf.h b/demos/ARM7-AT91SAM7S-GCC/chconf.h index 8cada3cd9..8f2c4b3e3 100644 --- a/demos/ARM7-AT91SAM7S-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/chconf.h @@ -18,9 +18,13 @@ */ /** - * @file templates/chconf.h - * @brief Configuration file template. + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * * @addtogroup config + * @details Kernel related settings and hooks. * @{ */ @@ -32,7 +36,7 @@ /*===========================================================================*/ /** - * @brief System tick frequency. + * @brief System tick frequency. * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ @@ -41,20 +45,22 @@ #endif /** - * @brief Round robin interval. + * @brief Round robin interval. * @details This constant is the number of system ticks allowed for the * threads before preemption occurs. Setting this value to zero - * disables the round robin mechanism. + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. * - * @note Disabling round robin makes the kernel more compact and generally - * faster but forbids multiple threads at the same priority level. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. */ #if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) #define CH_TIME_QUANTUM 20 #endif /** - * @brief Nested locks. + * @brief Nested locks. * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() * operations is allowed.
* For performance and code size reasons the recommended setting @@ -62,22 +68,22 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note The default is @p FALSE. + * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE #endif /** - * @brief Managed RAM size. + * @brief Managed RAM size. * @details Size of the RAM area to be managed by the OS. If set to zero * then the whole available RAM is used. The core memory is made * available to the heap allocator and/or can be used directly through * the simplified core memory allocator. * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_COREMEM. + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) #define CH_MEMCORE_SIZE 0 @@ -88,32 +94,32 @@ /*===========================================================================*/ /** - * @brief OS optimization. + * @brief OS optimization. * @details If enabled then time efficient rather than space efficient code * is used when two possible implementations exist. * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. */ #if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) #define CH_OPTIMIZE_SPEED TRUE #endif /** - * @brief Exotic optimization. + * @brief Exotic optimization. * @details If defined then a CPU register is used as storage for the global * @p currp variable. Caching this variable in a register greatly * improves both space and time OS efficiency. A side effect is that * one less register has to be saved during the context switch * resulting in lower RAM usage and faster context switch. * - * @note This option is only usable with the GCC compiler and is only useful - * on processors with many registers like ARM cores. - * @note If this option is enabled then ALL the libraries linked to the - * ChibiOS/RT code must be recompiled with the GCC option @p - * -ffixed-@. - * @note This option must be enabled in the Makefile, it is listed here for - * documentation only. + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. */ #if defined(__DOXYGEN__) #define CH_CURRP_REGISTER_CACHE "reg" @@ -124,209 +130,220 @@ /*===========================================================================*/ /** - * @brief Threads synchronization APIs. + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. * @details If enabled then the @p chThdWait() function is included in * the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) #define CH_USE_WAITEXIT TRUE #endif /** - * @brief Semaphores APIs. + * @brief Semaphores APIs. * @details If enabled then the Semaphores APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES TRUE #endif /** - * @brief Semaphores queuing mode. + * @brief Semaphores queuing mode. * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_SEMAPHORES_PRIORITY FALSE #endif /** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemWaitSignal() API + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API * is included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) #define CH_USE_SEMSW TRUE #endif /** - * @brief Mutexes APIs. + * @brief Mutexes APIs. * @details If enabled then the mutexes APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) #define CH_USE_MUTEXES TRUE #endif /** - * @brief Conditional Variables APIs. + * @brief Conditional Variables APIs. * @details If enabled then the conditional variables APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) #define CH_USE_CONDVARS TRUE #endif /** - * @brief Conditional Variables APIs with timeout. + * @brief Conditional Variables APIs with timeout. * @details If enabled then the conditional variables APIs with timeout * specification are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. */ #if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_CONDVARS_TIMEOUT TRUE #endif /** - * @brief Events Flags APIs. + * @brief Events Flags APIs. * @details If enabled then the event flags APIs are included in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) #define CH_USE_EVENTS TRUE #endif /** - * @brief Events Flags APIs with timeout. + * @brief Events Flags APIs with timeout. * @details If enabled then the events APIs with timeout specification * are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. */ #if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) #define CH_USE_EVENTS_TIMEOUT TRUE #endif /** - * @brief Synchronous Messages APIs. + * @brief Synchronous Messages APIs. * @details If enabled then the synchronous messages APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) #define CH_USE_MESSAGES TRUE #endif /** - * @brief Synchronous Messages queuing mode. + * @brief Synchronous Messages queuing mode. * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. */ #if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) #define CH_USE_MESSAGES_PRIORITY FALSE #endif /** - * @brief Mailboxes APIs. + * @brief Mailboxes APIs. * @details If enabled then the asynchronous messages (mailboxes) APIs are * included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) #define CH_USE_MAILBOXES TRUE #endif /** - * @brief I/O Queues APIs. + * @brief I/O Queues APIs. * @details If enabled then the I/O queues APIs are included in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) #define CH_USE_QUEUES TRUE #endif /** - * @brief Core Memory Manager APIs. + * @brief Core Memory Manager APIs. * @details If enabled then the core memory manager APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) #define CH_USE_MEMCORE TRUE #endif /** - * @brief Heap Allocator APIs. + * @brief Heap Allocator APIs. * @details If enabled then the memory heap allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. - * @note Mutexes are recommended. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. */ #if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) #define CH_USE_HEAP TRUE #endif /** - * @brief C-runtime allocator. + * @brief C-runtime allocator. * @details If enabled the the heap allocator APIs just wrap the C-runtime * @p malloc() and @p free() functions. * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the - * appropriate documentation. + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. */ #if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) #define CH_USE_MALLOC_HEAP FALSE #endif /** - * @brief Memory Pools Allocator APIs. + * @brief Memory Pools Allocator APIs. * @details If enabled then the memory pools allocator APIs are included * in the kernel. * - * @note The default is @p TRUE. + * @note The default is @p TRUE. */ #if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) #define CH_USE_MEMPOOLS TRUE #endif /** - * @brief Dynamic Threads APIs. + * @brief Dynamic Threads APIs. * @details If enabled then the dynamic threads creation APIs are included * in the kernel. * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. */ #if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) #define CH_USE_DYNAMIC TRUE @@ -337,71 +354,73 @@ /*===========================================================================*/ /** - * @brief Debug option, parameters checks. + * @brief Debug option, parameters checks. * @details If enabled then the checks on the API functions input * parameters are activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_CHECKS FALSE #endif /** - * @brief Debug option, consistency checks. + * @brief Debug option, consistency checks. * @details If enabled then all the assertions in the kernel code are * activated. This includes consistency checks inside the kernel, * runtime anomalies and port-defined checks. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_ASSERTS FALSE #endif /** - * @brief Debug option, trace buffer. + * @brief Debug option, trace buffer. * @details If enabled then the context switch circular trace buffer is * activated. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_TRACE FALSE #endif /** - * @brief Debug option, stack checks. + * @brief Debug option, stack checks. * @details If enabled then a runtime stack check is performed. * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. It - * may not be implemented or some ports. + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) #define CH_DBG_ENABLE_STACK_CHECK FALSE #endif /** - * @brief Debug option, stacks initialization. + * @brief Debug option, stacks initialization. * @details If enabled then the threads working area is filled with a byte * value when a thread is created. This can be useful for the * runtime measurement of the used stack. * - * @note The default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) #define CH_DBG_FILL_THREADS FALSE #endif /** - * @brief Debug option, threads profiling. + * @brief Debug option, threads profiling. * @details If enabled then a field is added to the @p Thread structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) #define CH_DBG_THREADS_PROFILING TRUE @@ -412,50 +431,70 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** - * @brief Threads initialization hook. + * @brief Threads initialization hook. * @details User initialization code added to the @p chThdInit() API. * - * @note It is invoked from within @p chThdInit() and implicitily from all - * the threads creation APIs. + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif /** - * @brief Threads finalization hook. + * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. * - * @note It is inserted into lock zone. - * @note It is also invoked when the threads simply return in order to - * terminate. + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif /** - * @brief Idle Loop hook. + * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h index 046d28300..8f2c4b3e3 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,11 +471,37 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ } #endif +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + #endif /* _CHCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 6ddb1d2d1..6e6c99ab4 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -434,8 +434,8 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ struct { \ /* Add threads custom fields here.*/ \ /* Space for the LWIP sys_timeouts structure.*/ \ @@ -450,9 +450,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ (tp)->p_lwipspace[0] = NULL; \ } #endif @@ -465,9 +465,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -476,8 +476,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARMCM0-LPC1114-GCC/chconf.h b/demos/ARMCM0-LPC1114-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARMCM0-LPC1114-GCC/chconf.h +++ b/demos/ARMCM0-LPC1114-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARMCM3-LPC1343-GCC/chconf.h b/demos/ARMCM3-LPC1343-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARMCM3-LPC1343-GCC/chconf.h +++ b/demos/ARMCM3-LPC1343-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/ARMCM3-STM32F107-GCC/chconf.h b/demos/ARMCM3-STM32F107-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/ARMCM3-STM32F107-GCC/chconf.h +++ b/demos/ARMCM3-STM32F107-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index ccab98d65..2c3129708 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index ccab98d65..2c3129708 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index f92563155..657bc057f 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h index 6522e0b3b..8f2c4b3e3 100644 --- a/demos/PPC-SPC563-GCC/chconf.h +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,8 +471,30 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h index 59a895f70..41bb68fc6 100644 --- a/demos/Posix-GCC/chconf.h +++ b/demos/Posix-GCC/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,12 +471,32 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ } #endif -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h index 55036c05d..6929552a1 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h @@ -434,8 +434,8 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ /* Add threads custom fields here.*/ #endif @@ -446,9 +446,9 @@ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -460,9 +460,9 @@ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -471,8 +471,30 @@ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index a426256ef..6929552a1 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -86,7 +86,7 @@ * @note Requires @p CH_USE_COREMEM. */ #if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 3072 +#define CH_MEMCORE_SIZE 128 #endif /*===========================================================================*/ @@ -191,7 +191,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES FALSE +#define CH_USE_MUTEXES TRUE #endif /** @@ -203,7 +203,7 @@ * @note Requires @p CH_USE_MUTEXES. */ #if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS FALSE +#define CH_USE_CONDVARS TRUE #endif /** @@ -272,7 +272,7 @@ * @note Requires @p CH_USE_SEMAPHORES. */ #if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES FALSE +#define CH_USE_MAILBOXES TRUE #endif /** @@ -434,8 +434,8 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ /* Add threads custom fields here.*/ #endif @@ -446,9 +446,9 @@ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -460,9 +460,9 @@ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -471,8 +471,30 @@ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ } #endif diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 59a895f70..41bb68fc6 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -434,11 +434,9 @@ * @brief Threads descriptor structure hook. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ -struct { \ - /* Add threads custom fields here.*/ \ -}; +#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS_HOOK \ + /* Add threads custom fields here.*/ #endif /** @@ -448,9 +446,9 @@ struct { \ * @note It is invoked from within @p chThdInit() and implicitily from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT(tp) { \ - /* Add threads initialization code here.*/ \ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ } #endif @@ -462,9 +460,9 @@ struct { \ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT(tp) { \ - /* Add threads finalization code here.*/ \ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ } #endif @@ -473,12 +471,32 @@ struct { \ * @details This hook is continuously invoked by the idle thread loop. */ #if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ } #endif -#define chThdGetExitEventSource(tp) (&(tp)->p_exitesource) +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ -- cgit v1.2.3 From 781b0b129cccbecba160effce8c4ddd68295b8b9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 11 Sep 2010 10:57:11 +0000 Subject: Fixed bug 3064204. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2175 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7S-GCC/halconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7X-GCC/halconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 10 ++++++++++ demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 10 ++++++++++ demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 10 ++++++++++ demos/ARM7-LPC214x-G++/halconf.h | 10 ++++++++++ demos/ARM7-LPC214x-GCC/halconf.h | 10 ++++++++++ demos/ARMCM0-LPC1114-GCC/halconf.h | 10 ++++++++++ demos/ARMCM3-LPC1343-GCC/halconf.h | 10 ++++++++++ demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 10 ++++++++++ demos/ARMCM3-STM32F107-GCC/halconf.h | 10 ++++++++++ demos/AVR-AT90CANx-GCC/halconf.h | 10 ++++++++++ demos/AVR-ATmega128-GCC/halconf.h | 10 ++++++++++ demos/MSP430-MSP430x1611-GCC/halconf.h | 10 ++++++++++ demos/PPC-SPC563-GCC/halconf.h | 10 ++++++++++ demos/Posix-GCC/halconf.h | 10 ++++++++++ demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 10 ++++++++++ demos/STM8S-STM8S208-RC/halconf.h | 10 ++++++++++ demos/Win32-MinGW/halconf.h | 10 ++++++++++ 21 files changed, 210 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index c941995ee..c65522e3a 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index c941995ee..c65522e3a 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index ab1b7677c..0fdc6cf1c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index ab1b7677c..0fdc6cf1c 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index c941995ee..c65522e3a 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/ARMCM0-LPC1114-GCC/halconf.h +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-LPC1343-GCC/halconf.h b/demos/ARMCM3-LPC1343-GCC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/ARMCM3-LPC1343-GCC/halconf.h +++ b/demos/ARMCM3-LPC1343-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index c941995ee..c65522e3a 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/ARMCM3-STM32F107-GCC/halconf.h b/demos/ARMCM3-STM32F107-GCC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/ARMCM3-STM32F107-GCC/halconf.h +++ b/demos/ARMCM3-STM32F107-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index de9c05fdf..f81870b13 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index de9c05fdf..f81870b13 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index 74aaff977..6e16e85a6 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index b870f61b8..6976d598e 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index 67d6c6d08..b0b87601a 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index a9d7369b9..87d0f835d 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index b870f61b8..6976d598e 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -62,6 +62,11 @@ #define CH_HAL_USE_ADC FALSE #endif +/* + * Default ADC settings overrides (uncomment to override). + */ +/*#define ADC_USE_WAIT TRUE*/ + /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -73,6 +78,11 @@ #define CH_HAL_USE_CAN FALSE #endif +/* + * Default CAN settings overrides (uncomment to override). + */ +/*#define CAN_USE_SLEEP_MODE TRUE*/ + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ -- cgit v1.2.3 From 759cb521269b63afd3f0f3f8229de11b54216694 Mon Sep 17 00:00:00 2001 From: liamstask Date: Tue, 21 Sep 2010 15:09:42 +0000 Subject: * remove typo mentioning a patched version of lwIP git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2185 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt index 7d3f7175a..14495cc0c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/readme.txt @@ -18,7 +18,7 @@ activates che ChibiOS/RT test suite, output on COM1. The demo was built using the YAGARTO toolchain but any toolchain based on GCC and GNU userspace programs will work. -The demo requires the patcher lwIP 1.3.1 stack, see: ./ext/readme.txt +The demo requires the lwIP 1.3.1 stack, included in ./ext ** Notes ** -- cgit v1.2.3 From 9716c406aca6180307960ebde7a852c34b7e97e1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 26 Sep 2010 14:57:24 +0000 Subject: Added a codeblocks demo project to the STM32F103 demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2205 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp | 310 +++++++++++++++++++++ .../codeblocks/ch/ch.workspace | 6 + 2 files changed, 316 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp create mode 100644 demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.workspace (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp b/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp new file mode 100644 index 000000000..82c5f1179 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp @@ -0,0 +1,310 @@ + + + + + + diff --git a/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.workspace b/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.workspace new file mode 100644 index 000000000..bee5a82f6 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.workspace @@ -0,0 +1,6 @@ + + + + + + -- cgit v1.2.3 From 75fb5ac2f5e12c8f8f8dc3769a2c0dc06b6d2d06 Mon Sep 17 00:00:00 2001 From: liamstask Date: Sun, 26 Sep 2010 21:15:08 +0000 Subject: * lwIP requires nested locks git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2206 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 6e6c99ab4..55ef1439d 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -71,7 +71,7 @@ * @note T he default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) -#define CH_USE_NESTED_LOCKS FALSE +#define CH_USE_NESTED_LOCKS TRUE #endif /** -- cgit v1.2.3 From efdf9a658b9bffb0a42dc792f2852f88873f4240 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 27 Sep 2010 18:43:55 +0000 Subject: Reverted name change for macro THREAD_EXT_FIELDS. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2210 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h | 6 +++--- demos/ARM7-AT91SAM7S-GCC/chconf.h | 6 +++--- demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h | 6 +++--- demos/ARM7-AT91SAM7X-GCC/chconf.h | 6 +++--- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 16 ++++++++-------- demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 6 +++--- demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 6 +++--- demos/ARM7-LPC214x-G++/chconf.h | 6 +++--- demos/ARM7-LPC214x-GCC/chconf.h | 6 +++--- demos/ARMCM0-LPC1114-GCC/chconf.h | 6 +++--- demos/ARMCM3-LPC1343-GCC/chconf.h | 6 +++--- demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 6 +++--- demos/ARMCM3-STM32F103-GCC/chconf.h | 6 +++--- demos/ARMCM3-STM32F107-GCC/chconf.h | 6 +++--- demos/AVR-AT90CANx-GCC/chconf.h | 6 +++--- demos/AVR-ATmega128-GCC/chconf.h | 6 +++--- demos/MSP430-MSP430x1611-GCC/chconf.h | 6 +++--- demos/PPC-SPC563-GCC/chconf.h | 6 +++--- demos/Posix-GCC/chconf.h | 6 +++--- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h | 6 +++--- demos/STM8S-STM8S208-RC/chconf.h | 6 +++--- demos/Win32-MinGW/chconf.h | 6 +++--- 22 files changed, 71 insertions(+), 71 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARM7-AT91SAM7S-GCC/chconf.h b/demos/ARM7-AT91SAM7S-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-AT91SAM7S-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 55ef1439d..f84bb536a 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -431,15 +431,15 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ -struct { \ - /* Add threads custom fields here.*/ \ - /* Space for the LWIP sys_timeouts structure.*/ \ - void *p_lwipspace[1]; \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ +struct { \ + /* Add threads custom fields here.*/ \ + /* Space for the LWIP sys_timeouts structure.*/ \ + void *p_lwipspace[1]; \ }; #endif @@ -453,7 +453,7 @@ struct { \ #if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) #define THREAD_EXT_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ - (tp)->p_lwipspace[0] = NULL; \ + (tp)->p_lwipspace[0] = NULL; \ } #endif diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARMCM0-LPC1114-GCC/chconf.h b/demos/ARMCM0-LPC1114-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARMCM0-LPC1114-GCC/chconf.h +++ b/demos/ARMCM0-LPC1114-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARMCM3-LPC1343-GCC/chconf.h b/demos/ARMCM3-LPC1343-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARMCM3-LPC1343-GCC/chconf.h +++ b/demos/ARMCM3-LPC1343-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/ARMCM3-STM32F107-GCC/chconf.h b/demos/ARMCM3-STM32F107-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/ARMCM3-STM32F107-GCC/chconf.h +++ b/demos/ARMCM3-STM32F107-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 2c3129708..8c10de14c 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 2c3129708..8c10de14c 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index 657bc057f..dbd5e4469 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h index 8f2c4b3e3..98bcdc40c 100644 --- a/demos/PPC-SPC563-GCC/chconf.h +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h index 41bb68fc6..3ced2ccbc 100644 --- a/demos/Posix-GCC/chconf.h +++ b/demos/Posix-GCC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h index 6929552a1..12b5c9e15 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index 6929552a1..12b5c9e15 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 41bb68fc6..3ced2ccbc 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -431,11 +431,11 @@ /*===========================================================================*/ /** - * @brief Threads descriptor structure hook. + * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p Thread structure. */ -#if !defined(THREAD_EXT_FIELDS_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS_HOOK \ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ /* Add threads custom fields here.*/ #endif -- cgit v1.2.3 From 441509bc2c585151a5d5974337d6fd2e156eab2a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 11 Oct 2010 18:55:06 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2247 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 0802ec7bc..2422f652b 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -46,10 +46,11 @@ MMCDriver MMCD1; static bool_t fs_ready = FALSE; /* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/ -static SPIConfig hs_spicfg = {IOPORT2, GPIOB_SPI2NSS, 0}; +static SPIConfig hs_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, 0}; /* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).*/ -static SPIConfig ls_spicfg = {IOPORT2, GPIOB_SPI2NSS, SPI_CR1_BR_2 | SPI_CR1_BR_1}; +static SPIConfig ls_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, + SPI_CR1_BR_2 | SPI_CR1_BR_1}; /* MMC configuration (empty).*/ static const MMCConfig mmc_cfg = {}; -- cgit v1.2.3 From c5053410867ea8538a918c4593075db04adaebca Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 11 Oct 2010 19:59:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2249 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 2422f652b..c9407731c 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -101,7 +101,7 @@ static FRESULT scan_files(char *path) /* Command line related. */ /*===========================================================================*/ -#define SHELL_WA_SIZE THD_WA_SIZE(1024) +#define SHELL_WA_SIZE THD_WA_SIZE(2048) #define TEST_WA_SIZE THD_WA_SIZE(256) static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) { -- cgit v1.2.3 From a7af0ac06b5cafe7dfadf3e292e3107a8e45ff21 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 17 Oct 2010 09:13:43 +0000 Subject: New LPC214x SPI device driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2264 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/Makefile | 2 +- demos/ARM7-LPC214x-FATFS-GCC/main.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile index 99ff790e9..17f023c4f 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/Makefile +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 + USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif # C++ specific options here (added to USE_OPT). diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c index 80d383356..92c4563e0 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -43,6 +43,7 @@ static bool_t fs_ready = FALSE; /* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0).*/ static SPIConfig hs_spicfg = { + NULL, IOPORT1, PA_SSEL1, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), @@ -52,6 +53,7 @@ static SPIConfig hs_spicfg = { /* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0).*/ static SPIConfig ls_spicfg = { + NULL, IOPORT1, PA_SSEL1, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), -- cgit v1.2.3 From bef0924474a4180b737e20fac0f27bcd468d1a2f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 17 Oct 2010 09:41:26 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2265 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile index 17f023c4f..99ff790e9 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/Makefile +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16 endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From b7e7258008897b11c6c8bbdc3220a49f3eaed949 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 17 Oct 2010 19:40:36 +0000 Subject: Unfinished AT91SAM7 SPI driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2266 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-FATFS-GCC/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c index fc8139146..9cc9221a3 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -45,17 +45,17 @@ static bool_t fs_ready = FALSE; /* Maximum speed SPI configuration (__MHz, NCPHA=1, CPOL=0).*/ static SPIConfig hs_spicfg = { + NULL, IOPORT1, PIOA_CS_MMC, - AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, (MAX_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 }; /* Low speed SPI configuration (192KHz, NCPHA=1, CPOL=0).*/ static SPIConfig ls_spicfg = { + NULL, IOPORT1, PIOA_CS_MMC, - AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, (MIN_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 }; -- cgit v1.2.3 From 66f21d9c87a9916e6737dc3de617c5496c1ea160 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 Oct 2010 11:51:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2270 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-FATFS-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c index 9cc9221a3..3e02fff74 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -303,7 +303,7 @@ int main(int argc, char **argv) { */ palSetPadMode(IOPORT1, PIOA_CS_MMC, PAL_MODE_OUTPUT_PUSHPULL); palSetPad(IOPORT1, PIOA_CS_MMC); - mmcObjectInit(&MMCD1, &SPID, + mmcObjectInit(&MMCD1, &SPID1, &ls_spicfg, &hs_spicfg, mmc_is_protected, mmc_is_inserted); mmcStart(&MMCD1, &mmc_cfg); -- cgit v1.2.3 From 341a89dfd55141c458b8a73b44b4188554208e46 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 Oct 2010 16:24:16 +0000 Subject: New AT91SAM7 SPI driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2271 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile index c74d12ab6..4fd0a9379 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From 16423f77811790eb11d089ed5ed45aa11abcb5af Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 Oct 2010 16:44:32 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2272 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/main.c | 6 +++--- demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h | 4 ++++ demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h | 4 ++++ 3 files changed, 11 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c index 478d2a606..5ebd0b9ff 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c @@ -45,17 +45,17 @@ static bool_t fs_ready = FALSE; /* Maximum speed SPI configuration (__MHz, NCPHA=1, CPOL=0).*/ static SPIConfig hs_spicfg = { + NULL, IOPORT1, PIOA_MMC_NPCS0, - AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, (MAX_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 }; /* Low speed SPI configuration (192KHz, NCPHA=1, CPOL=0).*/ static SPIConfig ls_spicfg = { + NULL, IOPORT1, PIOA_MMC_NPCS0, - AT91C_SPI_MSTR | AT91C_SPI_MODFDIS, (MIN_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 }; @@ -320,7 +320,7 @@ int main(int argc, char **argv) { */ palSetPadMode(IOPORT1, PIOA_MMC_NPCS0, PAL_MODE_OUTPUT_PUSHPULL); palSetPad(IOPORT1, PIOA_MMC_NPCS0); - mmcObjectInit(&MMCD1, &SPID, + mmcObjectInit(&MMCD1, &SPID1, &ls_spicfg, &hs_spicfg, mmc_is_protected, mmc_is_inserted); mmcStart(&MMCD1, &mmc_cfg); diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h index a8c41b07b..27117bfc7 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/mcuconf.h @@ -57,3 +57,7 @@ * SPI driver system settings. */ #define USE_AT91SAM7_SPI TRUE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h index a8c41b07b..7229a7e8a 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/mcuconf.h @@ -57,3 +57,7 @@ * SPI driver system settings. */ #define USE_AT91SAM7_SPI TRUE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 TRUE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) -- cgit v1.2.3 From 737df89c455794c2de3ec406923b820e5eb23c26 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 Oct 2010 18:16:54 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2273 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-GCC/mcuconf.h | 5 +++++ demos/ARM7-AT91SAM7X-GCC/mcuconf.h | 5 +++++ demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h | 5 +++++ demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h | 5 +++++ 4 files changed, 20 insertions(+) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-GCC/mcuconf.h b/demos/ARM7-AT91SAM7S-GCC/mcuconf.h index be2bcc852..519405ff1 100644 --- a/demos/ARM7-AT91SAM7S-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/mcuconf.h @@ -56,3 +56,8 @@ /* * SPI driver system settings. */ +#define USE_AT91SAM7_SPI FALSE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h index be2bcc852..519405ff1 100644 --- a/demos/ARM7-AT91SAM7X-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/mcuconf.h @@ -56,3 +56,8 @@ /* * SPI driver system settings. */ +#define USE_AT91SAM7_SPI FALSE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h index be2bcc852..519405ff1 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/mcuconf.h @@ -56,3 +56,8 @@ /* * SPI driver system settings. */ +#define USE_AT91SAM7_SPI FALSE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h index be2bcc852..519405ff1 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/mcuconf.h @@ -56,3 +56,8 @@ /* * SPI driver system settings. */ +#define USE_AT91SAM7_SPI FALSE +#define AT91SAM7_SPI_USE_SPI0 TRUE +#define AT91SAM7_SPI_USE_SPI1 FALSE +#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) +#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1) -- cgit v1.2.3 From 1a49558ed3e393ec8098000e6898218759921336 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 24 Oct 2010 16:07:45 +0000 Subject: LPC11xx HAL and Serial improvements, untested SPI driver added. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2281 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/halconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h index 87d0f835d..2c3afda84 100644 --- a/demos/ARMCM0-LPC1114-GCC/halconf.h +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -130,7 +130,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI TRUE #endif /* -- cgit v1.2.3 From d39721a6c2f050afe76421cf7409fc3e1803d154 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 24 Oct 2010 17:50:55 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2284 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/main.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 45496acfc..5f47acf1c 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -21,14 +21,28 @@ #include "hal.h" #include "test.h" + +/* Maximum speed SPI configuration (1MHz, CPHA=0, CPOL=0).*/ +static SPIConfig spicfg = { + NULL, + GPIO1, + GPIO1_SPI0SEL, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 0, + 48 +}; + /* * Red LED blinker thread, times are in milliseconds. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + uint8_t digit = 0; (void)arg; while (TRUE) { + spiStartSend(&SPID1, 1, &digit); + digit++; palClearPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); palSetPad(GPIO0, GPIO0_LED2); @@ -78,9 +92,10 @@ int main(int argc, char **argv) { (void)argv; /* - * Activates the serial driver 1 using the driver default configuration. + * Activates the SD1 and SPI1 drivers. */ - sdStart(&SD1, NULL); + sdStart(&SD1, NULL); /* Default: 38400,8,N,1. */ + spiStart(&SPID1, &spicfg); /* * Creates the blinker threads. -- cgit v1.2.3 From af0921235ffe94efb5467b3877b763d3c030cb0c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 24 Oct 2010 19:39:07 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2285 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/main.c | 1 - 1 file changed, 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 5f47acf1c..3a5197207 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -28,7 +28,6 @@ static SPIConfig spicfg = { GPIO1, GPIO1_SPI0SEL, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), - 0, 48 }; -- cgit v1.2.3 From da7438dffea3781f9228d6f322c6912631bb9a19 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 24 Oct 2010 20:00:20 +0000 Subject: LPC11xx DPI driver working, demo updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2286 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/main.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 3a5197207..70e8312ab 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -21,10 +21,14 @@ #include "hal.h" #include "test.h" +static void endsend(SPIDriver *spip) { + + spiUnselect(spip); +} /* Maximum speed SPI configuration (1MHz, CPHA=0, CPOL=0).*/ static SPIConfig spicfg = { - NULL, + endsend, GPIO1, GPIO1_SPI0SEL, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), @@ -40,6 +44,7 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { + spiSelect(&SPID1); spiStartSend(&SPID1, 1, &digit); digit++; palClearPad(GPIO0, GPIO0_LED2); -- cgit v1.2.3 From 63b9ef1051977ed1272df94915a2fd3fa4318aa0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 25 Oct 2010 17:02:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2290 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/main.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 70e8312ab..046ac6fe6 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -21,6 +21,18 @@ #include "hal.h" #include "test.h" +/* + * Conversion table from hex digit to 7 segments encoding, bit 5 controls the + * dot. + * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. + */ +static uint8_t digits[32] = { + 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, + 0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71, + 0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87, + 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 +}; + static void endsend(SPIDriver *spip) { spiUnselect(spip); @@ -40,17 +52,19 @@ static SPIConfig spicfg = { */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { - uint8_t digit = 0; + uint8_t i = 0; (void)arg; while (TRUE) { spiSelect(&SPID1); - spiStartSend(&SPID1, 1, &digit); - digit++; + spiStartSend(&SPID1, 1, &digits[i]); palClearPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiStartSend(&SPID1, 1, &digits[i | 0x10]); palSetPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); + i = (i + 1) & 15; } return 0; } -- cgit v1.2.3 From 3ea83706512a5051a185ac8ec4ba0094290a217d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 28 Oct 2010 18:39:40 +0000 Subject: LPC13xx SPI driver. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2300 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-LPC1343-GCC/halconf.h | 2 +- demos/ARMCM3-LPC1343-GCC/main.c | 37 +++++++++++++++++++++++++++++++++++-- 2 files changed, 36 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-LPC1343-GCC/halconf.h b/demos/ARMCM3-LPC1343-GCC/halconf.h index 87d0f835d..2c3afda84 100644 --- a/demos/ARMCM3-LPC1343-GCC/halconf.h +++ b/demos/ARMCM3-LPC1343-GCC/halconf.h @@ -130,7 +130,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#define CH_HAL_USE_SPI TRUE #endif /* diff --git a/demos/ARMCM3-LPC1343-GCC/main.c b/demos/ARMCM3-LPC1343-GCC/main.c index 45496acfc..092cecdbb 100644 --- a/demos/ARMCM3-LPC1343-GCC/main.c +++ b/demos/ARMCM3-LPC1343-GCC/main.c @@ -21,18 +21,50 @@ #include "hal.h" #include "test.h" +/* + * Conversion table from hex digit to 7 segments encoding, bit 5 controls the + * dot. + * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. + */ +static uint8_t digits[32] = { + 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, + 0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71, + 0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87, + 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 +}; + +static void endsend(SPIDriver *spip) { + + spiUnselect(spip); +} + +/* Maximum speed SPI configuration (1MHz, CPHA=0, CPOL=0).*/ +static SPIConfig spicfg = { + endsend, + GPIO1, + GPIO1_SPI0SEL, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 72 +}; + /* * Red LED blinker thread, times are in milliseconds. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + uint8_t i = 0; (void)arg; while (TRUE) { + spiSelect(&SPID1); + spiStartSend(&SPID1, 1, &digits[i]); palClearPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiStartSend(&SPID1, 1, &digits[i | 0x10]); palSetPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); + i = (i + 1) & 15; } return 0; } @@ -78,9 +110,10 @@ int main(int argc, char **argv) { (void)argv; /* - * Activates the serial driver 1 using the driver default configuration. + * Activates the SD1 and SPI1 drivers. */ - sdStart(&SD1, NULL); + sdStart(&SD1, NULL); /* Default: 38400,8,N,1. */ + spiStart(&SPID1, &spicfg); /* * Creates the blinker threads. -- cgit v1.2.3 From a884e58e2cea877f804cb643d4d1e0909bd1fa49 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 30 Oct 2010 11:18:28 +0000 Subject: Added a polled exchange function to the SPI driver model, implemented on LPCxxxx SPI drivers. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2302 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/main.c | 2 -- demos/ARMCM0-LPC1114-GCC/main.c | 29 ++++++++++++++--------------- demos/ARMCM3-LPC1343-GCC/main.c | 27 +++++++++++++-------------- 3 files changed, 27 insertions(+), 31 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c index 92c4563e0..ffe50af6a 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -47,7 +47,6 @@ static SPIConfig hs_spicfg = { IOPORT1, PA_SSEL1, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), - 0, 2 }; @@ -57,7 +56,6 @@ static SPIConfig ls_spicfg = { IOPORT1, PA_SSEL1, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), - 0, 254 }; diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 046ac6fe6..61d48003f 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -24,7 +24,7 @@ /* * Conversion table from hex digit to 7 segments encoding, bit 5 controls the * dot. - * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. + * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. */ static uint8_t digits[32] = { 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, @@ -33,14 +33,9 @@ static uint8_t digits[32] = { 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 }; -static void endsend(SPIDriver *spip) { - - spiUnselect(spip); -} - /* Maximum speed SPI configuration (1MHz, CPHA=0, CPOL=0).*/ static SPIConfig spicfg = { - endsend, + NULL, GPIO1, GPIO1_SPI0SEL, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), @@ -52,19 +47,13 @@ static SPIConfig spicfg = { */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { - uint8_t i = 0; (void)arg; while (TRUE) { - spiSelect(&SPID1); - spiStartSend(&SPID1, 1, &digits[i]); palClearPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); - spiSelect(&SPID1); - spiStartSend(&SPID1, 1, &digits[i | 0x10]); palSetPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); - i = (i + 1) & 15; } return 0; } @@ -105,6 +94,7 @@ static msg_t Thread2(void *arg) { * on entry. */ int main(int argc, char **argv) { + uint8_t i; (void)argc; (void)argv; @@ -122,13 +112,22 @@ int main(int argc, char **argv) { chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. + * Normal main() thread activity, in this demo it updates the 7-segments + * display on the LPCXpresso main board using the SPI driver. */ + i = 0; while (TRUE) { if (!palReadPad(GPIO0, GPIO0_SW3)) TestThread(&SD1); + spiSelect(&SPID1); + spiSend(&SPID1, 1, &digits[i]); /* Non polled method. */ + spiUnselect(&SPID1); chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiPolledExchange(&SPID1, digits[i | 0x10]); /* Polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + i = (i + 1) & 15; } return 0; } diff --git a/demos/ARMCM3-LPC1343-GCC/main.c b/demos/ARMCM3-LPC1343-GCC/main.c index 092cecdbb..a645bf3d2 100644 --- a/demos/ARMCM3-LPC1343-GCC/main.c +++ b/demos/ARMCM3-LPC1343-GCC/main.c @@ -33,14 +33,9 @@ static uint8_t digits[32] = { 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 }; -static void endsend(SPIDriver *spip) { - - spiUnselect(spip); -} - /* Maximum speed SPI configuration (1MHz, CPHA=0, CPOL=0).*/ static SPIConfig spicfg = { - endsend, + NULL, GPIO1, GPIO1_SPI0SEL, CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), @@ -52,19 +47,13 @@ static SPIConfig spicfg = { */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { - uint8_t i = 0; (void)arg; while (TRUE) { - spiSelect(&SPID1); - spiStartSend(&SPID1, 1, &digits[i]); palClearPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); - spiSelect(&SPID1); - spiStartSend(&SPID1, 1, &digits[i | 0x10]); palSetPad(GPIO0, GPIO0_LED2); chThdSleepMilliseconds(500); - i = (i + 1) & 15; } return 0; } @@ -105,6 +94,7 @@ static msg_t Thread2(void *arg) { * on entry. */ int main(int argc, char **argv) { + uint8_t i; (void)argc; (void)argv; @@ -122,13 +112,22 @@ int main(int argc, char **argv) { chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); /* - * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. + * Normal main() thread activity, in this demo it updates the 7-segments + * display on the LPCXpresso main board using the SPI driver. */ + i = 0; while (TRUE) { if (!palReadPad(GPIO0, GPIO0_SW3)) TestThread(&SD1); + spiSelect(&SPID1); + spiSend(&SPID1, 1, &digits[i]); /* Non polled method. */ + spiUnselect(&SPID1); chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiPolledExchange(&SPID1, digits[i | 0x10]); /* Polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + i = (i + 1) & 15; } return 0; } -- cgit v1.2.3 From 35d05f85d17de7ebd5cad4638ecd92d91e5be9aa Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 31 Oct 2010 07:36:07 +0000 Subject: Updated reports. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2309 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/halconf.h | 10 ---------- demos/AVR-ATmega128-GCC/halconf.h | 10 ---------- 2 files changed, 20 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index f81870b13..de9c05fdf 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -62,11 +62,6 @@ #define CH_HAL_USE_ADC FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). - */ -/*#define ADC_USE_WAIT TRUE*/ - /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -78,11 +73,6 @@ #define CH_HAL_USE_CAN FALSE #endif -/* - * Default CAN settings overrides (uncomment to override). - */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ - /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index f81870b13..de9c05fdf 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -62,11 +62,6 @@ #define CH_HAL_USE_ADC FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). - */ -/*#define ADC_USE_WAIT TRUE*/ - /*===========================================================================*/ /* CAN driver related settings. */ /*===========================================================================*/ @@ -78,11 +73,6 @@ #define CH_HAL_USE_CAN FALSE #endif -/* - * Default CAN settings overrides (uncomment to override). - */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ - /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ -- cgit v1.2.3 From a9753ea48ac394028762b6a3fa9812e0092bb08e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Nov 2010 10:23:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2317 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S208-RC/ch.rapp | 57 +++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 28 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 3573b8505..d5438c30b 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -10,15 +10,15 @@
- +
- + - + - + - + @@ -30,7 +30,7 @@ - + @@ -41,17 +41,17 @@
- +
- + - + - + - + - + @@ -66,11 +66,11 @@ - + - + @@ -85,11 +85,12 @@ - + + - + - + @@ -97,21 +98,21 @@
- +
- +
- +
- +
@@ -122,33 +123,33 @@
- +
- +
- +
- +
- +
- +
- + -- cgit v1.2.3 From 5da56bd07fca28900f9a53c51312be46d759e1d2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Nov 2010 10:53:18 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2318 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c | 9 +++++++-- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h | 18 ++++++++++++------ 2 files changed, 19 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c index 6ede94a3e..e9a5ad450 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c @@ -29,6 +29,7 @@ typedef void @far @interrupt (*interrupt_handler_t)(void); * Various external symbols. */ void _stext(void); +@far @interrupt void vector10(void); @far @interrupt void vector13(void); @far @interrupt void vector17(void); @far @interrupt void vector18(void); @@ -68,14 +69,18 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector7 */ {0x82, vector}, /* vector8 */ {0x82, vector}, /* vector9 */ +#if CH_HAL_USE_SPI && STM8_SPI_USE_SPI + {0x82, vector10}, +#else {0x82, vector}, /* vector10 */ +#endif {0x82, vector}, /* vector11 */ {0x82, vector}, /* vector12 */ {0x82, vector13}, /* vector13 */ {0x82, vector}, /* vector14 */ {0x82, vector}, /* vector15 */ {0x82, vector}, /* vector16 */ -#if USE_STM8_UART1 +#if CH_HAL_USE_SERIAL && STM8_SERIAL_USE_UART1 {0x82, vector17}, /* vector17 */ {0x82, vector18}, /* vector18 */ #else @@ -83,7 +88,7 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector18 */ #endif {0x82, vector}, /* vector19 */ -#if USE_STM8_UART2 || USE_STM8_UART3 +#if CH_HAL_USE_SERIAL && (STM8_SERIAL_USE_UART2 || STM8_SERIAL_USE_UART3) {0x82, vector20}, /* vector20 */ {0x82, vector21}, /* vector21 */ #else diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h index cf2ebd963..70aae8849 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h @@ -28,13 +28,19 @@ /* * HAL general settings. */ -#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI -#define STM8_HSI_DIVIDER CLK_HSI_DIV1 -#define STM8_CPU_DIVIDER CLK_CPU_DIV1 +#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI +#define STM8_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8_CPU_DIVIDER CLK_CPU_DIV1 /* * SERIAL driver system settings. */ -#define USE_STM8_UART1 FALSE -#define USE_STM8_UART2 TRUE -#define USE_STM8_UART3 FALSE +#define STM8_SERIAL_USE_UART1 FALSE +#define STM8_SERIAL_USE_UART2 TRUE +#define STM8_SERIAL_USE_UART3 FALSE + +/* + * SPI driver system settings. + */ +#define STM8_SPI_USE_SPI TRUE +#define STM8_SPI_ERROR_HOOK(spip) chSysHalt() -- cgit v1.2.3 From 38acf6953fa4221a1fa7f43d78bfb94402fc8f48 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Nov 2010 10:54:05 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2319 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp | 14 ++++++++++++-- .../raisonance/raisonance.stp | 14 ++++++++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index bdf62f54f..76cd87427 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -509,7 +509,12 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\spi_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c] ElemType=File @@ -1905,7 +1910,12 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h] ElemType=File diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index fd48997a1..254953e80 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -530,7 +530,12 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\spi_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c] ElemType=File @@ -1926,7 +1931,12 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h] ElemType=File -- cgit v1.2.3 From e19a2021c8c3b8d995f501d4ff417a0162138718 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Nov 2010 15:08:29 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2322 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile index 4fd0a9379..c74d12ab6 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile @@ -5,7 +5,7 @@ # Compiler options here. ifeq ($(USE_OPT),) - USE_OPT = -O0 -ggdb -fomit-frame-pointer -mabi=apcs-gnu + USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu endif # C++ specific options here (added to USE_OPT). -- cgit v1.2.3 From cdb04bd4815f8348a008da9ab765d191371312e0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Nov 2010 16:06:22 +0000 Subject: Fixed bug 3100901. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2323 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c index 8065a6b61..3c58e266a 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/lwip/lwipthread.c @@ -264,7 +264,7 @@ msg_t lwip_thread(void *p) { evtStart(&evt); chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID); chEvtRegisterMask(macGetReceiveEventSource(Ð1), &el1, FRAME_RECEIVED_ID); - chEvtPend(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); + chEvtAddFlags(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); /* Goes to the final priority after initialization.*/ chThdSetPriority(LWIP_THREAD_PRIORITY); -- cgit v1.2.3 From 24b7b8c7f8480189685e7a23c04981676a040239 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Nov 2010 16:12:09 +0000 Subject: Fixed bug 3100901 on uIP demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2324 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c index bbf08b820..4d0516c2c 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/web/webthread.c @@ -152,7 +152,7 @@ msg_t WebThread(void *p) { * Event sources setup. */ chEvtRegister(macGetReceiveEventSource(Ð1), &el0, FRAME_RECEIVED_ID); - chEvtPend(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ + chEvtAddFlags(EVENT_MASK(FRAME_RECEIVED_ID)); /* In case some frames are already buffered */ evtInit(&evt1, MS2ST(500)); evtStart(&evt1); -- cgit v1.2.3 From d8be44136c1e6d02ee105ac0791f9e6732551fec Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 1 Nov 2010 17:29:56 +0000 Subject: Fixed bug 3100946, renamed HAL switches removing the CH_ part. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2326 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 232 ++++++++++++++------- demos/ARM7-AT91SAM7S-GCC/halconf.h | 232 ++++++++++++++------- demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 232 ++++++++++++++------- demos/ARM7-AT91SAM7X-GCC/halconf.h | 232 ++++++++++++++------- demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 232 ++++++++++++++------- demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 232 ++++++++++++++------- demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 232 ++++++++++++++------- demos/ARM7-LPC214x-G++/halconf.h | 232 ++++++++++++++------- demos/ARM7-LPC214x-GCC/halconf.h | 232 ++++++++++++++------- demos/ARMCM0-LPC1114-GCC/halconf.h | 232 ++++++++++++++------- demos/ARMCM3-LPC1343-GCC/halconf.h | 232 ++++++++++++++------- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 232 ++++++++++++++------- demos/ARMCM3-STM32F103-GCC/halconf.h | 228 ++++++++++++++------ demos/ARMCM3-STM32F107-GCC/halconf.h | 232 ++++++++++++++------- demos/AVR-AT90CANx-GCC/halconf.h | 228 ++++++++++++++------ demos/AVR-ATmega128-GCC/halconf.h | 228 ++++++++++++++------ demos/MSP430-MSP430x1611-GCC/halconf.h | 232 ++++++++++++++------- demos/PPC-SPC563-GCC/halconf.h | 232 ++++++++++++++------- demos/Posix-GCC/halconf.h | 232 ++++++++++++++------- .../STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c | 6 +- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 232 ++++++++++++++------- demos/STM8S-STM8S208-RC/halconf.h | 232 ++++++++++++++------- demos/Win32-MinGW/halconf.h | 232 ++++++++++++++------- 23 files changed, 3554 insertions(+), 1544 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index c65522e3a..bc6c3b8d2 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index 87d0f835d..3186be527 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index c65522e3a..bc6c3b8d2 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index 87d0f835d..3186be527 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 0fdc6cf1c..3ccb9a219 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC TRUE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 0fdc6cf1c..3ccb9a219 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC TRUE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC TRUE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index c65522e3a..bc6c3b8d2 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index 87d0f835d..3186be527 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index 87d0f835d..3186be527 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h index 2c3afda84..9ed9ce905 100644 --- a/demos/ARMCM0-LPC1114-GCC/halconf.h +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-LPC1343-GCC/halconf.h b/demos/ARMCM3-LPC1343-GCC/halconf.h index 2c3afda84..9ed9ce905 100644 --- a/demos/ARMCM3-LPC1343-GCC/halconf.h +++ b/demos/ARMCM3-LPC1343-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index c65522e3a..bc6c3b8d2 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI TRUE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI TRUE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index a9d7369b9..3186be527 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -18,37 +18,93 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the SPI subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE #endif /*===========================================================================*/ @@ -56,10 +112,19 @@ /*===========================================================================*/ /** - * @brief Enables the ADC subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ @@ -67,97 +132,132 @@ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif /** - * @brief Enables the SERIAL subsystem. + * @brief Number of positive insertion queries before generating the + * insertion event. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Interval, in milliseconds, between insertion queries. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ /* UART driver related settings. */ /*===========================================================================*/ -/** - * @brief Enables the UART subsystem. - */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE -#endif - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/ARMCM3-STM32F107-GCC/halconf.h b/demos/ARMCM3-STM32F107-GCC/halconf.h index 87d0f835d..3186be527 100644 --- a/demos/ARMCM3-STM32F107-GCC/halconf.h +++ b/demos/ARMCM3-STM32F107-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index de9c05fdf..2eea483f4 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -18,37 +18,93 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the CAN subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE #endif /*===========================================================================*/ @@ -56,10 +112,19 @@ /*===========================================================================*/ /** - * @brief Enables the ADC subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ @@ -67,97 +132,132 @@ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif /** - * @brief Enables the SERIAL subsystem. + * @brief Number of positive insertion queries before generating the + * insertion event. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Interval, in milliseconds, between insertion queries. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -#define SERIAL_BUFFERS_SIZE 16 +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ /* UART driver related settings. */ /*===========================================================================*/ -/** - * @brief Enables the UART subsystem. - */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE -#endif - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index de9c05fdf..2eea483f4 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -18,37 +18,93 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL FALSE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the CAN subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE #endif /*===========================================================================*/ @@ -56,10 +112,19 @@ /*===========================================================================*/ /** - * @brief Enables the ADC subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ @@ -67,97 +132,132 @@ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif /** - * @brief Enables the SERIAL subsystem. + * @brief Number of positive insertion queries before generating the + * insertion event. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Interval, in milliseconds, between insertion queries. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -#define SERIAL_BUFFERS_SIZE 16 +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ /* UART driver related settings. */ /*===========================================================================*/ -/** - * @brief Enables the UART subsystem. - */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE -#endif - #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index 87d0f835d..3186be527 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index 6e16e85a6..64a634d85 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ /*#include "mcuconf.h"*/ -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL FALSE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL FALSE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index 6976d598e..acc98744c 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ /*#include "mcuconf.h"*/ -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c index e9a5ad450..76ebd1736 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c @@ -69,7 +69,7 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector7 */ {0x82, vector}, /* vector8 */ {0x82, vector}, /* vector9 */ -#if CH_HAL_USE_SPI && STM8_SPI_USE_SPI +#if HAL_USE_SPI && STM8_SPI_USE_SPI {0x82, vector10}, #else {0x82, vector}, /* vector10 */ @@ -80,7 +80,7 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector14 */ {0x82, vector}, /* vector15 */ {0x82, vector}, /* vector16 */ -#if CH_HAL_USE_SERIAL && STM8_SERIAL_USE_UART1 +#if HAL_USE_SERIAL && STM8_SERIAL_USE_UART1 {0x82, vector17}, /* vector17 */ {0x82, vector18}, /* vector18 */ #else @@ -88,7 +88,7 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector18 */ #endif {0x82, vector}, /* vector19 */ -#if CH_HAL_USE_SERIAL && (STM8_SERIAL_USE_UART2 || STM8_SERIAL_USE_UART3) +#if HAL_USE_SERIAL && (STM8_SERIAL_USE_UART2 || STM8_SERIAL_USE_UART3) {0x82, vector20}, /* vector20 */ {0x82, vector21}, /* vector21 */ #else diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index b0b87601a..3186be527 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -#define SERIAL_BUFFERS_SIZE 16 +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index 87d0f835d..3186be527 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ #include "mcuconf.h" -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index 6976d598e..acc98744c 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -18,156 +18,246 @@ */ /** - * @file templates/halconf.h - * @brief HAL configuration header. + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * * @addtogroup HAL_CONF * @{ */ /* - * HAL configuration file, this file allows to enable or disable the various - * device drivers from your application. You may also use this file in order - * to override the device drivers default settings. + * */ #ifndef _HALCONF_H_ #define _HALCONF_H_ -/* - * Uncomment the following line in order to include a mcu-related - * settings file. This file can be used to include platform specific - * header files or to override the low level drivers settings. - */ /*#include "mcuconf.h"*/ -/*===========================================================================*/ -/* PAL driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif /** - * @brief Enables the PAL subsystem. + * @brief Enables the ADC subsystem. */ -#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_PAL TRUE +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE #endif -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif /** - * @brief Enables the ADC subsystem. + * @brief Enables the I2C subsystem. */ -#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__) -#define CH_HAL_USE_ADC FALSE +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE #endif -/* - * Default ADC settings overrides (uncomment to override). +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. */ -/*#define ADC_USE_WAIT TRUE*/ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif /*===========================================================================*/ -/* CAN driver related settings. */ +/* ADC driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the CAN subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__) -#define CH_HAL_USE_CAN FALSE +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE #endif -/* - * Default CAN settings overrides (uncomment to override). +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. */ -/*#define CAN_USE_SLEEP_MODE TRUE*/ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif /*===========================================================================*/ -/* MAC driver related settings. */ +/* CAN driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MAC subsystem. + * @brief Sleep mode related APIs inclusion switch. */ -#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__) -#define CH_HAL_USE_MAC FALSE +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE #endif /*===========================================================================*/ -/* PWM driver related settings. */ +/* I2C driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the PWM subsystem. + * @brief Enables the mutual exclusion APIs on the I2C bus. */ -#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__) -#define CH_HAL_USE_PWM FALSE +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE #endif /*===========================================================================*/ -/* SERIAL driver related settings. */ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the SERIAL subsystem. + * @brief Block size for MMC transfers. */ -#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define CH_HAL_USE_SERIAL TRUE +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 #endif -/* - * Default SERIAL settings overrides (uncomment to override). +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. */ -/*#define SERIAL_DEFAULT_BITRATE 38400*/ -/*#define SERIAL_BUFFERS_SIZE 64*/ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif /** - * @brief Enables the SPI subsystem. + * @brief Interval, in milliseconds, between insertion queries. */ -#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_SPI FALSE +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 #endif -/* - * Default SPI settings overrides (uncomment to override). +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. */ -/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif /*===========================================================================*/ -/* MMC_SPI driver related settings. */ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the MMC_SPI subsystem. + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. */ -#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define CH_HAL_USE_MMC_SPI FALSE +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 #endif -/* - * Default MMC_SPI settings overrides (uncomment to override). +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. */ -/*#define MMC_SECTOR_SIZE 512*/ -/*#define MMC_NICE_WAITING TRUE*/ -/*#define MMC_POLLING_INTERVAL 10*/ -/*#define MMC_POLLING_DELAY 10*/ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif /*===========================================================================*/ -/* UART driver related settings. */ +/* SPI driver related settings. */ /*===========================================================================*/ /** - * @brief Enables the UART subsystem. + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. */ -#if !defined(CH_HAL_USE_UART) || defined(__DOXYGEN__) -#define CH_HAL_USE_UART FALSE +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE #endif +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + #endif /* _HALCONF_H_ */ /** @} */ -- cgit v1.2.3 From c922ada20f99517c4cb98118b954c9b1182fce2c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Nov 2010 10:02:07 +0000 Subject: Changes to the various Cortex vector tables. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2328 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- demos/ARMCM3-STM32F107-GCC/Makefile | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 8926ccbfc..7cdfe1e96 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -104,7 +104,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors_md.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index bf9247aba..33e4c838b 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors_md.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ @@ -128,7 +128,7 @@ CPPC = $(TRGT)g++ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy -AS = $(TRGT)gcc -x assembler-with-cpp +AS = $(TRGT)gcc OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary diff --git a/demos/ARMCM3-STM32F107-GCC/Makefile b/demos/ARMCM3-STM32F107-GCC/Makefile index c199576c6..9ad48509b 100644 --- a/demos/ARMCM3-STM32F107-GCC/Makefile +++ b/demos/ARMCM3-STM32F107-GCC/Makefile @@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors_cl.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From cf83a936139998a892f5e1063563eca3fe6525c3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Nov 2010 10:12:19 +0000 Subject: Improvements to the ARMCMx directories structure organization. Adjusted the affected makefiles (STM32 demos only). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2330 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 4 ++-- demos/ARMCM3-STM32F103-GCC/Makefile | 4 ++-- demos/ARMCM3-STM32F107-GCC/Makefile | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 7cdfe1e96..56fc2d719 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/ext/fatfs/fatfs.mk @@ -104,7 +104,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors_md.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors_md.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 33e4c838b..e4c34fadb 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors_md.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors_md.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-STM32F107-GCC/Makefile b/demos/ARMCM3-STM32F107-GCC/Makefile index 9ad48509b..647bdd3ce 100644 --- a/demos/ARMCM3-STM32F107-GCC/Makefile +++ b/demos/ARMCM3-STM32F107-GCC/Makefile @@ -60,7 +60,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/ST_STM3210C_EVAL/board.mk include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -102,7 +102,7 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/vectors_cl.s + $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors_cl.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From c7dab5762e8cdd914568e05bf85209bfbbaef639 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Nov 2010 10:27:34 +0000 Subject: Restored RIDE7 build files in the STM32F103 demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2332 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp | 163 ++++++++++++++++--------------- demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj | 4 +- 2 files changed, 84 insertions(+), 83 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp b/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp index 3dbacd826..e72957e50 100644 --- a/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp +++ b/demos/ARMCM3-STM32F103-GCC/ride7/ch.rapp @@ -1,103 +1,104 @@ - - - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - + - - - + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - +
- +
- + - +
- +
- - + +
- +
- +
@@ -105,34 +106,34 @@
- +
- +
- +
- +
- +
- +
- +
- + diff --git a/demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj b/demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj index 77591474e..d9f866c84 100644 --- a/demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj +++ b/demos/ARMCM3-STM32F103-GCC/ride7/ch.rprj @@ -1,4 +1,4 @@ - - + + \ No newline at end of file -- cgit v1.2.3 From ab3e17547f9cb49a7b78aca9da76de8556e1d6f0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Nov 2010 10:33:49 +0000 Subject: Fixed code:blocks STM32F103 project example. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2333 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp b/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp index 82c5f1179..b3bffac75 100644 --- a/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp +++ b/demos/ARMCM3-STM32F103-GCC/codeblocks/ch/ch.cbp @@ -42,11 +42,11 @@ - + + - @@ -224,10 +224,8 @@ - - - + + @@ -238,9 +236,7 @@ - - + -- cgit v1.2.3 From 260455d2d211db86713fbe6a1327be036dd637cf Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 6 Nov 2010 11:32:45 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2334 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index e4c34fadb..28a353c37 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -128,7 +128,7 @@ CPPC = $(TRGT)g++ LD = $(TRGT)gcc #LD = $(TRGT)g++ CP = $(TRGT)objcopy -AS = $(TRGT)gcc +AS = $(TRGT)gcc -x assembler-with-cpp OD = $(TRGT)objdump HEX = $(CP) -O ihex BIN = $(CP) -O binary -- cgit v1.2.3 From 5bc4fc844bceb9e16027edd3c67dfd58fdca6106 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 10 Nov 2010 19:03:28 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2342 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h index 70aae8849..757bba2ce 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h @@ -42,5 +42,5 @@ /* * SPI driver system settings. */ -#define STM8_SPI_USE_SPI TRUE +#define STM8_SPI_USE_SPI FALSE #define STM8_SPI_ERROR_HOOK(spip) chSysHalt() -- cgit v1.2.3 From c48b251d9100586a4a606ae5da65a43f7b6ee9d6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 10 Nov 2010 19:15:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2343 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw | 16 + .../cosmic/cosmic.stp | 2135 +++++++++++++++++++ .../STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c | 106 + demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h | 507 +++++ demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 263 +++ demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 75 + demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h | 46 + .../raisonance/raisonance.stp | 2156 ++++++++++++++++++++ 8 files changed, 5304 insertions(+) create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h create mode 100644 demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw new file mode 100644 index 000000000..a6630271a --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw @@ -0,0 +1,16 @@ +; STMicroelectronics Workspace file + +[Version] +Keyword=ST7Workspace-V0.7 + +[Project0] +Filename=cosmic\cosmic.stp +Dependencies= + +[Project1] +Filename=raisonance\raisonance.stp +Dependencies= +[Options] +ActiveProject=cosmic +ActiveConfig=Release +AddSortedElements=0 diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp new file mode 100644 index 000000000..76cd87427 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -0,0 +1,2135 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=cosmic +Toolset=STM8 Cosmic + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=cosmic +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,3,15,59,36 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=STM8 Cosmic +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.103.0= +String.104.0=Hstm8 +String.105.0=Lib +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,5,25,14,45,56 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,5,25,14,45,56 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,26,17,30,51 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,5,25,14,45,56 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv 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Files\test...\..\..\test\testqueues.h] +ElemType=File +PathName=..\..\..\test\testqueues.h +Next=Root.Include Files.Include Files\test...\..\..\test\testsem.h + +[Root.Include Files.Include Files\test...\..\..\test\testsem.h] +ElemType=File +PathName=..\..\..\test\testsem.h +Next=Root.Include Files.Include Files\test...\..\..\test\testthd.h + +[Root.Include Files.Include Files\test...\..\..\test\testthd.h] +ElemType=File +PathName=..\..\..\test\testthd.h \ No newline at end of file diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c new file mode 100644 index 000000000..76ebd1736 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c @@ -0,0 +1,106 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief Exception handler type. + */ +typedef void @far @interrupt (*interrupt_handler_t)(void); + +/* + * Various external symbols. + */ +void _stext(void); +@far @interrupt void vector10(void); +@far @interrupt void vector13(void); +@far @interrupt void vector17(void); +@far @interrupt void vector18(void); +@far @interrupt void vector20(void); +@far @interrupt void vector21(void); + +/** + * @brief Exception vector type. + */ +typedef struct { + uint8_t ev_instruction; + interrupt_handler_t ev_handler; +} exception_vector_t; + +/** + * @brief Undefined interrupt handler. + * @note It should never be invoked. + */ +@far @interrupt static void vector (void) +{ + return; +} + +/** + * @brief Exceptions table. + */ +exception_vector_t const _vectab[] = { + {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, vector}, /* trap */ + {0x82, vector}, /* vector0 */ + {0x82, vector}, /* vector1 */ + {0x82, vector}, /* vector2 */ + {0x82, vector}, /* vector3 */ + {0x82, vector}, /* vector4 */ + {0x82, vector}, /* vector5 */ + {0x82, vector}, /* vector6 */ + {0x82, vector}, /* vector7 */ + {0x82, vector}, /* vector8 */ + {0x82, vector}, /* vector9 */ +#if HAL_USE_SPI && STM8_SPI_USE_SPI + {0x82, vector10}, +#else + {0x82, vector}, /* vector10 */ +#endif + {0x82, vector}, /* vector11 */ + {0x82, vector}, /* vector12 */ + {0x82, vector13}, /* vector13 */ + {0x82, vector}, /* vector14 */ + {0x82, vector}, /* vector15 */ + {0x82, vector}, /* vector16 */ +#if HAL_USE_SERIAL && STM8_SERIAL_USE_UART1 + {0x82, vector17}, /* vector17 */ + {0x82, vector18}, /* vector18 */ +#else + {0x82, vector}, /* vector17 */ + {0x82, vector}, /* vector18 */ +#endif + {0x82, vector}, /* vector19 */ +#if HAL_USE_SERIAL && (STM8_SERIAL_USE_UART2 || STM8_SERIAL_USE_UART3) + {0x82, vector20}, /* vector20 */ + {0x82, vector21}, /* vector21 */ +#else + {0x82, vector}, /* vector20 */ + {0x82, vector}, /* vector21 */ +#endif + {0x82, vector}, /* vector22 */ + {0x82, vector}, /* vector23 */ + {0x82, vector}, /* vector24 */ + {0x82, vector}, /* vector25 */ + {0x82, vector}, /* vector26 */ + {0x82, vector}, /* vector27 */ + {0x82, vector}, /* vector28 */ + {0x82, vector}, /* vector29 */ +}; diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h new file mode 100644 index 000000000..12b5c9e15 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h @@ -0,0 +1,507 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 100 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 10 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 128 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED FALSE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h new file mode 100644 index 000000000..3186be527 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -0,0 +1,263 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +/* + * + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c new file mode 100644 index 000000000..35321bf62 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -0,0 +1,75 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 64); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + palSetPad(GPIOD, PD_LD10); + chThdSleepMilliseconds(500); + } + return 0; +} + +/* + * Entry point. + */ +void main(void) { + + /* + * Board/HAL initialization. + */ + hwinit(); + + /* + * OS initialization. + */ + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity. + */ + while (TRUE) { + if (palReadPad(GPIOG, 0) == PAL_LOW) + TestThread(&SD2); + if (palReadPad(GPIOG, 1) == PAL_LOW) + sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE); + chThdSleepMilliseconds(1000); + } +} diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h new file mode 100644 index 000000000..a65191d1f --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h @@ -0,0 +1,46 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM8 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + */ + +/* + * HAL general settings. + */ +#define STM8L_CLOCK_INIT TRUE +#define STM8L_HSI_ENABLED TRUE +#define STM8L_LSI_ENABLED TRUE +#define STM8L_HSE_ENABLED FALSE +#define STM8L_LSE_ENABLED TRUE +#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI +#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1 +#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_LSE +#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1 + +/* + * SERIAL driver system settings. + */ +#define STM8L_SERIAL_USE_USART1 TRUE +#define STM8L_SERIAL_USE_USART2 FALSE +#define STM8K_SERIAL_USE_USART3 FALSE diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp new file mode 100644 index 000000000..254953e80 --- /dev/null +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -0,0 +1,2156 @@ +; STMicroelectronics Project file + +[Version] +Keyword=ST7Project +Number=1.3 + +[Project] +Name=raisonance +Toolset=Raisonance + +[Config] +0=Config.0 +1=Config.1 + +[Config.0] +ConfigName=Debug +Target=$(ProjectSFile).elf +OutputFolder=Debug +Debug=$(TargetFName) + +[Config.1] +ConfigName=Release +Target=$(ProjectSFile).elf +OutputFolder=Release +Debug=$(TargetFName) + +[Root] +ElemType=Project +PathName=raisonance +Child=Root.Source Files +Config.0=Root.Config.0 +Config.1=Root.Config.1 + +[Root.Config.0] +Settings.0.0=Root.Config.0.Settings.0 +Settings.0.1=Root.Config.0.Settings.1 +Settings.0.2=Root.Config.0.Settings.2 +Settings.0.3=Root.Config.0.Settings.3 +Settings.0.4=Root.Config.0.Settings.4 +Settings.0.5=Root.Config.0.Settings.5 +Settings.0.6=Root.Config.0.Settings.6 +Settings.0.7=Root.Config.0.Settings.7 +Settings.0.8=Root.Config.0.Settings.8 + +[Root.Config.1] +Settings.1.0=Root.Config.1.Settings.0 +Settings.1.1=Root.Config.1.Settings.1 +Settings.1.2=Root.Config.1.Settings.2 +Settings.1.3=Root.Config.1.Settings.3 +Settings.1.4=Root.Config.1.Settings.4 +Settings.1.5=Root.Config.1.Settings.5 +Settings.1.6=Root.Config.1.Settings.6 +Settings.1.7=Root.Config.1.Settings.7 +Settings.1.8=Root.Config.1.Settings.8 + +[Root.Config.0.Settings.0] +String.6.0=2010,6,4,10,30,46 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Debug +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.0.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; + +[Root.Config.0.Settings.2] +String.2.0= +String.6.0=2010,6,4,10,10,40 +String.100.0=STM8S105C6 + +[Root.Config.0.Settings.3] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Config.0.Settings.4] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Config.0.Settings.5] +String.2.0=Running Pre-Link step +String.6.0=2010,6,4,10,10,40 +String.8.0= + +[Root.Config.0.Settings.6] +String.2.0=Running Linker +String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] DEBUGLINES DEBUGPUBLICS DEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) +String.3.1=omf2elf $(OutputPath)$(TargetSName).aof +String.4.0=$(OutputPath)$(TargetFName) +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,6,4,12,15,0 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.0.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.0.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.0] +String.6.0=2010,6,4,11,25,50 +String.100.0=ST Assembler Linker +String.100.1=ST7 Cosmic +String.100.2=STM8 Cosmic +String.100.3=ST7 Metrowerks V1.1 +String.100.4=Raisonance +String.101.0=Raisonance +String.102.0=C:\Programmi\Raisonance\Ride +String.103.0=bin +String.104.0=INC\ST7;INC +String.105.0=LIB\ST7 +String.106.0=Release +String.107.0=$(ProjectSFile).elf +Int.108=0 + +[Root.Config.1.Settings.1] +String.6.0=2010,6,4,10,10,40 +String.100.0=$(TargetFName) +String.101.0= +String.102.0= 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CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.101.0= +String.102.0= +Int.0=0 +Int.1=0 + +[Root.Config.1.Settings.7] +String.2.0=Running Post-Build step +String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX +String.6.0=2010,6,4,10,10,40 + +[Root.Config.1.Settings.8] +String.2.0=Performing Custom Build on $(InputFile) +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files] +ElemType=Folder +PathName=Source Files +Child=Root.Source Files...\demo\main.c +Next=Root.Include Files +Config.0=Root.Source Files.Config.0 +Config.1=Root.Source Files.Config.1 + +[Root.Source Files.Config.0] +Settings.0.0=Root.Source Files.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Config.0.Settings.3 + +[Root.Source Files.Config.1] +Settings.1.0=Root.Source Files.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Config.1.Settings.3 + +[Root.Source Files.Config.0.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c] +ElemType=File +PathName=..\demo\main.c +Next=Root.Source Files.Source Files\board +Config.0=Root.Source Files...\demo\main.c.Config.0 +Config.1=Root.Source Files...\demo\main.c.Config.1 + +[Root.Source Files...\demo\main.c.Config.0] +Settings.0.0=Root.Source Files...\demo\main.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files...\demo\main.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files...\demo\main.c.Config.0.Settings.2 + +[Root.Source Files...\demo\main.c.Config.1] +Settings.1.0=Root.Source Files...\demo\main.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files...\demo\main.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files...\demo\main.c.Config.1.Settings.2 + +[Root.Source Files...\demo\main.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,12,31 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files...\demo\main.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,12,31 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files...\demo\main.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\board] +ElemType=Folder +PathName=Source Files\board +Child=Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c +Next=Root.Source Files.Source Files\os +Config.0=Root.Source Files.Source Files\board.Config.0 +Config.1=Root.Source Files.Source Files\board.Config.1 + +[Root.Source Files.Source Files\board.Config.0] +Settings.0.0=Root.Source Files.Source Files\board.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\board.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\board.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\board.Config.0.Settings.3 + +[Root.Source Files.Source Files\board.Config.1] +Settings.1.0=Root.Source Files.Source Files\board.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\board.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\board.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\board.Config.1.Settings.3 + +[Root.Source Files.Source Files\board.Config.0.Settings.0] +String.6.0=2010,6,4,10,11,42 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\board.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\board.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board.Config.1.Settings.0] +String.6.0=2010,6,4,10,11,42 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\board.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\board.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c] +ElemType=File +PathName=..\..\..\boards\st_stm8s_discovery\board.c + +[Root.Source Files.Source Files\os] +ElemType=Folder +PathName=Source Files\os +Child=Root.Source Files.Source Files\os.Source Files\os\hal +Next=Root.Source Files.Source Files\test + +[Root.Source Files.Source Files\os.Source Files\os\hal] +ElemType=Folder +PathName=Source Files\os\hal +Child=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0] +String.6.0=2010,6,4,10,13,32 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0] +String.6.0=2010,6,4,10,13,32 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst 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Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,30 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,30 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chregistry.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,29 +String.8.0=Debug +Int.0=0 +Int.1=0 + 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Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,29 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chqueues.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,29 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,29 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmtx.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmsg.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmempools.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmemcore.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Debug +Int.0=0 +Int.1=0 + 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Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) 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Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + 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Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chlists.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1] 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OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chheap.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chevents.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\port] +ElemType=Folder +PathName=Source Files\os\port +Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.c + +[Root.Source Files.Source Files\test] +ElemType=Folder +PathName=Source Files\test +Child=Root.Source Files.Source Files\test...\..\..\test\testthd.c +Config.0=Root.Source Files.Source Files\test.Config.0 +Config.1=Root.Source Files.Source Files\test.Config.1 + +[Root.Source Files.Source Files\test.Config.0] +Settings.0.0=Root.Source Files.Source Files\test.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\test.Config.0.Settings.3 + +[Root.Source Files.Source Files\test.Config.1] +Settings.1.0=Root.Source Files.Source Files\test.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\test.Config.1.Settings.3 + +[Root.Source Files.Source Files\test.Config.0.Settings.0] +String.6.0=2010,6,4,10,11,52 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\test.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\test.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test.Config.1.Settings.0] +String.6.0=2010,6,4,10,11,52 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c] +ElemType=File +PathName=..\..\..\test\testthd.c +Next=Root.Source Files.Source Files\test...\..\..\test\testsem.c + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c] +ElemType=File +PathName=..\..\..\test\testsem.c +Next=Root.Source Files.Source Files\test...\..\..\test\testqueues.c + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c] +ElemType=File +PathName=..\..\..\test\testqueues.c +Next=Root.Source Files.Source Files\test...\..\..\test\testpools.c + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c] +ElemType=File +PathName=..\..\..\test\testpools.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmtx.c + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c] +ElemType=File +PathName=..\..\..\test\testmtx.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmsg.c + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c] +ElemType=File +PathName=..\..\..\test\testmsg.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmbox.c + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c] +ElemType=File +PathName=..\..\..\test\testmbox.c +Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c + +[Root.Source Files.Source Files\test...\..\..\test\testheap.c] +ElemType=File +PathName=..\..\..\test\testheap.c +Next=Root.Source Files.Source Files\test...\..\..\test\testevt.c + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c] +ElemType=File +PathName=..\..\..\test\testevt.c +Next=Root.Source Files.Source Files\test...\..\..\test\testdyn.c + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c] +ElemType=File +PathName=..\..\..\test\testdyn.c +Next=Root.Source Files.Source Files\test...\..\..\test\testbmk.c + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c] +ElemType=File +PathName=..\..\..\test\testbmk.c +Next=Root.Source Files.Source Files\test...\..\..\test\test.c + +[Root.Source Files.Source Files\test...\..\..\test\test.c] +ElemType=File +PathName=..\..\..\test\test.c + +[Root.Include Files] +ElemType=Folder +PathName=Include Files +Child=Root.Include Files...\demo\halconf.h +Config.0=Root.Include Files.Config.0 +Config.1=Root.Include Files.Config.1 + +[Root.Include Files.Config.0] +Settings.0.0=Root.Include Files.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Config.0.Settings.3 + +[Root.Include Files.Config.1] +Settings.1.0=Root.Include Files.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Config.1.Settings.3 + +[Root.Include Files.Config.0.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Config.1.Settings.0] +String.6.0=2010,6,4,10,10,40 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Config.1.Settings.3] +String.2.0=Performing Custom Build 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Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\stm8.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel] +ElemType=Folder +PathName=Include Files\os\kernel +Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h +Next=Root.Include Files.Include Files\os.Include Files\os\port + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chvt.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chthreads.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chthreads.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chthreads.h +Next=Root.Include Files.Include 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Files\os\kernel...\..\..\os\kernel\include\chlists.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chlists.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chlists.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chioch.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chioch.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chioch.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chinline.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chinline.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chinline.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chheap.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chevents.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdebug.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chcond.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chcond.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chcond.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h] +ElemType=File +PathName=..\..\..\os\kernel\include\ch.h + +[Root.Include Files.Include Files\os.Include Files\os\port] +ElemType=Folder +PathName=Include Files\os\port +Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chtypes.h +Next=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chcore.h + +[Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chcore.h] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.h + +[Root.Include Files.Include Files\test] +ElemType=Folder +PathName=Include Files\test +Child=Root.Include Files.Include Files\test...\..\..\test\testsem.h + +[Root.Include Files.Include Files\test...\..\..\test\testsem.h] +ElemType=File +PathName=..\..\..\test\testsem.h +Next=Root.Include Files.Include Files\test...\..\..\test\testqueues.h + +[Root.Include Files.Include Files\test...\..\..\test\testqueues.h] +ElemType=File +PathName=..\..\..\test\testqueues.h +Next=Root.Include Files.Include Files\test...\..\..\test\testpools.h + +[Root.Include Files.Include Files\test...\..\..\test\testpools.h] +ElemType=File +PathName=..\..\..\test\testpools.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmtx.h + +[Root.Include Files.Include Files\test...\..\..\test\testmtx.h] +ElemType=File +PathName=..\..\..\test\testmtx.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmsg.h + +[Root.Include Files.Include Files\test...\..\..\test\testmsg.h] +ElemType=File +PathName=..\..\..\test\testmsg.h +Next=Root.Include Files.Include Files\test...\..\..\test\testmbox.h + +[Root.Include Files.Include Files\test...\..\..\test\testmbox.h] +ElemType=File +PathName=..\..\..\test\testmbox.h +Next=Root.Include Files.Include Files\test...\..\..\test\testheap.h + +[Root.Include Files.Include Files\test...\..\..\test\testheap.h] +ElemType=File +PathName=..\..\..\test\testheap.h +Next=Root.Include Files.Include Files\test...\..\..\test\testevt.h + +[Root.Include Files.Include Files\test...\..\..\test\testevt.h] +ElemType=File +PathName=..\..\..\test\testevt.h +Next=Root.Include Files.Include Files\test...\..\..\test\testdyn.h + +[Root.Include Files.Include Files\test...\..\..\test\testdyn.h] +ElemType=File +PathName=..\..\..\test\testdyn.h +Next=Root.Include Files.Include Files\test...\..\..\test\testbmk.h + +[Root.Include Files.Include Files\test...\..\..\test\testbmk.h] +ElemType=File +PathName=..\..\..\test\testbmk.h +Next=Root.Include Files.Include Files\test...\..\..\test\test.h + +[Root.Include Files.Include Files\test...\..\..\test\test.h] +ElemType=File +PathName=..\..\..\test\test.h +Next=Root.Include Files.Include Files\test...\..\..\test\testthd.h + +[Root.Include Files.Include Files\test...\..\..\test\testthd.h] +ElemType=File +PathName=..\..\..\test\testthd.h \ No newline at end of file -- cgit v1.2.3 From e4cdc96106cefcc970f4b06e7ffed1032e6db0d2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 10 Nov 2010 19:26:40 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2344 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../cosmic/cosmic.stp | 170 ++++++++------------ .../raisonance/raisonance.stp | 174 ++++++++------------- 2 files changed, 132 insertions(+), 212 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp index 76cd87427..ddf8d87b0 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -74,7 +74,7 @@ String.6.0=2010,5,25,14,45,56 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8l_discovery;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo;..\..\..\os\hal\platforms\stm8l; [Root.Config.0.Settings.2] String.2.0= @@ -83,7 +83,7 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,26,17,30,51 @@ -157,7 +157,7 @@ String.6.0=2010,5,25,14,45,56 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8l_discovery;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo;..\..\..\os\hal\platforms\stm8l; [Root.Config.1.Settings.2] String.2.0= @@ -166,7 +166,7 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -247,7 +247,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -274,7 +274,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -306,7 +306,7 @@ Next=Root.Source Files.Source Files\board [Root.Source Files.Source Files\board] ElemType=Folder PathName=Source Files\board -Child=Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c +Child=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c Next=Root.Source Files.Source Files\os Config.0=Root.Source Files.Source Files\board.Config.0 Config.1=Root.Source Files.Source Files\board.Config.1 @@ -331,7 +331,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -358,7 +358,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -377,9 +377,9 @@ String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c] +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c] ElemType=File -PathName=..\..\..\boards\st_stm8s_discovery\board.c +PathName=..\..\..\boards\st_stm8l_discovery\board.c [Root.Source Files.Source Files\os] ElemType=Folder @@ -415,7 +415,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -442,7 +442,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -509,26 +509,11 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.c +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder @@ -568,7 +553,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -589,7 +574,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -627,7 +612,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -648,7 +633,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -686,7 +671,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -707,7 +692,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -745,7 +730,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,54,38 @@ -766,7 +751,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -804,7 +789,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -825,7 +810,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -863,7 +848,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -884,7 +869,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -922,7 +907,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -943,7 +928,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -981,7 +966,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1002,7 +987,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1040,7 +1025,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1061,7 +1046,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1099,7 +1084,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1120,7 +1105,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1158,7 +1143,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1179,7 +1164,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1217,7 +1202,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1238,7 +1223,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1276,7 +1261,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1297,7 +1282,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1335,7 +1320,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1356,7 +1341,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1394,7 +1379,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1415,7 +1400,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1453,7 +1438,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1474,7 +1459,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1511,7 +1496,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,54,38 @@ -1532,7 +1517,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1565,7 +1550,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1592,7 +1577,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1642,7 +1627,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1669,7 +1654,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1774,7 +1759,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1801,7 +1786,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1838,12 +1823,12 @@ Next=Root.Include Files.Include Files\board [Root.Include Files.Include Files\board] ElemType=Folder PathName=Include Files\board -Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8s_discovery\board.h +Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h Next=Root.Include Files.Include Files\os -[Root.Include Files.Include Files\board...\..\..\boards\st_stm8s_discovery\board.h] +[Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h] ElemType=File -PathName=..\..\..\boards\st_stm8s_discovery\board.h +PathName=..\..\..\boards\st_stm8l_discovery\board.h [Root.Include Files.Include Files\os] ElemType=Folder @@ -1910,41 +1895,16 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s_type.h +PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp index 254953e80..a3df6a1d6 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -74,7 +74,7 @@ String.6.0=2010,6,4,10,10,40 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; +String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8;..\..\..\os\hal\platforms\stm8l; [Root.Config.0.Settings.2] String.2.0= @@ -83,7 +83,7 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -143,7 +143,7 @@ String.6.0=2010,6,4,10,10,40 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; +String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8;..\..\..\os\hal\platforms\stm8l; [Root.Config.1.Settings.2] String.2.0= @@ -152,7 +152,7 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -219,7 +219,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -246,7 +246,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -297,7 +297,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -318,7 +318,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -327,7 +327,7 @@ String.8.0=Release [Root.Source Files.Source Files\board] ElemType=Folder PathName=Source Files\board -Child=Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c +Child=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c Next=Root.Source Files.Source Files\os Config.0=Root.Source Files.Source Files\board.Config.0 Config.1=Root.Source Files.Source Files\board.Config.1 @@ -352,7 +352,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -379,7 +379,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -398,9 +398,9 @@ String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8s_discovery\board.c] +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c] ElemType=File -PathName=..\..\..\boards\st_stm8s_discovery\board.c +PathName=..\..\..\boards\st_stm8l_discovery\board.c [Root.Source Files.Source Files\os] ElemType=Folder @@ -436,7 +436,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -463,7 +463,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -530,26 +530,11 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.c +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder @@ -589,7 +574,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -610,7 +595,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -648,7 +633,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -669,7 +654,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -707,7 +692,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -728,7 +713,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -766,7 +751,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -787,7 +772,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -825,7 +810,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -846,7 +831,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -884,7 +869,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -905,7 +890,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -943,7 +928,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -964,7 +949,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1002,7 +987,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1023,7 +1008,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1061,7 +1046,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1082,7 +1067,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1120,7 +1105,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1141,7 +1126,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1179,7 +1164,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1200,7 +1185,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1238,7 +1223,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1259,7 +1244,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1297,7 +1282,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1318,7 +1303,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1356,7 +1341,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1377,7 +1362,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1415,7 +1400,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1436,7 +1421,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1474,7 +1459,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1495,7 +1480,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1532,7 +1517,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1553,7 +1538,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1586,7 +1571,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1613,7 +1598,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1663,7 +1648,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1690,7 +1675,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1795,7 +1780,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1822,7 +1807,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1859,12 +1844,12 @@ Next=Root.Include Files.Include Files\board [Root.Include Files.Include Files\board] ElemType=Folder PathName=Include Files\board -Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8s_discovery\board.h +Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h Next=Root.Include Files.Include Files\os -[Root.Include Files.Include Files\board...\..\..\boards\st_stm8s_discovery\board.h] +[Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h] ElemType=File -PathName=..\..\..\boards\st_stm8s_discovery\board.h +PathName=..\..\..\boards\st_stm8l_discovery\board.h [Root.Include Files.Include Files\os] ElemType=Folder @@ -1931,41 +1916,16 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s_type.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h +PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.h +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder -- cgit v1.2.3 From a7b039fae4798eb96b28a8cb59267d26fb9261a9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 10 Nov 2010 21:46:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2345 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c | 12 +----------- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 4 ++-- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 14 +++++++------- 3 files changed, 10 insertions(+), 20 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c index 76ebd1736..5c041d9df 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c @@ -76,25 +76,15 @@ exception_vector_t const _vectab[] = { #endif {0x82, vector}, /* vector11 */ {0x82, vector}, /* vector12 */ - {0x82, vector13}, /* vector13 */ + {0x82, vector}, /* vector13 */ {0x82, vector}, /* vector14 */ {0x82, vector}, /* vector15 */ {0x82, vector}, /* vector16 */ -#if HAL_USE_SERIAL && STM8_SERIAL_USE_UART1 - {0x82, vector17}, /* vector17 */ - {0x82, vector18}, /* vector18 */ -#else {0x82, vector}, /* vector17 */ {0x82, vector}, /* vector18 */ -#endif {0x82, vector}, /* vector19 */ -#if HAL_USE_SERIAL && (STM8_SERIAL_USE_UART2 || STM8_SERIAL_USE_UART3) {0x82, vector20}, /* vector20 */ - {0x82, vector21}, /* vector21 */ -#else - {0x82, vector}, /* vector20 */ {0x82, vector}, /* vector21 */ -#endif {0x82, vector}, /* vector22 */ {0x82, vector}, /* vector23 */ {0x82, vector}, /* vector24 */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index 3186be527..e75f8b89d 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -41,7 +41,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE +#define HAL_USE_PAL FALSE #endif /** @@ -90,7 +90,7 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE +#define HAL_USE_SERIAL FALSE #endif /** diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c index 35321bf62..c8c8e44fe 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -29,9 +29,9 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { - palClearPad(GPIOD, PD_LD10); +// palClearPad(GPIOD, PD_LD10); chThdSleepMilliseconds(500); - palSetPad(GPIOD, PD_LD10); +// palSetPad(GPIOD, PD_LD10); chThdSleepMilliseconds(500); } return 0; @@ -55,7 +55,7 @@ void main(void) { /* * Activates the serial driver 1 using the driver default configuration. */ - sdStart(&SD2, NULL); +// sdStart(&SD2, NULL); /* * Creates the blinker thread. @@ -66,10 +66,10 @@ void main(void) { * Normal main() thread activity. */ while (TRUE) { - if (palReadPad(GPIOG, 0) == PAL_LOW) - TestThread(&SD2); - if (palReadPad(GPIOG, 1) == PAL_LOW) - sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE); +// if (palReadPad(GPIOG, 0) == PAL_LOW) +// TestThread(&SD2); +// if (palReadPad(GPIOG, 1) == PAL_LOW) +// sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE); chThdSleepMilliseconds(1000); } } -- cgit v1.2.3 From 27654c1bb64c74f7b5b5516945b24e1793ed8c12 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 11 Nov 2010 18:51:10 +0000 Subject: STM8L platform support (not tested yet). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2347 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../cosmic/cosmic.stp | 2837 ++++++++++++++++---- .../STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c | 257 +- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 4 +- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 16 +- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h | 2 +- .../raisonance/raisonance.stp | 2689 +++++++++++++++---- 6 files changed, 4698 insertions(+), 1107 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp index ddf8d87b0..e92076244 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -166,7 +166,7 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -274,7 +274,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -297,11 +297,119 @@ String.6.0=2010,5,25,14,45,56 ElemType=File PathName=..\demo\main.c Next=Root.Source Files.vectors.c +Config.0=Root.Source Files...\demo\main.c.Config.0 +Config.1=Root.Source Files...\demo\main.c.Config.1 + +[Root.Source Files...\demo\main.c.Config.0] +Settings.0.0=Root.Source Files...\demo\main.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files...\demo\main.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files...\demo\main.c.Config.0.Settings.2 + +[Root.Source Files...\demo\main.c.Config.1] +Settings.1.0=Root.Source Files...\demo\main.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files...\demo\main.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files...\demo\main.c.Config.1.Settings.2 + +[Root.Source Files...\demo\main.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files...\demo\main.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 +String.8.0=Debug + +[Root.Source Files...\demo\main.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files...\demo\main.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files...\demo\main.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 +String.8.0=Release [Root.Source Files.vectors.c] ElemType=File PathName=vectors.c Next=Root.Source Files.Source Files\board +Config.0=Root.Source Files.vectors.c.Config.0 +Config.1=Root.Source Files.vectors.c.Config.1 + +[Root.Source Files.vectors.c.Config.0] +Settings.0.0=Root.Source Files.vectors.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.vectors.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.vectors.c.Config.0.Settings.2 + +[Root.Source Files.vectors.c.Config.1] +Settings.1.0=Root.Source Files.vectors.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.vectors.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.vectors.c.Config.1.Settings.2 + +[Root.Source Files.vectors.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.vectors.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.vectors.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 +String.8.0=Debug + +[Root.Source Files.vectors.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.vectors.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.vectors.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 +String.8.0=Release [Root.Source Files.Source Files\board] ElemType=Folder @@ -358,7 +466,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -380,6 +488,60 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c] ElemType=File PathName=..\..\..\boards\st_stm8l_discovery\board.c +Config.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0 +Config.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 +String.8.0=Debug + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 +String.8.0=Release [Root.Source Files.Source Files\os] ElemType=Folder @@ -442,7 +604,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -465,93 +627,33 @@ String.6.0=2010,5,25,14,45,56 ElemType=File PathName=..\..\..\os\hal\src\adc.c Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c] -ElemType=File -PathName=..\..\..\os\hal\src\can.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c] -ElemType=File -PathName=..\..\..\os\hal\src\hal.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c] -ElemType=File -PathName=..\..\..\os\hal\src\mac.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c] -ElemType=File -PathName=..\..\..\os\hal\src\mmc_spi.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] -ElemType=File -PathName=..\..\..\os\hal\src\pal.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] -ElemType=File -PathName=..\..\..\os\hal\src\pwm.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] -ElemType=File -PathName=..\..\..\os\hal\src\serial.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c] -ElemType=File -PathName=..\..\..\os\hal\src\spi.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] -ElemType=Folder -PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\kernel] -ElemType=Folder -PathName=Source Files\os\kernel -Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c -Next=Root.Source Files.Source Files\os.Source Files\os\port - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chcond.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -559,20 +661,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -580,37 +682,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c] ElemType=File -PathName=..\..\..\os\kernel\src\chdebug.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 +PathName=..\..\..\os\hal\src\can.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -618,20 +720,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -639,37 +741,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c] ElemType=File -PathName=..\..\..\os\kernel\src\chevents.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 +PathName=..\..\..\os\hal\src\hal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -677,20 +779,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -698,96 +800,96 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c] ElemType=File -PathName=..\..\..\os\kernel\src\chheap.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 +PathName=..\..\..\os\hal\src\mac.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] -String.6.0=2010,6,3,11,20,12 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,54,38 +String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] -String.6.0=2010,6,3,11,20,12 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c] ElemType=File -PathName=..\..\..\os\kernel\src\chlists.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1 +PathName=..\..\..\os\hal\src\mmc_spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -795,20 +897,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -816,37 +918,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmboxes.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1 +PathName=..\..\..\os\hal\src\pal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -854,20 +956,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -875,37 +977,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmemcore.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1 +PathName=..\..\..\os\hal\src\pwm.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -913,20 +1015,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -934,37 +1036,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmempools.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1 +PathName=..\..\..\os\hal\src\serial.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -972,20 +1074,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -993,37 +1095,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmsg.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1 +PathName=..\..\..\os\hal\src\spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1031,20 +1133,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1052,37 +1154,56 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +ElemType=Folder +PathName=Source Files\os\hal\stm8 +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmtx.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1 +PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1090,20 +1211,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1111,37 +1232,43 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel] +ElemType=Folder +PathName=Source Files\os\kernel +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Next=Root.Source Files.Source Files\os.Source Files\os\port + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] ElemType=File -PathName=..\..\..\os\kernel\src\chqueues.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1 +PathName=..\..\..\os\kernel\src\chcond.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] String.6.0=2010,6,3,14,55,16 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1149,20 +1276,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] String.6.0=2010,6,3,14,55,16 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1170,37 +1297,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] ElemType=File -PathName=..\..\..\os\kernel\src\chregistry.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 +PathName=..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] String.6.0=2010,6,3,14,55,16 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1208,20 +1335,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] String.6.0=2010,6,3,14,55,16 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1229,37 +1356,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] ElemType=File -PathName=..\..\..\os\kernel\src\chschd.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1 +PathName=..\..\..\os\kernel\src\chevents.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1267,20 +1394,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1288,96 +1415,96 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] ElemType=File -PathName=..\..\..\os\kernel\src\chsem.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1 +PathName=..\..\..\os\kernel\src\chheap.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] +String.6.0=2010,6,3,11,20,12 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,6,5,11,54,38 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] +String.6.0=2010,6,3,11,20,12 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] ElemType=File -PathName=..\..\..\os\kernel\src\chsys.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1 +PathName=..\..\..\os\kernel\src\chlists.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1385,20 +1512,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1406,37 +1533,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] ElemType=File -PathName=..\..\..\os\kernel\src\chthreads.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1 +PathName=..\..\..\os\kernel\src\chmboxes.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1444,20 +1571,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1465,272 +1592,1564 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] ElemType=File -PathName=..\..\..\os\kernel\src\chvt.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1 +PathName=..\..\..\os\kernel\src\chmemcore.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0] -String.6.0=2010,6,2,17,48,49 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,54,38 +String.6.0=2010,6,5,11,53,48 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0] -String.6.0=2010,6,2,17,48,49 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\port] -ElemType=Folder -PathName=Source Files\os\port -Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\cosmic\stm8\chcore.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmempools.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 -Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 -Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,17 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0] +String.6.0=2010,6,3,14,55,16 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 +String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] +String.6.0=2010,6,3,14,55,16 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= 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+String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 +String.8.0=Release [Root.Include Files] ElemType=Folder @@ -1786,7 +3205,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1825,6 +3244,74 @@ ElemType=Folder PathName=Include Files\board Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h Next=Root.Include Files.Include Files\os +Config.0=Root.Include Files.Include Files\board.Config.0 +Config.1=Root.Include Files.Include Files\board.Config.1 + +[Root.Include Files.Include Files\board.Config.0] +Settings.0.0=Root.Include Files.Include Files\board.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\board.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\board.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\board.Config.0.Settings.3 + +[Root.Include Files.Include Files\board.Config.1] +Settings.1.0=Root.Include Files.Include Files\board.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\board.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\board.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\board.Config.1.Settings.3 + +[Root.Include Files.Include Files\board.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\board.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\board.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\board.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\board.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\board.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\board.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Include Files.Include Files\board.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h] ElemType=File @@ -1895,7 +3382,85 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h +Config.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0 +Config.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0] +Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1] +Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... 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-i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h] ElemType=File @@ -1911,6 +3476,74 @@ ElemType=Folder PathName=Include Files\os\kernel Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h Next=Root.Include Files.Include Files\os.Include Files\os\port +Config.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0 +Config.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0] +Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1] +Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h] ElemType=File @@ -2020,6 +3653,74 @@ PathName=..\..\..\os\kernel\include\chvt.h ElemType=Folder PathName=Include Files\os\port Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\cosmic\stm8\chcore.h +Config.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0 +Config.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0] +Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1] +Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\cosmic\stm8\chcore.h] ElemType=File @@ -2034,6 +3735,74 @@ PathName=..\..\..\os\ports\cosmic\stm8\chtypes.h ElemType=Folder PathName=Include Files\test Child=Root.Include Files.Include Files\test...\..\..\test\test.h +Config.0=Root.Include Files.Include Files\test.Config.0 +Config.1=Root.Include Files.Include Files\test.Config.1 + +[Root.Include Files.Include Files\test.Config.0] +Settings.0.0=Root.Include Files.Include Files\test.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\test.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\test.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\test.Config.0.Settings.3 + +[Root.Include Files.Include Files\test.Config.1] +Settings.1.0=Root.Include Files.Include Files\test.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\test.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\test.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\test.Config.1.Settings.3 + +[Root.Include Files.Include Files\test.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\test.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\test.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\test.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 + +[Root.Include Files.Include Files\test.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,55 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\test.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,5,11,53,48 + +[Root.Include Files.Include Files\test.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 + +[Root.Include Files.Include Files\test.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\test...\..\..\test\test.h] ElemType=File diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c index 5c041d9df..d35e6a51e 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c @@ -20,6 +20,11 @@ #include "ch.h" #include "hal.h" +/* This inclusion allows user ISR to be added to the HAL.*/ +#if defined(_USER_ISR_) +#include "user_isr.h" +#endif + /** * @brief Exception handler type. */ @@ -29,12 +34,37 @@ typedef void @far @interrupt (*interrupt_handler_t)(void); * Various external symbols. */ void _stext(void); +@far @interrupt void vector_trap(void); +@far @interrupt void vector0(void); +@far @interrupt void vector1(void); +@far @interrupt void vector2(void); +@far @interrupt void vector3(void); +@far @interrupt void vector4(void); +@far @interrupt void vector5(void); +@far @interrupt void vector6(void); +@far @interrupt void vector7(void); +@far @interrupt void vector8(void); +@far @interrupt void vector9(void); @far @interrupt void vector10(void); +@far @interrupt void vector11(void); +@far @interrupt void vector12(void); @far @interrupt void vector13(void); +@far @interrupt void vector14(void); +@far @interrupt void vector15(void); +@far @interrupt void vector16(void); @far @interrupt void vector17(void); @far @interrupt void vector18(void); +@far @interrupt void vector19(void); @far @interrupt void vector20(void); @far @interrupt void vector21(void); +@far @interrupt void vector22(void); +@far @interrupt void vector23(void); +@far @interrupt void vector24(void); +@far @interrupt void vector25(void); +@far @interrupt void vector26(void); +@far @interrupt void vector27(void); +@far @interrupt void vector28(void); +@far @interrupt void vector29(void); /** * @brief Exception vector type. @@ -45,12 +75,14 @@ typedef struct { } exception_vector_t; /** - * @brief Undefined interrupt handler. - * @note It should never be invoked. + * @brief Unhandled exception handler. + * @default This function is the default handler for all unused entries + * in the vector table. */ -@far @interrupt static void vector (void) +@far @interrupt void _unhandled_exception (void) { - return; + while (TRUE) + ; } /** @@ -58,39 +90,190 @@ typedef struct { */ exception_vector_t const _vectab[] = { {0x82, (interrupt_handler_t)_stext}, /* reset */ - {0x82, vector}, /* trap */ - {0x82, vector}, /* vector0 */ - {0x82, vector}, /* vector1 */ - {0x82, vector}, /* vector2 */ - {0x82, vector}, /* vector3 */ - {0x82, vector}, /* vector4 */ - {0x82, vector}, /* vector5 */ - {0x82, vector}, /* vector6 */ - {0x82, vector}, /* vector7 */ - {0x82, vector}, /* vector8 */ - {0x82, vector}, /* vector9 */ -#if HAL_USE_SPI && STM8_SPI_USE_SPI + +#if defined(_TRAP_ISR) + {0x82, vector_trap}, +#else + {0x82, _unhandled_exception}, /* trap */ +#endif + +#if defined(_TLI_ISR) + {0x82, vector0}, +#else + {0x82, _unhandled_exception}, /* vector0 */ +#endif + +#if defined(_FLASH_ISR) + {0x82, vector1}, +#else + {0x82, _unhandled_exception}, /* vector1 */ +#endif + +#if defined(_DMA10_ISR) || defined(_DMA11_ISR) + {0x82, vector2}, +#else + {0x82, _unhandled_exception}, /* vector2 */ +#endif + +#if defined(_DMA12_ISR) || defined(_DMA13_ISR) + {0x82, vector3}, +#else + {0x82, _unhandled_exception}, /* vector3 */ +#endif + +#if defined(_RTC_ISR) || defined(_LSE_CSS_ISR) + {0x82, vector4}, +#else + {0x82, _unhandled_exception}, /* vector4 */ +#endif + +#if defined(_EXTIE_ISR) || defined(_EXTIF_ISR) || defined(_PVD_ISR) + {0x82, vector5}, +#else + {0x82, _unhandled_exception}, /* vector5 */ +#endif + +#if defined(_EXTIB_ISR) || defined(_EXTIG_ISR) + {0x82, vector6}, +#else + {0x82, _unhandled_exception}, /* vector6 */ +#endif + +#if defined(_EXTID_ISR) || defined(_EXTIH_ISR) + {0x82, vector7}, +#else + {0x82, _unhandled_exception}, /* vector7 */ +#endif + +#if defined(_EXTI0_ISR) + {0x82, vector8}, +#else + {0x82, _unhandled_exception}, /* vector8 */ +#endif + +#if defined(_EXTI1_ISR) + {0x82, vector9}, +#else + {0x82, _unhandled_exception}, /* vector9 */ +#endif + +#if defined(_EXTI2_ISR) {0x82, vector10}, #else - {0x82, vector}, /* vector10 */ -#endif - {0x82, vector}, /* vector11 */ - {0x82, vector}, /* vector12 */ - {0x82, vector}, /* vector13 */ - {0x82, vector}, /* vector14 */ - {0x82, vector}, /* vector15 */ - {0x82, vector}, /* vector16 */ - {0x82, vector}, /* vector17 */ - {0x82, vector}, /* vector18 */ - {0x82, vector}, /* vector19 */ - {0x82, vector20}, /* vector20 */ - {0x82, vector}, /* vector21 */ - {0x82, vector}, /* vector22 */ - {0x82, vector}, /* vector23 */ - {0x82, vector}, /* vector24 */ - {0x82, vector}, /* vector25 */ - {0x82, vector}, /* vector26 */ - {0x82, vector}, /* vector27 */ - {0x82, vector}, /* vector28 */ - {0x82, vector}, /* vector29 */ + {0x82, _unhandled_exception}, /* vector10 */ +#endif + +#if defined(_EXTI3_ISR) + {0x82, vector11}, +#else + {0x82, _unhandled_exception}, /* vector11 */ +#endif + +#if defined(_EXTI4_ISR) + {0x82, vector12}, +#else + {0x82, _unhandled_exception}, /* vector12 */ +#endif + +#if defined(_EXTI5_ISR) + {0x82, vector13}, +#else + {0x82, _unhandled_exception}, /* vector13 */ +#endif + +#if defined(_EXTI6_ISR) + {0x82, vector14}, +#else + {0x82, _unhandled_exception}, /* vector14 */ +#endif + +#if defined(_EXTI7_ISR) + {0x82, vector15}, +#else + {0x82, _unhandled_exception}, /* vector15 */ +#endif + +#if defined(_LCD_ISR) || defined(_AES_ISR) + {0x82, vector16}, +#else + {0x82, _unhandled_exception}, /* vector16 */ +#endif + +#if defined(_CLK_ISR) || defined(_TIM1_BREAK_ISR) || defined(_DAC_ISR) + {0x82, vector17}, +#else + {0x82, _unhandled_exception}, /* vector17 */ +#endif + +#if defined(_COMP1_ISR) || defined(_COMP2_ISR) || defined(_ADC1_ISR) + {0x82, vector18}, +#else + {0x82, _unhandled_exception}, /* vector18 */ +#endif + +#if defined(_TIM2_OVERFLOW_ISR) || defined(_USART2_TRANSMIT_ISR) + {0x82, vector19}, +#else + {0x82, _unhandled_exception}, /* vector19 */ +#endif + +#if defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) + {0x82, vector20}, +#else + {0x82, _unhandled_exception}, /* vector20 */ +#endif + +#if defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) + {0x82, vector21}, +#else + {0x82, _unhandled_exception}, /* vector21 */ +#endif + +#if defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) + {0x82, vector22}, +#else + {0x82, _unhandled_exception}, /* vector22 */ +#endif + +#if defined(_TIM1_UPDATE_ISR) + {0x82, vector23}, +#else + {0x82, _unhandled_exception}, /* vector23 */ +#endif + +#if defined(_TIM1_COMPARE_ISR) + {0x82, vector24}, +#else + {0x82, _unhandled_exception}, /* vector24 */ +#endif + +#if defined(_TIM4_UPDATE_ISR) + {0x82, vector25}, +#else + {0x82, _unhandled_exception}, /* vector25 */ +#endif + +#if defined(_SPI1_ISR) + {0x82, vector26}, +#else + {0x82, _unhandled_exception}, /* vector26 */ +#endif + +#if defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) + {0x82, vector27}, +#else + {0x82, _unhandled_exception}, /* vector27 */ +#endif + +#if defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) + {0x82, vector28}, +#else + {0x82, _unhandled_exception}, /* vector28 */ +#endif + +#if defined(_SPI2_ISR) || defined(_I2C1_ISR) + {0x82, vector29}, +#else + {0x82, _unhandled_exception}, /* vector29 */ +#endif }; diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index e75f8b89d..3186be527 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -41,7 +41,7 @@ * @brief Enables the PAL subsystem. */ #if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL FALSE +#define HAL_USE_PAL TRUE #endif /** @@ -90,7 +90,7 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL FALSE +#define HAL_USE_SERIAL TRUE #endif /** diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c index c8c8e44fe..522499fcc 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -29,9 +29,13 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { -// palClearPad(GPIOD, PD_LD10); + palClearPad(GPIOC, PC_LED4); chThdSleepMilliseconds(500); -// palSetPad(GPIOD, PD_LD10); + palSetPad(GPIOC, PC_LED4); + chThdSleepMilliseconds(500); + palClearPad(GPIOE, PE_LED3); + chThdSleepMilliseconds(500); + palSetPad(GPIOE, PE_LED3); chThdSleepMilliseconds(500); } return 0; @@ -55,7 +59,7 @@ void main(void) { /* * Activates the serial driver 1 using the driver default configuration. */ -// sdStart(&SD2, NULL); + sdStart(&SD1, NULL); /* * Creates the blinker thread. @@ -66,10 +70,8 @@ void main(void) { * Normal main() thread activity. */ while (TRUE) { -// if (palReadPad(GPIOG, 0) == PAL_LOW) -// TestThread(&SD2); -// if (palReadPad(GPIOG, 1) == PAL_LOW) -// sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE); + if (palReadPad(GPIOC, PC_BUTTON) == PAL_LOW) + TestThread(&SD1); chThdSleepMilliseconds(1000); } } diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h index a65191d1f..d37723781 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h @@ -43,4 +43,4 @@ */ #define STM8L_SERIAL_USE_USART1 TRUE #define STM8L_SERIAL_USE_USART2 FALSE -#define STM8K_SERIAL_USE_USART3 FALSE +#define STM8L_SERIAL_USE_USART3 FALSE diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp index a3df6a1d6..1d1aa5538 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Programmi\Raisonance\Ride +String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -83,7 +83,7 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -130,7 +130,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Programmi\Raisonance\Ride +String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -219,7 +219,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -352,7 +352,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -401,6 +401,59 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c] ElemType=File PathName=..\..\..\boards\st_stm8l_discovery\board.c +Config.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0 +Config.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\os] ElemType=Folder @@ -436,7 +489,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -486,152 +539,91 @@ String.6.0=2010,6,4,10,10,40 ElemType=File PathName=..\..\..\os\hal\src\spi.c Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] -ElemType=File -PathName=..\..\..\os\hal\src\serial.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] -ElemType=File -PathName=..\..\..\os\hal\src\pwm.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] -ElemType=File -PathName=..\..\..\os\hal\src\pal.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c] -ElemType=File -PathName=..\..\..\os\hal\src\mmc_spi.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c] -ElemType=File -PathName=..\..\..\os\hal\src\mac.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c] -ElemType=File -PathName=..\..\..\os\hal\src\hal.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c] -ElemType=File -PathName=..\..\..\os\hal\src\can.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c] -ElemType=File -PathName=..\..\..\os\hal\src\adc.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] -ElemType=Folder -PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\kernel] -ElemType=Folder -PathName=Source Files\os\kernel -Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c -Next=Root.Source Files.Source Files\os.Source Files\os\port - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chvt.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,31 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,31 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] ElemType=File -PathName=..\..\..\os\kernel\src\chthreads.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1 +PathName=..\..\..\os\hal\src\serial.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,31 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -639,58 +631,57 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,31 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] ElemType=File -PathName=..\..\..\os\kernel\src\chsys.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1 +PathName=..\..\..\os\hal\src\pwm.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,30 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -698,58 +689,57 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,30 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] ElemType=File -PathName=..\..\..\os\kernel\src\chsem.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1 +PathName=..\..\..\os\hal\src\pal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,30 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -757,58 +747,57 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,30 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c] ElemType=File -PathName=..\..\..\os\kernel\src\chschd.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1 +PathName=..\..\..\os\hal\src\mmc_spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,30 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -816,58 +805,57 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,30 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c] ElemType=File -PathName=..\..\..\os\kernel\src\chregistry.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 +PathName=..\..\..\os\hal\src\mac.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,29 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -875,58 +863,57 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,29 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c] ElemType=File -PathName=..\..\..\os\kernel\src\chqueues.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1 +PathName=..\..\..\os\hal\src\hal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,29 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -934,58 +921,57 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,29 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmtx.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1 +PathName=..\..\..\os\hal\src\can.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,28 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -993,58 +979,57 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmsg.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1 +PathName=..\..\..\os\hal\src\adc.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 +Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,28 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1052,58 +1037,76 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +ElemType=Folder +PathName=Source Files\os\hal\stm8 +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmempools.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1 +PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source 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Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1111,117 +1114,122 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel] +ElemType=Folder +PathName=Source Files\os\kernel +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c +Next=Root.Source Files.Source Files\os.Source Files\os\port + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmemcore.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1 +PathName=..\..\..\os\kernel\src\chvt.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source 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Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,28 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,31 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,31 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c] ElemType=File -PathName=..\..\..\os\kernel\src\chmboxes.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1 +PathName=..\..\..\os\kernel\src\chthreads.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,31 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1229,20 +1237,20 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,31 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1250,37 +1258,37 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c] ElemType=File -PathName=..\..\..\os\kernel\src\chlists.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1 +PathName=..\..\..\os\kernel\src\chsys.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,30 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1288,20 +1296,20 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,30 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1309,96 +1317,96 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c] ElemType=File -PathName=..\..\..\os\kernel\src\chheap.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 +PathName=..\..\..\os\kernel\src\chsem.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,30 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,30 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c] ElemType=File -PathName=..\..\..\os\kernel\src\chevents.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 +PathName=..\..\..\os\kernel\src\chschd.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,30 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1406,20 +1414,20 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,30 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1427,37 +1435,37 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] ElemType=File -PathName=..\..\..\os\kernel\src\chdebug.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 +PathName=..\..\..\os\kernel\src\chregistry.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,29 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1465,20 +1473,20 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,29 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1486,36 +1494,37 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] ElemType=File -PathName=..\..\..\os\kernel\src\chcond.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 +PathName=..\..\..\os\kernel\src\chqueues.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,29 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1523,20 +1532,20 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,29 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -1544,82 +1553,724 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\port] -ElemType=Folder -PathName=Source Files\os\port -Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmtx.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 -Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 -Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] -String.6.0=2010,6,4,10,13,43 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,28 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 +String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] -String.6.0=2010,6,4,10,13,43 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 +String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmsg.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source 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Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chmemcore.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source 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$(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,28 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= 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Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chlists.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chheap.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chevents.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] +String.6.0=2010,6,4,10,14,27 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 +String.8.0=Release + +[Root.Source Files.Source Files\os.Source Files\os\port] +ElemType=Folder +PathName=Source Files\os\port +Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] +String.6.0=2010,6,4,10,13,43 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c] +ElemType=File +PathName=..\..\..\os\ports\rc\stm8\chcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\test] ElemType=Folder @@ -1646,112 +2297,748 @@ String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test.Config.0.Settings.1] +[Root.Source Files.Source Files\test.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Source Files.Source Files\test.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Source Files.Source Files\test.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test.Config.1.Settings.0] +String.6.0=2010,6,4,10,11,52 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c] +ElemType=File +PathName=..\..\..\test\testthd.c +Next=Root.Source Files.Source Files\test...\..\..\test\testsem.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c] +ElemType=File +PathName=..\..\..\test\testsem.c +Next=Root.Source Files.Source Files\test...\..\..\test\testqueues.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c] +ElemType=File +PathName=..\..\..\test\testqueues.c +Next=Root.Source Files.Source Files\test...\..\..\test\testpools.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c] +ElemType=File +PathName=..\..\..\test\testpools.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmtx.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c] +ElemType=File +PathName=..\..\..\test\testmtx.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmsg.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 +String.8.0=Debug -[Root.Source Files.Source Files\test.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 +String.6.0=2010,6,26,17,22,23 -[Root.Source Files.Source Files\test.Config.0.Settings.3] +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c] +ElemType=File +PathName=..\..\..\test\testmsg.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmbox.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test.Config.1.Settings.0] -String.6.0=2010,6,4,10,11,52 +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test.Config.1.Settings.1] +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 -[Root.Source Files.Source Files\test.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c] +ElemType=File +PathName=..\..\..\test\testmbox.c +Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug -[Root.Source Files.Source Files\test.Config.1.Settings.3] +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c] -ElemType=File -PathName=..\..\..\test\testthd.c -Next=Root.Source Files.Source Files\test...\..\..\test\testsem.c +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c] +[Root.Source Files.Source Files\test...\..\..\test\testheap.c] ElemType=File -PathName=..\..\..\test\testsem.c -Next=Root.Source Files.Source Files\test...\..\..\test\testqueues.c +PathName=..\..\..\test\testheap.c +Next=Root.Source Files.Source Files\test...\..\..\test\testevt.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c] -ElemType=File -PathName=..\..\..\test\testqueues.c -Next=Root.Source Files.Source Files\test...\..\..\test\testpools.c +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c] -ElemType=File -PathName=..\..\..\test\testpools.c -Next=Root.Source Files.Source Files\test...\..\..\test\testmtx.c +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c] -ElemType=File -PathName=..\..\..\test\testmtx.c -Next=Root.Source Files.Source Files\test...\..\..\test\testmsg.c +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c] -ElemType=File -PathName=..\..\..\test\testmsg.c -Next=Root.Source Files.Source Files\test...\..\..\test\testmbox.c +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c] -ElemType=File -PathName=..\..\..\test\testmbox.c -Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testheap.c] -ElemType=File -PathName=..\..\..\test\testheap.c -Next=Root.Source Files.Source Files\test...\..\..\test\testevt.c +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\test...\..\..\test\testevt.c] ElemType=File PathName=..\..\..\test\testevt.c Next=Root.Source Files.Source Files\test...\..\..\test\testdyn.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\test...\..\..\test\testdyn.c] ElemType=File PathName=..\..\..\test\testdyn.c Next=Root.Source Files.Source Files\test...\..\..\test\testbmk.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\test...\..\..\test\testbmk.c] ElemType=File PathName=..\..\..\test\testbmk.c Next=Root.Source Files.Source Files\test...\..\..\test\test.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\test...\..\..\test\test.c] ElemType=File PathName=..\..\..\test\test.c +Config.0=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0 +Config.1=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1 + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 +String.8.0=Debug + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 [Root.Include Files] ElemType=Folder @@ -1780,7 +3067,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1846,6 +3133,74 @@ ElemType=Folder PathName=Include Files\board Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h Next=Root.Include Files.Include Files\os +Config.0=Root.Include Files.Include Files\board.Config.0 +Config.1=Root.Include Files.Include Files\board.Config.1 + +[Root.Include Files.Include Files\board.Config.0] +Settings.0.0=Root.Include Files.Include Files\board.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\board.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\board.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\board.Config.0.Settings.3 + +[Root.Include Files.Include Files\board.Config.1] +Settings.1.0=Root.Include Files.Include Files\board.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\board.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\board.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\board.Config.1.Settings.3 + +[Root.Include Files.Include Files\board.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\board.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Include Files\board.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Include Files\board.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Include Files\board.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\board.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\board.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\board.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h] ElemType=File @@ -1916,7 +3271,85 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h +Config.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0 +Config.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0] +Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1] +Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h] ElemType=File @@ -1932,6 +3365,74 @@ ElemType=Folder PathName=Include Files\os\kernel Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h Next=Root.Include Files.Include Files\os.Include Files\os\port +Config.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0 +Config.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0] +Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1] +Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h] ElemType=File @@ -2041,6 +3542,74 @@ PathName=..\..\..\os\kernel\include\ch.h ElemType=Folder PathName=Include Files\os\port Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h +Config.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0 +Config.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0] +Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1] +Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h] ElemType=File @@ -2055,6 +3624,74 @@ PathName=..\..\..\os\ports\rc\stm8\chcore.h ElemType=Folder PathName=Include Files\test Child=Root.Include Files.Include Files\test...\..\..\test\testsem.h +Config.0=Root.Include Files.Include Files\test.Config.0 +Config.1=Root.Include Files.Include Files\test.Config.1 + +[Root.Include Files.Include Files\test.Config.0] +Settings.0.0=Root.Include Files.Include Files\test.Config.0.Settings.0 +Settings.0.1=Root.Include Files.Include Files\test.Config.0.Settings.1 +Settings.0.2=Root.Include Files.Include Files\test.Config.0.Settings.2 +Settings.0.3=Root.Include Files.Include Files\test.Config.0.Settings.3 + +[Root.Include Files.Include Files\test.Config.1] +Settings.1.0=Root.Include Files.Include Files\test.Config.1.Settings.0 +Settings.1.1=Root.Include Files.Include Files\test.Config.1.Settings.1 +Settings.1.2=Root.Include Files.Include Files\test.Config.1.Settings.2 +Settings.1.3=Root.Include Files.Include Files\test.Config.1.Settings.3 + +[Root.Include Files.Include Files\test.Config.0.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\test.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,42,15 + +[Root.Include Files.Include Files\test.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,46,5 + +[Root.Include Files.Include Files\test.Config.0.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Include Files.Include Files\test.Config.1.Settings.0] +String.6.0=2010,11,11,12,10,56 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Include Files.Include Files\test.Config.1.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\test.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,6,26,17,22,23 + +[Root.Include Files.Include Files\test.Config.1.Settings.3] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\test...\..\..\test\testsem.h] ElemType=File -- cgit v1.2.3 From 630bc516bf10c219d98d1c04466ce79de400d2ba Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 11 Nov 2010 18:52:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2348 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp | 4 ++-- demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp index e92076244..da9fe97d9 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp index 1d1aa5538..4fb729b4c 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -130,7 +130,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 -- cgit v1.2.3 From c62c1a4d629a8ec5094e2c964640d64a07fa6063 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 12 Nov 2010 18:59:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2350 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp | 18 ++++++++++++++---- .../raisonance/raisonance.stp | 18 ++++++++++++++---- 2 files changed, 28 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp index da9fe97d9..28cbf07ac 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -1235,9 +1235,14 @@ String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder PathName=Source Files\os\kernel -Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c Next=Root.Source Files.Source Files\os.Source Files\os\port +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c + [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] ElemType=File PathName=..\..\..\os\kernel\src\chcond.c @@ -3474,7 +3479,7 @@ PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder PathName=Include Files\os\kernel -Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h +Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\port Config.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0 Config.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1 @@ -3545,6 +3550,11 @@ String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdynamic.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h + [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h] ElemType=File PathName=..\..\..\os\kernel\include\ch.h diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp index 4fb729b4c..4b388bc3e 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Programmi\Raisonance\Ride +String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -130,7 +130,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Programmi\Raisonance\Ride +String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -1137,9 +1137,14 @@ String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder PathName=Source Files\os\kernel -Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c Next=Root.Source Files.Source Files\os.Source Files\os\port +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c + [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] ElemType=File PathName=..\..\..\os\kernel\src\chvt.c @@ -3363,7 +3368,7 @@ PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder PathName=Include Files\os\kernel -Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h +Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\port Config.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0 Config.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1 @@ -3434,6 +3439,11 @@ String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdynamic.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h + [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h] ElemType=File PathName=..\..\..\os\kernel\include\chvt.h -- cgit v1.2.3 From 8f4e3df95a7acc2bbaa82df41b6486ac9cb3a074 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 12 Nov 2010 21:28:25 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2351 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw | 2 +- .../cosmic/cosmic.stp | 3024 +++++-------------- .../raisonance/raisonance.stp | 3059 +++++--------------- 3 files changed, 1463 insertions(+), 4622 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw index a6630271a..015f8e015 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw @@ -12,5 +12,5 @@ Filename=raisonance\raisonance.stp Dependencies= [Options] ActiveProject=cosmic -ActiveConfig=Release +ActiveConfig=Debug AddSortedElements=0 diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp index 28cbf07ac..d0f4755c8 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -78,15 +78,15 @@ String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\po [Root.Config.0.Settings.2] String.2.0= -String.6.0=2010,5,25,14,45,56 -String.100.0=STM8S105C6 +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,26,17,30,51 +String.6.0=2010,11,12,20,31,15 [Root.Config.0.Settings.4] String.2.0=Assembling $(InputFile)... @@ -105,13 +105,13 @@ String.2.0=Running Linker String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile$(OutputPath)$(TargetSName).lkf String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 String.4.0=$(OutputPath)$(TargetFName) -String.5.0= -String.6.0=2010,6,4,10,29,4 +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,11,12,20,41,51 String.100.0= String.101.0=crtsi.st7 String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it String.102.1=+seg .text -a .const -n .text -String.102.2=+seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +String.102.2=+seg .eeprom -b 0x1000 -m 0x400 -n .eeprom String.102.3=+seg .bsct -b 0x0 -m 0x100 -n .bsct String.102.4=+seg .ubsct -a .bsct -n .ubsct String.102.5=+seg .bit -a .ubsct -n .bit -id @@ -119,11 +119,11 @@ String.102.6=+seg .share -a .bit -n .share -is String.102.7=+seg .data -b 0x100 -m 0x700 -n .data String.102.8=+seg .bss -a .data -n .bss String.103.0=Code,Constants[0x8080-0xffff]=.const,.text -String.103.1=Eeprom[0x4000-0x43ff]=.eeprom +String.103.1=Eeprom[0x1000-0x13ff]=.eeprom String.103.2=Zero Page[0x0-0xff]=.bsct,.ubsct,.bit,.share String.103.3=Ram[0x100-0x7ff]=.data,.bss String.104.0=0x7ff -String.105.0=libisl0.sm8;libm0.sm8 +String.105.0=libis0.sm8;libm0.sm8 Int.0=0 Int.1=0 @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -161,15 +161,15 @@ String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\po [Root.Config.1.Settings.2] String.2.0= -String.6.0=2010,5,25,14,45,56 -String.100.0=STM8S105C6 +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,31,15 [Root.Config.1.Settings.4] String.2.0=Assembling $(InputFile)... @@ -188,13 +188,13 @@ String.2.0=Running Linker String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile$(OutputPath)$(TargetSName).lkf String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 String.4.0=$(OutputPath)$(TargetFName) -String.5.0= -String.6.0=2010,6,5,11,53,48 +String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map +String.6.0=2010,11,12,20,32,28 String.100.0= String.101.0=crtsi.st7 String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it String.102.1=+seg .text -a .const -n .text -String.102.2=+seg .eeprom -b 0x4000 -m 0x400 -n .eeprom +String.102.2=+seg .eeprom -b 0x1000 -m 0x400 -n .eeprom String.102.3=+seg .bsct -b 0x0 -m 0x100 -n .bsct String.102.4=+seg .ubsct -a .bsct -n .ubsct String.102.5=+seg .bit -a .ubsct -n .bit -id @@ -202,7 +202,7 @@ String.102.6=+seg .share -a .bit -n .share -is String.102.7=+seg .data -b 0x100 -m 0x700 -n .data String.102.8=+seg .bss -a .data -n .bss String.103.0=Code,Constants[0x8080-0xffff]=.const,.text -String.103.1=Eeprom[0x4000-0x43ff]=.eeprom +String.103.1=Eeprom[0x1000-0x13ff]=.eeprom String.103.2=Zero Page[0x0-0xff]=.bsct,.ubsct,.bit,.share String.103.3=Ram[0x100-0x7ff]=.data,.bss String.104.0=0x7ff @@ -247,10 +247,10 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,31,15 [Root.Source Files.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... @@ -274,10 +274,10 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,31,15 [Root.Source Files.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... @@ -311,7 +311,7 @@ Settings.1.1=Root.Source Files...\demo\main.c.Config.1.Settings.1 Settings.1.2=Root.Source Files...\demo\main.c.Config.1.Settings.2 [Root.Source Files...\demo\main.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 @@ -325,14 +325,14 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files...\demo\main.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug [Root.Source Files...\demo\main.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 @@ -346,10 +346,10 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Release [Root.Source Files.vectors.c] @@ -370,7 +370,7 @@ Settings.1.1=Root.Source Files.vectors.c.Config.1.Settings.1 Settings.1.2=Root.Source Files.vectors.c.Config.1.Settings.2 [Root.Source Files.vectors.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 @@ -384,14 +384,14 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.vectors.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug [Root.Source Files.vectors.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 @@ -405,10 +405,10 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.vectors.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Release [Root.Source Files.Source Files\board] @@ -432,17 +432,17 @@ Settings.1.2=Root.Source Files.Source Files\board.Config.1.Settings.2 Settings.1.3=Root.Source Files.Source Files\board.Config.1.Settings.3 [Root.Source Files.Source Files\board.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\board.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... @@ -459,17 +459,17 @@ String.5.0= String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\board.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\board.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... @@ -488,60 +488,6 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c] ElemType=File PathName=..\..\..\boards\st_stm8l_discovery\board.c -Config.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0 -Config.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 -String.8.0=Debug - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 -String.8.0=Release [Root.Source Files.Source Files\os] ElemType=Folder @@ -570,17 +516,17 @@ Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Sett Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0] -String.6.0=2010,6,3,14,55,16 +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... @@ -597,17 +543,17 @@ String.5.0= String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0] -String.6.0=2010,6,3,14,55,16 +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... @@ -627,2534 +573,1346 @@ String.6.0=2010,5,25,14,45,56 ElemType=File PathName=..\..\..\os\hal\src\adc.c Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c] +ElemType=File +PathName=..\..\..\os\hal\src\can.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c] +ElemType=File +PathName=..\..\..\os\hal\src\hal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c] +ElemType=File +PathName=..\..\..\os\hal\src\mac.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c] +ElemType=File +PathName=..\..\..\os\hal\src\mmc_spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] +ElemType=File +PathName=..\..\..\os\hal\src\pal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] +ElemType=File +PathName=..\..\..\os\hal\src\pwm.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] +ElemType=File +PathName=..\..\..\os\hal\src\serial.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c] +ElemType=File +PathName=..\..\..\os\hal\src\spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +ElemType=Folder +PathName=Source Files\os\hal\stm8 +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\kernel] +ElemType=Folder +PathName=Source Files\os\kernel +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\port + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery 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Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l 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Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source 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Files\os\hal...\..\..\os\hal\src\mac.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] ElemType=File -PathName=..\..\..\os\hal\src\mac.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1 +PathName=..\..\..\os\kernel\src\chevents.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source 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Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery 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-co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source 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Files\os\hal...\..\..\os\hal\src\pwm.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] ElemType=File -PathName=..\..\..\os\hal\src\pwm.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1 +PathName=..\..\..\os\kernel\src\chmboxes.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source 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Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 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String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source 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Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source 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String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Release -[Root.Source Files.Source Files\test...\..\..\test\testevt.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] ElemType=File -PathName=..\..\..\test\testevt.c -Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1 +PathName=..\..\..\os\kernel\src\chregistry.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 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String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 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Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source 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-i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 -String.8.0=Debug +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 +[Root.Source Files.Source Files\test.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).ls +String.6.0=2010,6,2,8,54,4 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.1] +[Root.Source Files.Source Files\test.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 -String.8.0=Release +[Root.Source Files.Source Files\test...\..\..\test\test.c] +ElemType=File +PathName=..\..\..\test\test.c +Next=Root.Source Files.Source Files\test...\..\..\test\testbmk.c + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c] +ElemType=File +PathName=..\..\..\test\testbmk.c +Next=Root.Source Files.Source Files\test...\..\..\test\testdyn.c + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c] +ElemType=File +PathName=..\..\..\test\testdyn.c +Next=Root.Source Files.Source Files\test...\..\..\test\testevt.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c] +[Root.Source Files.Source Files\test...\..\..\test\testevt.c] ElemType=File -PathName=..\..\..\test\testthd.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1 +PathName=..\..\..\test\testevt.c +Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.2 +[Root.Source Files.Source Files\test...\..\..\test\testheap.c] +ElemType=File +PathName=..\..\..\test\testheap.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmbox.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.2 +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c] +ElemType=File +PathName=..\..\..\test\testmbox.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmsg.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Debug -Int.0=0 -Int.1=0 +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c] +ElemType=File +PathName=..\..\..\test\testmsg.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmtx.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c] +ElemType=File +PathName=..\..\..\test\testmtx.c +Next=Root.Source Files.Source Files\test...\..\..\test\testpools.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 -String.8.0=Debug +[Root.Source Files.Source Files\test...\..\..\test\testpools.c] +ElemType=File +PathName=..\..\..\test\testpools.c +Next=Root.Source Files.Source Files\test...\..\..\test\testqueues.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c] +ElemType=File +PathName=..\..\..\test\testqueues.c +Next=Root.Source Files.Source Files\test...\..\..\test\testsem.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 +[Root.Source Files.Source Files\test...\..\..\test\testsem.c] +ElemType=File +PathName=..\..\..\test\testsem.c +Next=Root.Source Files.Source Files\test...\..\..\test\testthd.c -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 -String.8.0=Release +[Root.Source Files.Source Files\test...\..\..\test\testthd.c] +ElemType=File +PathName=..\..\..\test\testthd.c [Root.Include Files] ElemType=Folder @@ -3183,10 +1941,10 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 [Root.Include Files.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... @@ -3210,10 +1968,10 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 +String.6.0=2010,11,12,20,27,7 [Root.Include Files.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... @@ -3249,74 +2007,6 @@ ElemType=Folder PathName=Include Files\board Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h Next=Root.Include Files.Include Files\os -Config.0=Root.Include Files.Include Files\board.Config.0 -Config.1=Root.Include Files.Include Files\board.Config.1 - -[Root.Include Files.Include Files\board.Config.0] -Settings.0.0=Root.Include Files.Include Files\board.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\board.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\board.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\board.Config.0.Settings.3 - -[Root.Include Files.Include Files\board.Config.1] -Settings.1.0=Root.Include Files.Include Files\board.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\board.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\board.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\board.Config.1.Settings.3 - -[Root.Include Files.Include Files\board.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\board.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\board.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\board.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\board.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\board.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\board.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,2,8,54,4 - -[Root.Include Files.Include Files\board.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h] ElemType=File @@ -3388,74 +2078,6 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h ElemType=Folder PathName=Include Files\os\hal\stm8 Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h -Config.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0 -Config.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0] -Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1] -Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,2,8,54,4 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h] ElemType=File @@ -3481,74 +2103,6 @@ ElemType=Folder PathName=Include Files\os\kernel Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\port -Config.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0 -Config.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0] -Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1] -Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,2,8,54,4 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] ElemType=File @@ -3663,74 +2217,6 @@ PathName=..\..\..\os\kernel\include\chvt.h ElemType=Folder PathName=Include Files\os\port Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\cosmic\stm8\chcore.h -Config.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0 -Config.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0] -Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1] -Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,2,8,54,4 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\cosmic\stm8\chcore.h] ElemType=File @@ -3745,74 +2231,6 @@ PathName=..\..\..\os\ports\cosmic\stm8\chtypes.h ElemType=Folder PathName=Include Files\test Child=Root.Include Files.Include Files\test...\..\..\test\test.h -Config.0=Root.Include Files.Include Files\test.Config.0 -Config.1=Root.Include Files.Include Files\test.Config.1 - -[Root.Include Files.Include Files\test.Config.0] -Settings.0.0=Root.Include Files.Include Files\test.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\test.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\test.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\test.Config.0.Settings.3 - -[Root.Include Files.Include Files\test.Config.1] -Settings.1.0=Root.Include Files.Include Files\test.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\test.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\test.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\test.Config.1.Settings.3 - -[Root.Include Files.Include Files\test.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\test.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\test.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\test.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 - -[Root.Include Files.Include Files\test.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,55 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\test.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,5,11,53,48 - -[Root.Include Files.Include Files\test.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=castm8 -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).ls -String.6.0=2010,6,2,8,54,4 - -[Root.Include Files.Include Files\test.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,5,25,14,45,56 [Root.Include Files.Include Files\test...\..\..\test\test.h] ElemType=File diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp index 4b388bc3e..b33235920 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -78,22 +78,22 @@ String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\sr [Root.Config.0.Settings.2] String.2.0= -String.6.0=2010,6,4,10,10,40 -String.100.0=STM8S105C6 +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,32,28 [Root.Config.0.Settings.4] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 +String.6.0=2010,11,12,20,27,7 [Root.Config.0.Settings.5] String.2.0=Running Pre-Link step @@ -106,8 +106,8 @@ String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(Toolse String.3.1=omf2elf $(OutputPath)$(TargetSName).aof String.4.0=$(OutputPath)$(TargetFName) String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map -String.6.0=2010,6,4,12,15,0 -String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.6.0=2010,11,12,20,17,36 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x101) EEPROMSTART(0x1000) EEPROMSIZE(0x400) String.101.0= String.102.0= Int.0=0 @@ -130,7 +130,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -147,22 +147,22 @@ String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\sr [Root.Config.1.Settings.2] String.2.0= -String.6.0=2010,6,4,10,10,40 -String.100.0=STM8S105C6 +String.6.0=2010,11,12,20,6,17 +String.100.0=STM8L152C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Config.1.Settings.4] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Config.1.Settings.5] String.2.0=Running Pre-Link step @@ -174,9 +174,9 @@ String.2.0=Running Linker String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] NODEBUGLINES NODEBUGPUBLICS NODEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) String.3.1=omf2elf $(OutputPath)$(TargetSName).aof String.4.0=$(OutputPath)$(TargetFName) -String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map -String.6.0=2010,6,4,12,15,0 -String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400) +String.5.0= +String.6.0=2010,11,12,20,27,7 +String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x101) EEPROMSTART(0x1000) EEPROMSIZE(0x400) String.101.0= String.102.0= Int.0=0 @@ -219,17 +219,17 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,32,28 [Root.Source Files.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -246,17 +246,17 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -283,7 +283,7 @@ Settings.1.1=Root.Source Files...\demo\main.c.Config.1.Settings.1 Settings.1.2=Root.Source Files...\demo\main.c.Config.1.Settings.2 [Root.Source Files...\demo\main.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,12,31 +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 @@ -297,14 +297,14 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug [Root.Source Files...\demo\main.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,12,31 +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 @@ -318,11 +318,10 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\board] ElemType=Folder @@ -345,24 +344,24 @@ Settings.1.2=Root.Source Files.Source Files\board.Config.1.Settings.2 Settings.1.3=Root.Source Files.Source Files\board.Config.1.Settings.3 [Root.Source Files.Source Files\board.Config.0.Settings.0] -String.6.0=2010,6,4,10,11,42 +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\board.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\board.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -372,24 +371,24 @@ String.5.0= String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\board.Config.1.Settings.0] -String.6.0=2010,6,4,10,11,42 +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\board.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\board.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -401,59 +400,6 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c] ElemType=File PathName=..\..\..\boards\st_stm8l_discovery\board.c -Config.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0 -Config.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\board...\..\..\boards\st_stm8l_discovery\board.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 [Root.Source Files.Source Files\os] ElemType=Folder @@ -482,24 +428,24 @@ Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Sett Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.0] -String.6.0=2010,6,4,10,13,32 +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -509,24 +455,24 @@ String.5.0= String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.0] -String.6.0=2010,6,4,10,13,32 +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -539,2511 +485,1328 @@ String.6.0=2010,6,4,10,10,40 ElemType=File PathName=..\..\..\os\hal\src\spi.c Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] +ElemType=File +PathName=..\..\..\os\hal\src\serial.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] +ElemType=File +PathName=..\..\..\os\hal\src\pwm.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] +ElemType=File +PathName=..\..\..\os\hal\src\pal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c] +ElemType=File +PathName=..\..\..\os\hal\src\mmc_spi.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c] +ElemType=File +PathName=..\..\..\os\hal\src\mac.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c] +ElemType=File +PathName=..\..\..\os\hal\src\hal.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c] +ElemType=File +PathName=..\..\..\os\hal\src\can.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c + +[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c] +ElemType=File +PathName=..\..\..\os\hal\src\adc.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +ElemType=Folder +PathName=Source Files\os\hal\stm8 +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c + +[Root.Source Files.Source Files\os.Source Files\os\kernel] +ElemType=Folder +PathName=Source Files\os\kernel +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\port + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] ElemType=File -PathName=..\..\..\os\hal\src\serial.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1 +PathName=..\..\..\os\kernel\src\chvt.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,26,10 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,29,17 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,26,10 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\serial.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,29,17 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c] ElemType=File -PathName=..\..\..\os\hal\src\pwm.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1 +PathName=..\..\..\os\kernel\src\chthreads.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pwm.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c] ElemType=File -PathName=..\..\..\os\hal\src\pal.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1 +PathName=..\..\..\os\kernel\src\chsys.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\pal.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c] ElemType=File -PathName=..\..\..\os\hal\src\mmc_spi.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1 +PathName=..\..\..\os\kernel\src\chsem.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mmc_spi.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c] ElemType=File -PathName=..\..\..\os\hal\src\mac.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1 +PathName=..\..\..\os\kernel\src\chschd.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\mac.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] ElemType=File -PathName=..\..\..\os\hal\src\hal.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1 +PathName=..\..\..\os\kernel\src\chregistry.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\hal.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] ElemType=File -PathName=..\..\..\os\hal\src\can.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.2 +PathName=..\..\..\os\kernel\src\chqueues.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\can.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c] -ElemType=File -PathName=..\..\..\os\hal\src\adc.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] -ElemType=Folder -PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\os.Source Files\os\kernel] -ElemType=Folder -PathName=Source Files\os\kernel -Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c -Next=Root.Source Files.Source Files\os.Source Files\os\port - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chdynamic.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chvt.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,31 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,31 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chthreads.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,31 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,31 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chsys.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,30 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,30 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chsem.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,30 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,30 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chschd.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,30 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,30 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chregistry.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,29 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,29 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chqueues.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,29 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,29 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chmtx.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chmsg.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chmempools.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chmemcore.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,28 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chmboxes.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chlists.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chheap.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chevents.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chdebug.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chcond.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] -String.6.0=2010,6,4,10,14,27 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 -String.8.0=Release - -[Root.Source Files.Source Files\os.Source Files\os\port] -ElemType=Folder -PathName=Source Files\os\port -Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 -Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 -Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] -String.6.0=2010,6,4,10,13,43 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] -String.6.0=2010,6,4,10,13,43 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c] -ElemType=File -PathName=..\..\..\os\ports\rc\stm8\chcore.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\test] -ElemType=Folder -PathName=Source Files\test -Child=Root.Source Files.Source Files\test...\..\..\test\testthd.c -Config.0=Root.Source Files.Source Files\test.Config.0 -Config.1=Root.Source Files.Source Files\test.Config.1 - -[Root.Source Files.Source Files\test.Config.0] -Settings.0.0=Root.Source Files.Source Files\test.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test.Config.0.Settings.2 -Settings.0.3=Root.Source Files.Source Files\test.Config.0.Settings.3 - -[Root.Source Files.Source Files\test.Config.1] -Settings.1.0=Root.Source Files.Source Files\test.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test.Config.1.Settings.2 -Settings.1.3=Root.Source Files.Source Files\test.Config.1.Settings.3 - -[Root.Source Files.Source Files\test.Config.0.Settings.0] -String.6.0=2010,6,4,10,11,52 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\test.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 - -[Root.Source Files.Source Files\test.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 - -[Root.Source Files.Source Files\test.Config.0.Settings.3] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test.Config.1.Settings.0] -String.6.0=2010,6,4,10,11,52 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\test.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\test.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\test.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] ElemType=File -PathName=..\..\..\test\testthd.c -Next=Root.Source Files.Source Files\test...\..\..\test\testsem.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1 +PathName=..\..\..\os\kernel\src\chmtx.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testthd.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] ElemType=File -PathName=..\..\..\test\testsem.c -Next=Root.Source Files.Source Files\test...\..\..\test\testqueues.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1 +PathName=..\..\..\os\kernel\src\chmsg.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testsem.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] ElemType=File -PathName=..\..\..\test\testqueues.c -Next=Root.Source Files.Source Files\test...\..\..\test\testpools.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1 +PathName=..\..\..\os\kernel\src\chmempools.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testqueues.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] ElemType=File -PathName=..\..\..\test\testpools.c -Next=Root.Source Files.Source Files\test...\..\..\test\testmtx.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1 +PathName=..\..\..\os\kernel\src\chmemcore.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testpools.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] ElemType=File -PathName=..\..\..\test\testmtx.c -Next=Root.Source Files.Source Files\test...\..\..\test\testmsg.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1 +PathName=..\..\..\os\kernel\src\chmboxes.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testmtx.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] ElemType=File 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Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testmsg.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] ElemType=File -PathName=..\..\..\test\testmbox.c -Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1 +PathName=..\..\..\os\kernel\src\chheap.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,26,10 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,29,17 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,26,10 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testmbox.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,29,17 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] ElemType=File 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Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testheap.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] ElemType=File -PathName=..\..\..\test\testevt.c -Next=Root.Source Files.Source Files\test...\..\..\test\testdyn.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1 +PathName=..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testevt.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] ElemType=File -PathName=..\..\..\test\testdyn.c -Next=Root.Source Files.Source Files\test...\..\..\test\testbmk.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1 +PathName=..\..\..\os\kernel\src\chcond.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testdyn.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c] -ElemType=File -PathName=..\..\..\test\testbmk.c -Next=Root.Source Files.Source Files\test...\..\..\test\test.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1 +[Root.Source Files.Source Files\os.Source Files\os\port] +ElemType=Folder +PathName=Source Files\os\port +Child=Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\testbmk.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Source Files.Source Files\test...\..\..\test\test.c] +[Root.Source Files.Source Files\os.Source Files\os\port...\..\..\os\ports\rc\stm8\chcore.c] ElemType=File -PathName=..\..\..\test\test.c -Config.0=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0 -Config.1=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1 +PathName=..\..\..\os\ports\rc\stm8\chcore.c -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.2 +[Root.Source Files.Source Files\test] +ElemType=Folder +PathName=Source Files\test +Child=Root.Source Files.Source Files\test...\..\..\test\testthd.c +Config.0=Root.Source Files.Source Files\test.Config.0 +Config.1=Root.Source Files.Source Files\test.Config.1 + +[Root.Source Files.Source Files\test.Config.0] +Settings.0.0=Root.Source Files.Source Files\test.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\test.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\test.Config.0.Settings.2 +Settings.0.3=Root.Source Files.Source Files\test.Config.0.Settings.3 -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.2 +[Root.Source Files.Source Files\test.Config.1] +Settings.1.0=Root.Source Files.Source Files\test.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\test.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\test.Config.1.Settings.2 +Settings.1.3=Root.Source Files.Source Files\test.Config.1.Settings.3 -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 +[Root.Source Files.Source Files\test.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.1] +[Root.Source Files.Source Files\test.Config.0.Settings.1] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\test.Config.0.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 + +[Root.Source Files.Source Files\test.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.0.Settings.2] +[Root.Source Files.Source Files\test.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 -String.8.0=Debug +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 +[Root.Source Files.Source Files\test.Config.1.Settings.2] +String.2.0=Assembling $(InputFile)... +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.1] +[Root.Source Files.Source Files\test.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,6,4,10,10,40 -[Root.Source Files.Source Files\test...\..\..\test\test.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +[Root.Source Files.Source Files\test...\..\..\test\testthd.c] +ElemType=File +PathName=..\..\..\test\testthd.c +Next=Root.Source Files.Source Files\test...\..\..\test\testsem.c + +[Root.Source Files.Source Files\test...\..\..\test\testsem.c] +ElemType=File +PathName=..\..\..\test\testsem.c +Next=Root.Source Files.Source Files\test...\..\..\test\testqueues.c + +[Root.Source Files.Source Files\test...\..\..\test\testqueues.c] +ElemType=File +PathName=..\..\..\test\testqueues.c +Next=Root.Source Files.Source Files\test...\..\..\test\testpools.c + +[Root.Source Files.Source Files\test...\..\..\test\testpools.c] +ElemType=File +PathName=..\..\..\test\testpools.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmtx.c + +[Root.Source Files.Source Files\test...\..\..\test\testmtx.c] +ElemType=File +PathName=..\..\..\test\testmtx.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmsg.c + +[Root.Source Files.Source Files\test...\..\..\test\testmsg.c] +ElemType=File +PathName=..\..\..\test\testmsg.c +Next=Root.Source Files.Source Files\test...\..\..\test\testmbox.c + +[Root.Source Files.Source Files\test...\..\..\test\testmbox.c] +ElemType=File +PathName=..\..\..\test\testmbox.c +Next=Root.Source Files.Source Files\test...\..\..\test\testheap.c + +[Root.Source Files.Source Files\test...\..\..\test\testheap.c] +ElemType=File +PathName=..\..\..\test\testheap.c +Next=Root.Source Files.Source Files\test...\..\..\test\testevt.c + +[Root.Source Files.Source Files\test...\..\..\test\testevt.c] +ElemType=File +PathName=..\..\..\test\testevt.c +Next=Root.Source Files.Source Files\test...\..\..\test\testdyn.c + +[Root.Source Files.Source Files\test...\..\..\test\testdyn.c] +ElemType=File +PathName=..\..\..\test\testdyn.c +Next=Root.Source Files.Source Files\test...\..\..\test\testbmk.c + +[Root.Source Files.Source Files\test...\..\..\test\testbmk.c] +ElemType=File +PathName=..\..\..\test\testbmk.c +Next=Root.Source Files.Source Files\test...\..\..\test\test.c + +[Root.Source Files.Source Files\test...\..\..\test\test.c] +ElemType=File +PathName=..\..\..\test\test.c [Root.Include Files] ElemType=Folder @@ -3072,17 +1835,17 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 +String.6.0=2010,11,12,20,27,7 [Root.Include Files.Config.0.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 +String.6.0=2010,11,12,20,27,7 [Root.Include Files.Config.0.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -3099,17 +1862,17 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Include Files.Config.1.Settings.2] String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 +String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT MODESTM8 String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 +String.6.0=2010,11,12,20,27,7 [Root.Include Files.Config.1.Settings.3] String.2.0=Performing Custom Build on $(InputFile) @@ -3138,74 +1901,6 @@ ElemType=Folder PathName=Include Files\board Child=Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h Next=Root.Include Files.Include Files\os -Config.0=Root.Include Files.Include Files\board.Config.0 -Config.1=Root.Include Files.Include Files\board.Config.1 - -[Root.Include Files.Include Files\board.Config.0] -Settings.0.0=Root.Include Files.Include Files\board.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\board.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\board.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\board.Config.0.Settings.3 - -[Root.Include Files.Include Files\board.Config.1] -Settings.1.0=Root.Include Files.Include Files\board.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\board.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\board.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\board.Config.1.Settings.3 - -[Root.Include Files.Include Files\board.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\board.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 - -[Root.Include Files.Include Files\board.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 - -[Root.Include Files.Include Files\board.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Include Files.Include Files\board.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\board.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\board.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\board.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\board...\..\..\boards\st_stm8l_discovery\board.h] ElemType=File @@ -3277,74 +1972,6 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h ElemType=Folder PathName=Include Files\os\hal\stm8 Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h -Config.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0 -Config.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0] -Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1] -Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h] ElemType=File @@ -3370,74 +1997,6 @@ ElemType=Folder PathName=Include Files\os\kernel Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\port -Config.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0 -Config.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0] -Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1] -Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\os.Include Files\os\kernel.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] ElemType=File @@ -3552,74 +2111,6 @@ PathName=..\..\..\os\kernel\include\ch.h ElemType=Folder PathName=Include Files\os\port Child=Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h -Config.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0 -Config.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0] -Settings.0.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1] -Settings.1.0=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\os.Include Files\os\port.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\os.Include Files\os\port...\..\..\os\ports\rc\stm8\chtypes.h] ElemType=File @@ -3634,74 +2125,6 @@ PathName=..\..\..\os\ports\rc\stm8\chcore.h ElemType=Folder PathName=Include Files\test Child=Root.Include Files.Include Files\test...\..\..\test\testsem.h -Config.0=Root.Include Files.Include Files\test.Config.0 -Config.1=Root.Include Files.Include Files\test.Config.1 - -[Root.Include Files.Include Files\test.Config.0] -Settings.0.0=Root.Include Files.Include Files\test.Config.0.Settings.0 -Settings.0.1=Root.Include Files.Include Files\test.Config.0.Settings.1 -Settings.0.2=Root.Include Files.Include Files\test.Config.0.Settings.2 -Settings.0.3=Root.Include Files.Include Files\test.Config.0.Settings.3 - -[Root.Include Files.Include Files\test.Config.1] -Settings.1.0=Root.Include Files.Include Files\test.Config.1.Settings.0 -Settings.1.1=Root.Include Files.Include Files\test.Config.1.Settings.1 -Settings.1.2=Root.Include Files.Include Files\test.Config.1.Settings.2 -Settings.1.3=Root.Include Files.Include Files\test.Config.1.Settings.3 - -[Root.Include Files.Include Files\test.Config.0.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\test.Config.0.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,42,15 - -[Root.Include Files.Include Files\test.Config.0.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,46,5 - -[Root.Include Files.Include Files\test.Config.0.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Include Files.Include Files\test.Config.1.Settings.0] -String.6.0=2010,11,11,12,10,56 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Include Files.Include Files\test.Config.1.Settings.1] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\test.Config.1.Settings.2] -String.2.0=Assembling $(InputFile)... -String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET NOPR ERRORPRINT NOCOND NOLIST NOLISTINCLUDE NOGEN NOSB NOXREF MODESTM8 -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,6,26,17,22,23 - -[Root.Include Files.Include Files\test.Config.1.Settings.3] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 [Root.Include Files.Include Files\test...\..\..\test\testsem.h] ElemType=File -- cgit v1.2.3 From 9e53be4d3ccbd10f89bd14352c68d9c1b1dae80e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 12 Nov 2010 23:04:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2354 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp | 12 +++++++++++- .../STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp | 12 +++++++++++- 2 files changed, 22 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index 76cd87427..00ead83c6 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -657,7 +657,7 @@ String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] ElemType=File PathName=..\..\..\os\kernel\src\chevents.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 @@ -713,6 +713,11 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 String.8.0=Release +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c + [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] ElemType=File PathName=..\..\..\os\kernel\src\chheap.c @@ -1970,6 +1975,11 @@ Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\ker [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h] ElemType=File PathName=..\..\..\os\kernel\include\chevents.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chheap.h] diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index 254953e80..680eab87c 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -1386,7 +1386,7 @@ String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] ElemType=File PathName=..\..\..\os\kernel\src\chevents.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 @@ -1442,6 +1442,11 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 String.8.0=Release +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c + [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] ElemType=File PathName=..\..\..\os\kernel\src\chdebug.c @@ -2061,6 +2066,11 @@ Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\ker [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h] ElemType=File PathName=..\..\..\os\kernel\include\chevents.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h] -- cgit v1.2.3 From 688c495b28d6307050f370717c295f2f889e3b3c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 12 Nov 2010 23:07:49 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2355 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c index 522499fcc..459ac2e7a 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -59,7 +59,7 @@ void main(void) { /* * Activates the serial driver 1 using the driver default configuration. */ - sdStart(&SD1, NULL); +// sdStart(&SD1, NULL); /* * Creates the blinker thread. @@ -70,8 +70,8 @@ void main(void) { * Normal main() thread activity. */ while (TRUE) { - if (palReadPad(GPIOC, PC_BUTTON) == PAL_LOW) - TestThread(&SD1); +// if (palReadPad(GPIOC, PC_BUTTON) == PAL_LOW) +// TestThread(&SD1); chThdSleepMilliseconds(1000); } } -- cgit v1.2.3 From be60d348aa1f67e1c9a4667aa996318c1a43067f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Nov 2010 08:59:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2356 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 2 +- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 4 ++++ demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index 3186be527..40bb5dbb1 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -90,7 +90,7 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL TRUE +#define HAL_USE_SERIAL FALSE #endif /** diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c index 459ac2e7a..d0d7b4060 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -51,6 +51,10 @@ void main(void) { */ hwinit(); + palClearPad(GPIOC, PC_LED4); + palSetPad(GPIOE, PE_LED3); + while(1); + /* * OS initialization. */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h index d37723781..ea9759ad5 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h @@ -28,7 +28,7 @@ /* * HAL general settings. */ -#define STM8L_CLOCK_INIT TRUE +#define STM8L_NO_CLOCK_INIT TRUE #define STM8L_HSI_ENABLED TRUE #define STM8L_LSI_ENABLED TRUE #define STM8L_HSE_ENABLED FALSE -- cgit v1.2.3 From 11c89928eac9e2a9916940b8f634f3d96b60f17e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Nov 2010 09:41:55 +0000 Subject: STM8L Demo and PAL driver working now. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2357 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c | 2 +- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c index d35e6a51e..ea2f03c9a 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c @@ -211,7 +211,7 @@ exception_vector_t const _vectab[] = { {0x82, _unhandled_exception}, /* vector18 */ #endif -#if defined(_TIM2_OVERFLOW_ISR) || defined(_USART2_TRANSMIT_ISR) +#if defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) {0x82, vector19}, #else {0x82, _unhandled_exception}, /* vector19 */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c index d0d7b4060..6e61e0521 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -29,14 +29,14 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { - palClearPad(GPIOC, PC_LED4); - chThdSleepMilliseconds(500); palSetPad(GPIOC, PC_LED4); chThdSleepMilliseconds(500); - palClearPad(GPIOE, PE_LED3); + palClearPad(GPIOC, PC_LED4); chThdSleepMilliseconds(500); palSetPad(GPIOE, PE_LED3); chThdSleepMilliseconds(500); + palClearPad(GPIOE, PE_LED3); + chThdSleepMilliseconds(500); } return 0; } @@ -51,10 +51,6 @@ void main(void) { */ hwinit(); - palClearPad(GPIOC, PC_LED4); - palSetPad(GPIOE, PE_LED3); - while(1); - /* * OS initialization. */ -- cgit v1.2.3 From 1d6a32367685583864d10cba03102578e15f04c8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Nov 2010 09:59:02 +0000 Subject: STM8L clock initialization now apparently working. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2358 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h index ea9759ad5..69a205fb6 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h @@ -28,7 +28,7 @@ /* * HAL general settings. */ -#define STM8L_NO_CLOCK_INIT TRUE +#define STM8L_NO_CLOCK_INIT FALSE #define STM8L_HSI_ENABLED TRUE #define STM8L_LSI_ENABLED TRUE #define STM8L_HSE_ENABLED FALSE -- cgit v1.2.3 From bb6d225f57811ded378ffcb2457454decdb98e1c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 13 Nov 2010 16:59:32 +0000 Subject: Initial STM8L support. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2359 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw | 2 +- .../cosmic/cosmic.stp | 187 ++++++++++--------- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 2 +- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 16 +- .../raisonance/raisonance.stp | 200 ++++++++++++--------- 5 files changed, 229 insertions(+), 178 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw index 015f8e015..a6630271a 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/ChibiOS-RT.stw @@ -12,5 +12,5 @@ Filename=raisonance\raisonance.stp Dependencies= [Options] ActiveProject=cosmic -ActiveConfig=Debug +ActiveConfig=Release AddSortedElements=0 diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp index d0f4755c8..6f1accdef 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -83,7 +83,7 @@ String.100.0=STM8L152C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,31,15 @@ -106,22 +106,22 @@ String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeIntege String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 String.4.0=$(OutputPath)$(TargetFName) String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map -String.6.0=2010,11,12,20,41,51 +String.6.0=2010,11,13,11,54,55 String.100.0= String.101.0=crtsi.st7 String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it String.102.1=+seg .text -a .const -n .text String.102.2=+seg .eeprom -b 0x1000 -m 0x400 -n .eeprom -String.102.3=+seg .bsct -b 0x0 -m 0x100 -n .bsct +String.102.3=+seg .bsct -b 0x0 -m 0x40 -n .bsct String.102.4=+seg .ubsct -a .bsct -n .ubsct String.102.5=+seg .bit -a .ubsct -n .bit -id String.102.6=+seg .share -a .bit -n .share -is -String.102.7=+seg .data -b 0x100 -m 0x700 -n .data +String.102.7=+seg .data -b 0x40 -m 0x7c0 -n .data String.102.8=+seg .bss -a .data -n .bss String.103.0=Code,Constants[0x8080-0xffff]=.const,.text String.103.1=Eeprom[0x1000-0x13ff]=.eeprom -String.103.2=Zero Page[0x0-0xff]=.bsct,.ubsct,.bit,.share -String.103.3=Ram[0x100-0x7ff]=.data,.bss +String.103.2=Zero Page[0x0-0x3f]=.bsct,.ubsct,.bit,.share +String.103.3=Ram[0x40-0x7ff]=.data,.bss String.104.0=0x7ff String.105.0=libis0.sm8;libm0.sm8 Int.0=0 @@ -166,7 +166,7 @@ String.100.0=STM8L152C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,31,15 @@ -189,22 +189,22 @@ String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeIntege String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8 String.4.0=$(OutputPath)$(TargetFName) String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map -String.6.0=2010,11,12,20,32,28 +String.6.0=2010,11,13,11,54,55 String.100.0= String.101.0=crtsi.st7 String.102.0=+seg .const -b 0x8080 -m 0x7f80 -n .const -it String.102.1=+seg .text -a .const -n .text String.102.2=+seg .eeprom -b 0x1000 -m 0x400 -n .eeprom -String.102.3=+seg .bsct -b 0x0 -m 0x100 -n .bsct +String.102.3=+seg .bsct -b 0x0 -m 0x40 -n .bsct String.102.4=+seg .ubsct -a .bsct -n .ubsct String.102.5=+seg .bit -a .ubsct -n .bit -id String.102.6=+seg .share -a .bit -n .share -is -String.102.7=+seg .data -b 0x100 -m 0x700 -n .data +String.102.7=+seg .data -b 0x40 -m 0x7c0 -n .data String.102.8=+seg .bss -a .data -n .bss String.103.0=Code,Constants[0x8080-0xffff]=.const,.text String.103.1=Eeprom[0x1000-0x13ff]=.eeprom -String.103.2=Zero Page[0x0-0xff]=.bsct,.ubsct,.bit,.share -String.103.3=Ram[0x100-0x7ff]=.data,.bss +String.103.2=Zero Page[0x0-0x3f]=.bsct,.ubsct,.bit,.share +String.103.3=Ram[0x40-0x7ff]=.data,.bss String.104.0=0x7ff String.105.0=libisl0.sm8;libm0.sm8 Int.0=0 @@ -247,7 +247,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,31,15 @@ -274,7 +274,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,31,15 @@ -325,7 +325,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files...\demo\main.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -346,7 +346,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -384,7 +384,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.vectors.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -405,7 +405,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.vectors.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -439,7 +439,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -466,7 +466,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -523,7 +523,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -550,7 +550,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -612,29 +612,29 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\s [Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c] ElemType=File PathName=..\..\..\os\hal\src\spi.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L] ElemType=Folder -PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c +PathName=Source Files\os\hal\STM8L +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\shared_isr.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\shared_isr.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c @@ -676,7 +676,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -697,7 +697,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -735,7 +735,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -756,7 +756,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -794,7 +794,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -815,7 +815,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -853,7 +853,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -874,7 +874,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -912,7 +912,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,28,21 @@ -933,7 +933,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +mods0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,28,21 @@ -971,7 +971,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -992,7 +992,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1030,7 +1030,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1051,7 +1051,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1089,7 +1089,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1110,7 +1110,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1148,7 +1148,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1169,7 +1169,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1207,7 +1207,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1228,7 +1228,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1266,7 +1266,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1287,7 +1287,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1325,7 +1325,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1346,7 +1346,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1384,7 +1384,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1405,7 +1405,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1443,7 +1443,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1464,7 +1464,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1502,7 +1502,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1523,7 +1523,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1561,7 +1561,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1582,7 +1582,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1620,7 +1620,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1641,7 +1641,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1678,7 +1678,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,28,21 @@ -1699,7 +1699,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +mods0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,28,21 @@ -1732,7 +1732,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1759,7 +1759,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1809,7 +1809,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1836,7 +1836,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1941,7 +1941,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -1968,7 +1968,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\..\..\os\hal\platforms\stm8l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 @@ -2072,29 +2072,44 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\in [Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\spi.h] ElemType=File PathName=..\..\..\os\hal\include\spi.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8 +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L] ElemType=Folder -PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h +PathName=Include Files\os\hal\STM8L +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_mdp.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_mdp.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_mdp.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_md.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_md.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_md.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_hd.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_hd.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_hd.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\stm8l15x.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\stm8l15x.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index 40bb5dbb1..3186be527 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -90,7 +90,7 @@ * @brief Enables the SERIAL subsystem. */ #if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL FALSE +#define HAL_USE_SERIAL TRUE #endif /** diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c index 6e61e0521..d1545a84d 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -30,13 +30,13 @@ static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { palSetPad(GPIOC, PC_LED4); - chThdSleepMilliseconds(500); + chThdSleepMilliseconds(250); palClearPad(GPIOC, PC_LED4); - chThdSleepMilliseconds(500); + chThdSleepMilliseconds(250); palSetPad(GPIOE, PE_LED3); - chThdSleepMilliseconds(500); + chThdSleepMilliseconds(250); palClearPad(GPIOE, PE_LED3); - chThdSleepMilliseconds(500); + chThdSleepMilliseconds(250); } return 0; } @@ -58,8 +58,10 @@ void main(void) { /* * Activates the serial driver 1 using the driver default configuration. + * The STM8L-Discovery requires USART1 pins remapping on PA2 and PA3. */ -// sdStart(&SD1, NULL); + SYSCFG->RMPCR1 = 0x1C; + sdStart(&SD1, NULL); /* * Creates the blinker thread. @@ -70,8 +72,8 @@ void main(void) { * Normal main() thread activity. */ while (TRUE) { -// if (palReadPad(GPIOC, PC_BUTTON) == PAL_LOW) -// TestThread(&SD1); + if (palReadPad(GPIOC, PC_BUTTON) == PAL_LOW) + TestThread(&SD1); chThdSleepMilliseconds(1000); } } diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp index b33235920..be7b81a1c 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -83,7 +83,7 @@ String.100.0=STM8L152C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,32,28 @@ -105,8 +105,8 @@ String.2.0=Running Linker String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(ToolsetLibOpts) -CustomOutFile[$(ProjectSFile).elf] DEBUGLINES DEBUGPUBLICS DEBUGSYMBOLS -CustomRunHexConv -customMapFile -customMapFilePR($(OutputPath)$(TargetSName).map) String.3.1=omf2elf $(OutputPath)$(TargetSName).aof String.4.0=$(OutputPath)$(TargetFName) -String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map -String.6.0=2010,11,12,20,17,36 +String.5.0= +String.6.0=2010,11,13,16,33,31 String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x101) EEPROMSTART(0x1000) EEPROMSIZE(0x400) String.101.0= String.102.0= @@ -139,11 +139,11 @@ String.107.0=$(ProjectSFile).elf Int.108=0 [Root.Config.1.Settings.1] -String.6.0=2010,6,4,10,10,40 +String.6.0=2010,11,13,17,40,20 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8;..\..\..\os\hal\platforms\stm8l; +String.103.0=.\;..\demo;..\..\..\boards\st_stm8l_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\os\ports\rc\stm8;..\..\..\os\hal\platforms\stm8l;..\..\..\test; [Root.Config.1.Settings.2] String.2.0= @@ -152,7 +152,7 @@ String.100.0=STM8L152C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -175,7 +175,7 @@ String.3.0=rlstm8 -P $(ObjectFiles) TO($(OutputPath)$(TargetSName).aof) $(Toolse String.3.1=omf2elf $(OutputPath)$(TargetSName).aof String.4.0=$(OutputPath)$(TargetFName) String.5.0= -String.6.0=2010,11,12,20,27,7 +String.6.0=2010,11,13,16,33,31 String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x101) EEPROMSTART(0x1000) EEPROMSIZE(0x400) String.101.0= String.102.0= @@ -219,7 +219,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,32,28 @@ -246,7 +246,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -297,7 +297,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -318,10 +318,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\board] ElemType=Folder @@ -351,7 +352,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -378,7 +379,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -435,7 +436,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -462,7 +463,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -524,31 +525,31 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\a [Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c] ElemType=File PathName=..\..\..\os\hal\src\adc.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L] ElemType=Folder -PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c +PathName=Source Files\os\hal\STM8L +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\shared_isr.c] -ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c - -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\shared_isr.c + +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\shared_isr.c] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder @@ -588,7 +589,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -609,10 +610,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] ElemType=File @@ -646,7 +648,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,29,17 @@ -667,10 +669,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,29,17 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c] ElemType=File @@ -704,7 +707,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -725,10 +728,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c] ElemType=File @@ -762,7 +766,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -783,10 +787,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c] ElemType=File @@ -820,7 +825,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -841,10 +846,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c] ElemType=File @@ -878,7 +884,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -899,10 +905,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c] ElemType=File @@ -936,7 +943,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -957,10 +964,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c] ElemType=File @@ -994,7 +1002,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1015,10 +1023,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c] ElemType=File @@ -1052,7 +1061,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1073,10 +1082,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c] ElemType=File @@ -1110,7 +1120,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1131,10 +1141,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c] ElemType=File @@ -1168,7 +1179,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1189,10 +1200,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c] ElemType=File @@ -1226,7 +1238,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1247,10 +1259,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c] ElemType=File @@ -1284,7 +1297,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1305,10 +1318,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c] ElemType=File @@ -1342,7 +1356,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1363,10 +1377,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c] ElemType=File @@ -1400,7 +1415,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,29,17 @@ -1421,10 +1436,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,29,17 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] ElemType=File @@ -1458,7 +1474,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1479,10 +1495,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] ElemType=File @@ -1516,7 +1533,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1537,10 +1554,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] ElemType=File @@ -1573,7 +1591,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1594,10 +1612,11 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 +String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\port] ElemType=Folder @@ -1626,7 +1645,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1653,7 +1672,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1703,7 +1722,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1730,7 +1749,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1835,7 +1854,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1862,7 +1881,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 @@ -1966,31 +1985,46 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\in [Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\adc.h] ElemType=File PathName=..\..\..\os\hal\include\adc.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8 +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L] ElemType=Folder -PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h +PathName=Include Files\os\hal\STM8L +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\serial_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\pal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_mdp.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\stm8l15x.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_mdp.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_mdp.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_md.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8l\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_md.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_md.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_hd.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_hd.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\hal_lld_stm8l_hd.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\hal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\stm8l15x.h + +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\STM8L...\..\..\os\hal\platforms\stm8l\stm8l15x.h] +ElemType=File +PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder -- cgit v1.2.3 From 208c4fe1ef35eb7ae8c1dc63f6137da9010dec3f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 14 Nov 2010 19:17:44 +0000 Subject: Single and improved STM32 vectors file. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2367 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 3 +-- demos/ARMCM3-STM32F103-GCC/Makefile | 3 +-- demos/ARMCM3-STM32F107-GCC/Makefile | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index 56fc2d719..a90ae3ded 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -103,8 +103,7 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors_md.s +ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 28a353c37..460f602ee 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -101,8 +101,7 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors_md.s +ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-STM32F107-GCC/Makefile b/demos/ARMCM3-STM32F107-GCC/Makefile index 647bdd3ce..c4e2a6a0a 100644 --- a/demos/ARMCM3-STM32F107-GCC/Makefile +++ b/demos/ARMCM3-STM32F107-GCC/Makefile @@ -101,8 +101,7 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/vectors_cl.s +ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From 5962467685985de2d79a85a1fcf8b1961d3d72de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 15 Nov 2010 19:44:09 +0000 Subject: Added STM32VL-Discovery demo. Changes to all the board files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2370 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile | 204 ++++++++++ demos/ARMCM3-STM32F100-DISCOVERY-GCC/ch.ld | 113 ++++++ demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h | 507 ++++++++++++++++++++++++ demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h | 263 ++++++++++++ demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 73 ++++ demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h | 117 ++++++ demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt | 28 ++ 7 files changed, 1305 insertions(+) create mode 100644 demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile create mode 100644 demos/ARMCM3-STM32F100-DISCOVERY-GCC/ch.ld create mode 100644 demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h create mode 100644 demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h create mode 100644 demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c create mode 100644 demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h create mode 100644 demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile new file mode 100644 index 000000000..f474b8b9d --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile @@ -0,0 +1,204 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable register caching optimization (read documentation). +ifeq ($(USE_CURRP_CACHING),) + USE_CURRP_CACHING = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Enable this if you really want to use the STM FWLib. +ifeq ($(USE_FWLIB),) + USE_FWLIB = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Define linker script file here +LDSCRIPT= ch.ld + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/ST_STM32VL_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m3 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DCORTEX_USE_BASEPRI=TRUE + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +ifeq ($(USE_FWLIB),yes) + include $(CHIBIOS)/ext/stm32lib/stm32lib.mk + CSRC += $(STM32SRC) + INCDIR += $(STM32INC) + USE_OPT += -DUSE_STDPERIPH_DRIVER +endif + +include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/ch.ld b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/ch.ld new file mode 100644 index 000000000..4ec9bdabd --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/ch.ld @@ -0,0 +1,113 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * ST32F100xB memory setup. + */ +__main_stack_size__ = 0x0400; +__process_stack_size__ = 0x0400; +__stacks_total_size__ = __main_stack_size__ + __process_stack_size__; + +MEMORY +{ + flash : org = 0x08000000, len = 128k + ram : org = 0x20000000, len = 8k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + + .text : ALIGN(16) SUBALIGN(16) + { + _text = .; + KEEP(*(vectors)) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ctors : + { + PROVIDE(_ctors_start_ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(_ctors_end_ = .); + } > flash + + .dtors : + { + PROVIDE(_dtors_start_ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(_dtors_end_ = .); + } > flash + + .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)} + + __exidx_start = .; + .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash + __exidx_end = .; + + .eh_frame_hdr : {*(.eh_frame_hdr)} + + .eh_frame : ONLY_IF_RO {*(.eh_frame)} + + . = ALIGN(4); + _etext = .; + _textdata = _etext; + + .data : + { + _data = .; + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + _edata = .; + } > ram AT > flash + + .bss : + { + _bss_start = .; + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__ - __stacks_total_size__; diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h new file mode 100644 index 000000000..98bcdc40c --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h @@ -0,0 +1,507 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note T he default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h new file mode 100644 index 000000000..3186be527 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h @@ -0,0 +1,263 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +/* + * + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c new file mode 100644 index 000000000..05f0712e4 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -0,0 +1,73 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palSetPad(GPIOC, GPIOC_LED4); + chThdSleepMilliseconds(250); + palClearPad(GPIOC, GPIOC_LED4); + chThdSleepMilliseconds(250); + palSetPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(250); + palClearPad(GPIOC, GPIOC_LED3); + chThdSleepMilliseconds(250); + } + return 0; +} + +/* + * Entry point, note, the main() function is already a thread in the system + * on entry. + */ +int main(int argc, char **argv) { + + (void)argc; + (void)argv; + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD1); + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h new file mode 100644 index 000000000..d1ad23373 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h @@ -0,0 +1,117 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 3 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV1 +#define STM32_PPRE2 STM32_PPRE2_DIV1 +#define STM32_ADCPRE STM32_ADCPRE_DIV2 +#define STM32_MCO STM32_MCO_NOCLOCK + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 3 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_PWM1_IRQ_PRIORITY 7 +#define STM32_PWM_PWM2_IRQ_PRIORITY 7 +#define STM32_PWM_PWM3_IRQ_PRIORITY 7 +#define STM32_PWM_PWM4_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 2 +#define STM32_SPI_SPI2_DMA_PRIORITY 2 +#define STM32_SPI_SPI3_DMA_PRIORITY 2 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt() diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt new file mode 100644 index 000000000..f2f69f7c6 --- /dev/null +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt @@ -0,0 +1,28 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M3 STM32F100xB. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32VL-Discovery board. + +** The Demo ** + +The demo flashes the board LEDs using a thread, by pressing the button located +on the board the test procedure is activated with output on the serial port +COM1 (USART1). + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distribited +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com -- cgit v1.2.3 From 354bd66eb083691cab4c2c29b32a836805ac5edc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 16 Nov 2010 18:39:47 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2371 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h | 24 +++++++++++----------- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h | 9 ++++++-- demos/STM8S-STM8S208-RC/mcuconf.h | 23 +++++++++++++++------ 3 files changed, 36 insertions(+), 20 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h index 69a205fb6..27a71ee9c 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h @@ -28,19 +28,19 @@ /* * HAL general settings. */ -#define STM8L_NO_CLOCK_INIT FALSE -#define STM8L_HSI_ENABLED TRUE -#define STM8L_LSI_ENABLED TRUE -#define STM8L_HSE_ENABLED FALSE -#define STM8L_LSE_ENABLED TRUE -#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI -#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1 -#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_LSE -#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1 +#define STM8L_NO_CLOCK_INIT FALSE +#define STM8L_HSI_ENABLED TRUE +#define STM8L_LSI_ENABLED TRUE +#define STM8L_HSE_ENABLED FALSE +#define STM8L_LSE_ENABLED TRUE +#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI +#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1 +#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_LSE +#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1 /* * SERIAL driver system settings. */ -#define STM8L_SERIAL_USE_USART1 TRUE -#define STM8L_SERIAL_USE_USART2 FALSE -#define STM8L_SERIAL_USE_USART3 FALSE +#define STM8L_SERIAL_USE_USART1 TRUE +#define STM8L_SERIAL_USE_USART2 FALSE +#define STM8L_SERIAL_USE_USART3 FALSE diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h index 757bba2ce..61b572a82 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h @@ -28,9 +28,14 @@ /* * HAL general settings. */ -#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI +#define STM8_NO_CLOCK_INIT FALSE +#define STM8_HSI_ENABLED FALSE +#define STM8_LSI_ENABLED TRUE +#define STM8_HSE_ENABLED TRUE +#define STM8_SYSCLK_SOURCE CLK_SYSSEL_HSE #define STM8_HSI_DIVIDER CLK_HSI_DIV1 #define STM8_CPU_DIVIDER CLK_CPU_DIV1 +#define STM8_CAN_DIVIDER_VALUE 1 /* * SERIAL driver system settings. @@ -42,5 +47,5 @@ /* * SPI driver system settings. */ -#define STM8_SPI_USE_SPI FALSE +#define STM8_SPI_USE_SPI TRUE #define STM8_SPI_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/STM8S-STM8S208-RC/mcuconf.h b/demos/STM8S-STM8S208-RC/mcuconf.h index c2148ac5b..53b52fb2a 100644 --- a/demos/STM8S-STM8S208-RC/mcuconf.h +++ b/demos/STM8S-STM8S208-RC/mcuconf.h @@ -28,13 +28,24 @@ /* * HAL general settings. */ -#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI -#define STM8_HSI_DIVIDER CLK_HSI_DIV1 -#define STM8_CPU_DIVIDER CLK_CPU_DIV1 +#define STM8_NO_CLOCK_INIT FALSE +#define STM8_HSI_ENABLED FALSE +#define STM8_LSI_ENABLED TRUE +#define STM8_HSE_ENABLED TRUE +#define STM8_SYSCLK_SOURCE CLK_SYSSEL_HSI +#define STM8_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8_CPU_DIVIDER CLK_CPU_DIV1 +#define STM8_CAN_DIVIDER_VALUE 1 /* * SERIAL driver system settings. */ -#define USE_STM8_UART1 TRUE -#define USE_STM8_UART2 FALSE -#define USE_STM8_UART3 FALSE +#define USE_STM8_UART1 TRUE +#define USE_STM8_UART2 FALSE +#define USE_STM8_UART3 FALSE + +/* + * SPI driver system settings. + */ +#define STM8_SPI_USE_SPI TRUE +#define STM8_SPI_ERROR_HOOK(spip) chSysHalt() -- cgit v1.2.3 From 6eaff61f5552943434ccb81bc40a42af80a100c3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 17 Nov 2010 08:06:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2376 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 2 +- demos/ARMCM3-LPC1343-GCC/Makefile | 2 +- demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F107-GCC/Makefile | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index 5c481ec20..ee2ca97bc 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -189,4 +189,4 @@ ULIBS = # End of user defines ############################################################################## -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-LPC1343-GCC/Makefile b/demos/ARMCM3-LPC1343-GCC/Makefile index 0bc5276b4..173685b26 100644 --- a/demos/ARMCM3-LPC1343-GCC/Makefile +++ b/demos/ARMCM3-LPC1343-GCC/Makefile @@ -190,4 +190,4 @@ ULIBS = # End of user defines ############################################################################## -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile index f474b8b9d..ef033772f 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile index a90ae3ded..f8733c3ae 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/Makefile @@ -204,4 +204,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 460f602ee..7b0e82f90 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM3-STM32F107-GCC/Makefile b/demos/ARMCM3-STM32F107-GCC/Makefile index c4e2a6a0a..bd265aef1 100644 --- a/demos/ARMCM3-STM32F107-GCC/Makefile +++ b/demos/ARMCM3-STM32F107-GCC/Makefile @@ -201,4 +201,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk -- cgit v1.2.3 From 605283dd163861b9ecc0a02f235007214c0c8064 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 17 Nov 2010 13:56:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2379 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/Makefile | 3 +-- demos/ARMCM3-LPC1343-GCC/Makefile | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/Makefile b/demos/ARMCM0-LPC1114-GCC/Makefile index ee2ca97bc..7ed1b6e78 100644 --- a/demos/ARMCM0-LPC1114-GCC/Makefile +++ b/demos/ARMCM0-LPC1114-GCC/Makefile @@ -96,8 +96,7 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/vectors.s +ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ diff --git a/demos/ARMCM3-LPC1343-GCC/Makefile b/demos/ARMCM3-LPC1343-GCC/Makefile index 173685b26..dc3cc484f 100644 --- a/demos/ARMCM3-LPC1343-GCC/Makefile +++ b/demos/ARMCM3-LPC1343-GCC/Makefile @@ -96,8 +96,7 @@ TCSRC = TCPPSRC = # List ASM source files here -ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC13xx/vectors.s +ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ -- cgit v1.2.3 From 4bdb862f3cde0aeac8a4c8af2c0a540f7f4cd991 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 17 Nov 2010 14:10:19 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2384 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c | 132 ++++++++-------- .../cosmic/cosmic.stp | 166 ++++++++++---------- .../STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c | 76 ++++----- .../raisonance/raisonance.stp | 170 ++++++++++----------- demos/STM8S-STM8S208-RC/ch.rapp | 10 +- 5 files changed, 277 insertions(+), 277 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c index ea2f03c9a..bd7ed41b5 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/vectors.c @@ -70,8 +70,8 @@ void _stext(void); * @brief Exception vector type. */ typedef struct { - uint8_t ev_instruction; - interrupt_handler_t ev_handler; + uint8_t ev_instruction; + interrupt_handler_t ev_handler; } exception_vector_t; /** @@ -81,7 +81,7 @@ typedef struct { */ @far @interrupt void _unhandled_exception (void) { - while (TRUE) + while (TRUE) ; } @@ -89,191 +89,191 @@ typedef struct { * @brief Exceptions table. */ exception_vector_t const _vectab[] = { - {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, (interrupt_handler_t)_stext}, /* reset */ #if defined(_TRAP_ISR) - {0x82, vector_trap}, + {0x82, vector_trap}, #else - {0x82, _unhandled_exception}, /* trap */ + {0x82, _unhandled_exception}, /* trap */ #endif #if defined(_TLI_ISR) - {0x82, vector0}, + {0x82, vector0}, #else - {0x82, _unhandled_exception}, /* vector0 */ + {0x82, _unhandled_exception}, /* vector0 */ #endif #if defined(_FLASH_ISR) - {0x82, vector1}, + {0x82, vector1}, #else - {0x82, _unhandled_exception}, /* vector1 */ + {0x82, _unhandled_exception}, /* vector1 */ #endif #if defined(_DMA10_ISR) || defined(_DMA11_ISR) - {0x82, vector2}, + {0x82, vector2}, #else - {0x82, _unhandled_exception}, /* vector2 */ + {0x82, _unhandled_exception}, /* vector2 */ #endif #if defined(_DMA12_ISR) || defined(_DMA13_ISR) - {0x82, vector3}, + {0x82, vector3}, #else - {0x82, _unhandled_exception}, /* vector3 */ + {0x82, _unhandled_exception}, /* vector3 */ #endif #if defined(_RTC_ISR) || defined(_LSE_CSS_ISR) - {0x82, vector4}, + {0x82, vector4}, #else - {0x82, _unhandled_exception}, /* vector4 */ + {0x82, _unhandled_exception}, /* vector4 */ #endif #if defined(_EXTIE_ISR) || defined(_EXTIF_ISR) || defined(_PVD_ISR) - {0x82, vector5}, + {0x82, vector5}, #else - {0x82, _unhandled_exception}, /* vector5 */ + {0x82, _unhandled_exception}, /* vector5 */ #endif #if defined(_EXTIB_ISR) || defined(_EXTIG_ISR) - {0x82, vector6}, + {0x82, vector6}, #else - {0x82, _unhandled_exception}, /* vector6 */ + {0x82, _unhandled_exception}, /* vector6 */ #endif #if defined(_EXTID_ISR) || defined(_EXTIH_ISR) - {0x82, vector7}, + {0x82, vector7}, #else - {0x82, _unhandled_exception}, /* vector7 */ + {0x82, _unhandled_exception}, /* vector7 */ #endif #if defined(_EXTI0_ISR) - {0x82, vector8}, + {0x82, vector8}, #else - {0x82, _unhandled_exception}, /* vector8 */ + {0x82, _unhandled_exception}, /* vector8 */ #endif #if defined(_EXTI1_ISR) - {0x82, vector9}, + {0x82, vector9}, #else - {0x82, _unhandled_exception}, /* vector9 */ + {0x82, _unhandled_exception}, /* vector9 */ #endif #if defined(_EXTI2_ISR) - {0x82, vector10}, + {0x82, vector10}, #else - {0x82, _unhandled_exception}, /* vector10 */ + {0x82, _unhandled_exception}, /* vector10 */ #endif #if defined(_EXTI3_ISR) - {0x82, vector11}, + {0x82, vector11}, #else - {0x82, _unhandled_exception}, /* vector11 */ + {0x82, _unhandled_exception}, /* vector11 */ #endif #if defined(_EXTI4_ISR) - {0x82, vector12}, + {0x82, vector12}, #else - {0x82, _unhandled_exception}, /* vector12 */ + {0x82, _unhandled_exception}, /* vector12 */ #endif #if defined(_EXTI5_ISR) - {0x82, vector13}, + {0x82, vector13}, #else - {0x82, _unhandled_exception}, /* vector13 */ + {0x82, _unhandled_exception}, /* vector13 */ #endif #if defined(_EXTI6_ISR) - {0x82, vector14}, + {0x82, vector14}, #else - {0x82, _unhandled_exception}, /* vector14 */ + {0x82, _unhandled_exception}, /* vector14 */ #endif #if defined(_EXTI7_ISR) - {0x82, vector15}, + {0x82, vector15}, #else - {0x82, _unhandled_exception}, /* vector15 */ + {0x82, _unhandled_exception}, /* vector15 */ #endif #if defined(_LCD_ISR) || defined(_AES_ISR) - {0x82, vector16}, + {0x82, vector16}, #else - {0x82, _unhandled_exception}, /* vector16 */ + {0x82, _unhandled_exception}, /* vector16 */ #endif #if defined(_CLK_ISR) || defined(_TIM1_BREAK_ISR) || defined(_DAC_ISR) - {0x82, vector17}, + {0x82, vector17}, #else - {0x82, _unhandled_exception}, /* vector17 */ + {0x82, _unhandled_exception}, /* vector17 */ #endif #if defined(_COMP1_ISR) || defined(_COMP2_ISR) || defined(_ADC1_ISR) - {0x82, vector18}, + {0x82, vector18}, #else - {0x82, _unhandled_exception}, /* vector18 */ + {0x82, _unhandled_exception}, /* vector18 */ #endif #if defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) - {0x82, vector19}, + {0x82, vector19}, #else - {0x82, _unhandled_exception}, /* vector19 */ + {0x82, _unhandled_exception}, /* vector19 */ #endif #if defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) - {0x82, vector20}, + {0x82, vector20}, #else - {0x82, _unhandled_exception}, /* vector20 */ + {0x82, _unhandled_exception}, /* vector20 */ #endif #if defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) - {0x82, vector21}, + {0x82, vector21}, #else - {0x82, _unhandled_exception}, /* vector21 */ + {0x82, _unhandled_exception}, /* vector21 */ #endif #if defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) - {0x82, vector22}, + {0x82, vector22}, #else - {0x82, _unhandled_exception}, /* vector22 */ + {0x82, _unhandled_exception}, /* vector22 */ #endif #if defined(_TIM1_UPDATE_ISR) - {0x82, vector23}, + {0x82, vector23}, #else - {0x82, _unhandled_exception}, /* vector23 */ + {0x82, _unhandled_exception}, /* vector23 */ #endif #if defined(_TIM1_COMPARE_ISR) - {0x82, vector24}, + {0x82, vector24}, #else - {0x82, _unhandled_exception}, /* vector24 */ + {0x82, _unhandled_exception}, /* vector24 */ #endif #if defined(_TIM4_UPDATE_ISR) - {0x82, vector25}, + {0x82, vector25}, #else - {0x82, _unhandled_exception}, /* vector25 */ + {0x82, _unhandled_exception}, /* vector25 */ #endif #if defined(_SPI1_ISR) - {0x82, vector26}, + {0x82, vector26}, #else - {0x82, _unhandled_exception}, /* vector26 */ + {0x82, _unhandled_exception}, /* vector26 */ #endif #if defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) - {0x82, vector27}, + {0x82, vector27}, #else - {0x82, _unhandled_exception}, /* vector27 */ + {0x82, _unhandled_exception}, /* vector27 */ #endif #if defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) - {0x82, vector28}, + {0x82, vector28}, #else - {0x82, _unhandled_exception}, /* vector28 */ + {0x82, _unhandled_exception}, /* vector28 */ #endif #if defined(_SPI2_ISR) || defined(_I2C1_ISR) - {0x82, vector29}, + {0x82, vector29}, #else - {0x82, _unhandled_exception}, /* vector29 */ + {0x82, _unhandled_exception}, /* vector29 */ #endif }; diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index 00ead83c6..d37b0f305 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -74,7 +74,7 @@ String.6.0=2010,5,25,14,45,56 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; [Root.Config.0.Settings.2] String.2.0= @@ -83,7 +83,7 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,26,17,30,51 @@ -157,7 +157,7 @@ String.6.0=2010,5,25,14,45,56 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; [Root.Config.1.Settings.2] String.2.0= @@ -166,7 +166,7 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -247,7 +247,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -274,7 +274,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -331,7 +331,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -358,7 +358,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -415,7 +415,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -442,7 +442,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -509,26 +509,26 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder @@ -568,7 +568,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -589,7 +589,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -627,7 +627,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -648,7 +648,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -686,7 +686,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -707,7 +707,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -750,7 +750,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,54,38 @@ -771,7 +771,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -809,7 +809,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -830,7 +830,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -868,7 +868,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -889,7 +889,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -927,7 +927,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -948,7 +948,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -986,7 +986,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1007,7 +1007,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1045,7 +1045,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1066,7 +1066,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1104,7 +1104,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1125,7 +1125,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1163,7 +1163,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1184,7 +1184,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1222,7 +1222,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1243,7 +1243,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1281,7 +1281,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1302,7 +1302,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1340,7 +1340,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1361,7 +1361,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1399,7 +1399,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1420,7 +1420,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1458,7 +1458,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1479,7 +1479,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1516,7 +1516,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,54,38 @@ -1537,7 +1537,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1570,7 +1570,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1597,7 +1597,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1647,7 +1647,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1674,7 +1674,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1779,7 +1779,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1806,7 +1806,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1915,41 +1915,41 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h +PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h +PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h +PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h +PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h +PathName=..\..\..\os\hal \platforms\stm8s\stm8.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h +PathName=..\..\..\os\hal \platforms\stm8s\stm8s.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s_type.h +PathName=..\..\..\os\hal \platforms\stm8s\stm8s_type.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c index 76ebd1736..f97703b7f 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c @@ -40,8 +40,8 @@ void _stext(void); * @brief Exception vector type. */ typedef struct { - uint8_t ev_instruction; - interrupt_handler_t ev_handler; + uint8_t ev_instruction; + interrupt_handler_t ev_handler; } exception_vector_t; /** @@ -50,57 +50,57 @@ typedef struct { */ @far @interrupt static void vector (void) { - return; + return; } /** * @brief Exceptions table. */ exception_vector_t const _vectab[] = { - {0x82, (interrupt_handler_t)_stext}, /* reset */ - {0x82, vector}, /* trap */ - {0x82, vector}, /* vector0 */ - {0x82, vector}, /* vector1 */ - {0x82, vector}, /* vector2 */ - {0x82, vector}, /* vector3 */ - {0x82, vector}, /* vector4 */ - {0x82, vector}, /* vector5 */ - {0x82, vector}, /* vector6 */ - {0x82, vector}, /* vector7 */ - {0x82, vector}, /* vector8 */ - {0x82, vector}, /* vector9 */ + {0x82, (interrupt_handler_t)_stext}, /* reset */ + {0x82, vector}, /* trap */ + {0x82, vector}, /* vector0 */ + {0x82, vector}, /* vector1 */ + {0x82, vector}, /* vector2 */ + {0x82, vector}, /* vector3 */ + {0x82, vector}, /* vector4 */ + {0x82, vector}, /* vector5 */ + {0x82, vector}, /* vector6 */ + {0x82, vector}, /* vector7 */ + {0x82, vector}, /* vector8 */ + {0x82, vector}, /* vector9 */ #if HAL_USE_SPI && STM8_SPI_USE_SPI - {0x82, vector10}, + {0x82, vector10}, #else - {0x82, vector}, /* vector10 */ + {0x82, vector}, /* vector10 */ #endif - {0x82, vector}, /* vector11 */ - {0x82, vector}, /* vector12 */ - {0x82, vector13}, /* vector13 */ - {0x82, vector}, /* vector14 */ - {0x82, vector}, /* vector15 */ - {0x82, vector}, /* vector16 */ + {0x82, vector}, /* vector11 */ + {0x82, vector}, /* vector12 */ + {0x82, vector13}, /* vector13 */ + {0x82, vector}, /* vector14 */ + {0x82, vector}, /* vector15 */ + {0x82, vector}, /* vector16 */ #if HAL_USE_SERIAL && STM8_SERIAL_USE_UART1 - {0x82, vector17}, /* vector17 */ - {0x82, vector18}, /* vector18 */ + {0x82, vector17}, /* vector17 */ + {0x82, vector18}, /* vector18 */ #else - {0x82, vector}, /* vector17 */ - {0x82, vector}, /* vector18 */ + {0x82, vector}, /* vector17 */ + {0x82, vector}, /* vector18 */ #endif - {0x82, vector}, /* vector19 */ + {0x82, vector}, /* vector19 */ #if HAL_USE_SERIAL && (STM8_SERIAL_USE_UART2 || STM8_SERIAL_USE_UART3) {0x82, vector20}, /* vector20 */ - {0x82, vector21}, /* vector21 */ + {0x82, vector21}, /* vector21 */ #else {0x82, vector}, /* vector20 */ - {0x82, vector}, /* vector21 */ + {0x82, vector}, /* vector21 */ #endif - {0x82, vector}, /* vector22 */ - {0x82, vector}, /* vector23 */ - {0x82, vector}, /* vector24 */ - {0x82, vector}, /* vector25 */ - {0x82, vector}, /* vector26 */ - {0x82, vector}, /* vector27 */ - {0x82, vector}, /* vector28 */ - {0x82, vector}, /* vector29 */ + {0x82, vector}, /* vector22 */ + {0x82, vector}, /* vector23 */ + {0x82, vector}, /* vector24 */ + {0x82, vector}, /* vector25 */ + {0x82, vector}, /* vector26 */ + {0x82, vector}, /* vector27 */ + {0x82, vector}, /* vector28 */ + {0x82, vector}, /* vector29 */ }; diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index 680eab87c..77a3130ad 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -74,7 +74,7 @@ String.6.0=2010,6,4,10,10,40 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; [Root.Config.0.Settings.2] String.2.0= @@ -83,7 +83,7 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -143,7 +143,7 @@ String.6.0=2010,6,4,10,10,40 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; [Root.Config.1.Settings.2] String.2.0= @@ -152,7 +152,7 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -219,7 +219,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -246,7 +246,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -297,7 +297,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -318,7 +318,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -352,7 +352,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -379,7 +379,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -436,7 +436,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -463,7 +463,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -530,26 +530,26 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.c +PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder @@ -589,7 +589,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -610,7 +610,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -648,7 +648,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -669,7 +669,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -707,7 +707,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -728,7 +728,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -766,7 +766,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -787,7 +787,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -825,7 +825,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -846,7 +846,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -884,7 +884,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -905,7 +905,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -943,7 +943,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -964,7 +964,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1002,7 +1002,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1023,7 +1023,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1061,7 +1061,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1082,7 +1082,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1120,7 +1120,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1141,7 +1141,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1179,7 +1179,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1200,7 +1200,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1238,7 +1238,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1259,7 +1259,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1297,7 +1297,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1318,7 +1318,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1356,7 +1356,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1377,7 +1377,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1415,7 +1415,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1436,7 +1436,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1479,7 +1479,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1500,7 +1500,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1537,7 +1537,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1558,7 +1558,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1591,7 +1591,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1618,7 +1618,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1668,7 +1668,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1695,7 +1695,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1800,7 +1800,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1827,7 +1827,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1936,41 +1936,41 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\spi_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h +PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s_type.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s_type.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h +PathName=..\..\..\os\hal \platforms\stm8s\stm8s_type.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8s.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h +PathName=..\..\..\os\hal \platforms\stm8s\stm8s.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\stm8.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\stm8.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h +PathName=..\..\..\os\hal \platforms\stm8s\stm8.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h +PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h +PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h] ElemType=File -PathName=..\..\..\os\hal\platforms\stm8\hal_lld.h +PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index d5438c30b..8299af114 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -82,10 +82,10 @@ - - - - + + + + @@ -101,7 +101,7 @@
- + -- cgit v1.2.3 From 5008068ce440a8220d2486a0f69e05d72e857565 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 18 Nov 2010 13:09:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2386 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../cosmic/cosmic.stp | 169 ++++++++++---------- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h | 26 ++-- .../raisonance/raisonance.stp | 173 ++++++++++----------- demos/STM8S-STM8S208-RC/ch.rapp | 10 +- demos/STM8S-STM8S208-RC/mcuconf.h | 26 ++-- 5 files changed, 197 insertions(+), 207 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index d37b0f305..0aa8ea683 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -74,7 +74,7 @@ String.6.0=2010,5,25,14,45,56 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8s;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; [Root.Config.0.Settings.2] String.2.0= @@ -83,7 +83,7 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,26,17,30,51 @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Programmi\COSMIC\CXSTM8_32K +String.102.0=C:\Program Files\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -157,7 +157,7 @@ String.6.0=2010,5,25,14,45,56 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; +String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8s;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo; [Root.Config.1.Settings.2] String.2.0= @@ -166,7 +166,7 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -247,7 +247,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -274,7 +274,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -331,7 +331,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -358,7 +358,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -415,7 +415,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -442,7 +442,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -509,26 +509,26 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder @@ -568,7 +568,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -589,7 +589,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -627,7 +627,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -648,7 +648,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -686,7 +686,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -707,7 +707,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -750,7 +750,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,54,38 @@ -771,7 +771,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -809,7 +809,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -830,7 +830,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -868,7 +868,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -889,7 +889,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -927,7 +927,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -948,7 +948,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -986,7 +986,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1007,7 +1007,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1045,7 +1045,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1066,7 +1066,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1104,7 +1104,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1125,7 +1125,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1163,7 +1163,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1184,7 +1184,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1222,7 +1222,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1243,7 +1243,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1281,7 +1281,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1302,7 +1302,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1340,7 +1340,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1361,7 +1361,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1399,7 +1399,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1420,7 +1420,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1458,7 +1458,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1479,7 +1479,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1516,7 +1516,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +mods0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,54,38 @@ -1537,7 +1537,7 @@ String.6.0=2010,5,25,14,45,56 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +mods0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1570,7 +1570,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1597,7 +1597,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1647,7 +1647,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1674,7 +1674,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1779,7 +1779,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1806,7 +1806,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal \platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) +String.3.0=cxstm8 +modsl0 -customC-pp -customLst-l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8s -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,6,5,11,53,48 @@ -1915,41 +1915,36 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h +PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h +PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h +PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h +PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\stm8.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h +PathName=..\..\..\os\hal\platforms\stm8s\stm8s.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h] -ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\stm8s_type.h +PathName=..\..\..\os\hal\platforms\stm8s\stm8s_type.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h index 61b572a82..814143da2 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h @@ -28,24 +28,24 @@ /* * HAL general settings. */ -#define STM8_NO_CLOCK_INIT FALSE -#define STM8_HSI_ENABLED FALSE -#define STM8_LSI_ENABLED TRUE -#define STM8_HSE_ENABLED TRUE -#define STM8_SYSCLK_SOURCE CLK_SYSSEL_HSE -#define STM8_HSI_DIVIDER CLK_HSI_DIV1 -#define STM8_CPU_DIVIDER CLK_CPU_DIV1 -#define STM8_CAN_DIVIDER_VALUE 1 +#define STM8S_NO_CLOCK_INIT FALSE +#define STM8S_HSI_ENABLED FALSE +#define STM8S_LSI_ENABLED TRUE +#define STM8S_HSE_ENABLED TRUE +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSE +#define STM8S_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 +#define STM8S_CAN_DIVIDER_VALUE 1 /* * SERIAL driver system settings. */ -#define STM8_SERIAL_USE_UART1 FALSE -#define STM8_SERIAL_USE_UART2 TRUE -#define STM8_SERIAL_USE_UART3 FALSE +#define STM8S_SERIAL_USE_UART1 FALSE +#define STM8S_SERIAL_USE_UART2 TRUE +#define STM8S_SERIAL_USE_UART3 FALSE /* * SPI driver system settings. */ -#define STM8_SPI_USE_SPI TRUE -#define STM8_SPI_ERROR_HOOK(spip) chSysHalt() +#define STM8S_SPI_USE_SPI TRUE +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index 77a3130ad..351f449c8 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Programmi\Raisonance\Ride +String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -74,7 +74,7 @@ String.6.0=2010,6,4,10,10,40 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; [Root.Config.0.Settings.2] String.2.0= @@ -83,7 +83,7 @@ String.100.0=STM8S105C6 [Root.Config.0.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -130,7 +130,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Programmi\Raisonance\Ride +String.102.0=C:\Program Files\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -143,7 +143,7 @@ String.6.0=2010,6,4,10,10,40 String.100.0=$(TargetFName) String.101.0= String.102.0= -String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal \platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; +String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8s;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8; [Root.Config.1.Settings.2] String.2.0= @@ -152,7 +152,7 @@ String.100.0=STM8S105C6 [Root.Config.1.Settings.3] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -219,7 +219,7 @@ Int.1=0 [Root.Source Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -246,7 +246,7 @@ Int.1=0 [Root.Source Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -297,7 +297,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -318,7 +318,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files...\demo\main.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -352,7 +352,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -379,7 +379,7 @@ Int.1=0 [Root.Source Files.Source Files\board.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -436,7 +436,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -463,7 +463,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\hal.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -530,26 +530,26 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\s [Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] ElemType=Folder PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.c +PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder @@ -589,7 +589,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -610,7 +610,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -648,7 +648,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -669,7 +669,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chthreads.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -707,7 +707,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -728,7 +728,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsys.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -766,7 +766,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -787,7 +787,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chsem.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -825,7 +825,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -846,7 +846,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chschd.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -884,7 +884,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -905,7 +905,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chregistry.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -943,7 +943,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -964,7 +964,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chqueues.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1002,7 +1002,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1023,7 +1023,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmtx.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1061,7 +1061,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1082,7 +1082,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmsg.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1120,7 +1120,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1141,7 +1141,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmempools.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1179,7 +1179,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1200,7 +1200,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmemcore.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1238,7 +1238,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1259,7 +1259,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chmboxes.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1297,7 +1297,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1318,7 +1318,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chlists.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1356,7 +1356,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(page0) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1377,7 +1377,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chheap.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(page0) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1415,7 +1415,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1436,7 +1436,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1479,7 +1479,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1500,7 +1500,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1537,7 +1537,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1558,7 +1558,7 @@ String.6.0=2010,6,4,10,10,40 [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1591,7 +1591,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1618,7 +1618,7 @@ Int.1=0 [Root.Source Files.Source Files\os.Source Files\os\port.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1668,7 +1668,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1695,7 +1695,7 @@ Int.1=0 [Root.Source Files.Source Files\test.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1800,7 +1800,7 @@ Int.1=0 [Root.Include Files.Config.0.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,42,15 @@ -1827,7 +1827,7 @@ Int.1=0 [Root.Include Files.Config.1.Settings.1] String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal \platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB NOIS CD CO SB LAOB PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8s) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,6,26,17,22,23 @@ -1936,41 +1936,36 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\h [Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] ElemType=Folder PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\spi_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h +PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s_type.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\stm8s_type.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h +PathName=..\..\..\os\hal\platforms\stm8s\stm8s_type.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8s.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h +PathName=..\..\..\os\hal\platforms\stm8s\stm8s.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\stm8.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\stm8.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h +PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h +PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h] ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h - -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal \platforms\stm8s\hal_lld.h] -ElemType=File -PathName=..\..\..\os\hal \platforms\stm8s\hal_lld.h +PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 8299af114..85071d41a 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -82,10 +82,10 @@ - - - - + + + + @@ -101,7 +101,7 @@
- + diff --git a/demos/STM8S-STM8S208-RC/mcuconf.h b/demos/STM8S-STM8S208-RC/mcuconf.h index 53b52fb2a..bb38a3760 100644 --- a/demos/STM8S-STM8S208-RC/mcuconf.h +++ b/demos/STM8S-STM8S208-RC/mcuconf.h @@ -28,24 +28,24 @@ /* * HAL general settings. */ -#define STM8_NO_CLOCK_INIT FALSE -#define STM8_HSI_ENABLED FALSE -#define STM8_LSI_ENABLED TRUE -#define STM8_HSE_ENABLED TRUE -#define STM8_SYSCLK_SOURCE CLK_SYSSEL_HSI -#define STM8_HSI_DIVIDER CLK_HSI_DIV1 -#define STM8_CPU_DIVIDER CLK_CPU_DIV1 -#define STM8_CAN_DIVIDER_VALUE 1 +#define STM8S_NO_CLOCK_INIT FALSE +#define STM8S_HSI_ENABLED FALSE +#define STM8S_LSI_ENABLED TRUE +#define STM8S_HSE_ENABLED TRUE +#define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSI +#define STM8S_HSI_DIVIDER CLK_HSI_DIV1 +#define STM8S_CPU_DIVIDER CLK_CPU_DIV1 +#define STM8S_CAN_DIVIDER_VALUE 1 /* * SERIAL driver system settings. */ -#define USE_STM8_UART1 TRUE -#define USE_STM8_UART2 FALSE -#define USE_STM8_UART3 FALSE +#define USE_STM8S_UART1 TRUE +#define USE_STM8S_UART2 FALSE +#define USE_STM8S_UART3 FALSE /* * SPI driver system settings. */ -#define STM8_SPI_USE_SPI TRUE -#define STM8_SPI_ERROR_HOOK(spip) chSysHalt() +#define STM8S_SPI_USE_SPI TRUE +#define STM8S_SPI_ERROR_HOOK(spip) chSysHalt() -- cgit v1.2.3 From 3ae01fd47b63b190ee6d7588d8721e8edad3d150 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 19 Nov 2010 18:45:11 +0000 Subject: ARM7/9 port update, other improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2389 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile | 6 +++--- demos/ARM7-AT91SAM7S-GCC/Makefile | 6 +++--- demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile | 6 +++--- demos/ARM7-AT91SAM7X-GCC/Makefile | 6 +++--- demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile | 6 +++--- demos/ARM7-AT91SAM7X-UIP-GCC/Makefile | 6 +++--- demos/ARM7-LPC214x-FATFS-GCC/Makefile | 6 +++--- demos/ARM7-LPC214x-G++/Makefile | 6 +++--- demos/ARM7-LPC214x-GCC/Makefile | 6 +++--- 9 files changed, 27 insertions(+), 27 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile index 576b7ecbc..58fe3829a 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_SAM7_P256/board.mk include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/ext/fatfs/fatfs.mk @@ -91,13 +91,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(FATFSINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7 # # Project, sources and paths diff --git a/demos/ARM7-AT91SAM7S-GCC/Makefile b/demos/ARM7-AT91SAM7S-GCC/Makefile index fcb9ae999..515224c81 100644 --- a/demos/ARM7-AT91SAM7S-GCC/Makefile +++ b/demos/ARM7-AT91SAM7S-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_SAM7_P256/board.mk include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -87,12 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7 # # Project, sources and paths diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile index c74d12ab6..6b1542c2c 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/ext/fatfs/fatfs.mk @@ -91,13 +91,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(FATFSINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7 # # Project, sources and paths diff --git a/demos/ARM7-AT91SAM7X-GCC/Makefile b/demos/ARM7-AT91SAM7X-GCC/Makefile index f9db0679b..e6480eb1c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -87,12 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7 # # Project, sources and paths diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile index 3890b27ed..4caf96ebf 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include ./lwip/lwip.mk @@ -96,12 +96,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 \ + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7 \ ./lwip # diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile index 641cbdb76..bad6e49f8 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -100,12 +100,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/AT91SAM7 \ + $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7 \ ./web $(CHIBIOS)/ext/uip-1.0/uip $(CHIBIOS)/ext/uip-1.0/apps/webserver # diff --git a/demos/ARM7-LPC214x-FATFS-GCC/Makefile b/demos/ARM7-LPC214x-FATFS-GCC/Makefile index 99ff790e9..d69954793 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/Makefile +++ b/demos/ARM7-LPC214x-FATFS-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk include $(CHIBIOS)/ext/fatfs/fatfs.mk @@ -92,13 +92,13 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/LPC214x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(FATFSINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x + $(CHIBIOS)/os/ports/GCC/ARM/LPC214x # # Project, sources and paths diff --git a/demos/ARM7-LPC214x-G++/Makefile b/demos/ARM7-LPC214x-G++/Makefile index 549fd8f1f..118ec0cae 100644 --- a/demos/ARM7-LPC214x-G++/Makefile +++ b/demos/ARM7-LPC214x-G++/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -87,12 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/LPC214x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x + $(CHIBIOS)/os/ports/GCC/ARM/LPC214x # # Project, sources and paths diff --git a/demos/ARM7-LPC214x-GCC/Makefile b/demos/ARM7-LPC214x-GCC/Makefile index 99b7202cd..ac9a4d653 100644 --- a/demos/ARM7-LPC214x-GCC/Makefile +++ b/demos/ARM7-LPC214x-GCC/Makefile @@ -47,7 +47,7 @@ CHIBIOS = ../.. include $(CHIBIOS)/boards/OLIMEX_LPC_P2148/board.mk include $(CHIBIOS)/os/hal/platforms/LPC214x/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARM7/port.mk +include $(CHIBIOS)/os/ports/GCC/ARM/port.mk include $(CHIBIOS)/os/kernel/kernel.mk include $(CHIBIOS)/test/test.mk @@ -87,12 +87,12 @@ TCPPSRC = # List ASM source files here ASMSRC = $(PORTASM) \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x/vectors.s + $(CHIBIOS)/os/ports/GCC/ARM/LPC214x/vectors.s INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ $(HALINC) $(PLATFORMINC) $(BOARDINC) \ $(CHIBIOS)/os/various \ - $(CHIBIOS)/os/ports/GCC/ARM7/LPC214x + $(CHIBIOS)/os/ports/GCC/ARM/LPC214x # # Project, sources and paths -- cgit v1.2.3 From 0d717a5f9fe78ad4857677baf9d0000c2304a6ca Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 20 Nov 2010 10:46:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2391 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index 4d90741c1..907f0d8ee 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -25,14 +25,14 @@ #include "web/web.h" static WORKING_AREA(waThread1, 64); -static msg_t Thread1(void *arg) { +static msg_t Thread1(void *p) { - (void)arg; + (void)p; while (TRUE) { - palClearPad(IOPORT2, PIOB_LCD_BL); - chThdSleepMilliseconds(900); palSetPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(100); + palClearPad(IOPORT2, PIOB_LCD_BL); + chThdSleepMilliseconds(900); } return 0; } -- cgit v1.2.3 From ef765be75f392d516bf77b307df5e2192458b3cc Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 20 Nov 2010 11:13:15 +0000 Subject: Fixed a misplaced comment in all the halconf.h files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2394 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h | 4 ---- demos/ARM7-AT91SAM7S-GCC/halconf.h | 4 ---- demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h | 4 ---- demos/ARM7-AT91SAM7X-GCC/halconf.h | 4 ---- demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h | 4 ---- demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h | 4 ---- demos/ARM7-LPC214x-FATFS-GCC/halconf.h | 4 ---- demos/ARM7-LPC214x-G++/halconf.h | 4 ---- demos/ARM7-LPC214x-GCC/halconf.h | 4 ---- demos/ARMCM0-LPC1114-GCC/halconf.h | 4 ---- demos/ARMCM3-LPC1343-GCC/halconf.h | 4 ---- demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h | 4 ---- demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h | 4 ---- demos/ARMCM3-STM32F103-GCC/halconf.h | 4 ---- demos/ARMCM3-STM32F107-GCC/halconf.h | 4 ---- demos/AVR-AT90CANx-GCC/halconf.h | 4 ---- demos/AVR-ATmega128-GCC/halconf.h | 4 ---- demos/MSP430-MSP430x1611-GCC/halconf.h | 4 ---- demos/PPC-SPC563-GCC/halconf.h | 4 ---- demos/Posix-GCC/halconf.h | 4 ---- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h | 4 ---- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h | 4 ---- demos/STM8S-STM8S208-RC/halconf.h | 4 ---- demos/Win32-MinGW/halconf.h | 4 ---- 24 files changed, 96 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index bc6c3b8d2..bafc9df7a 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index bc6c3b8d2..bafc9df7a 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 3ccb9a219..268525a61 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 3ccb9a219..268525a61 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index bc6c3b8d2..bafc9df7a 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index 3186be527..890f3896b 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARMCM0-LPC1114-GCC/halconf.h b/demos/ARMCM0-LPC1114-GCC/halconf.h index 9ed9ce905..479c87021 100644 --- a/demos/ARMCM0-LPC1114-GCC/halconf.h +++ b/demos/ARMCM0-LPC1114-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARMCM3-LPC1343-GCC/halconf.h b/demos/ARMCM3-LPC1343-GCC/halconf.h index 9ed9ce905..479c87021 100644 --- a/demos/ARMCM3-LPC1343-GCC/halconf.h +++ b/demos/ARMCM3-LPC1343-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h index bc6c3b8d2..bafc9df7a 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARMCM3-STM32F103-GCC/halconf.h b/demos/ARMCM3-STM32F103-GCC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/ARMCM3-STM32F103-GCC/halconf.h +++ b/demos/ARMCM3-STM32F103-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/ARMCM3-STM32F107-GCC/halconf.h b/demos/ARMCM3-STM32F107-GCC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/ARMCM3-STM32F107-GCC/halconf.h +++ b/demos/ARMCM3-STM32F107-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index 2eea483f4..e355d7bbc 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index 2eea483f4..e355d7bbc 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index 64a634d85..2e37f10ed 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index acc98744c..30695a2a3 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index 3186be527..890f3896b 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index 3186be527..890f3896b 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index 3186be527..890f3896b 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index acc98744c..30695a2a3 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -28,10 +28,6 @@ * @{ */ -/* - * - */ - #ifndef _HALCONF_H_ #define _HALCONF_H_ -- cgit v1.2.3 From 87098feb4116ed3eb8d6f03c77c899e77cad04ab Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 20 Nov 2010 11:21:36 +0000 Subject: Increased blinker thread stack size on some demos. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2395 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-FATFS-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-GCC/main.c b/demos/ARM7-AT91SAM7S-GCC/main.c index 4077ffb58..82e1ee5f2 100644 --- a/demos/ARM7-AT91SAM7S-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-GCC/main.c @@ -21,7 +21,7 @@ #include "hal.h" #include "test.h" -static WORKING_AREA(waThread1, 64); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *p) { (void)p; diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c index 3e02fff74..3ed2ab0e6 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -230,7 +230,7 @@ static const ShellConfig shell_cfg1 = { /* * LCD blinker thread, times are in milliseconds. */ -static WORKING_AREA(waThread1, 64); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *p) { (void)p; diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index a560bc439..f5514b41a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -21,7 +21,7 @@ #include "hal.h" #include "test.h" -static WORKING_AREA(waThread1, 64); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *p) { (void)p; diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index 907f0d8ee..895766132 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -24,7 +24,7 @@ #include "lwip/lwipthread.h" #include "web/web.h" -static WORKING_AREA(waThread1, 64); +static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *p) { (void)p; diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c index 5db4864b9..3a3f5eeb6 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -24,11 +24,11 @@ #include "web/webthread.h" static WORKING_AREA(waWebThread, 1024); -static WORKING_AREA(waThread1, 128); -static msg_t Thread1(void *arg) { +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *p) { - (void)arg; + (void)p; while (TRUE) { palSetPad(IOPORT2, PIOB_LCD_BL); chThdSleepMilliseconds(100); -- cgit v1.2.3 From 32e43fdb02ddb7582866c29dad5e6c87f3315605 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Nov 2010 13:45:22 +0000 Subject: Fixed bug 3114481. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2409 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h | 4 +- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 113 +++++++++++++++++++++++-- demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h | 4 +- 3 files changed, 109 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h index 890f3896b..02a280269 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h @@ -44,7 +44,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC FALSE +#define HAL_USE_ADC TRUE #endif /** @@ -79,7 +79,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE +#define HAL_USE_PWM TRUE #endif /** diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 05f0712e4..aea56bab2 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -21,21 +21,101 @@ #include "hal.h" #include "test.h" +static void pwmpcb(PWMDriver *pwmp); +static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +#define ADC_GRP1_NUM_CHANNELS 2 +#define ADC_GRP1_BUF_DEPTH 4 + +/* + * ADC samples buffer. + */ +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH] = +{ + 2048, 0, + 2048, 0, + 2048, 0, + 2048, 0 +}; + +/* + * ADC conversion group. + * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. + * Channels: IN10, Sensor. + */ +static const ADCConversionGroup adcgrpcfg = { + FALSE, + ADC_GRP1_NUM_CHANNELS, + adccb, + 0, + ADC_CR2_EXTSEL_SWSTART | ADC_CR2_TSVREFE, + 0, + 0, + ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), + 0, + ADC_SQR3_SQ1_N(ADC_CHANNEL_SENSOR) | ADC_SQR3_SQ0_N(ADC_CHANNEL_IN10) +}; + +/* + * ADC configuration structure, empty for STM32, there is nothing to configure. + */ +static const ADCConfig adccfg = { +}; + +/* + * PWM configuration structure. + */ +static PWMConfig pwmcfg = { + pwmpcb, + { + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + PWM_COMPUTE_PSC(STM32_TIMCLK1, 10000), /* 10KHz PWM clock frequency. */ + PWM_COMPUTE_ARR(10000, 1000000000), /* PWM period 1S (in nS). */ + 0 +}; + +/* + * PWM cyclic callback. PWM channels are reprogrammed using a duty cycle + * calculated as average of the last sampling operations. + */ +static void pwmpcb(PWMDriver *pwmp) { + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the previous ADC sampling + operation.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + chSysLockFromIsr(); + pwmEnableChannelI(pwmp, 2, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch1)); + pwmEnableChannelI(pwmp, 3, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch2)); + + /* Starts an asynchronous ADC conversion operation, the conversion + will be executed in parallel to the current PWM cycle and will + terminate before the next PWM cycle.*/ +// adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + chSysUnlockFromIsr(); +} + /* - * Red LEDs blinker thread, times are in milliseconds. + * ADC end conversion callback. + */ +void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { + + (void)adcp; (void) buffer; (void) n; +} + +/* + * Red and blue LEDs blinker thread, times are in milliseconds. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { (void)arg; while (TRUE) { - palSetPad(GPIOC, GPIOC_LED4); - chThdSleepMilliseconds(250); - palClearPad(GPIOC, GPIOC_LED4); - chThdSleepMilliseconds(250); - palSetPad(GPIOC, GPIOC_LED3); - chThdSleepMilliseconds(250); - palClearPad(GPIOC, GPIOC_LED3); chThdSleepMilliseconds(250); } return 0; @@ -55,6 +135,23 @@ int main(int argc, char **argv) { */ sdStart(&SD1, NULL); + /* + * Initializes the ADC driver 1. + */ + adcStart(&ADCD1, &adccfg); + + /* + * Initializes the PWM driver 1, re-routes the TIM3 outputs, programs the + * pins as alternate functions and finally enables channels with zero + * initial duty cycle. + * Note, the AFIO access routes the TIM3 output pins on the PC6...PC9 + * where the LEDs are connected. + */ + pwmStart(&PWMD3, &pwmcfg); + AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_0 | AFIO_MAPR_TIM3_REMAP_1; + palSetGroupMode(GPIOC, PAL_PORT_BIT(GPIOC_LED3) | PAL_PORT_BIT(GPIOC_LED4), + PAL_MODE_STM32_ALTERNATE_PUSHPULL); + /* * Creates the blinker thread. */ diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h index d1ad23373..0ff6793f2 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h @@ -61,9 +61,9 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM3 TRUE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_PWM1_IRQ_PRIORITY 7 #define STM32_PWM_PWM2_IRQ_PRIORITY 7 -- cgit v1.2.3 From d573d5f308f2df192be15c82890d04db13217987 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Nov 2010 14:21:11 +0000 Subject: Improved STM32VL-Discovery demo. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2410 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h | 2 +- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 74 ++++++++++++++++++++----- demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt | 8 ++- 3 files changed, 65 insertions(+), 19 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h index 02a280269..10c78a7ba 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/halconf.h @@ -93,7 +93,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE +#define HAL_USE_SPI TRUE #endif /** diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index aea56bab2..0dbcc8354 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -23,20 +23,18 @@ static void pwmpcb(PWMDriver *pwmp); static void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n); +static void spicb(SPIDriver *spip); +/* Total number of channels to be sampled by a single ADC operation.*/ #define ADC_GRP1_NUM_CHANNELS 2 + +/* Depth of the conversion buffer, channels are sampled four times each.*/ #define ADC_GRP1_BUF_DEPTH 4 /* * ADC samples buffer. */ -static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH] = -{ - 2048, 0, - 2048, 0, - 2048, 0, - 2048, 0 -}; +static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; /* * ADC conversion group. @@ -53,7 +51,7 @@ static const ADCConversionGroup adcgrpcfg = { 0, ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), 0, - ADC_SQR3_SQ1_N(ADC_CHANNEL_SENSOR) | ADC_SQR3_SQ0_N(ADC_CHANNEL_IN10) + ADC_SQR3_SQ1_N(ADC_CHANNEL_IN10) | ADC_SQR3_SQ0_N(ADC_CHANNEL_SENSOR) }; /* @@ -63,7 +61,9 @@ static const ADCConfig adccfg = { }; /* - * PWM configuration structure. + * PWM configuration structure. + * Cyclic callback enabled, channels 3 and 4 enabled without callbacks, + * the active state is a logic one. */ static PWMConfig pwmcfg = { pwmpcb, @@ -78,6 +78,18 @@ static PWMConfig pwmcfg = { 0 }; +/* + * SPI configuration structure. + * Maximum speed (12MHz), CPHA=0, CPOL=0, 16bits frames, MSb transmitted first. + * The slave select line is the pin GPIOA_SPI1NSS on the port GPIOA. + */ +static const SPIConfig spicfg = { + spicb, + GPIOA, + GPIOA_SPI1NSS, + SPI_CR1_DFF +}; + /* * PWM cyclic callback. PWM channels are reprogrammed using a duty cycle * calculated as average of the last sampling operations. @@ -90,33 +102,60 @@ static void pwmpcb(PWMDriver *pwmp) { avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ pwmEnableChannelI(pwmp, 2, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch1)); pwmEnableChannelI(pwmp, 3, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch2)); /* Starts an asynchronous ADC conversion operation, the conversion will be executed in parallel to the current PWM cycle and will terminate before the next PWM cycle.*/ -// adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); chSysUnlockFromIsr(); } /* - * ADC end conversion callback. + * ADC end conversion callback. + * The latest samples are transmitted into a single SPI transaction. */ void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { - (void)adcp; (void) buffer; (void) n; + (void) buffer; (void) n; + /* Note, only in the ADC_COMPLETE state because the ADC driver fires an + intermediate callback when the buffer is half full.*/ + if (adcp->ad_state == ADC_COMPLETE) { + /* SPI slave selection and transmission start.*/ + chSysLockFromIsr(); + spiSelectI(&SPID1); + spiStartSendI(&SPID1, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + chSysUnlockFromIsr(); + } +} + +/* + * SPI end transfer callback. + */ +static void spicb(SPIDriver *spip) { + + /* On transfer end just releases the slave select line.*/ + chSysLockFromIsr(); + spiUnselectI(spip); + chSysUnlockFromIsr(); } /* - * Red and blue LEDs blinker thread, times are in milliseconds. + * This is a periodic thread that does absolutely nothing except sleeping and + * increase a counter. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { + static uint32_t seconds_counter; (void)arg; while (TRUE) { - chThdSleepMilliseconds(250); + chThdSleepMilliseconds(1000); + seconds_counter++; } return 0; } @@ -135,6 +174,11 @@ int main(int argc, char **argv) { */ sdStart(&SD1, NULL); + /* + * Initializes the SPI driver 1. + */ + spiStart(&SPID1, &spicfg); + /* * Initializes the ADC driver 1. */ @@ -153,7 +197,7 @@ int main(int argc, char **argv) { PAL_MODE_STM32_ALTERNATE_PUSHPULL); /* - * Creates the blinker thread. + * Creates the example thread. */ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt index f2f69f7c6..8423d1394 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt @@ -8,9 +8,11 @@ The demo runs on an ST STM32VL-Discovery board. ** The Demo ** -The demo flashes the board LEDs using a thread, by pressing the button located -on the board the test procedure is activated with output on the serial port -COM1 (USART1). +The demo shows how to use the ADC, PWM and SPI drivers using asynchronous +APIs. The ADC samples two channels and modulates the PWM using the sample +values. The sample data is also transmitted on the SPI port 1. +By pressing the button located on the board the test procedure is activated +with output on the serial port COM1 (USART1). ** Build Procedure ** -- cgit v1.2.3 From 2018975c3ebca410dd2f8b9a35fe510f4996fa77 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 21 Nov 2010 19:10:46 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2415 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 6 ++++-- demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 0dbcc8354..c413e7986 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -46,7 +46,7 @@ static const ADCConversionGroup adcgrpcfg = { ADC_GRP1_NUM_CHANNELS, adccb, 0, - ADC_CR2_EXTSEL_SWSTART | ADC_CR2_TSVREFE, + ADC_CR2_EXTSEL_SWSTART | ADC_CR2_TSVREFE | ADC_CR2_CONT, 0, 0, ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), @@ -181,8 +181,10 @@ int main(int argc, char **argv) { /* * Initializes the ADC driver 1. + * The pin PC0 on the port GPIOC is programmed as analog input. */ adcStart(&ADCD1, &adccfg); + palSetGroupMode(GPIOC, PAL_PORT_BIT(0), PAL_MODE_INPUT_ANALOG); /* * Initializes the PWM driver 1, re-routes the TIM3 outputs, programs the @@ -206,7 +208,7 @@ int main(int argc, char **argv) { * sleeping in a loop and check the button state. */ while (TRUE) { - if (palReadPad(IOPORT1, GPIOA_BUTTON)) + if (palReadPad(GPIOA, GPIOA_BUTTON)) TestThread(&SD1); chThdSleepMilliseconds(500); } diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt index 8423d1394..4d80483e8 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt @@ -9,8 +9,9 @@ The demo runs on an ST STM32VL-Discovery board. ** The Demo ** The demo shows how to use the ADC, PWM and SPI drivers using asynchronous -APIs. The ADC samples two channels and modulates the PWM using the sample -values. The sample data is also transmitted on the SPI port 1. +APIs. The ADC samples two channels (temperature sensor and PC0) and modulates +the PWM using the sampled values. The sample data is also transmitted on +the SPI port 1. By pressing the button located on the board the test procedure is activated with output on the serial port COM1 (USART1). -- cgit v1.2.3 From a7436d9f8f1b1a4b5af84df7e1f2a166d4144554 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Nov 2010 17:35:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2419 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index c413e7986..78cb48340 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -101,6 +101,7 @@ static void pwmpcb(PWMDriver *pwmp) { operation.*/ avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + chSysLockFromIsr(); /* Changes the channels pulse width, the change will be effective @@ -108,6 +109,7 @@ static void pwmpcb(PWMDriver *pwmp) { pwmEnableChannelI(pwmp, 2, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch1)); pwmEnableChannelI(pwmp, 3, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch2)); + /* Starts an asynchronous ADC conversion operation, the conversion will be executed in parallel to the current PWM cycle and will terminate before the next PWM cycle.*/ -- cgit v1.2.3 From ab51c68e2d3833c35ee7d151b1eeea8a3bd9943e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Nov 2010 17:50:39 +0000 Subject: Demo working now. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2420 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 30 ++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 78cb48340..2b8294a0e 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -95,24 +95,11 @@ static const SPIConfig spicfg = { * calculated as average of the last sampling operations. */ static void pwmpcb(PWMDriver *pwmp) { - adcsample_t avg_ch1, avg_ch2; - - /* Calculates the average values from the previous ADC sampling - operation.*/ - avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; - avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; - - chSysLockFromIsr(); - - /* Changes the channels pulse width, the change will be effective - starting from the next cycle.*/ - pwmEnableChannelI(pwmp, 2, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch1)); - pwmEnableChannelI(pwmp, 3, PWM_FRACTION_TO_WIDTH(pwmp, 4096, avg_ch2)); - /* Starts an asynchronous ADC conversion operation, the conversion will be executed in parallel to the current PWM cycle and will terminate before the next PWM cycle.*/ + chSysLockFromIsr(); adcStartConversionI(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); chSysUnlockFromIsr(); } @@ -127,10 +114,23 @@ void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { /* Note, only in the ADC_COMPLETE state because the ADC driver fires an intermediate callback when the buffer is half full.*/ if (adcp->ad_state == ADC_COMPLETE) { - /* SPI slave selection and transmission start.*/ + adcsample_t avg_ch1, avg_ch2; + + /* Calculates the average values from the ADC samples.*/ + avg_ch1 = (samples[0] + samples[2] + samples[4] + samples[6]) / 4; + avg_ch2 = (samples[1] + samples[3] + samples[5] + samples[7]) / 4; + chSysLockFromIsr(); + + /* Changes the channels pulse width, the change will be effective + starting from the next cycle.*/ + pwmEnableChannelI(&PWMD3, 2, PWM_FRACTION_TO_WIDTH(&PWMD3, 4096, avg_ch1)); + pwmEnableChannelI(&PWMD3, 3, PWM_FRACTION_TO_WIDTH(&PWMD3, 4096, avg_ch2)); + + /* SPI slave selection and transmission start.*/ spiSelectI(&SPID1); spiStartSendI(&SPID1, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH, samples); + chSysUnlockFromIsr(); } } -- cgit v1.2.3 From 294bc9ab4223b9ac30690dae76c058ed0bb9de69 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Nov 2010 17:54:09 +0000 Subject: Fixed a warning. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2421 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 2b8294a0e..b3b77a71b 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -96,6 +96,8 @@ static const SPIConfig spicfg = { */ static void pwmpcb(PWMDriver *pwmp) { + (void)pwmp; + /* Starts an asynchronous ADC conversion operation, the conversion will be executed in parallel to the current PWM cycle and will terminate before the next PWM cycle.*/ -- cgit v1.2.3 From 20db157d8506a0878241182a584240841b12b7b2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Nov 2010 17:57:16 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2422 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index b3b77a71b..c4ba64cda 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -149,8 +149,8 @@ static void spicb(SPIDriver *spip) { } /* - * This is a periodic thread that does absolutely nothing except sleeping and - * increase a counter. + * This is a periodic thread that does absolutely nothing except increasing + * a seconds counter. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { -- cgit v1.2.3 From 64c9d79b312dd40757cbcb66003c10690f415079 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 22 Nov 2010 18:05:35 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2423 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index c4ba64cda..c86d00e4c 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -209,7 +209,9 @@ int main(int argc, char **argv) { /* * Normal main() thread activity, in this demo it does nothing except - * sleeping in a loop and check the button state. + * sleeping in a loop and check the button state, when the button is + * pressed the test procedure is launched with output on the serial + * driver 1. */ while (TRUE) { if (palReadPad(GPIOA, GPIOA_BUTTON)) -- cgit v1.2.3 From a5bdf86e5b89a7abb281ac5514c7d6cb4d64c365 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 23 Nov 2010 16:16:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2424 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 8 ++++++-- demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index c86d00e4c..b1bc37c29 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -39,15 +39,17 @@ static adcsample_t samples[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH]; /* * ADC conversion group. * Mode: Linear buffer, 4 samples of 2 channels, SW triggered. - * Channels: IN10, Sensor. + * Channels: IN10 (41.5 cycles sample time) + * Sensor (239.5 cycles sample time) */ static const ADCConversionGroup adcgrpcfg = { FALSE, ADC_GRP1_NUM_CHANNELS, adccb, + /* HW dependent part.*/ 0, ADC_CR2_EXTSEL_SWSTART | ADC_CR2_TSVREFE | ADC_CR2_CONT, - 0, + ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5), 0, ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), 0, @@ -73,6 +75,7 @@ static PWMConfig pwmcfg = { {PWM_OUTPUT_ACTIVE_HIGH, NULL}, {PWM_OUTPUT_ACTIVE_HIGH, NULL} }, + /* HW dependent part.*/ PWM_COMPUTE_PSC(STM32_TIMCLK1, 10000), /* 10KHz PWM clock frequency. */ PWM_COMPUTE_ARR(10000, 1000000000), /* PWM period 1S (in nS). */ 0 @@ -85,6 +88,7 @@ static PWMConfig pwmcfg = { */ static const SPIConfig spicfg = { spicb, + /* HW dependent part.*/ GPIOA, GPIOA_SPI1NSS, SPI_CR1_DFF diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt index 4d80483e8..7f19c0889 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/readme.txt @@ -10,7 +10,7 @@ The demo runs on an ST STM32VL-Discovery board. The demo shows how to use the ADC, PWM and SPI drivers using asynchronous APIs. The ADC samples two channels (temperature sensor and PC0) and modulates -the PWM using the sampled values. The sample data is also transmitted on +the PWM using the sampled values. The sample data is also transmitted using the SPI port 1. By pressing the button located on the board the test procedure is activated with output on the serial port COM1 (USART1). -- cgit v1.2.3 From c852dcb3c960198f49c5fdd8619a6d5d581d9136 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 25 Nov 2010 18:32:45 +0000 Subject: Improved ADC and SPI driver models. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2426 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index b1bc37c29..445872f00 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -187,17 +187,9 @@ int main(int argc, char **argv) { */ spiStart(&SPID1, &spicfg); - /* - * Initializes the ADC driver 1. - * The pin PC0 on the port GPIOC is programmed as analog input. - */ - adcStart(&ADCD1, &adccfg); - palSetGroupMode(GPIOC, PAL_PORT_BIT(0), PAL_MODE_INPUT_ANALOG); - /* * Initializes the PWM driver 1, re-routes the TIM3 outputs, programs the - * pins as alternate functions and finally enables channels with zero - * initial duty cycle. + * pins as alternate functions. * Note, the AFIO access routes the TIM3 output pins on the PC6...PC9 * where the LEDs are connected. */ @@ -206,6 +198,14 @@ int main(int argc, char **argv) { palSetGroupMode(GPIOC, PAL_PORT_BIT(GPIOC_LED3) | PAL_PORT_BIT(GPIOC_LED4), PAL_MODE_STM32_ALTERNATE_PUSHPULL); + /* + * Initializes the ADC driver 1 and performs a conversion. + * The pin PC0 on the port GPIOC is programmed as analog input. + */ + adcStart(&ADCD1, &adccfg); + palSetGroupMode(GPIOC, PAL_PORT_BIT(0), PAL_MODE_INPUT_ANALOG); + adcConvert(&ADCD1, &adcgrpcfg, samples, ADC_GRP1_BUF_DEPTH); + /* * Creates the example thread. */ -- cgit v1.2.3 From 9fe796d536f7a076977714139774c16582a48f98 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 26 Nov 2010 19:24:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2428 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 445872f00..6565aae8a 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -95,8 +95,8 @@ static const SPIConfig spicfg = { }; /* - * PWM cyclic callback. PWM channels are reprogrammed using a duty cycle - * calculated as average of the last sampling operations. + * PWM cyclic callback. + * A new ADC conversion is started. */ static void pwmpcb(PWMDriver *pwmp) { @@ -112,6 +112,7 @@ static void pwmpcb(PWMDriver *pwmp) { /* * ADC end conversion callback. + * The PWM channels are reprogrammed using the latest ADC samples. * The latest samples are transmitted into a single SPI transaction. */ void adccb(ADCDriver *adcp, adcsample_t *buffer, size_t n) { -- cgit v1.2.3 From 5d58cff918416389a2585e70860101a532757d3c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Nov 2010 10:07:20 +0000 Subject: Updated reports. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2429 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 8 ++ .../cosmic/cosmic.stp | 126 +++++++++---------- .../raisonance/raisonance.stp | 134 ++++++++++----------- 3 files changed, 138 insertions(+), 130 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 6565aae8a..b11101548 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -183,6 +183,14 @@ int main(int argc, char **argv) { */ sdStart(&SD1, NULL); + /* + * If the user button is pressed after the reset then the test suite is + * executed immediately before activating the various device drivers in + * order to not alter the benchmark scores. + */ + if (palReadPad(GPIOA, GPIOA_BUTTON)) + TestThread(&SD1); + /* * Initializes the SPI driver 1. */ diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp index 6f1accdef..b3822ef15 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/cosmic/cosmic.stp @@ -641,40 +641,40 @@ PathName=..\..\..\os\hal\platforms\stm8l\hal_lld.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder PathName=Source Files\os\kernel -Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c Next=Root.Source Files.Source Files\os.Source Files\os\port -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] ElemType=File -PathName=..\..\..\os\kernel\src\chdynamic.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1 +PathName=..\..\..\os\kernel\src\chcond.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -682,20 +682,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -703,37 +703,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] ElemType=File -PathName=..\..\..\os\kernel\src\chcond.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1 +PathName=..\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -741,20 +741,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chcond.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -762,37 +762,37 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 String.8.0=Release -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] ElemType=File -PathName=..\..\..\os\kernel\src\chdebug.c +PathName=..\..\..\os\kernel\src\chdynamic.c Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1 +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2 +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0] String.6.0=2010,11,12,20,29,53 String.8.0=Debug Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.0.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -800,20 +800,20 @@ String.5.0=$(IntermPath)$(InputName).ls String.6.0=2010,11,12,20,27,7 String.8.0=Debug -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.0] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0] String.6.0=2010,11,12,20,29,53 String.8.0=Release Int.0=0 Int.1=0 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.1] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1] String.2.0=Performing Custom Build on $(InputFile) String.3.0= String.4.0= String.5.0= String.6.0=2010,5,25,14,45,56 -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c.Config.1.Settings.2] +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] String.2.0=Compiling $(InputFile)... String.3.0=cxstm8 -i..\..\..\os\hal\platforms\stm8l +modsl0 -customC-pp -customLst-ll -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\boards\st_stm8l_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile) String.4.0=$(IntermPath)$(InputName).$(ObjectExt) @@ -2116,14 +2116,9 @@ PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder PathName=Include Files\os\kernel -Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h +Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h Next=Root.Include Files.Include Files\os.Include Files\os\port -[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] -ElemType=File -PathName=..\..\..\os\kernel\include\chdynamic.h -Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h - [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\ch.h] ElemType=File PathName=..\..\..\os\kernel\include\ch.h @@ -2137,6 +2132,11 @@ Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\ker [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h] ElemType=File PathName=..\..\..\os\kernel\include\chdebug.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h] diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp index be7b81a1c..400535deb 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/raisonance/raisonance.stp @@ -554,68 +554,9 @@ PathName=..\..\..\os\hal\platforms\stm8l\shared_isr.c [Root.Source Files.Source Files\os.Source Files\os\kernel] ElemType=Folder PathName=Source Files\os\kernel -Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c +Child=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c Next=Root.Source Files.Source Files\os.Source Files\os\port -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] -ElemType=File -PathName=..\..\..\os\kernel\src\chdynamic.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c -Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0 -Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0] -Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0 -Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1 -Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1] -Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0 -Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1 -Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0] -String.6.0=2010,11,12,20,29,54 -String.8.0=Debug -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,11,12,20,27,7 -String.8.0=Debug - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0] -String.6.0=2010,11,12,20,29,54 -String.8.0=Release -Int.0=0 -Int.1=0 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1] -String.2.0=Performing Custom Build on $(InputFile) -String.3.0= -String.4.0= -String.5.0= -String.6.0=2010,6,4,10,10,40 - -[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] -String.2.0=Compiling $(InputFile)... -String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) -String.4.0=$(IntermPath)$(InputName).$(ObjectExt) -String.5.0=$(IntermPath)$(InputName).lst -String.6.0=2010,11,12,20,27,7 -String.8.0=Release - [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chvt.c] ElemType=File PathName=..\..\..\os\kernel\src\chvt.c @@ -1445,7 +1386,7 @@ String.8.0=Release [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c] ElemType=File PathName=..\..\..\os\kernel\src\chevents.c -Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.0 Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chevents.c.Config.1 @@ -1501,6 +1442,65 @@ String.5.0=$(IntermPath)$(InputName).lst String.6.0=2010,11,12,20,27,7 String.8.0=Release +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c] +ElemType=File +PathName=..\..\..\os\kernel\src\chdynamic.c +Next=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c +Config.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0 +Config.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0] +Settings.0.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0 +Settings.0.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1 +Settings.0.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1] +Settings.1.0=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0 +Settings.1.1=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1 +Settings.1.2=Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Debug +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.0.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Debug + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.0] +String.6.0=2010,11,12,20,29,54 +String.8.0=Release +Int.0=0 +Int.1=0 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.1] +String.2.0=Performing Custom Build on $(InputFile) +String.3.0= +String.4.0= +String.5.0= +String.6.0=2010,6,4,10,10,40 + +[Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdynamic.c.Config.1.Settings.2] +String.2.0=Compiling $(InputFile)... +String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DGC(data) AUTO -customSpeedOpt -CustomOptimOT(7,SPEED) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\boards\st_stm8l_discovery) PIN(..\demo) PIN(..\..\..\os\kernel\include) PIN(..\..\..\os\hal\include) PIN(..\..\..\test) PIN(..\..\..\os\ports\rc\stm8) PIN(..\..\..\os\hal\platforms\stm8l) +String.4.0=$(IntermPath)$(InputName).$(ObjectExt) +String.5.0=$(IntermPath)$(InputName).lst +String.6.0=2010,11,12,20,27,7 +String.8.0=Release + [Root.Source Files.Source Files\os.Source Files\os\kernel...\..\..\os\kernel\src\chdebug.c] ElemType=File PathName=..\..\..\os\kernel\src\chdebug.c @@ -2029,14 +2029,9 @@ PathName=..\..\..\os\hal\platforms\stm8l\stm8l15x.h [Root.Include Files.Include Files\os.Include Files\os\kernel] ElemType=Folder PathName=Include Files\os\kernel -Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h +Child=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h Next=Root.Include Files.Include Files\os.Include Files\os\port -[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] -ElemType=File -PathName=..\..\..\os\kernel\include\chdynamic.h -Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h - [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chvt.h] ElemType=File PathName=..\..\..\os\kernel\include\chvt.h @@ -2125,6 +2120,11 @@ Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\ker [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chevents.h] ElemType=File PathName=..\..\..\os\kernel\include\chevents.h +Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h + +[Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdynamic.h] +ElemType=File +PathName=..\..\..\os\kernel\include\chdynamic.h Next=Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h [Root.Include Files.Include Files\os.Include Files\os\kernel...\..\..\os\kernel\include\chdebug.h] -- cgit v1.2.3 From e89ce00860c0c3df61c50f516e4fec59f75ad1df Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Nov 2010 10:27:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2430 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../cosmic/cosmic.stp | 52 +++++++++++----------- .../raisonance/raisonance.stp | 52 +++++++++++----------- 2 files changed, 52 insertions(+), 52 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index 0aa8ea683..2baf85710 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -504,29 +504,29 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\s [Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\spi.c] ElemType=File PathName=..\..\..\os\hal\src\spi.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s] ElemType=Folder -PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c +PathName=Source Files\os\hal\stm8s +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.c @@ -1910,39 +1910,39 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\in [Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\spi.h] ElemType=File PathName=..\..\..\os\hal\include\spi.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8 +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s] ElemType=Folder -PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h +PathName=Include Files\os\hal\stm8s +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s_type.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s_type.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\stm8s_type.h diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index 351f449c8..4176b9ecc 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -525,29 +525,29 @@ Next=Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\a [Root.Source Files.Source Files\os.Source Files\os\hal...\..\..\os\hal\src\adc.c] ElemType=File PathName=..\..\..\os\hal\src\adc.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8 +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s] ElemType=Folder -PathName=Source Files\os\hal\stm8 -Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c +PathName=Source Files\os\hal\stm8s +Child=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.c -Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c +Next=Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.c -[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.c] +[Root.Source Files.Source Files\os.Source Files\os\hal.Source Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.c] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.c @@ -1931,39 +1931,39 @@ Next=Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\in [Root.Include Files.Include Files\os.Include Files\os\hal...\..\..\os\hal\include\adc.h] ElemType=File PathName=..\..\..\os\hal\include\adc.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8 +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s] ElemType=Folder -PathName=Include Files\os\hal\stm8 -Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h +PathName=Include Files\os\hal\stm8s +Child=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\spi_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\spi_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\spi_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s_type.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s_type.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s_type.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\stm8s_type.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\stm8s.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\stm8s.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\stm8s.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\serial_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\serial_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\serial_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\pal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\pal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\pal_lld.h -Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h +Next=Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.h -[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8...\..\..\os\hal\platforms\stm8s\hal_lld.h] +[Root.Include Files.Include Files\os.Include Files\os\hal.Include Files\os\hal\stm8s...\..\..\os\hal\platforms\stm8s\hal_lld.h] ElemType=File PathName=..\..\..\os\hal\platforms\stm8s\hal_lld.h -- cgit v1.2.3 From 59d0598d8f61d247b7e092d97f861fedb3a11a5b Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Nov 2010 11:11:45 +0000 Subject: Fixed problem in STM8S vectors file for the Cosmic compiler. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2431 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c index f97703b7f..494943416 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c @@ -69,7 +69,7 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector7 */ {0x82, vector}, /* vector8 */ {0x82, vector}, /* vector9 */ -#if HAL_USE_SPI && STM8_SPI_USE_SPI +#if HAL_USE_SPI && STM8S_SPI_USE_SPI {0x82, vector10}, #else {0x82, vector}, /* vector10 */ @@ -80,7 +80,7 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector14 */ {0x82, vector}, /* vector15 */ {0x82, vector}, /* vector16 */ -#if HAL_USE_SERIAL && STM8_SERIAL_USE_UART1 +#if HAL_USE_SERIAL && STM8S_SERIAL_USE_UART1 {0x82, vector17}, /* vector17 */ {0x82, vector18}, /* vector18 */ #else @@ -88,7 +88,7 @@ exception_vector_t const _vectab[] = { {0x82, vector}, /* vector18 */ #endif {0x82, vector}, /* vector19 */ -#if HAL_USE_SERIAL && (STM8_SERIAL_USE_UART2 || STM8_SERIAL_USE_UART3) +#if HAL_USE_SERIAL && (STM8S_SERIAL_USE_UART2 || STM8S_SERIAL_USE_UART3) {0x82, vector20}, /* vector20 */ {0x82, vector21}, /* vector21 */ #else -- cgit v1.2.3 From f13dabb9985c5604c4150f4c8476ba74607f293d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Nov 2010 11:29:25 +0000 Subject: Fixes to the STM8S RIDE7 project. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2433 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw | 2 +- .../cosmic/cosmic.stp | 4 +- .../raisonance/raisonance.stp | 4 +- demos/STM8S-STM8S208-RC/ch.rapp | 69 +++++++++++----------- demos/STM8S-STM8S208-RC/ch.rprj | 2 +- demos/STM8S-STM8S208-RC/mcuconf.h | 10 ++-- 6 files changed, 47 insertions(+), 44 deletions(-) (limited to 'demos') diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw index a6630271a..130504bef 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw @@ -11,6 +11,6 @@ Dependencies= Filename=raisonance\raisonance.stp Dependencies= [Options] -ActiveProject=cosmic +ActiveProject=raisonance ActiveConfig=Release AddSortedElements=0 diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp index 2baf85710..a477aa256 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib @@ -144,7 +144,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=STM8 Cosmic -String.102.0=C:\Program Files\COSMIC\CXSTM8_32K +String.102.0=C:\Programmi\COSMIC\CXSTM8_32K String.103.0= String.104.0=Hstm8 String.105.0=Lib diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp index 4176b9ecc..de4b0c75e 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp @@ -61,7 +61,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 @@ -130,7 +130,7 @@ String.100.2=STM8 Cosmic String.100.3=ST7 Metrowerks V1.1 String.100.4=Raisonance String.101.0=Raisonance -String.102.0=C:\Program Files\Raisonance\Ride +String.102.0=C:\Programmi\Raisonance\Ride String.103.0=bin String.104.0=INC\ST7;INC String.105.0=LIB\ST7 diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index 85071d41a..fbe5413e6 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -1,8 +1,9 @@ - - + + + @@ -10,15 +11,15 @@
- +
- + - + - + - + @@ -30,7 +31,7 @@ - + @@ -41,17 +42,17 @@
- +
- + - + - + - + - + @@ -66,11 +67,11 @@ - + - + @@ -82,15 +83,17 @@ - - - - - + + + + + + + - + @@ -98,21 +101,21 @@
- +
- +
- +
- +
@@ -123,33 +126,33 @@
- +
- +
- +
- +
- +
- +
- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index ad8b9b39e..138f43304 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/mcuconf.h b/demos/STM8S-STM8S208-RC/mcuconf.h index bb38a3760..198106dec 100644 --- a/demos/STM8S-STM8S208-RC/mcuconf.h +++ b/demos/STM8S-STM8S208-RC/mcuconf.h @@ -29,9 +29,9 @@ * HAL general settings. */ #define STM8S_NO_CLOCK_INIT FALSE -#define STM8S_HSI_ENABLED FALSE +#define STM8S_HSI_ENABLED TRUE #define STM8S_LSI_ENABLED TRUE -#define STM8S_HSE_ENABLED TRUE +#define STM8S_HSE_ENABLED FALSE #define STM8S_SYSCLK_SOURCE CLK_SYSSEL_HSI #define STM8S_HSI_DIVIDER CLK_HSI_DIV1 #define STM8S_CPU_DIVIDER CLK_CPU_DIV1 @@ -40,9 +40,9 @@ /* * SERIAL driver system settings. */ -#define USE_STM8S_UART1 TRUE -#define USE_STM8S_UART2 FALSE -#define USE_STM8S_UART3 FALSE +#define STM8S_SERIAL_USE_UART1 TRUE +#define STM8S_SERIAL_USE_UART2 FALSE +#define STM8S_SERIAL_USE_UART3 FALSE /* * SPI driver system settings. -- cgit v1.2.3 From 9b7b5ce6bfd67fc6317445651af4906c7a54c528 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 27 Nov 2010 19:16:40 +0000 Subject: Fixed bug 3120785. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2439 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h | 10 ++++++---- demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h | 10 ++++++---- demos/ARMCM3-STM32F103-GCC/mcuconf.h | 10 ++++++---- demos/ARMCM3-STM32F107-GCC/mcuconf.h | 10 ++++++---- 4 files changed, 24 insertions(+), 16 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h index 0ff6793f2..017a37fde 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/mcuconf.h @@ -65,10 +65,12 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 TRUE #define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM_PWM4_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 /* * SERIAL driver system settings. diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index 42022d23c..251197a66 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -65,10 +65,12 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM_PWM4_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 /* * SERIAL driver system settings. diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index 42022d23c..251197a66 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -65,10 +65,12 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM_PWM4_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 /* * SERIAL driver system settings. diff --git a/demos/ARMCM3-STM32F107-GCC/mcuconf.h b/demos/ARMCM3-STM32F107-GCC/mcuconf.h index b11c2aae9..a0374fc04 100644 --- a/demos/ARMCM3-STM32F107-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F107-GCC/mcuconf.h @@ -68,10 +68,12 @@ #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_PWM1_IRQ_PRIORITY 7 -#define STM32_PWM_PWM2_IRQ_PRIORITY 7 -#define STM32_PWM_PWM3_IRQ_PRIORITY 7 -#define STM32_PWM_PWM4_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 /* * SERIAL driver system settings. -- cgit v1.2.3 From ef0b196ab912a89d2923264bf5a8b2b492b15cba Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 28 Nov 2010 14:21:34 +0000 Subject: Removed obsolete options from some makefiles. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2451 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile | 2 +- demos/ARMCM3-STM32F103-GCC/Makefile | 2 +- demos/ARMCM3-STM32F107-GCC/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile index ef033772f..00405071a 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/Makefile @@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DCORTEX_USE_BASEPRI=TRUE +DDEFS = # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F103-GCC/Makefile b/demos/ARMCM3-STM32F103-GCC/Makefile index 7b0e82f90..74f23b072 100644 --- a/demos/ARMCM3-STM32F103-GCC/Makefile +++ b/demos/ARMCM3-STM32F103-GCC/Makefile @@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DCORTEX_USE_BASEPRI=TRUE +DDEFS = # List all default ASM defines here, like -D_DEBUG=1 DADEFS = diff --git a/demos/ARMCM3-STM32F107-GCC/Makefile b/demos/ARMCM3-STM32F107-GCC/Makefile index bd265aef1..dc4ebeeeb 100644 --- a/demos/ARMCM3-STM32F107-GCC/Makefile +++ b/demos/ARMCM3-STM32F107-GCC/Makefile @@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra # # List all default C defines here, like -D_DEBUG=1 -DDEFS = -DCORTEX_USE_BASEPRI=TRUE +DDEFS = # List all default ASM defines here, like -D_DEBUG=1 DADEFS = -- cgit v1.2.3 From 68b05c757a60ba3bddbfb76d02b992f96d1e63f9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 2 Dec 2010 17:40:37 +0000 Subject: Fixed typo in configuration files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2453 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h | 2 +- demos/ARM7-AT91SAM7S-GCC/chconf.h | 2 +- demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h | 2 +- demos/ARM7-AT91SAM7X-GCC/chconf.h | 2 +- demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h | 2 +- demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h | 2 +- demos/ARM7-LPC214x-FATFS-GCC/chconf.h | 2 +- demos/ARM7-LPC214x-G++/chconf.h | 2 +- demos/ARM7-LPC214x-GCC/chconf.h | 2 +- demos/ARMCM0-LPC1114-GCC/chconf.h | 2 +- demos/ARMCM3-LPC1343-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F103-GCC/chconf.h | 2 +- demos/ARMCM3-STM32F107-GCC/chconf.h | 2 +- demos/AVR-AT90CANx-GCC/chconf.h | 2 +- demos/AVR-ATmega128-GCC/chconf.h | 2 +- demos/MSP430-MSP430x1611-GCC/chconf.h | 2 +- demos/PPC-SPC563-GCC/chconf.h | 2 +- demos/Posix-GCC/chconf.h | 2 +- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h | 2 +- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h | 2 +- demos/STM8S-STM8S208-RC/chconf.h | 2 +- demos/Win32-MinGW/chconf.h | 2 +- 24 files changed, 24 insertions(+), 24 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARM7-AT91SAM7S-GCC/chconf.h b/demos/ARM7-AT91SAM7S-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-AT91SAM7S-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index f84bb536a..a7ff720a7 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS TRUE diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARMCM0-LPC1114-GCC/chconf.h b/demos/ARMCM0-LPC1114-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARMCM0-LPC1114-GCC/chconf.h +++ b/demos/ARMCM0-LPC1114-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARMCM3-LPC1343-GCC/chconf.h b/demos/ARMCM3-LPC1343-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARMCM3-LPC1343-GCC/chconf.h +++ b/demos/ARMCM3-LPC1343-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARMCM3-STM32F103-GCC/chconf.h b/demos/ARMCM3-STM32F103-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARMCM3-STM32F103-GCC/chconf.h +++ b/demos/ARMCM3-STM32F103-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/ARMCM3-STM32F107-GCC/chconf.h b/demos/ARMCM3-STM32F107-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/ARMCM3-STM32F107-GCC/chconf.h +++ b/demos/ARMCM3-STM32F107-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 8c10de14c..c982a771d 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 8c10de14c..c982a771d 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index dbd5e4469..ce35b359d 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h index 98bcdc40c..3353391ca 100644 --- a/demos/PPC-SPC563-GCC/chconf.h +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h index 3ced2ccbc..6b9da5975 100644 --- a/demos/Posix-GCC/chconf.h +++ b/demos/Posix-GCC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h index 12b5c9e15..7e0ba6086 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h index 12b5c9e15..7e0ba6086 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index 12b5c9e15..7e0ba6086 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index 3ced2ccbc..6b9da5975 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -68,7 +68,7 @@ * You may use this option if you need to merge ChibiOS/RT with * external libraries that require nested lock/unlock operations. * - * @note T he default is @p FALSE. + * @note The default is @p FALSE. */ #if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) #define CH_USE_NESTED_LOCKS FALSE -- cgit v1.2.3 From f650ce36c1566f76604a7483bce91ca0d508456f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 5 Dec 2010 11:47:18 +0000 Subject: Better mcuconf.h file for LPC11xx. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2459 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/mcuconf.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/mcuconf.h b/demos/ARMCM0-LPC1114-GCC/mcuconf.h index abab32579..aafb2901d 100644 --- a/demos/ARMCM0-LPC1114-GCC/mcuconf.h +++ b/demos/ARMCM0-LPC1114-GCC/mcuconf.h @@ -31,6 +31,11 @@ /* * HAL driver system settings. */ +#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC11xx_SYSPLL_MUL 4 +#define LPC11xx_SYSPLL_DIV 4 +#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC11xx_SYSABHCLK_DIV 1 /* * ADC driver system settings. @@ -47,7 +52,19 @@ /* * SERIAL driver system settings. */ +#define LPC11xx_SERIAL_USE_UART0 TRUE +#define LPC11xx_SERIAL_FIFO_PRELOAD 16 +#define LPC11xx_SERIAL_UART0CLKDIV 1 +#define LPC11xx_SERIAL_UART0_IRQ_PRIORITY 3 /* * SPI driver system settings. */ +#define LPC11xx_SPI_USE_SSP0 TRUE +#define LPC11xx_SPI_USE_SSP1 FALSE +#define LPC11xx_SPI_SSP0CLKDIV 1 +#define LPC11xx_SPI_SSP1CLKDIV 1 +#define LPC11xx_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP1_IRQ_PRIORITY 1 +#define LPC11xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 -- cgit v1.2.3 From d8edc8d012500fa4b97d7f8f9dc1aa15bfd9014e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 5 Dec 2010 12:18:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2460 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-LPC1343-GCC/mcuconf.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'demos') diff --git a/demos/ARMCM3-LPC1343-GCC/mcuconf.h b/demos/ARMCM3-LPC1343-GCC/mcuconf.h index 5eb8abe4a..f5d119449 100644 --- a/demos/ARMCM3-LPC1343-GCC/mcuconf.h +++ b/demos/ARMCM3-LPC1343-GCC/mcuconf.h @@ -31,6 +31,11 @@ /* * HAL driver system settings. */ +#define LPC13xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC13xx_SYSPLL_MUL 6 +#define LPC13xx_SYSPLL_DIV 4 +#define LPC13xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC13xx_SYSABHCLK_DIV 1 /* * ADC driver system settings. @@ -47,7 +52,16 @@ /* * SERIAL driver system settings. */ +#define LPC13xx_SERIAL_USE_UART0 TRUE +#define LPC13xx_SERIAL_FIFO_PRELOAD 16 +#define LPC13xx_SERIAL_UART0CLKDIV 1 +#define LPC13xx_SERIAL_UART0_IRQ_PRIORITY 3 /* * SPI driver system settings. */ +#define LPC13xx_SPI_USE_SSP0 TRUE +#define LPC13xx_SPI_SSP0CLKDIV 1 +#define LPC13xx_SPI_SSP0_IRQ_PRIORITY 5 +#define LPC13xx_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#define LPC13xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11 -- cgit v1.2.3 From bf311d77cb64a72df9ab657f8a0930c1939f70fd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 7 Dec 2010 16:47:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2464 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/main.c | 4 +++- demos/ARMCM3-LPC1343-GCC/main.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 61d48003f..2b05b6f5d 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -33,7 +33,9 @@ static uint8_t digits[32] = { 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 }; -/* Maximum speed SPI configuration (1MHz, CPHA=0, CPOL=0).*/ +/* + * SPI configuration (1MHz, CPHA=0, CPOL=0). + */ static SPIConfig spicfg = { NULL, GPIO1, diff --git a/demos/ARMCM3-LPC1343-GCC/main.c b/demos/ARMCM3-LPC1343-GCC/main.c index a645bf3d2..996db61b3 100644 --- a/demos/ARMCM3-LPC1343-GCC/main.c +++ b/demos/ARMCM3-LPC1343-GCC/main.c @@ -33,7 +33,9 @@ static uint8_t digits[32] = { 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 }; -/* Maximum speed SPI configuration (1MHz, CPHA=0, CPOL=0).*/ +/* + * SPI configuration (1MHz, CPHA=0, CPOL=0). + */ static SPIConfig spicfg = { NULL, GPIO1, -- cgit v1.2.3 From 1df1af83f8f93fae997ba8870ee68a97526f6194 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 11 Dec 2010 09:07:18 +0000 Subject: ADC configuration change. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2468 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index b11101548..07ab18537 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -48,7 +48,7 @@ static const ADCConversionGroup adcgrpcfg = { adccb, /* HW dependent part.*/ 0, - ADC_CR2_EXTSEL_SWSTART | ADC_CR2_TSVREFE | ADC_CR2_CONT, + ADC_CR2_TSVREFE | ADC_CR2_CONT, ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5), 0, ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), -- cgit v1.2.3 From 7d66301e92b84f645e2134819cb9b24caf786d6a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 11 Dec 2010 17:35:55 +0000 Subject: More STM32 ADC improvements. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2472 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 07ab18537..4d4df9297 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -48,7 +48,7 @@ static const ADCConversionGroup adcgrpcfg = { adccb, /* HW dependent part.*/ 0, - ADC_CR2_TSVREFE | ADC_CR2_CONT, + ADC_CR2_TSVREFE, ADC_SMPR1_SMP_AN10(ADC_SAMPLE_41P5) | ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_239P5), 0, ADC_SQR1_NUM_CH(ADC_GRP1_NUM_CHANNELS), -- cgit v1.2.3 From 975780704949e2ed551c3e50a81ea5e45d28a0af Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 14 Dec 2010 22:27:09 +0000 Subject: Added working prototype Cortex-Mx port for IAR compiler and related demo for STM32. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2479 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-IAR/ch.ewd | 1659 ++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-IAR/ch.ewp | 2156 ++++++++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-IAR/ch.eww | 10 + demos/ARMCM3-STM32F103-IAR/ch.icf | 34 + demos/ARMCM3-STM32F103-IAR/chconf.h | 507 ++++++++ demos/ARMCM3-STM32F103-IAR/halconf.h | 259 ++++ demos/ARMCM3-STM32F103-IAR/main.c | 69 ++ demos/ARMCM3-STM32F103-IAR/mcuconf.h | 119 ++ 8 files changed, 4813 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-IAR/ch.ewd create mode 100644 demos/ARMCM3-STM32F103-IAR/ch.ewp create mode 100644 demos/ARMCM3-STM32F103-IAR/ch.eww create mode 100644 demos/ARMCM3-STM32F103-IAR/ch.icf create mode 100644 demos/ARMCM3-STM32F103-IAR/chconf.h create mode 100644 demos/ARMCM3-STM32F103-IAR/halconf.h create mode 100644 demos/ARMCM3-STM32F103-IAR/main.c create mode 100644 demos/ARMCM3-STM32F103-IAR/mcuconf.h (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-IAR/ch.ewd b/demos/ARMCM3-STM32F103-IAR/ch.ewd new file mode 100644 index 000000000..9d8c77ba5 --- /dev/null +++ b/demos/ARMCM3-STM32F103-IAR/ch.ewd @@ -0,0 +1,1659 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + JLINK_ID + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 1 + 1 + 1 + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + 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+ + $PROJ_DIR$\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\os\hal\src\uart.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\os\kernel\include\chioch.h + + + $PROJ_DIR$\..\..\os\kernel\include\chlists.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmboxes.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmemcore.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmempools.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmsg.h + + + $PROJ_DIR$\..\..\os\kernel\include\chmtx.h + + + $PROJ_DIR$\..\..\os\kernel\include\chqueues.h + + + $PROJ_DIR$\..\..\os\kernel\include\chregistry.h + + + $PROJ_DIR$\..\..\os\kernel\include\chschd.h + + + $PROJ_DIR$\..\..\os\kernel\include\chsem.h + + + $PROJ_DIR$\..\..\os\kernel\include\chstreams.h + + + $PROJ_DIR$\..\..\os\kernel\include\chsys.h + + + $PROJ_DIR$\..\..\os\kernel\include\chthreads.h + + + $PROJ_DIR$\..\..\os\kernel\include\chvt.h + + + + src + + $PROJ_DIR$\..\..\os\kernel\src\chcond.c + + + $PROJ_DIR$\..\..\os\kernel\src\chdebug.c + + + $PROJ_DIR$\..\..\os\kernel\src\chdynamic.c + + + $PROJ_DIR$\..\..\os\kernel\src\chevents.c + + + $PROJ_DIR$\..\..\os\kernel\src\chheap.c + + + $PROJ_DIR$\..\..\os\kernel\src\chlists.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmboxes.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmemcore.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmempools.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmsg.c + + + $PROJ_DIR$\..\..\os\kernel\src\chmtx.c + + + $PROJ_DIR$\..\..\os\kernel\src\chqueues.c + + + $PROJ_DIR$\..\..\os\kernel\src\chregistry.c + + + $PROJ_DIR$\..\..\os\kernel\src\chschd.c + + + $PROJ_DIR$\..\..\os\kernel\src\chsem.c + + + $PROJ_DIR$\..\..\os\kernel\src\chsys.c + + + $PROJ_DIR$\..\..\os\kernel\src\chthreads.c + + + $PROJ_DIR$\..\..\os\kernel\src\chvt.c + + + + + platform + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\adc_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\adc_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\can_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\can_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\core_cm3.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\hal_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\hal_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\hal_lld_f100.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\hal_lld_f103.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\hal_lld_f105_f107.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\pal_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\pal_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\pwm_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\pwm_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\serial_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\serial_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\spi_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\spi_lld.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\stm32_dma.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\stm32_dma.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\stm32f10x.h + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\uart_lld.c + + + $PROJ_DIR$\..\..\os\hal\platforms\STM32\uart_lld.h + + + + port + + STM32 + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\STM32\cmparams.h + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\STM32\vectors.s + + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\os\ports\IAR\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\test\test.c + + + $PROJ_DIR$\..\..\test\test.h + + + $PROJ_DIR$\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\test\testthd.h + + + + $PROJ_DIR$\chconf.h + + + $PROJ_DIR$\halconf.h + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\mcuconf.h + + + + diff --git a/demos/ARMCM3-STM32F103-IAR/ch.eww b/demos/ARMCM3-STM32F103-IAR/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-STM32F103-IAR/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-STM32F103-IAR/ch.icf b/demos/ARMCM3-STM32F103-IAR/ch.icf new file mode 100644 index 000000000..17c43efc9 --- /dev/null +++ b/demos/ARMCM3-STM32F103-IAR/ch.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the Process Stack.*/ +define symbol __ICFEDIT_size_pstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PSTACK with alignment = 8, size = __ICFEDIT_size_pstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { block PSTACK, block CSTACK, readwrite, block HEAP }; diff --git a/demos/ARMCM3-STM32F103-IAR/chconf.h b/demos/ARMCM3-STM32F103-IAR/chconf.h new file mode 100644 index 000000000..1010979ac --- /dev/null +++ b/demos/ARMCM3-STM32F103-IAR/chconf.h @@ -0,0 +1,507 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/* Kernel parameters. */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Nested locks. + * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock() + * operations is allowed.
+ * For performance and code size reasons the recommended setting + * is to leave this option disabled.
+ * You may use this option if you need to merge ChibiOS/RT with + * external libraries that require nested lock/unlock operations. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__) +#define CH_USE_NESTED_LOCKS FALSE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_COREMEM. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 8192 +#endif + +/*===========================================================================*/ +/* Performance options. */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** + * @brief Exotic optimization. + * @details If defined then a CPU register is used as storage for the global + * @p currp variable. Caching this variable in a register greatly + * improves both space and time OS efficiency. A side effect is that + * one less register has to be saved during the context switch + * resulting in lower RAM usage and faster context switch. + * + * @note This option is only usable with the GCC compiler and is only useful + * on processors with many registers like ARM cores. + * @note If this option is enabled then ALL the libraries linked to the + * ChibiOS/RT code must be recompiled with the GCC option @p + * -ffixed-@. + * @note This option must be enabled in the Makefile, it is listed here for + * documentation only. + */ +#if defined(__DOXYGEN__) +#define CH_CURRP_REGISTER_CACHE "reg" +#endif + +/*===========================================================================*/ +/* Subsystem options. */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/*===========================================================================*/ +/* Debug options. */ +/*===========================================================================*/ + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/*===========================================================================*/ +/* Kernel hooks. */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitily from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-IAR/halconf.h b/demos/ARMCM3-STM32F103-IAR/halconf.h new file mode 100644 index 000000000..890f3896b --- /dev/null +++ b/demos/ARMCM3-STM32F103-IAR/halconf.h @@ -0,0 +1,259 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* PWM driver related settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM3-STM32F103-IAR/main.c b/demos/ARMCM3-STM32F103-IAR/main.c new file mode 100644 index 000000000..fca30c731 --- /dev/null +++ b/demos/ARMCM3-STM32F103-IAR/main.c @@ -0,0 +1,69 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * Red LEDs blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + while (TRUE) { + palClearPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + palSetPad(IOPORT3, GPIOC_LED); + chThdSleepMilliseconds(500); + } +} + +/* + * Entry point. + */ +int main(int argc, char **argv) { + void hwinit1(void); + + (void)argc; + (void)argv; + + hwinit1(); + + /* + * Activates the serial driver 2 using the driver default configuration. + */ + sdStart(&SD2, NULL); + + /* + * Creates the blinker thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (TRUE) { + if (palReadPad(IOPORT1, GPIOA_BUTTON)) + TestThread(&SD2); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/ARMCM3-STM32F103-IAR/mcuconf.h b/demos/ARMCM3-STM32F103-IAR/mcuconf.h new file mode 100644 index 000000000..251197a66 --- /dev/null +++ b/demos/ARMCM3-STM32F103-IAR/mcuconf.h @@ -0,0 +1,119 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * STM32 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_PLLMUL_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_MCO STM32_MCO_NOCLOCK + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 3 +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_ERROR_HOOK() chSysHalt() + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 2 +#define STM32_SPI_SPI2_DMA_PRIORITY 2 +#define STM32_SPI_SPI3_DMA_PRIORITY 2 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_SPI_SPI3_DMA_ERROR_HOOK() chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt() -- cgit v1.2.3 From b67722afdc0d5b141b998358a558730f532daec0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 15 Dec 2010 21:41:09 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2483 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-IAR/ch.ewp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-IAR/ch.ewp b/demos/ARMCM3-STM32F103-IAR/ch.ewp index 504fd31ed..61e51d576 100644 --- a/demos/ARMCM3-STM32F103-IAR/ch.ewp +++ b/demos/ARMCM3-STM32F103-IAR/ch.ewp @@ -1171,7 +1171,7 @@ @@ -1732,7 +1732,6 @@ Debug - Release board -- cgit v1.2.3 From 1aad1a508faeeb61b23764e02daa8494c9c61b55 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 18 Dec 2010 09:24:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2491 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-IAR/main.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-IAR/main.c b/demos/ARMCM3-STM32F103-IAR/main.c index fca30c731..a3a5c062e 100644 --- a/demos/ARMCM3-STM32F103-IAR/main.c +++ b/demos/ARMCM3-STM32F103-IAR/main.c @@ -40,13 +40,10 @@ static msg_t Thread1(void *arg) { * Entry point. */ int main(int argc, char **argv) { - void hwinit1(void); (void)argc; (void)argv; - hwinit1(); - /* * Activates the serial driver 2 using the driver default configuration. */ -- cgit v1.2.3 From 7d7d9727f9a280d63157ac9997fe271610f05b1e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 09:13:54 +0000 Subject: STM32 board files and demos now use the new organization. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2497 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 13 +++++++++++-- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 13 +++++++++++-- demos/ARMCM3-STM32F103-GCC/main.c | 15 ++++++++++++--- demos/ARMCM3-STM32F103-IAR/main.c | 16 ++++++++++++++-- demos/ARMCM3-STM32F107-GCC/main.c | 15 ++++++++++++--- 5 files changed, 60 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index 4d4df9297..a94600203 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -170,14 +170,23 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 1 using the driver default configuration. */ diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index c9407731c..1d0018b9b 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -264,8 +264,7 @@ static void RemoveHandler(eventid_t id) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -278,6 +277,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index 0072f0958..e133e6e3b 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -22,7 +22,7 @@ #include "test.h" /* - * Red LEDs blinker thread, times are in milliseconds. + * Red LED blinker thread, times are in milliseconds. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { @@ -38,14 +38,23 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/ARMCM3-STM32F103-IAR/main.c b/demos/ARMCM3-STM32F103-IAR/main.c index a3a5c062e..e133e6e3b 100644 --- a/demos/ARMCM3-STM32F103-IAR/main.c +++ b/demos/ARMCM3-STM32F103-IAR/main.c @@ -22,7 +22,7 @@ #include "test.h" /* - * Red LEDs blinker thread, times are in milliseconds. + * Red LED blinker thread, times are in milliseconds. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { @@ -34,16 +34,27 @@ static msg_t Thread1(void *arg) { palSetPad(IOPORT3, GPIOC_LED); chThdSleepMilliseconds(500); } + return 0; } /* - * Entry point. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 2 using the driver default configuration. */ @@ -63,4 +74,5 @@ int main(int argc, char **argv) { TestThread(&SD2); chThdSleepMilliseconds(500); } + return 0; } diff --git a/demos/ARMCM3-STM32F107-GCC/main.c b/demos/ARMCM3-STM32F107-GCC/main.c index bddf485c0..fe463af89 100644 --- a/demos/ARMCM3-STM32F107-GCC/main.c +++ b/demos/ARMCM3-STM32F107-GCC/main.c @@ -22,7 +22,7 @@ #include "test.h" /* - * Red LEDs blinker thread, times are in milliseconds. + * Red LED blinker thread, times are in milliseconds. */ static WORKING_AREA(waThread1, 128); static msg_t Thread1(void *arg) { @@ -38,14 +38,23 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 2 using the driver default configuration. */ -- cgit v1.2.3 From ada9fb82aac5f1bc2465d4555380c2bef40cb8d3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 09:36:44 +0000 Subject: LPC1xxx board files and demos updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2498 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-GCC/main.c | 13 +++++++++++-- demos/ARMCM3-LPC1343-GCC/main.c | 13 +++++++++++-- 2 files changed, 22 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 2b05b6f5d..14f913a0a 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -92,8 +92,7 @@ static msg_t Thread2(void *arg) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { uint8_t i; @@ -101,6 +100,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the SD1 and SPI1 drivers. */ diff --git a/demos/ARMCM3-LPC1343-GCC/main.c b/demos/ARMCM3-LPC1343-GCC/main.c index 996db61b3..0600865f3 100644 --- a/demos/ARMCM3-LPC1343-GCC/main.c +++ b/demos/ARMCM3-LPC1343-GCC/main.c @@ -92,8 +92,7 @@ static msg_t Thread2(void *arg) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { uint8_t i; @@ -101,6 +100,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the SD1 and SPI1 drivers. */ -- cgit v1.2.3 From f131e4297dc619b3f3148a079c634f2cec0fd687 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 10:03:11 +0000 Subject: LPC214x board files and demos updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2499 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-LPC214x-FATFS-GCC/main.c | 13 +++++++++++-- demos/ARM7-LPC214x-G++/main.cpp | 13 +++++++++++-- demos/ARM7-LPC214x-GCC/main.c | 13 +++++++++++-- 3 files changed, 33 insertions(+), 6 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c index ffe50af6a..9edae1db7 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -221,8 +221,7 @@ static void RemoveHandler(eventid_t id) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -236,6 +235,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index b6b7c83ba..8a9ca1c05 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -142,8 +142,7 @@ static void TimerHandler(eventid_t id) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -155,6 +154,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + System::Init(); + /* * Activates the serial driver 2 using the driver default configuration. */ diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 9ac1b7698..6cc8037f6 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -60,14 +60,23 @@ static msg_t Thread2(void *arg) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 2 using the driver default configuration. */ -- cgit v1.2.3 From 35c315a77a92d8ca0efefea329770c6bf9adca2d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 10:25:31 +0000 Subject: AT91SAM7x board files and demos updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2500 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/main.c | 13 +++++++++++-- demos/ARM7-AT91SAM7S-GCC/main.c | 14 ++++++++++++-- demos/ARM7-AT91SAM7X-FATFS-GCC/main.c | 13 +++++++++++-- demos/ARM7-AT91SAM7X-GCC/main.c | 13 +++++++++++-- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 13 +++++++++++-- demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 13 +++++++++++-- 6 files changed, 67 insertions(+), 12 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c index 5ebd0b9ff..95c5c94a3 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c @@ -291,8 +291,7 @@ static void RemoveHandler(eventid_t id) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -305,6 +304,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 1 using the driver default configuration. */ diff --git a/demos/ARM7-AT91SAM7S-GCC/main.c b/demos/ARM7-AT91SAM7S-GCC/main.c index 82e1ee5f2..49ce3df70 100644 --- a/demos/ARM7-AT91SAM7S-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-GCC/main.c @@ -35,13 +35,23 @@ static msg_t Thread1(void *p) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { + (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 1 using the driver default configuration. */ diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c index 3ed2ab0e6..5708cb3b3 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -274,8 +274,7 @@ static void RemoveHandler(eventid_t id) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { static const evhandler_t evhndl[] = { @@ -288,6 +287,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 1 using the driver default configuration. */ diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index f5514b41a..a4af5dadb 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -35,13 +35,22 @@ static msg_t Thread1(void *p) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 1 using the driver default configuration. */ diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index 895766132..bee5b36c9 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -38,14 +38,23 @@ static msg_t Thread1(void *p) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 1 using the driver default configuration. */ diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c index 3a3f5eeb6..1fd5fcf52 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -39,14 +39,23 @@ static msg_t Thread1(void *p) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 2 using the driver default configuration. */ -- cgit v1.2.3 From ace3f844709b1bfdd4c88acbc943bdecf29f9f21 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 10:39:21 +0000 Subject: AVR board files and demos updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2501 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/AVR-AT90CANx-GCC/main.c | 13 +++++++++---- demos/AVR-ATmega128-GCC/main.c | 13 +++++++++---- 2 files changed, 18 insertions(+), 8 deletions(-) (limited to 'demos') diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index f922efed0..79888a55a 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -38,6 +38,9 @@ static void TimerHandler(eventid_t id) { TestThread(&SD2); } +/* + * Application entry point. + */ int main(int argc, char **argv) { static EvTimer evt; static evhandler_t handlers[1] = { @@ -45,12 +48,14 @@ int main(int argc, char **argv) { }; static EventListener el0; - hwinit(); - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ + halInit(); chSysInit(); /* diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index b63d793b5..c02ef5404 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -41,6 +41,9 @@ static void TimerHandler(eventid_t id) { TestThread(&SD2); } +/* + * Application entry point. + */ int main(int argc, char **argv) { static EvTimer evt; static evhandler_t handlers[1] = { @@ -48,12 +51,14 @@ int main(int argc, char **argv) { }; static EventListener el0; - hwinit(); - /* - * The main() function becomes a thread here then the interrupts are - * enabled and ChibiOS/RT goes live. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ + halInit(); chSysInit(); /* -- cgit v1.2.3 From 13f5b1b97fa1ca9516665807682c164aa926fb78 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 10:50:04 +0000 Subject: MSP430 board files and demo updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2502 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/MSP430-MSP430x1611-GCC/main.c | 11 ++++++++--- demos/MSP430-MSP430x1611-GCC/mcuconf.h | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) (limited to 'demos') diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index 3bac249d0..c010b89b3 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -38,7 +38,7 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, the interrupts are disabled on entry. + * Application entry point. */ int main(int argc, char **argv) { @@ -46,9 +46,14 @@ int main(int argc, char **argv) { (void)argv; /* - * Hardware initialization, see board.c. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ - hwinit(); + halInit(); + chSysInit(); /* * Activates the serial driver 2 using the driver default configuration. diff --git a/demos/MSP430-MSP430x1611-GCC/mcuconf.h b/demos/MSP430-MSP430x1611-GCC/mcuconf.h index 72c180648..c79252c86 100644 --- a/demos/MSP430-MSP430x1611-GCC/mcuconf.h +++ b/demos/MSP430-MSP430x1611-GCC/mcuconf.h @@ -28,7 +28,7 @@ /* * HAL driver system settings. */ -#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK +#define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_DCOCLK /* * ADC driver system settings. -- cgit v1.2.3 From fa1b222c21a4c2aee932d6605facb9706bf0dae3 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 11:02:56 +0000 Subject: PPC board files and demo updated (to be tested). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2503 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/PPC-SPC563-GCC/main.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'demos') diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index 6e65e2263..f5c6c9b40 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -145,8 +145,7 @@ static msg_t Thread1(void *arg) { } /* - * Entry point, note, the main() function is already a thread in the system - * on entry. + * Application entry point. */ int main(int argc, char **argv) { Thread *shelltp = NULL; @@ -154,6 +153,16 @@ int main(int argc, char **argv) { (void)argc; (void)argv; + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + /* * Activates the serial driver 1 using the driver default configuration. */ -- cgit v1.2.3 From e3a932e0e64d54c083e534541ac1ab36c4b82046 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 11:20:30 +0000 Subject: Win32 simulator updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2505 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Win32-MinGW/Makefile | 5 ++++- demos/Win32-MinGW/board.h | 23 ----------------------- demos/Win32-MinGW/main.c | 10 +++++----- 3 files changed, 9 insertions(+), 29 deletions(-) delete mode 100644 demos/Win32-MinGW/board.h (limited to 'demos') diff --git a/demos/Win32-MinGW/Makefile b/demos/Win32-MinGW/Makefile index c1a452297..652c60b44 100644 --- a/demos/Win32-MinGW/Makefile +++ b/demos/Win32-MinGW/Makefile @@ -57,6 +57,7 @@ UADEFS = # Imported source files CHIBIOS = ../.. +include $(CHIBIOS)/boards/simulator/board.mk include ${CHIBIOS}/os/hal/hal.mk include ${CHIBIOS}/os/hal/platforms/Win32/platform.mk include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk @@ -69,6 +70,7 @@ SRC = ${PORTSRC} \ ${TESTSRC} \ ${HALSRC} \ ${PLATFORMSRC} \ + $(BOARDSRC) \ ${CHIBIOS}/os/various/shell.c \ main.c @@ -76,7 +78,8 @@ SRC = ${PORTSRC} \ ASRC = # List all user directories here -UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ ${CHIBIOS}/os/various # List the user directory to look for the libraries here diff --git a/demos/Win32-MinGW/board.h b/demos/Win32-MinGW/board.h deleted file mode 100644 index 7b89d92d0..000000000 --- a/demos/Win32-MinGW/board.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#endif /* _BOARD_H_ */ diff --git a/demos/Win32-MinGW/main.c b/demos/Win32-MinGW/main.c index aa6d29716..9ce9b284a 100644 --- a/demos/Win32-MinGW/main.c +++ b/demos/Win32-MinGW/main.c @@ -220,13 +220,13 @@ int main(void) { EventListener sd1fel, sd2fel, tel; /* - * HAL initialization. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ halInit(); - - /* - * ChibiOS/RT initialization. - */ chSysInit(); /* -- cgit v1.2.3 From 7c1828c96c3b05cba909d6051d112725f2310d66 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 11:38:07 +0000 Subject: Updated Posix simulator. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2508 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/Posix-GCC/Makefile | 5 ++++- demos/Posix-GCC/board.h | 23 ----------------------- demos/Posix-GCC/main.c | 10 +++++----- 3 files changed, 9 insertions(+), 29 deletions(-) delete mode 100644 demos/Posix-GCC/board.h (limited to 'demos') diff --git a/demos/Posix-GCC/Makefile b/demos/Posix-GCC/Makefile index 37caaf9bd..3a8b43c90 100644 --- a/demos/Posix-GCC/Makefile +++ b/demos/Posix-GCC/Makefile @@ -57,6 +57,7 @@ UADEFS = # Imported source files CHIBIOS = ../.. +include $(CHIBIOS)/boards/simulator/board.mk include ${CHIBIOS}/os/hal/hal.mk include ${CHIBIOS}/os/hal/platforms/Posix/platform.mk include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk @@ -69,6 +70,7 @@ SRC = ${PORTSRC} \ ${TESTSRC} \ ${HALSRC} \ ${PLATFORMSRC} \ + $(BOARDSRC) \ ${CHIBIOS}/os/various/shell.c \ main.c @@ -76,7 +78,8 @@ SRC = ${PORTSRC} \ ASRC = # List all user directories here -UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) $(HALINC) $(PLATFORMINC) \ +UINCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ ${CHIBIOS}/os/various # List the user directory to look for the libraries here diff --git a/demos/Posix-GCC/board.h b/demos/Posix-GCC/board.h deleted file mode 100644 index 7b89d92d0..000000000 --- a/demos/Posix-GCC/board.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#endif /* _BOARD_H_ */ diff --git a/demos/Posix-GCC/main.c b/demos/Posix-GCC/main.c index 28e136bc8..fdce30ffd 100644 --- a/demos/Posix-GCC/main.c +++ b/demos/Posix-GCC/main.c @@ -169,13 +169,13 @@ int main(void) { EventListener sd1fel, sd2fel, tel; /* - * HAL initialization. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ halInit(); - - /* - * ChibiOS/RT initialization. - */ chSysInit(); /* -- cgit v1.2.3 From 675adde160fba196043bb471ae36a222238db49e Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 19 Dec 2010 12:50:56 +0000 Subject: STM8 board files and demos updated. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2509 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c | 14 ++--- demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw | 2 +- demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c | 14 ++--- demos/STM8S-STM8S208-RC/ch.rapp | 59 +++++++++++----------- demos/STM8S-STM8S208-RC/ch.rprj | 2 +- demos/STM8S-STM8S208-RC/main.c | 14 ++--- 6 files changed, 53 insertions(+), 52 deletions(-) (limited to 'demos') diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c index d1545a84d..6245449cf 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c @@ -42,18 +42,18 @@ static msg_t Thread1(void *arg) { } /* - * Entry point. + * Application entry point. */ void main(void) { /* - * Board/HAL initialization. - */ - hwinit(); - - /* - * OS initialization. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ + halInit(); chSysInit(); /* diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw index 130504bef..a6630271a 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw @@ -11,6 +11,6 @@ Dependencies= Filename=raisonance\raisonance.stp Dependencies= [Options] -ActiveProject=raisonance +ActiveProject=cosmic ActiveConfig=Release AddSortedElements=0 diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c index 35321bf62..41f38ac80 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c @@ -38,18 +38,18 @@ static msg_t Thread1(void *arg) { } /* - * Entry point. + * Application entry point. */ void main(void) { /* - * Board/HAL initialization. - */ - hwinit(); - - /* - * OS initialization. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ + halInit(); chSysInit(); /* diff --git a/demos/STM8S-STM8S208-RC/ch.rapp b/demos/STM8S-STM8S208-RC/ch.rapp index fbe5413e6..3b4e4b047 100644 --- a/demos/STM8S-STM8S208-RC/ch.rapp +++ b/demos/STM8S-STM8S208-RC/ch.rapp @@ -1,6 +1,6 @@ - - + + @@ -11,15 +11,15 @@
- +
- + - + - + - + @@ -31,7 +31,7 @@ - + @@ -42,17 +42,17 @@
- +
- + - + - + - + - + @@ -67,11 +67,11 @@ - + - + @@ -88,12 +88,13 @@ + - + - + @@ -101,21 +102,21 @@
- +
- +
- +
- +
@@ -126,33 +127,33 @@
- +
- +
- +
- +
- +
- +
- + diff --git a/demos/STM8S-STM8S208-RC/ch.rprj b/demos/STM8S-STM8S208-RC/ch.rprj index 138f43304..ad8b9b39e 100644 --- a/demos/STM8S-STM8S208-RC/ch.rprj +++ b/demos/STM8S-STM8S208-RC/ch.rprj @@ -1,4 +1,4 @@ - + \ No newline at end of file diff --git a/demos/STM8S-STM8S208-RC/main.c b/demos/STM8S-STM8S208-RC/main.c index 4e714fc15..c676f05d5 100644 --- a/demos/STM8S-STM8S208-RC/main.c +++ b/demos/STM8S-STM8S208-RC/main.c @@ -38,18 +38,18 @@ static msg_t Thread1(void *arg) { } /* - * Entry point. + * Application entry point. */ void main(void) { /* - * Board/HAL initialization. - */ - hwinit(); - - /* - * OS initialization. + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. */ + halInit(); chSysInit(); /* -- cgit v1.2.3 From f2386f6a22c55842203278c5b1f9691c5ac5f8fd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 21 Dec 2010 10:30:39 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2515 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARM7-AT91SAM7S-FATFS-GCC/main.c | 5 +---- demos/ARM7-AT91SAM7S-GCC/main.c | 5 +---- demos/ARM7-AT91SAM7X-FATFS-GCC/main.c | 5 +---- demos/ARM7-AT91SAM7X-GCC/main.c | 4 +--- demos/ARM7-AT91SAM7X-LWIP-GCC/main.c | 5 +---- demos/ARM7-AT91SAM7X-UIP-GCC/main.c | 5 +---- demos/ARM7-LPC214x-FATFS-GCC/main.c | 5 +---- demos/ARM7-LPC214x-G++/main.cpp | 5 +---- demos/ARM7-LPC214x-GCC/main.c | 5 +---- demos/ARMCM0-LPC1114-GCC/main.c | 5 +---- demos/ARMCM3-LPC1343-GCC/main.c | 5 +---- demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c | 5 +---- demos/ARMCM3-STM32F103-FATFS-GCC/main.c | 5 +---- demos/ARMCM3-STM32F103-GCC/main.c | 5 +---- demos/ARMCM3-STM32F103-IAR/main.c | 5 +---- demos/ARMCM3-STM32F107-GCC/main.c | 5 +---- demos/AVR-AT90CANx-GCC/main.c | 2 +- demos/AVR-ATmega128-GCC/main.c | 2 +- demos/MSP430-MSP430x1611-GCC/main.c | 5 +---- demos/PPC-SPC563-GCC/main.c | 5 +---- 20 files changed, 20 insertions(+), 73 deletions(-) (limited to 'demos') diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c index 95c5c94a3..faf8c5a8d 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c @@ -293,7 +293,7 @@ static void RemoveHandler(eventid_t id) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { static const evhandler_t evhndl[] = { InsertHandler, RemoveHandler @@ -301,9 +301,6 @@ int main(int argc, char **argv) { Thread *shelltp = NULL; struct EventListener el0, el1; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers diff --git a/demos/ARM7-AT91SAM7S-GCC/main.c b/demos/ARM7-AT91SAM7S-GCC/main.c index 49ce3df70..c49576c34 100644 --- a/demos/ARM7-AT91SAM7S-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-GCC/main.c @@ -37,10 +37,7 @@ static msg_t Thread1(void *p) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c index 5708cb3b3..3c3f2aae4 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -276,7 +276,7 @@ static void RemoveHandler(eventid_t id) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { static const evhandler_t evhndl[] = { InsertHandler, RemoveHandler @@ -284,9 +284,6 @@ int main(int argc, char **argv) { Thread *shelltp = NULL; struct EventListener el0, el1; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers diff --git a/demos/ARM7-AT91SAM7X-GCC/main.c b/demos/ARM7-AT91SAM7X-GCC/main.c index a4af5dadb..d42ebfe68 100644 --- a/demos/ARM7-AT91SAM7X-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-GCC/main.c @@ -37,9 +37,7 @@ static msg_t Thread1(void *p) { /* * Application entry point. */ -int main(int argc, char **argv) { - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c index bee5b36c9..d8ff64965 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/main.c @@ -40,10 +40,7 @@ static msg_t Thread1(void *p) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c index 1fd5fcf52..81ec5f89a 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/main.c @@ -41,10 +41,7 @@ static msg_t Thread1(void *p) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c index 9edae1db7..44afc36fd 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -223,7 +223,7 @@ static void RemoveHandler(eventid_t id) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { static const evhandler_t evhndl[] = { TimerHandler, InsertHandler, @@ -232,9 +232,6 @@ int main(int argc, char **argv) { static EvTimer evt; struct EventListener el0, el1, el2; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers diff --git a/demos/ARM7-LPC214x-G++/main.cpp b/demos/ARM7-LPC214x-G++/main.cpp index 8a9ca1c05..ca99c67ef 100644 --- a/demos/ARM7-LPC214x-G++/main.cpp +++ b/demos/ARM7-LPC214x-G++/main.cpp @@ -144,16 +144,13 @@ static void TimerHandler(eventid_t id) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { static const evhandler_t evhndl[] = { TimerHandler }; static EvTimer evt; struct EventListener el0; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers diff --git a/demos/ARM7-LPC214x-GCC/main.c b/demos/ARM7-LPC214x-GCC/main.c index 6cc8037f6..e4810d125 100644 --- a/demos/ARM7-LPC214x-GCC/main.c +++ b/demos/ARM7-LPC214x-GCC/main.c @@ -62,10 +62,7 @@ static msg_t Thread2(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARMCM0-LPC1114-GCC/main.c b/demos/ARMCM0-LPC1114-GCC/main.c index 14f913a0a..6080d1d72 100644 --- a/demos/ARMCM0-LPC1114-GCC/main.c +++ b/demos/ARMCM0-LPC1114-GCC/main.c @@ -94,12 +94,9 @@ static msg_t Thread2(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { uint8_t i; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers diff --git a/demos/ARMCM3-LPC1343-GCC/main.c b/demos/ARMCM3-LPC1343-GCC/main.c index 0600865f3..10e21bb9b 100644 --- a/demos/ARMCM3-LPC1343-GCC/main.c +++ b/demos/ARMCM3-LPC1343-GCC/main.c @@ -94,12 +94,9 @@ static msg_t Thread2(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { uint8_t i; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers diff --git a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c index a94600203..4b5978775 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY-GCC/main.c @@ -172,10 +172,7 @@ static msg_t Thread1(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c index 1d0018b9b..58a966278 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/main.c +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/main.c @@ -266,7 +266,7 @@ static void RemoveHandler(eventid_t id) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { static const evhandler_t evhndl[] = { InsertHandler, RemoveHandler @@ -274,9 +274,6 @@ int main(int argc, char **argv) { Thread *shelltp = NULL; struct EventListener el0, el1; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c index e133e6e3b..5856e07b5 100644 --- a/demos/ARMCM3-STM32F103-GCC/main.c +++ b/demos/ARMCM3-STM32F103-GCC/main.c @@ -40,10 +40,7 @@ static msg_t Thread1(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARMCM3-STM32F103-IAR/main.c b/demos/ARMCM3-STM32F103-IAR/main.c index e133e6e3b..5856e07b5 100644 --- a/demos/ARMCM3-STM32F103-IAR/main.c +++ b/demos/ARMCM3-STM32F103-IAR/main.c @@ -40,10 +40,7 @@ static msg_t Thread1(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/ARMCM3-STM32F107-GCC/main.c b/demos/ARMCM3-STM32F107-GCC/main.c index fe463af89..73bc0b402 100644 --- a/demos/ARMCM3-STM32F107-GCC/main.c +++ b/demos/ARMCM3-STM32F107-GCC/main.c @@ -40,10 +40,7 @@ static msg_t Thread1(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/AVR-AT90CANx-GCC/main.c b/demos/AVR-AT90CANx-GCC/main.c index 79888a55a..f170a4c27 100644 --- a/demos/AVR-AT90CANx-GCC/main.c +++ b/demos/AVR-AT90CANx-GCC/main.c @@ -41,7 +41,7 @@ static void TimerHandler(eventid_t id) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { static EvTimer evt; static evhandler_t handlers[1] = { TimerHandler diff --git a/demos/AVR-ATmega128-GCC/main.c b/demos/AVR-ATmega128-GCC/main.c index c02ef5404..e1cb2a9d6 100644 --- a/demos/AVR-ATmega128-GCC/main.c +++ b/demos/AVR-ATmega128-GCC/main.c @@ -44,7 +44,7 @@ static void TimerHandler(eventid_t id) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { static EvTimer evt; static evhandler_t handlers[1] = { TimerHandler diff --git a/demos/MSP430-MSP430x1611-GCC/main.c b/demos/MSP430-MSP430x1611-GCC/main.c index c010b89b3..999ea8f49 100644 --- a/demos/MSP430-MSP430x1611-GCC/main.c +++ b/demos/MSP430-MSP430x1611-GCC/main.c @@ -40,10 +40,7 @@ static msg_t Thread1(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { - - (void)argc; - (void)argv; +int main(void) { /* * System initializations. diff --git a/demos/PPC-SPC563-GCC/main.c b/demos/PPC-SPC563-GCC/main.c index f5c6c9b40..3210716ae 100644 --- a/demos/PPC-SPC563-GCC/main.c +++ b/demos/PPC-SPC563-GCC/main.c @@ -147,12 +147,9 @@ static msg_t Thread1(void *arg) { /* * Application entry point. */ -int main(int argc, char **argv) { +int main(void) { Thread *shelltp = NULL; - (void)argc; - (void)argv; - /* * System initializations. * - HAL initialization, this also initializes the configured device drivers -- cgit v1.2.3 From bbf9515ebbbe37b3835f382d8724c5888b303744 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 21 Dec 2010 19:51:33 +0000 Subject: Keil port and demo (working but not complete). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2517 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt | 2007 +++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/keil/ch.uvproj | 1040 +++++++++++++++ 2 files changed, 3047 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt create mode 100644 demos/ARMCM3-STM32F103-GCC/keil/ch.uvproj (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt new file mode 100644 index 000000000..2402a0bd6 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt @@ -0,0 +1,2007 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + Demo + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\lst\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Reference Manual + DATASHTS\ST\STM32F10xxx.PDF + + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 8 + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + 0 + DLGTARM + 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..\..\..\os\hal\platforms\STM32\spi_lld.h + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32\stm32_dma.h + + + stm32f10x.h + 5 + ..\..\..\os\hal\platforms\STM32\stm32f10x.h + + + uart_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\uart_lld.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + + + + + + -- cgit v1.2.3 From 7ea532c6041bbd6012166aefd8f3aa01368a92fb Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 21 Dec 2010 22:01:51 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2519 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt | 58 +++++++++++--------------------- 1 file changed, 20 insertions(+), 38 deletions(-) (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt index 2402a0bd6..341c325d7 100644 --- a/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt +++ b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt @@ -240,8 +240,8 @@ 0 0 0 - 0 - 0 + 73 + 73 0 ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s cstartup.s @@ -597,8 +597,8 @@ 0 0 0 - 0 - 0 + 4 + 4 0 ..\..\..\os\kernel\src\chsys.c chsys.c @@ -994,10 +994,10 @@ 1 0 0 - 13 + 68 0 - 76 - 98 + 79 + 92 0 ..\..\..\os\hal\src\can.c can.c @@ -1024,8 +1024,8 @@ 0 58 0 - 61 - 81 + 0 + 0 0 ..\..\..\os\hal\src\i2c.c i2c.c @@ -1050,10 +1050,10 @@ 1 0 0 - 40 + 1 0 226 - 245 + 233 0 ..\..\..\os\hal\src\mmc_spi.c mmc_spi.c @@ -1080,8 +1080,8 @@ 0 56 0 - 67 - 81 + 0 + 0 0 ..\..\..\os\hal\src\pwm.c pwm.c @@ -1956,7 +1956,7 @@ 0 0 32 - 44 + 39 0 ..\main.c main.c @@ -1968,37 +1968,19 @@ 0 100 - 3 + 1 ..\main.c 0 32 - 44 - - - ..\..\..\os\hal\src\serial.c - 32 - 106 - 120 - - - ..\..\..\os\hal\src\adc.c - 13 - 85 - 101 - - - ..\..\..\os\hal\src\can.c - 58 - 76 - 91 + 39 - ..\..\..\os\hal\src\mmc_spi.c - 40 - 226 - 245 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + 0 + 73 + 73 -- cgit v1.2.3 From f8d5fa9066126abff066978e4cfcff44917fac52 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 22 Dec 2010 07:14:01 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2520 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/iar/ch.ewp | 2155 +++++++++++++++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/iar/ch.eww | 10 + demos/ARMCM3-STM32F103-GCC/iar/ch.icf | 37 + 3 files changed, 2202 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-GCC/iar/ch.ewp create mode 100644 demos/ARMCM3-STM32F103-GCC/iar/ch.eww create mode 100644 demos/ARMCM3-STM32F103-GCC/iar/ch.icf (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/iar/ch.ewp b/demos/ARMCM3-STM32F103-GCC/iar/ch.ewp new file mode 100644 index 000000000..58d4b025e --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/iar/ch.ewp @@ -0,0 +1,2155 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 18 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 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$PROJ_DIR$\..\..\..\os\hal\include\uart.h + + + + src + + $PROJ_DIR$\..\..\..\os\hal\src\adc.c + + + $PROJ_DIR$\..\..\..\os\hal\src\can.c + + + $PROJ_DIR$\..\..\..\os\hal\src\hal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\i2c.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mac.c + + + $PROJ_DIR$\..\..\..\os\hal\src\mmc_spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pal.c + + + $PROJ_DIR$\..\..\..\os\hal\src\pwm.c + + + $PROJ_DIR$\..\..\..\os\hal\src\serial.c + + + $PROJ_DIR$\..\..\..\os\hal\src\spi.c + + + $PROJ_DIR$\..\..\..\os\hal\src\uart.c + + + + + kernel + + include + + $PROJ_DIR$\..\..\..\os\kernel\include\ch.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chcond.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdebug.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chdynamic.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chevents.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chheap.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chinline.h + + + $PROJ_DIR$\..\..\..\os\kernel\include\chioch.h + + + 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$PROJ_DIR$\..\..\..\os\hal\platforms\STM32\stm32f10x.h + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.c + + + $PROJ_DIR$\..\..\..\os\hal\platforms\STM32\uart_lld.h + + + + port + + STM32 + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\cmparams.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\STM32\vectors.s + + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcore_v7m.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chcoreasm_v7m.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\chtypes.h + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\cstartup.s + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.c + + + $PROJ_DIR$\..\..\..\os\ports\IAR\ARMCMx\nvic.h + + + + + test + + $PROJ_DIR$\..\..\..\test\test.c + + + $PROJ_DIR$\..\..\..\test\test.h + + + $PROJ_DIR$\..\..\..\test\testbmk.c + + + $PROJ_DIR$\..\..\..\test\testbmk.h + + + $PROJ_DIR$\..\..\..\test\testdyn.c + + + $PROJ_DIR$\..\..\..\test\testdyn.h + + + $PROJ_DIR$\..\..\..\test\testevt.c + + + $PROJ_DIR$\..\..\..\test\testevt.h + + + $PROJ_DIR$\..\..\..\test\testheap.c + + + $PROJ_DIR$\..\..\..\test\testheap.h + + + $PROJ_DIR$\..\..\..\test\testmbox.c + + + $PROJ_DIR$\..\..\..\test\testmbox.h + + + $PROJ_DIR$\..\..\..\test\testmsg.c + + + $PROJ_DIR$\..\..\..\test\testmsg.h + + + $PROJ_DIR$\..\..\..\test\testmtx.c + + + $PROJ_DIR$\..\..\..\test\testmtx.h + + + $PROJ_DIR$\..\..\..\test\testpools.c + + + $PROJ_DIR$\..\..\..\test\testpools.h + + + $PROJ_DIR$\..\..\..\test\testqueues.c + + + $PROJ_DIR$\..\..\..\test\testqueues.h + + + $PROJ_DIR$\..\..\..\test\testsem.c + + + $PROJ_DIR$\..\..\..\test\testsem.h + + + $PROJ_DIR$\..\..\..\test\testthd.c + + + $PROJ_DIR$\..\..\..\test\testthd.h + + + + $PROJ_DIR$\..\chconf.h + + + $PROJ_DIR$\..\halconf.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\mcuconf.h + + + + diff --git a/demos/ARMCM3-STM32F103-GCC/iar/ch.eww b/demos/ARMCM3-STM32F103-GCC/iar/ch.eww new file mode 100644 index 000000000..f9b3b2000 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/iar/ch.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ch.ewp + + + + + diff --git a/demos/ARMCM3-STM32F103-GCC/iar/ch.icf b/demos/ARMCM3-STM32F103-GCC/iar/ch.icf new file mode 100644 index 000000000..c14393d39 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/iar/ch.icf @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the Process Stack.*/ +define symbol __ICFEDIT_size_pstack__ = 0x400; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PSTACK with alignment = 8, size = __ICFEDIT_size_pstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block SYSHEAP with alignment = 8, size = 0 { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section .intvec }; +place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { block PSTACK, block CSTACK, readwrite, block HEAP, block SYSHEAP}; + +define exported symbol __heap_end__ = end(RAM_region) + 1; -- cgit v1.2.3 From 29edac9fa14a7104535bd420e8542859a25d29c6 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 22 Dec 2010 07:27:34 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2521 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/iar/ch.ewp | 2 +- demos/ARMCM3-STM32F103-GCC/iar/settings/ch.wsdt | 66 +++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 1 deletion(-) create mode 100644 demos/ARMCM3-STM32F103-GCC/iar/settings/ch.wsdt (limited to 'demos') diff --git a/demos/ARMCM3-STM32F103-GCC/iar/ch.ewp b/demos/ARMCM3-STM32F103-GCC/iar/ch.ewp index 58d4b025e..142d53b34 100644 --- a/demos/ARMCM3-STM32F103-GCC/iar/ch.ewp +++ b/demos/ARMCM3-STM32F103-GCC/iar/ch.ewp @@ -275,7 +275,7 @@